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block: Mark bdrv_replace_child_noperm() GRAPH_WRLOCK
[qemu/kevin.git] / target / arm / tcg / cpu32.c
blob1f918ff5375a76ddc2ea0b5018752bb7b500637b
1 /*
2 * QEMU ARM TCG-only CPUs.
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This code is licensed under the GNU GPL v2 or later.
7 *
8 * SPDX-License-Identifier: GPL-2.0-or-later
9 */
10
11 #include "qemu/osdep.h"
12 #include "cpu.h"
13 #include "hw/core/tcg-cpu-ops.h"
14 #include "internals.h"
15 #include "target/arm/idau.h"
16 #if !defined(CONFIG_USER_ONLY)
17 #include "hw/boards.h"
18 #endif
19 #include "cpregs.h"
20 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
21 #include "hw/intc/armv7m_nvic.h"
22 #endif
23
24
25 /* Share AArch32 -cpu max features with AArch64. */
26 void aa32_max_features(ARMCPU *cpu)
27 {
28 uint32_t t;
29
30 /* Add additional features supported by QEMU */
31 t = cpu->isar.id_isar5;
32 t = FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */
33 t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */
34 t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */
35 t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
36 t = FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */
37 t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */
38 cpu->isar.id_isar5 = t;
39
40 t = cpu->isar.id_isar6;
41 t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */
42 t = FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */
43 t = FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */
44 t = FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */
45 t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */
46 t = FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */
47 t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */
48 cpu->isar.id_isar6 = t;
49
50 t = cpu->isar.mvfr1;
51 t = FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */
52 t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */
53 cpu->isar.mvfr1 = t;
54
55 t = cpu->isar.mvfr2;
56 t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
57 t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
58 cpu->isar.mvfr2 = t;
59
60 t = cpu->isar.id_mmfr3;
61 t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */
62 cpu->isar.id_mmfr3 = t;
63
64 t = cpu->isar.id_mmfr4;
65 t = FIELD_DP32(t, ID_MMFR4, HPDS, 2); /* FEAT_HPDS2 */
66 t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
67 t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */
68 t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */
69 t = FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT */
70 cpu->isar.id_mmfr4 = t;
71
72 t = cpu->isar.id_mmfr5;
73 t = FIELD_DP32(t, ID_MMFR5, ETS, 1); /* FEAT_ETS */
74 cpu->isar.id_mmfr5 = t;
75
76 t = cpu->isar.id_pfr0;
77 t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */
78 t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
79 t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */
80 cpu->isar.id_pfr0 = t;
81
82 t = cpu->isar.id_pfr2;
83 t = FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */
84 t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */
85 cpu->isar.id_pfr2 = t;
86
87 t = cpu->isar.id_dfr0;
88 t = FIELD_DP32(t, ID_DFR0, COPDBG, 9); /* FEAT_Debugv8p4 */
89 t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */
90 t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */
91 cpu->isar.id_dfr0 = t;
92 }
93
94 /* CPU models. These are not needed for the AArch64 linux-user build. */
95 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
96
97 #if !defined(CONFIG_USER_ONLY)
98 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
99 {
100 CPUClass *cc = CPU_GET_CLASS(cs);
101 ARMCPU *cpu = ARM_CPU(cs);
102 CPUARMState *env = &cpu->env;
103 bool ret = false;
104
105 /*
106 * ARMv7-M interrupt masking works differently than -A or -R.
107 * There is no FIQ/IRQ distinction. Instead of I and F bits
108 * masking FIQ and IRQ interrupts, an exception is taken only
109 * if it is higher priority than the current execution priority
110 * (which depends on state like BASEPRI, FAULTMASK and the
111 * currently active exception).
112 */
113 if (interrupt_request & CPU_INTERRUPT_HARD
114 && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
115 cs->exception_index = EXCP_IRQ;
116 cc->tcg_ops->do_interrupt(cs);
117 ret = true;
118 }
119 return ret;
120 }
121 #endif /* !CONFIG_USER_ONLY */
122
123 static void arm926_initfn(Object *obj)
124 {
125 ARMCPU *cpu = ARM_CPU(obj);
126
127 cpu->dtb_compatible = "arm,arm926";
128 set_feature(&cpu->env, ARM_FEATURE_V5);
129 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
130 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
131 cpu->midr = 0x41069265;
132 cpu->reset_fpsid = 0x41011090;
133 cpu->ctr = 0x1dd20d2;
134 cpu->reset_sctlr = 0x00090078;
135
136 /*
137 * ARMv5 does not have the ID_ISAR registers, but we can still
138 * set the field to indicate Jazelle support within QEMU.
139 */
140 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
141 /*
142 * Similarly, we need to set MVFR0 fields to enable vfp and short vector
143 * support even though ARMv5 doesn't have this register.
144 */
145 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
146 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
147 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
148 }
149
150 static void arm946_initfn(Object *obj)
151 {
152 ARMCPU *cpu = ARM_CPU(obj);
153
154 cpu->dtb_compatible = "arm,arm946";
155 set_feature(&cpu->env, ARM_FEATURE_V5);
156 set_feature(&cpu->env, ARM_FEATURE_PMSA);
157 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
158 cpu->midr = 0x41059461;
159 cpu->ctr = 0x0f004006;
160 cpu->reset_sctlr = 0x00000078;
161 }
162
163 static void arm1026_initfn(Object *obj)
164 {
165 ARMCPU *cpu = ARM_CPU(obj);
166
167 cpu->dtb_compatible = "arm,arm1026";
168 set_feature(&cpu->env, ARM_FEATURE_V5);
169 set_feature(&cpu->env, ARM_FEATURE_AUXCR);
170 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
171 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
172 cpu->midr = 0x4106a262;
173 cpu->reset_fpsid = 0x410110a0;
174 cpu->ctr = 0x1dd20d2;
175 cpu->reset_sctlr = 0x00090078;
176 cpu->reset_auxcr = 1;
177
178 /*
179 * ARMv5 does not have the ID_ISAR registers, but we can still
180 * set the field to indicate Jazelle support within QEMU.
181 */
182 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
183 /*
184 * Similarly, we need to set MVFR0 fields to enable vfp and short vector
185 * support even though ARMv5 doesn't have this register.
186 */
187 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
188 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
189 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
190
191 {
192 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
193 ARMCPRegInfo ifar = {
194 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
195 .access = PL1_RW,
196 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
197 .resetvalue = 0
198 };
199 define_one_arm_cp_reg(cpu, &ifar);
200 }
201 }
202
203 static void arm1136_r2_initfn(Object *obj)
204 {
205 ARMCPU *cpu = ARM_CPU(obj);
206 /*
207 * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
208 * older core than plain "arm1136". In particular this does not
209 * have the v6K features.
210 * These ID register values are correct for 1136 but may be wrong
211 * for 1136_r2 (in particular r0p2 does not actually implement most
212 * of the ID registers).
213 */
214
215 cpu->dtb_compatible = "arm,arm1136";
216 set_feature(&cpu->env, ARM_FEATURE_V6);
217 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
218 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
219 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
220 cpu->midr = 0x4107b362;
221 cpu->reset_fpsid = 0x410120b4;
222 cpu->isar.mvfr0 = 0x11111111;
223 cpu->isar.mvfr1 = 0x00000000;
224 cpu->ctr = 0x1dd20d2;
225 cpu->reset_sctlr = 0x00050078;
226 cpu->isar.id_pfr0 = 0x111;
227 cpu->isar.id_pfr1 = 0x1;
228 cpu->isar.id_dfr0 = 0x2;
229 cpu->id_afr0 = 0x3;
230 cpu->isar.id_mmfr0 = 0x01130003;
231 cpu->isar.id_mmfr1 = 0x10030302;
232 cpu->isar.id_mmfr2 = 0x01222110;
233 cpu->isar.id_isar0 = 0x00140011;
234 cpu->isar.id_isar1 = 0x12002111;
235 cpu->isar.id_isar2 = 0x11231111;
236 cpu->isar.id_isar3 = 0x01102131;
237 cpu->isar.id_isar4 = 0x141;
238 cpu->reset_auxcr = 7;
239 }
240
241 static void arm1136_initfn(Object *obj)
242 {
243 ARMCPU *cpu = ARM_CPU(obj);
244
245 cpu->dtb_compatible = "arm,arm1136";
246 set_feature(&cpu->env, ARM_FEATURE_V6K);
247 set_feature(&cpu->env, ARM_FEATURE_V6);
248 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
249 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
250 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
251 cpu->midr = 0x4117b363;
252 cpu->reset_fpsid = 0x410120b4;
253 cpu->isar.mvfr0 = 0x11111111;
254 cpu->isar.mvfr1 = 0x00000000;
255 cpu->ctr = 0x1dd20d2;
256 cpu->reset_sctlr = 0x00050078;
257 cpu->isar.id_pfr0 = 0x111;
258 cpu->isar.id_pfr1 = 0x1;
259 cpu->isar.id_dfr0 = 0x2;
260 cpu->id_afr0 = 0x3;
261 cpu->isar.id_mmfr0 = 0x01130003;
262 cpu->isar.id_mmfr1 = 0x10030302;
263 cpu->isar.id_mmfr2 = 0x01222110;
264 cpu->isar.id_isar0 = 0x00140011;
265 cpu->isar.id_isar1 = 0x12002111;
266 cpu->isar.id_isar2 = 0x11231111;
267 cpu->isar.id_isar3 = 0x01102131;
268 cpu->isar.id_isar4 = 0x141;
269 cpu->reset_auxcr = 7;
270 }
271
272 static void arm1176_initfn(Object *obj)
273 {
274 ARMCPU *cpu = ARM_CPU(obj);
275
276 cpu->dtb_compatible = "arm,arm1176";
277 set_feature(&cpu->env, ARM_FEATURE_V6K);
278 set_feature(&cpu->env, ARM_FEATURE_VAPA);
279 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
280 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
281 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
282 set_feature(&cpu->env, ARM_FEATURE_EL3);
283 cpu->midr = 0x410fb767;
284 cpu->reset_fpsid = 0x410120b5;
285 cpu->isar.mvfr0 = 0x11111111;
286 cpu->isar.mvfr1 = 0x00000000;
287 cpu->ctr = 0x1dd20d2;
288 cpu->reset_sctlr = 0x00050078;
289 cpu->isar.id_pfr0 = 0x111;
290 cpu->isar.id_pfr1 = 0x11;
291 cpu->isar.id_dfr0 = 0x33;
292 cpu->id_afr0 = 0;
293 cpu->isar.id_mmfr0 = 0x01130003;
294 cpu->isar.id_mmfr1 = 0x10030302;
295 cpu->isar.id_mmfr2 = 0x01222100;
296 cpu->isar.id_isar0 = 0x0140011;
297 cpu->isar.id_isar1 = 0x12002111;
298 cpu->isar.id_isar2 = 0x11231121;
299 cpu->isar.id_isar3 = 0x01102131;
300 cpu->isar.id_isar4 = 0x01141;
301 cpu->reset_auxcr = 7;
302 }
303
304 static void arm11mpcore_initfn(Object *obj)
305 {
306 ARMCPU *cpu = ARM_CPU(obj);
307
308 cpu->dtb_compatible = "arm,arm11mpcore";
309 set_feature(&cpu->env, ARM_FEATURE_V6K);
310 set_feature(&cpu->env, ARM_FEATURE_VAPA);
311 set_feature(&cpu->env, ARM_FEATURE_MPIDR);
312 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
313 cpu->midr = 0x410fb022;
314 cpu->reset_fpsid = 0x410120b4;
315 cpu->isar.mvfr0 = 0x11111111;
316 cpu->isar.mvfr1 = 0x00000000;
317 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
318 cpu->isar.id_pfr0 = 0x111;
319 cpu->isar.id_pfr1 = 0x1;
320 cpu->isar.id_dfr0 = 0;
321 cpu->id_afr0 = 0x2;
322 cpu->isar.id_mmfr0 = 0x01100103;
323 cpu->isar.id_mmfr1 = 0x10020302;
324 cpu->isar.id_mmfr2 = 0x01222000;
325 cpu->isar.id_isar0 = 0x00100011;
326 cpu->isar.id_isar1 = 0x12002111;
327 cpu->isar.id_isar2 = 0x11221011;
328 cpu->isar.id_isar3 = 0x01102131;
329 cpu->isar.id_isar4 = 0x141;
330 cpu->reset_auxcr = 1;
331 }
332
333 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
334 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
335 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
336 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
337 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
338 };
339
340 static void cortex_a8_initfn(Object *obj)
341 {
342 ARMCPU *cpu = ARM_CPU(obj);
343
344 cpu->dtb_compatible = "arm,cortex-a8";
345 set_feature(&cpu->env, ARM_FEATURE_V7);
346 set_feature(&cpu->env, ARM_FEATURE_NEON);
347 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
348 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
349 set_feature(&cpu->env, ARM_FEATURE_EL3);
350 cpu->midr = 0x410fc080;
351 cpu->reset_fpsid = 0x410330c0;
352 cpu->isar.mvfr0 = 0x11110222;
353 cpu->isar.mvfr1 = 0x00011111;
354 cpu->ctr = 0x82048004;
355 cpu->reset_sctlr = 0x00c50078;
356 cpu->isar.id_pfr0 = 0x1031;
357 cpu->isar.id_pfr1 = 0x11;
358 cpu->isar.id_dfr0 = 0x400;
359 cpu->id_afr0 = 0;
360 cpu->isar.id_mmfr0 = 0x31100003;
361 cpu->isar.id_mmfr1 = 0x20000000;
362 cpu->isar.id_mmfr2 = 0x01202000;
363 cpu->isar.id_mmfr3 = 0x11;
364 cpu->isar.id_isar0 = 0x00101111;
365 cpu->isar.id_isar1 = 0x12112111;
366 cpu->isar.id_isar2 = 0x21232031;
367 cpu->isar.id_isar3 = 0x11112131;
368 cpu->isar.id_isar4 = 0x00111142;
369 cpu->isar.dbgdidr = 0x15141000;
370 cpu->clidr = (1 << 27) | (2 << 24) | 3;
371 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
372 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
373 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
374 cpu->reset_auxcr = 2;
375 cpu->isar.reset_pmcr_el0 = 0x41002000;
376 define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
377 }
378
379 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
380 /*
381 * power_control should be set to maximum latency. Again,
382 * default to 0 and set by private hook
383 */
384 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
385 .access = PL1_RW, .resetvalue = 0,
386 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
387 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
388 .access = PL1_RW, .resetvalue = 0,
389 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
390 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
391 .access = PL1_RW, .resetvalue = 0,
392 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
393 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
394 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
395 /* TLB lockdown control */
396 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
397 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
398 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
399 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
400 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
401 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
402 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
403 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
404 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
405 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
406 };
407
408 static void cortex_a9_initfn(Object *obj)
409 {
410 ARMCPU *cpu = ARM_CPU(obj);
411
412 cpu->dtb_compatible = "arm,cortex-a9";
413 set_feature(&cpu->env, ARM_FEATURE_V7);
414 set_feature(&cpu->env, ARM_FEATURE_NEON);
415 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
416 set_feature(&cpu->env, ARM_FEATURE_EL3);
417 /*
418 * Note that A9 supports the MP extensions even for
419 * A9UP and single-core A9MP (which are both different
420 * and valid configurations; we don't model A9UP).
421 */
422 set_feature(&cpu->env, ARM_FEATURE_V7MP);
423 set_feature(&cpu->env, ARM_FEATURE_CBAR);
424 cpu->midr = 0x410fc090;
425 cpu->reset_fpsid = 0x41033090;
426 cpu->isar.mvfr0 = 0x11110222;
427 cpu->isar.mvfr1 = 0x01111111;
428 cpu->ctr = 0x80038003;
429 cpu->reset_sctlr = 0x00c50078;
430 cpu->isar.id_pfr0 = 0x1031;
431 cpu->isar.id_pfr1 = 0x11;
432 cpu->isar.id_dfr0 = 0x000;
433 cpu->id_afr0 = 0;
434 cpu->isar.id_mmfr0 = 0x00100103;
435 cpu->isar.id_mmfr1 = 0x20000000;
436 cpu->isar.id_mmfr2 = 0x01230000;
437 cpu->isar.id_mmfr3 = 0x00002111;
438 cpu->isar.id_isar0 = 0x00101111;
439 cpu->isar.id_isar1 = 0x13112111;
440 cpu->isar.id_isar2 = 0x21232041;
441 cpu->isar.id_isar3 = 0x11112131;
442 cpu->isar.id_isar4 = 0x00111142;
443 cpu->isar.dbgdidr = 0x35141000;
444 cpu->clidr = (1 << 27) | (1 << 24) | 3;
445 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
446 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
447 cpu->isar.reset_pmcr_el0 = 0x41093000;
448 define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
449 }
450
451 #ifndef CONFIG_USER_ONLY
452 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
453 {
454 MachineState *ms = MACHINE(qdev_get_machine());
455
456 /*
457 * Linux wants the number of processors from here.
458 * Might as well set the interrupt-controller bit too.
459 */
460 return ((ms->smp.cpus - 1) << 24) | (1 << 23);
461 }
462 #endif
463
464 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
465 #ifndef CONFIG_USER_ONLY
466 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
467 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
468 .writefn = arm_cp_write_ignore, },
469 #endif
470 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
471 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
472 };
473
474 static void cortex_a7_initfn(Object *obj)
475 {
476 ARMCPU *cpu = ARM_CPU(obj);
477
478 cpu->dtb_compatible = "arm,cortex-a7";
479 set_feature(&cpu->env, ARM_FEATURE_V7VE);
480 set_feature(&cpu->env, ARM_FEATURE_NEON);
481 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
482 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
483 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
484 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
485 set_feature(&cpu->env, ARM_FEATURE_EL2);
486 set_feature(&cpu->env, ARM_FEATURE_EL3);
487 set_feature(&cpu->env, ARM_FEATURE_PMU);
488 cpu->midr = 0x410fc075;
489 cpu->reset_fpsid = 0x41023075;
490 cpu->isar.mvfr0 = 0x10110222;
491 cpu->isar.mvfr1 = 0x11111111;
492 cpu->ctr = 0x84448003;
493 cpu->reset_sctlr = 0x00c50078;
494 cpu->isar.id_pfr0 = 0x00001131;
495 cpu->isar.id_pfr1 = 0x00011011;
496 cpu->isar.id_dfr0 = 0x02010555;
497 cpu->id_afr0 = 0x00000000;
498 cpu->isar.id_mmfr0 = 0x10101105;
499 cpu->isar.id_mmfr1 = 0x40000000;
500 cpu->isar.id_mmfr2 = 0x01240000;
501 cpu->isar.id_mmfr3 = 0x02102211;
502 /*
503 * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
504 * table 4-41 gives 0x02101110, which includes the arm div insns.
505 */
506 cpu->isar.id_isar0 = 0x02101110;
507 cpu->isar.id_isar1 = 0x13112111;
508 cpu->isar.id_isar2 = 0x21232041;
509 cpu->isar.id_isar3 = 0x11112131;
510 cpu->isar.id_isar4 = 0x10011142;
511 cpu->isar.dbgdidr = 0x3515f005;
512 cpu->isar.dbgdevid = 0x01110f13;
513 cpu->isar.dbgdevid1 = 0x1;
514 cpu->clidr = 0x0a200023;
515 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
516 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
517 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
518 cpu->isar.reset_pmcr_el0 = 0x41072000;
519 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
520 }
521
522 static void cortex_a15_initfn(Object *obj)
523 {
524 ARMCPU *cpu = ARM_CPU(obj);
525
526 cpu->dtb_compatible = "arm,cortex-a15";
527 set_feature(&cpu->env, ARM_FEATURE_V7VE);
528 set_feature(&cpu->env, ARM_FEATURE_NEON);
529 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
530 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
531 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
532 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
533 set_feature(&cpu->env, ARM_FEATURE_EL2);
534 set_feature(&cpu->env, ARM_FEATURE_EL3);
535 set_feature(&cpu->env, ARM_FEATURE_PMU);
536 /* r4p0 cpu, not requiring expensive tlb flush errata */
537 cpu->midr = 0x414fc0f0;
538 cpu->revidr = 0x0;
539 cpu->reset_fpsid = 0x410430f0;
540 cpu->isar.mvfr0 = 0x10110222;
541 cpu->isar.mvfr1 = 0x11111111;
542 cpu->ctr = 0x8444c004;
543 cpu->reset_sctlr = 0x00c50078;
544 cpu->isar.id_pfr0 = 0x00001131;
545 cpu->isar.id_pfr1 = 0x00011011;
546 cpu->isar.id_dfr0 = 0x02010555;
547 cpu->id_afr0 = 0x00000000;
548 cpu->isar.id_mmfr0 = 0x10201105;
549 cpu->isar.id_mmfr1 = 0x20000000;
550 cpu->isar.id_mmfr2 = 0x01240000;
551 cpu->isar.id_mmfr3 = 0x02102211;
552 cpu->isar.id_isar0 = 0x02101110;
553 cpu->isar.id_isar1 = 0x13112111;
554 cpu->isar.id_isar2 = 0x21232041;
555 cpu->isar.id_isar3 = 0x11112131;
556 cpu->isar.id_isar4 = 0x10011142;
557 cpu->isar.dbgdidr = 0x3515f021;
558 cpu->isar.dbgdevid = 0x01110f13;
559 cpu->isar.dbgdevid1 = 0x0;
560 cpu->clidr = 0x0a200023;
561 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
562 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
563 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
564 cpu->isar.reset_pmcr_el0 = 0x410F3000;
565 define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
566 }
567
568 static void cortex_m0_initfn(Object *obj)
569 {
570 ARMCPU *cpu = ARM_CPU(obj);
571 set_feature(&cpu->env, ARM_FEATURE_V6);
572 set_feature(&cpu->env, ARM_FEATURE_M);
573
574 cpu->midr = 0x410cc200;
575
576 /*
577 * These ID register values are not guest visible, because
578 * we do not implement the Main Extension. They must be set
579 * to values corresponding to the Cortex-M0's implemented
580 * features, because QEMU generally controls its emulation
581 * by looking at ID register fields. We use the same values as
582 * for the M3.
583 */
584 cpu->isar.id_pfr0 = 0x00000030;
585 cpu->isar.id_pfr1 = 0x00000200;
586 cpu->isar.id_dfr0 = 0x00100000;
587 cpu->id_afr0 = 0x00000000;
588 cpu->isar.id_mmfr0 = 0x00000030;
589 cpu->isar.id_mmfr1 = 0x00000000;
590 cpu->isar.id_mmfr2 = 0x00000000;
591 cpu->isar.id_mmfr3 = 0x00000000;
592 cpu->isar.id_isar0 = 0x01141110;
593 cpu->isar.id_isar1 = 0x02111000;
594 cpu->isar.id_isar2 = 0x21112231;
595 cpu->isar.id_isar3 = 0x01111110;
596 cpu->isar.id_isar4 = 0x01310102;
597 cpu->isar.id_isar5 = 0x00000000;
598 cpu->isar.id_isar6 = 0x00000000;
599 }
600
601 static void cortex_m3_initfn(Object *obj)
602 {
603 ARMCPU *cpu = ARM_CPU(obj);
604 set_feature(&cpu->env, ARM_FEATURE_V7);
605 set_feature(&cpu->env, ARM_FEATURE_M);
606 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
607 cpu->midr = 0x410fc231;
608 cpu->pmsav7_dregion = 8;
609 cpu->isar.id_pfr0 = 0x00000030;
610 cpu->isar.id_pfr1 = 0x00000200;
611 cpu->isar.id_dfr0 = 0x00100000;
612 cpu->id_afr0 = 0x00000000;
613 cpu->isar.id_mmfr0 = 0x00000030;
614 cpu->isar.id_mmfr1 = 0x00000000;
615 cpu->isar.id_mmfr2 = 0x00000000;
616 cpu->isar.id_mmfr3 = 0x00000000;
617 cpu->isar.id_isar0 = 0x01141110;
618 cpu->isar.id_isar1 = 0x02111000;
619 cpu->isar.id_isar2 = 0x21112231;
620 cpu->isar.id_isar3 = 0x01111110;
621 cpu->isar.id_isar4 = 0x01310102;
622 cpu->isar.id_isar5 = 0x00000000;
623 cpu->isar.id_isar6 = 0x00000000;
624 }
625
626 static void cortex_m4_initfn(Object *obj)
627 {
628 ARMCPU *cpu = ARM_CPU(obj);
629
630 set_feature(&cpu->env, ARM_FEATURE_V7);
631 set_feature(&cpu->env, ARM_FEATURE_M);
632 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
633 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
634 cpu->midr = 0x410fc240; /* r0p0 */
635 cpu->pmsav7_dregion = 8;
636 cpu->isar.mvfr0 = 0x10110021;
637 cpu->isar.mvfr1 = 0x11000011;
638 cpu->isar.mvfr2 = 0x00000000;
639 cpu->isar.id_pfr0 = 0x00000030;
640 cpu->isar.id_pfr1 = 0x00000200;
641 cpu->isar.id_dfr0 = 0x00100000;
642 cpu->id_afr0 = 0x00000000;
643 cpu->isar.id_mmfr0 = 0x00000030;
644 cpu->isar.id_mmfr1 = 0x00000000;
645 cpu->isar.id_mmfr2 = 0x00000000;
646 cpu->isar.id_mmfr3 = 0x00000000;
647 cpu->isar.id_isar0 = 0x01141110;
648 cpu->isar.id_isar1 = 0x02111000;
649 cpu->isar.id_isar2 = 0x21112231;
650 cpu->isar.id_isar3 = 0x01111110;
651 cpu->isar.id_isar4 = 0x01310102;
652 cpu->isar.id_isar5 = 0x00000000;
653 cpu->isar.id_isar6 = 0x00000000;
654 }
655
656 static void cortex_m7_initfn(Object *obj)
657 {
658 ARMCPU *cpu = ARM_CPU(obj);
659
660 set_feature(&cpu->env, ARM_FEATURE_V7);
661 set_feature(&cpu->env, ARM_FEATURE_M);
662 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
663 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
664 cpu->midr = 0x411fc272; /* r1p2 */
665 cpu->pmsav7_dregion = 8;
666 cpu->isar.mvfr0 = 0x10110221;
667 cpu->isar.mvfr1 = 0x12000011;
668 cpu->isar.mvfr2 = 0x00000040;
669 cpu->isar.id_pfr0 = 0x00000030;
670 cpu->isar.id_pfr1 = 0x00000200;
671 cpu->isar.id_dfr0 = 0x00100000;
672 cpu->id_afr0 = 0x00000000;
673 cpu->isar.id_mmfr0 = 0x00100030;
674 cpu->isar.id_mmfr1 = 0x00000000;
675 cpu->isar.id_mmfr2 = 0x01000000;
676 cpu->isar.id_mmfr3 = 0x00000000;
677 cpu->isar.id_isar0 = 0x01101110;
678 cpu->isar.id_isar1 = 0x02112000;
679 cpu->isar.id_isar2 = 0x20232231;
680 cpu->isar.id_isar3 = 0x01111131;
681 cpu->isar.id_isar4 = 0x01310132;
682 cpu->isar.id_isar5 = 0x00000000;
683 cpu->isar.id_isar6 = 0x00000000;
684 }
685
686 static void cortex_m33_initfn(Object *obj)
687 {
688 ARMCPU *cpu = ARM_CPU(obj);
689
690 set_feature(&cpu->env, ARM_FEATURE_V8);
691 set_feature(&cpu->env, ARM_FEATURE_M);
692 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
693 set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
694 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
695 cpu->midr = 0x410fd213; /* r0p3 */
696 cpu->pmsav7_dregion = 16;
697 cpu->sau_sregion = 8;
698 cpu->isar.mvfr0 = 0x10110021;
699 cpu->isar.mvfr1 = 0x11000011;
700 cpu->isar.mvfr2 = 0x00000040;
701 cpu->isar.id_pfr0 = 0x00000030;
702 cpu->isar.id_pfr1 = 0x00000210;
703 cpu->isar.id_dfr0 = 0x00200000;
704 cpu->id_afr0 = 0x00000000;
705 cpu->isar.id_mmfr0 = 0x00101F40;
706 cpu->isar.id_mmfr1 = 0x00000000;
707 cpu->isar.id_mmfr2 = 0x01000000;
708 cpu->isar.id_mmfr3 = 0x00000000;
709 cpu->isar.id_isar0 = 0x01101110;
710 cpu->isar.id_isar1 = 0x02212000;
711 cpu->isar.id_isar2 = 0x20232232;
712 cpu->isar.id_isar3 = 0x01111131;
713 cpu->isar.id_isar4 = 0x01310132;
714 cpu->isar.id_isar5 = 0x00000000;
715 cpu->isar.id_isar6 = 0x00000000;
716 cpu->clidr = 0x00000000;
717 cpu->ctr = 0x8000c000;
718 }
719
720 static void cortex_m55_initfn(Object *obj)
721 {
722 ARMCPU *cpu = ARM_CPU(obj);
723
724 set_feature(&cpu->env, ARM_FEATURE_V8);
725 set_feature(&cpu->env, ARM_FEATURE_V8_1M);
726 set_feature(&cpu->env, ARM_FEATURE_M);
727 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
728 set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
729 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
730 cpu->midr = 0x410fd221; /* r0p1 */
731 cpu->revidr = 0;
732 cpu->pmsav7_dregion = 16;
733 cpu->sau_sregion = 8;
734 /* These are the MVFR* values for the FPU + full MVE configuration */
735 cpu->isar.mvfr0 = 0x10110221;
736 cpu->isar.mvfr1 = 0x12100211;
737 cpu->isar.mvfr2 = 0x00000040;
738 cpu->isar.id_pfr0 = 0x20000030;
739 cpu->isar.id_pfr1 = 0x00000230;
740 cpu->isar.id_dfr0 = 0x10200000;
741 cpu->id_afr0 = 0x00000000;
742 cpu->isar.id_mmfr0 = 0x00111040;
743 cpu->isar.id_mmfr1 = 0x00000000;
744 cpu->isar.id_mmfr2 = 0x01000000;
745 cpu->isar.id_mmfr3 = 0x00000011;
746 cpu->isar.id_isar0 = 0x01103110;
747 cpu->isar.id_isar1 = 0x02212000;
748 cpu->isar.id_isar2 = 0x20232232;
749 cpu->isar.id_isar3 = 0x01111131;
750 cpu->isar.id_isar4 = 0x01310132;
751 cpu->isar.id_isar5 = 0x00000000;
752 cpu->isar.id_isar6 = 0x00000000;
753 cpu->clidr = 0x00000000; /* caches not implemented */
754 cpu->ctr = 0x8303c003;
755 }
756
757 static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
758 /* Dummy the TCM region regs for the moment */
759 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
760 .access = PL1_RW, .type = ARM_CP_CONST },
761 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
762 .access = PL1_RW, .type = ARM_CP_CONST },
763 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
764 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
765 };
766
767 static void cortex_r5_initfn(Object *obj)
768 {
769 ARMCPU *cpu = ARM_CPU(obj);
770
771 set_feature(&cpu->env, ARM_FEATURE_V7);
772 set_feature(&cpu->env, ARM_FEATURE_V7MP);
773 set_feature(&cpu->env, ARM_FEATURE_PMSA);
774 set_feature(&cpu->env, ARM_FEATURE_PMU);
775 cpu->midr = 0x411fc153; /* r1p3 */
776 cpu->isar.id_pfr0 = 0x0131;
777 cpu->isar.id_pfr1 = 0x001;
778 cpu->isar.id_dfr0 = 0x010400;
779 cpu->id_afr0 = 0x0;
780 cpu->isar.id_mmfr0 = 0x0210030;
781 cpu->isar.id_mmfr1 = 0x00000000;
782 cpu->isar.id_mmfr2 = 0x01200000;
783 cpu->isar.id_mmfr3 = 0x0211;
784 cpu->isar.id_isar0 = 0x02101111;
785 cpu->isar.id_isar1 = 0x13112111;
786 cpu->isar.id_isar2 = 0x21232141;
787 cpu->isar.id_isar3 = 0x01112131;
788 cpu->isar.id_isar4 = 0x0010142;
789 cpu->isar.id_isar5 = 0x0;
790 cpu->isar.id_isar6 = 0x0;
791 cpu->mp_is_up = true;
792 cpu->pmsav7_dregion = 16;
793 cpu->isar.reset_pmcr_el0 = 0x41151800;
794 define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
795 }
796
797 static void cortex_r52_initfn(Object *obj)
798 {
799 ARMCPU *cpu = ARM_CPU(obj);
800
801 set_feature(&cpu->env, ARM_FEATURE_V8);
802 set_feature(&cpu->env, ARM_FEATURE_EL2);
803 set_feature(&cpu->env, ARM_FEATURE_PMSA);
804 set_feature(&cpu->env, ARM_FEATURE_NEON);
805 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
806 cpu->midr = 0x411fd133; /* r1p3 */
807 cpu->revidr = 0x00000000;
808 cpu->reset_fpsid = 0x41034023;
809 cpu->isar.mvfr0 = 0x10110222;
810 cpu->isar.mvfr1 = 0x12111111;
811 cpu->isar.mvfr2 = 0x00000043;
812 cpu->ctr = 0x8144c004;
813 cpu->reset_sctlr = 0x30c50838;
814 cpu->isar.id_pfr0 = 0x00000131;
815 cpu->isar.id_pfr1 = 0x10111001;
816 cpu->isar.id_dfr0 = 0x03010006;
817 cpu->id_afr0 = 0x00000000;
818 cpu->isar.id_mmfr0 = 0x00211040;
819 cpu->isar.id_mmfr1 = 0x40000000;
820 cpu->isar.id_mmfr2 = 0x01200000;
821 cpu->isar.id_mmfr3 = 0xf0102211;
822 cpu->isar.id_mmfr4 = 0x00000010;
823 cpu->isar.id_isar0 = 0x02101110;
824 cpu->isar.id_isar1 = 0x13112111;
825 cpu->isar.id_isar2 = 0x21232142;
826 cpu->isar.id_isar3 = 0x01112131;
827 cpu->isar.id_isar4 = 0x00010142;
828 cpu->isar.id_isar5 = 0x00010001;
829 cpu->isar.dbgdidr = 0x77168000;
830 cpu->clidr = (1 << 27) | (1 << 24) | 0x3;
831 cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
832 cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
833
834 cpu->pmsav7_dregion = 16;
835 cpu->pmsav8r_hdregion = 16;
836 }
837
838 static void cortex_r5f_initfn(Object *obj)
839 {
840 ARMCPU *cpu = ARM_CPU(obj);
841
842 cortex_r5_initfn(obj);
843 cpu->isar.mvfr0 = 0x10110221;
844 cpu->isar.mvfr1 = 0x00000011;
845 }
846
847 static void ti925t_initfn(Object *obj)
848 {
849 ARMCPU *cpu = ARM_CPU(obj);
850 set_feature(&cpu->env, ARM_FEATURE_V4T);
851 set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
852 cpu->midr = ARM_CPUID_TI925T;
853 cpu->ctr = 0x5109149;
854 cpu->reset_sctlr = 0x00000070;
855 }
856
857 static void sa1100_initfn(Object *obj)
858 {
859 ARMCPU *cpu = ARM_CPU(obj);
860
861 cpu->dtb_compatible = "intel,sa1100";
862 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
863 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
864 cpu->midr = 0x4401A11B;
865 cpu->reset_sctlr = 0x00000070;
866 }
867
868 static void sa1110_initfn(Object *obj)
869 {
870 ARMCPU *cpu = ARM_CPU(obj);
871 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
872 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
873 cpu->midr = 0x6901B119;
874 cpu->reset_sctlr = 0x00000070;
875 }
876
877 static void pxa250_initfn(Object *obj)
878 {
879 ARMCPU *cpu = ARM_CPU(obj);
880
881 cpu->dtb_compatible = "marvell,xscale";
882 set_feature(&cpu->env, ARM_FEATURE_V5);
883 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
884 cpu->midr = 0x69052100;
885 cpu->ctr = 0xd172172;
886 cpu->reset_sctlr = 0x00000078;
887 }
888
889 static void pxa255_initfn(Object *obj)
890 {
891 ARMCPU *cpu = ARM_CPU(obj);
892
893 cpu->dtb_compatible = "marvell,xscale";
894 set_feature(&cpu->env, ARM_FEATURE_V5);
895 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
896 cpu->midr = 0x69052d00;
897 cpu->ctr = 0xd172172;
898 cpu->reset_sctlr = 0x00000078;
899 }
900
901 static void pxa260_initfn(Object *obj)
902 {
903 ARMCPU *cpu = ARM_CPU(obj);
904
905 cpu->dtb_compatible = "marvell,xscale";
906 set_feature(&cpu->env, ARM_FEATURE_V5);
907 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
908 cpu->midr = 0x69052903;
909 cpu->ctr = 0xd172172;
910 cpu->reset_sctlr = 0x00000078;
911 }
912
913 static void pxa261_initfn(Object *obj)
914 {
915 ARMCPU *cpu = ARM_CPU(obj);
916
917 cpu->dtb_compatible = "marvell,xscale";
918 set_feature(&cpu->env, ARM_FEATURE_V5);
919 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
920 cpu->midr = 0x69052d05;
921 cpu->ctr = 0xd172172;
922 cpu->reset_sctlr = 0x00000078;
923 }
924
925 static void pxa262_initfn(Object *obj)
926 {
927 ARMCPU *cpu = ARM_CPU(obj);
928
929 cpu->dtb_compatible = "marvell,xscale";
930 set_feature(&cpu->env, ARM_FEATURE_V5);
931 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
932 cpu->midr = 0x69052d06;
933 cpu->ctr = 0xd172172;
934 cpu->reset_sctlr = 0x00000078;
935 }
936
937 static void pxa270a0_initfn(Object *obj)
938 {
939 ARMCPU *cpu = ARM_CPU(obj);
940
941 cpu->dtb_compatible = "marvell,xscale";
942 set_feature(&cpu->env, ARM_FEATURE_V5);
943 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
944 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
945 cpu->midr = 0x69054110;
946 cpu->ctr = 0xd172172;
947 cpu->reset_sctlr = 0x00000078;
948 }
949
950 static void pxa270a1_initfn(Object *obj)
951 {
952 ARMCPU *cpu = ARM_CPU(obj);
953
954 cpu->dtb_compatible = "marvell,xscale";
955 set_feature(&cpu->env, ARM_FEATURE_V5);
956 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
957 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
958 cpu->midr = 0x69054111;
959 cpu->ctr = 0xd172172;
960 cpu->reset_sctlr = 0x00000078;
961 }
962
963 static void pxa270b0_initfn(Object *obj)
964 {
965 ARMCPU *cpu = ARM_CPU(obj);
966
967 cpu->dtb_compatible = "marvell,xscale";
968 set_feature(&cpu->env, ARM_FEATURE_V5);
969 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
970 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
971 cpu->midr = 0x69054112;
972 cpu->ctr = 0xd172172;
973 cpu->reset_sctlr = 0x00000078;
974 }
975
976 static void pxa270b1_initfn(Object *obj)
977 {
978 ARMCPU *cpu = ARM_CPU(obj);
979
980 cpu->dtb_compatible = "marvell,xscale";
981 set_feature(&cpu->env, ARM_FEATURE_V5);
982 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
983 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
984 cpu->midr = 0x69054113;
985 cpu->ctr = 0xd172172;
986 cpu->reset_sctlr = 0x00000078;
987 }
988
989 static void pxa270c0_initfn(Object *obj)
990 {
991 ARMCPU *cpu = ARM_CPU(obj);
992
993 cpu->dtb_compatible = "marvell,xscale";
994 set_feature(&cpu->env, ARM_FEATURE_V5);
995 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
996 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
997 cpu->midr = 0x69054114;
998 cpu->ctr = 0xd172172;
999 cpu->reset_sctlr = 0x00000078;
1000 }
1001
1002 static void pxa270c5_initfn(Object *obj)
1003 {
1004 ARMCPU *cpu = ARM_CPU(obj);
1005
1006 cpu->dtb_compatible = "marvell,xscale";
1007 set_feature(&cpu->env, ARM_FEATURE_V5);
1008 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1009 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1010 cpu->midr = 0x69054117;
1011 cpu->ctr = 0xd172172;
1012 cpu->reset_sctlr = 0x00000078;
1013 }
1014
1015 static const struct TCGCPUOps arm_v7m_tcg_ops = {
1016 .initialize = arm_translate_init,
1017 .synchronize_from_tb = arm_cpu_synchronize_from_tb,
1018 .debug_excp_handler = arm_debug_excp_handler,
1019 .restore_state_to_opc = arm_restore_state_to_opc,
1020
1021 #ifdef CONFIG_USER_ONLY
1022 .record_sigsegv = arm_cpu_record_sigsegv,
1023 .record_sigbus = arm_cpu_record_sigbus,
1024 #else
1025 .tlb_fill = arm_cpu_tlb_fill,
1026 .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt,
1027 .do_interrupt = arm_v7m_cpu_do_interrupt,
1028 .do_transaction_failed = arm_cpu_do_transaction_failed,
1029 .do_unaligned_access = arm_cpu_do_unaligned_access,
1030 .adjust_watchpoint_address = arm_adjust_watchpoint_address,
1031 .debug_check_watchpoint = arm_debug_check_watchpoint,
1032 .debug_check_breakpoint = arm_debug_check_breakpoint,
1033 #endif /* !CONFIG_USER_ONLY */
1034 };
1035
1036 static void arm_v7m_class_init(ObjectClass *oc, void *data)
1037 {
1038 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1039 CPUClass *cc = CPU_CLASS(oc);
1040
1041 acc->info = data;
1042 cc->tcg_ops = &arm_v7m_tcg_ops;
1043 cc->gdb_core_xml_file = "arm-m-profile.xml";
1044 }
1045
1046 #ifndef TARGET_AARCH64
1047 /*
1048 * -cpu max: a CPU with as many features enabled as our emulation supports.
1049 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
1050 * this only needs to handle 32 bits, and need not care about KVM.
1051 */
1052 static void arm_max_initfn(Object *obj)
1053 {
1054 ARMCPU *cpu = ARM_CPU(obj);
1055
1056 /* aarch64_a57_initfn, advertising none of the aarch64 features */
1057 cpu->dtb_compatible = "arm,cortex-a57";
1058 set_feature(&cpu->env, ARM_FEATURE_V8);
1059 set_feature(&cpu->env, ARM_FEATURE_NEON);
1060 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
1061 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
1062 set_feature(&cpu->env, ARM_FEATURE_EL2);
1063 set_feature(&cpu->env, ARM_FEATURE_EL3);
1064 set_feature(&cpu->env, ARM_FEATURE_PMU);
1065 cpu->midr = 0x411fd070;
1066 cpu->revidr = 0x00000000;
1067 cpu->reset_fpsid = 0x41034070;
1068 cpu->isar.mvfr0 = 0x10110222;
1069 cpu->isar.mvfr1 = 0x12111111;
1070 cpu->isar.mvfr2 = 0x00000043;
1071 cpu->ctr = 0x8444c004;
1072 cpu->reset_sctlr = 0x00c50838;
1073 cpu->isar.id_pfr0 = 0x00000131;
1074 cpu->isar.id_pfr1 = 0x00011011;
1075 cpu->isar.id_dfr0 = 0x03010066;
1076 cpu->id_afr0 = 0x00000000;
1077 cpu->isar.id_mmfr0 = 0x10101105;
1078 cpu->isar.id_mmfr1 = 0x40000000;
1079 cpu->isar.id_mmfr2 = 0x01260000;
1080 cpu->isar.id_mmfr3 = 0x02102211;
1081 cpu->isar.id_isar0 = 0x02101110;
1082 cpu->isar.id_isar1 = 0x13112111;
1083 cpu->isar.id_isar2 = 0x21232042;
1084 cpu->isar.id_isar3 = 0x01112131;
1085 cpu->isar.id_isar4 = 0x00011142;
1086 cpu->isar.id_isar5 = 0x00011121;
1087 cpu->isar.id_isar6 = 0;
1088 cpu->isar.dbgdidr = 0x3516d000;
1089 cpu->isar.dbgdevid = 0x00110f13;
1090 cpu->isar.dbgdevid1 = 0x2;
1091 cpu->isar.reset_pmcr_el0 = 0x41013000;
1092 cpu->clidr = 0x0a200023;
1093 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
1094 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
1095 cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
1096 define_cortex_a72_a57_a53_cp_reginfo(cpu);
1097
1098 aa32_max_features(cpu);
1099
1100 #ifdef CONFIG_USER_ONLY
1101 /*
1102 * Break with true ARMv8 and add back old-style VFP short-vector support.
1103 * Only do this for user-mode, where -cpu max is the default, so that
1104 * older v6 and v7 programs are more likely to work without adjustment.
1105 */
1106 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
1107 #endif
1108 }
1109 #endif /* !TARGET_AARCH64 */
1110
1111 static const ARMCPUInfo arm_tcg_cpus[] = {
1112 { .name = "arm926", .initfn = arm926_initfn },
1113 { .name = "arm946", .initfn = arm946_initfn },
1114 { .name = "arm1026", .initfn = arm1026_initfn },
1115 /*
1116 * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1117 * older core than plain "arm1136". In particular this does not
1118 * have the v6K features.
1119 */
1120 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
1121 { .name = "arm1136", .initfn = arm1136_initfn },
1122 { .name = "arm1176", .initfn = arm1176_initfn },
1123 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1124 { .name = "cortex-a7", .initfn = cortex_a7_initfn },
1125 { .name = "cortex-a8", .initfn = cortex_a8_initfn },
1126 { .name = "cortex-a9", .initfn = cortex_a9_initfn },
1127 { .name = "cortex-a15", .initfn = cortex_a15_initfn },
1128 { .name = "cortex-m0", .initfn = cortex_m0_initfn,
1129 .class_init = arm_v7m_class_init },
1130 { .name = "cortex-m3", .initfn = cortex_m3_initfn,
1131 .class_init = arm_v7m_class_init },
1132 { .name = "cortex-m4", .initfn = cortex_m4_initfn,
1133 .class_init = arm_v7m_class_init },
1134 { .name = "cortex-m7", .initfn = cortex_m7_initfn,
1135 .class_init = arm_v7m_class_init },
1136 { .name = "cortex-m33", .initfn = cortex_m33_initfn,
1137 .class_init = arm_v7m_class_init },
1138 { .name = "cortex-m55", .initfn = cortex_m55_initfn,
1139 .class_init = arm_v7m_class_init },
1140 { .name = "cortex-r5", .initfn = cortex_r5_initfn },
1141 { .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
1142 { .name = "cortex-r52", .initfn = cortex_r52_initfn },
1143 { .name = "ti925t", .initfn = ti925t_initfn },
1144 { .name = "sa1100", .initfn = sa1100_initfn },
1145 { .name = "sa1110", .initfn = sa1110_initfn },
1146 { .name = "pxa250", .initfn = pxa250_initfn },
1147 { .name = "pxa255", .initfn = pxa255_initfn },
1148 { .name = "pxa260", .initfn = pxa260_initfn },
1149 { .name = "pxa261", .initfn = pxa261_initfn },
1150 { .name = "pxa262", .initfn = pxa262_initfn },
1151 /* "pxa270" is an alias for "pxa270-a0" */
1152 { .name = "pxa270", .initfn = pxa270a0_initfn },
1153 { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
1154 { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
1155 { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
1156 { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
1157 { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
1158 { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
1159 #ifndef TARGET_AARCH64
1160 { .name = "max", .initfn = arm_max_initfn },
1161 #endif
1162 #ifdef CONFIG_USER_ONLY
1163 { .name = "any", .initfn = arm_max_initfn },
1164 #endif
1165 };
1166
1167 static const TypeInfo idau_interface_type_info = {
1168 .name = TYPE_IDAU_INTERFACE,
1169 .parent = TYPE_INTERFACE,
1170 .class_size = sizeof(IDAUInterfaceClass),
1171 };
1172
1173 static void arm_tcg_cpu_register_types(void)
1174 {
1175 size_t i;
1176
1177 type_register_static(&idau_interface_type_info);
1178 for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) {
1179 arm_cpu_register(&arm_tcg_cpus[i]);
1180 }
1181 }
1182
1183 type_init(arm_tcg_cpu_register_types)
1184
1185 #endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */
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