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block: Mark bdrv_replace_child_noperm() GRAPH_WRLOCK
[qemu/kevin.git] / hw / usb / hcd-ehci.c
blob19b4534c20c10d78d5e3d1fdca7aefc168e9265a
1 /*
2 * QEMU USB EHCI Emulation
3 *
4 * Copyright(c) 2008 Emutex Ltd. (address@hidden)
5 * Copyright(c) 2011-2012 Red Hat, Inc.
6 *
7 * Red Hat Authors:
8 * Gerd Hoffmann <kraxel@redhat.com>
9 * Hans de Goede <hdegoede@redhat.com>
10 *
11 * EHCI project was started by Mark Burkley, with contributions by
12 * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf,
13 * Jan Kiszka and Vincent Palatin contributed bugfixes.
14 *
15 * This library is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU Lesser General Public
17 * License as published by the Free Software Foundation; either
18 * version 2.1 of the License, or (at your option) any later version.
19 *
20 * This library is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 * Lesser General Public License for more details.
24 *
25 * You should have received a copy of the GNU Lesser General Public License
26 * along with this program; if not, see <http://www.gnu.org/licenses/>.
27 */
28
29 #include "qemu/osdep.h"
30 #include "qapi/error.h"
31 #include "hw/irq.h"
32 #include "hw/usb/ehci-regs.h"
33 #include "hw/usb/hcd-ehci.h"
34 #include "migration/vmstate.h"
35 #include "trace.h"
36 #include "qemu/error-report.h"
37 #include "qemu/main-loop.h"
38 #include "sysemu/runstate.h"
39
40 #define FRAME_TIMER_FREQ 1000
41 #define FRAME_TIMER_NS (NANOSECONDS_PER_SECOND / FRAME_TIMER_FREQ)
42 #define UFRAME_TIMER_NS (FRAME_TIMER_NS / 8)
43
44 #define NB_MAXINTRATE 8 // Max rate at which controller issues ints
45 #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction
46 #define MAX_QH 100 // Max allowable queue heads in a chain
47 #define MIN_UFR_PER_TICK 24 /* Min frames to process when catching up */
48 #define PERIODIC_ACTIVE 512 /* Micro-frames */
49
50 /* Internal periodic / asynchronous schedule state machine states
51 */
52 typedef enum {
53 EST_INACTIVE = 1000,
54 EST_ACTIVE,
55 EST_EXECUTING,
56 EST_SLEEPING,
57 /* The following states are internal to the state machine function
58 */
59 EST_WAITLISTHEAD,
60 EST_FETCHENTRY,
61 EST_FETCHQH,
62 EST_FETCHITD,
63 EST_FETCHSITD,
64 EST_ADVANCEQUEUE,
65 EST_FETCHQTD,
66 EST_EXECUTE,
67 EST_WRITEBACK,
68 EST_HORIZONTALQH
69 } EHCI_STATES;
70
71 /* macros for accessing fields within next link pointer entry */
72 #define NLPTR_GET(x) ((x) & 0xffffffe0)
73 #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3)
74 #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid
75
76 /* link pointer types */
77 #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor
78 #define NLPTR_TYPE_QH 1 // queue head
79 #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor
80 #define NLPTR_TYPE_FSTN 3 // frame span traversal node
81
82 #define SET_LAST_RUN_CLOCK(s) \
83 (s)->last_run_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
84
85 /* nifty macros from Arnon's EHCI version */
86 #define get_field(data, field) \
87 (((data) & field##_MASK) >> field##_SH)
88
89 #define set_field(data, newval, field) do { \
90 uint32_t val = *data; \
91 val &= ~ field##_MASK; \
92 val |= ((newval) << field##_SH) & field##_MASK; \
93 *data = val; \
94 } while(0)
95
96 static const char *ehci_state_names[] = {
97 [EST_INACTIVE] = "INACTIVE",
98 [EST_ACTIVE] = "ACTIVE",
99 [EST_EXECUTING] = "EXECUTING",
100 [EST_SLEEPING] = "SLEEPING",
101 [EST_WAITLISTHEAD] = "WAITLISTHEAD",
102 [EST_FETCHENTRY] = "FETCH ENTRY",
103 [EST_FETCHQH] = "FETCH QH",
104 [EST_FETCHITD] = "FETCH ITD",
105 [EST_ADVANCEQUEUE] = "ADVANCEQUEUE",
106 [EST_FETCHQTD] = "FETCH QTD",
107 [EST_EXECUTE] = "EXECUTE",
108 [EST_WRITEBACK] = "WRITEBACK",
109 [EST_HORIZONTALQH] = "HORIZONTALQH",
110 };
111
112 static const char *ehci_mmio_names[] = {
113 [USBCMD] = "USBCMD",
114 [USBSTS] = "USBSTS",
115 [USBINTR] = "USBINTR",
116 [FRINDEX] = "FRINDEX",
117 [PERIODICLISTBASE] = "P-LIST BASE",
118 [ASYNCLISTADDR] = "A-LIST ADDR",
119 [CONFIGFLAG] = "CONFIGFLAG",
120 };
121
122 static int ehci_state_executing(EHCIQueue *q);
123 static int ehci_state_writeback(EHCIQueue *q);
124 static int ehci_state_advqueue(EHCIQueue *q);
125 static int ehci_fill_queue(EHCIPacket *p);
126 static void ehci_free_packet(EHCIPacket *p);
127
128 static const char *nr2str(const char **n, size_t len, uint32_t nr)
129 {
130 if (nr < len && n[nr] != NULL) {
131 return n[nr];
132 } else {
133 return "unknown";
134 }
135 }
136
137 static const char *state2str(uint32_t state)
138 {
139 return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state);
140 }
141
142 static const char *addr2str(hwaddr addr)
143 {
144 return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr);
145 }
146
147 static void ehci_trace_usbsts(uint32_t mask, int state)
148 {
149 /* interrupts */
150 if (mask & USBSTS_INT) {
151 trace_usb_ehci_usbsts("INT", state);
152 }
153 if (mask & USBSTS_ERRINT) {
154 trace_usb_ehci_usbsts("ERRINT", state);
155 }
156 if (mask & USBSTS_PCD) {
157 trace_usb_ehci_usbsts("PCD", state);
158 }
159 if (mask & USBSTS_FLR) {
160 trace_usb_ehci_usbsts("FLR", state);
161 }
162 if (mask & USBSTS_HSE) {
163 trace_usb_ehci_usbsts("HSE", state);
164 }
165 if (mask & USBSTS_IAA) {
166 trace_usb_ehci_usbsts("IAA", state);
167 }
168
169 /* status */
170 if (mask & USBSTS_HALT) {
171 trace_usb_ehci_usbsts("HALT", state);
172 }
173 if (mask & USBSTS_REC) {
174 trace_usb_ehci_usbsts("REC", state);
175 }
176 if (mask & USBSTS_PSS) {
177 trace_usb_ehci_usbsts("PSS", state);
178 }
179 if (mask & USBSTS_ASS) {
180 trace_usb_ehci_usbsts("ASS", state);
181 }
182 }
183
184 static inline void ehci_set_usbsts(EHCIState *s, int mask)
185 {
186 if ((s->usbsts & mask) == mask) {
187 return;
188 }
189 ehci_trace_usbsts(mask, 1);
190 s->usbsts |= mask;
191 }
192
193 static inline void ehci_clear_usbsts(EHCIState *s, int mask)
194 {
195 if ((s->usbsts & mask) == 0) {
196 return;
197 }
198 ehci_trace_usbsts(mask, 0);
199 s->usbsts &= ~mask;
200 }
201
202 /* update irq line */
203 static inline void ehci_update_irq(EHCIState *s)
204 {
205 int level = 0;
206
207 if ((s->usbsts & USBINTR_MASK) & s->usbintr) {
208 level = 1;
209 }
210
211 trace_usb_ehci_irq(level, s->frindex, s->usbsts, s->usbintr);
212 qemu_set_irq(s->irq, level);
213 }
214
215 /* flag interrupt condition */
216 static inline void ehci_raise_irq(EHCIState *s, int intr)
217 {
218 if (intr & (USBSTS_PCD | USBSTS_FLR | USBSTS_HSE)) {
219 s->usbsts |= intr;
220 ehci_update_irq(s);
221 } else {
222 s->usbsts_pending |= intr;
223 }
224 }
225
226 /*
227 * Commit pending interrupts (added via ehci_raise_irq),
228 * at the rate allowed by "Interrupt Threshold Control".
229 */
230 static inline void ehci_commit_irq(EHCIState *s)
231 {
232 uint32_t itc;
233
234 if (!s->usbsts_pending) {
235 return;
236 }
237 if (s->usbsts_frindex > s->frindex) {
238 return;
239 }
240
241 itc = (s->usbcmd >> 16) & 0xff;
242 s->usbsts |= s->usbsts_pending;
243 s->usbsts_pending = 0;
244 s->usbsts_frindex = s->frindex + itc;
245 ehci_update_irq(s);
246 }
247
248 static void ehci_update_halt(EHCIState *s)
249 {
250 if (s->usbcmd & USBCMD_RUNSTOP) {
251 ehci_clear_usbsts(s, USBSTS_HALT);
252 } else {
253 if (s->astate == EST_INACTIVE && s->pstate == EST_INACTIVE) {
254 ehci_set_usbsts(s, USBSTS_HALT);
255 }
256 }
257 }
258
259 static void ehci_set_state(EHCIState *s, int async, int state)
260 {
261 if (async) {
262 trace_usb_ehci_state("async", state2str(state));
263 s->astate = state;
264 if (s->astate == EST_INACTIVE) {
265 ehci_clear_usbsts(s, USBSTS_ASS);
266 ehci_update_halt(s);
267 } else {
268 ehci_set_usbsts(s, USBSTS_ASS);
269 }
270 } else {
271 trace_usb_ehci_state("periodic", state2str(state));
272 s->pstate = state;
273 if (s->pstate == EST_INACTIVE) {
274 ehci_clear_usbsts(s, USBSTS_PSS);
275 ehci_update_halt(s);
276 } else {
277 ehci_set_usbsts(s, USBSTS_PSS);
278 }
279 }
280 }
281
282 static int ehci_get_state(EHCIState *s, int async)
283 {
284 return async ? s->astate : s->pstate;
285 }
286
287 static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr)
288 {
289 if (async) {
290 s->a_fetch_addr = addr;
291 } else {
292 s->p_fetch_addr = addr;
293 }
294 }
295
296 static int ehci_get_fetch_addr(EHCIState *s, int async)
297 {
298 return async ? s->a_fetch_addr : s->p_fetch_addr;
299 }
300
301 static void ehci_trace_qh(EHCIQueue *q, hwaddr addr, EHCIqh *qh)
302 {
303 /* need three here due to argument count limits */
304 trace_usb_ehci_qh_ptrs(q, addr, qh->next,
305 qh->current_qtd, qh->next_qtd, qh->altnext_qtd);
306 trace_usb_ehci_qh_fields(addr,
307 get_field(qh->epchar, QH_EPCHAR_RL),
308 get_field(qh->epchar, QH_EPCHAR_MPLEN),
309 get_field(qh->epchar, QH_EPCHAR_EPS),
310 get_field(qh->epchar, QH_EPCHAR_EP),
311 get_field(qh->epchar, QH_EPCHAR_DEVADDR));
312 trace_usb_ehci_qh_bits(addr,
313 (bool)(qh->epchar & QH_EPCHAR_C),
314 (bool)(qh->epchar & QH_EPCHAR_H),
315 (bool)(qh->epchar & QH_EPCHAR_DTC),
316 (bool)(qh->epchar & QH_EPCHAR_I));
317 }
318
319 static void ehci_trace_qtd(EHCIQueue *q, hwaddr addr, EHCIqtd *qtd)
320 {
321 /* need three here due to argument count limits */
322 trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext);
323 trace_usb_ehci_qtd_fields(addr,
324 get_field(qtd->token, QTD_TOKEN_TBYTES),
325 get_field(qtd->token, QTD_TOKEN_CPAGE),
326 get_field(qtd->token, QTD_TOKEN_CERR),
327 get_field(qtd->token, QTD_TOKEN_PID));
328 trace_usb_ehci_qtd_bits(addr,
329 (bool)(qtd->token & QTD_TOKEN_IOC),
330 (bool)(qtd->token & QTD_TOKEN_ACTIVE),
331 (bool)(qtd->token & QTD_TOKEN_HALT),
332 (bool)(qtd->token & QTD_TOKEN_BABBLE),
333 (bool)(qtd->token & QTD_TOKEN_XACTERR));
334 }
335
336 static void ehci_trace_itd(EHCIState *s, hwaddr addr, EHCIitd *itd)
337 {
338 trace_usb_ehci_itd(addr, itd->next,
339 get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT),
340 get_field(itd->bufptr[2], ITD_BUFPTR_MULT),
341 get_field(itd->bufptr[0], ITD_BUFPTR_EP),
342 get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR));
343 }
344
345 static void ehci_trace_sitd(EHCIState *s, hwaddr addr,
346 EHCIsitd *sitd)
347 {
348 trace_usb_ehci_sitd(addr, sitd->next,
349 (bool)(sitd->results & SITD_RESULTS_ACTIVE));
350 }
351
352 static void ehci_trace_guest_bug(EHCIState *s, const char *message)
353 {
354 trace_usb_ehci_guest_bug(message);
355 }
356
357 static inline bool ehci_enabled(EHCIState *s)
358 {
359 return s->usbcmd & USBCMD_RUNSTOP;
360 }
361
362 static inline bool ehci_async_enabled(EHCIState *s)
363 {
364 return ehci_enabled(s) && (s->usbcmd & USBCMD_ASE);
365 }
366
367 static inline bool ehci_periodic_enabled(EHCIState *s)
368 {
369 return ehci_enabled(s) && (s->usbcmd & USBCMD_PSE);
370 }
371
372 /* Get an array of dwords from main memory */
373 static inline int get_dwords(EHCIState *ehci, uint32_t addr,
374 uint32_t *buf, int num)
375 {
376 int i;
377
378 if (!ehci->as) {
379 ehci_raise_irq(ehci, USBSTS_HSE);
380 ehci->usbcmd &= ~USBCMD_RUNSTOP;
381 trace_usb_ehci_dma_error();
382 return -1;
383 }
384
385 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
386 dma_memory_read(ehci->as, addr, buf, sizeof(*buf),
387 MEMTXATTRS_UNSPECIFIED);
388 *buf = le32_to_cpu(*buf);
389 }
390
391 return num;
392 }
393
394 /* Put an array of dwords in to main memory */
395 static inline int put_dwords(EHCIState *ehci, uint32_t addr,
396 uint32_t *buf, int num)
397 {
398 int i;
399
400 if (!ehci->as) {
401 ehci_raise_irq(ehci, USBSTS_HSE);
402 ehci->usbcmd &= ~USBCMD_RUNSTOP;
403 trace_usb_ehci_dma_error();
404 return -1;
405 }
406
407 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
408 uint32_t tmp = cpu_to_le32(*buf);
409 dma_memory_write(ehci->as, addr, &tmp, sizeof(tmp),
410 MEMTXATTRS_UNSPECIFIED);
411 }
412
413 return num;
414 }
415
416 static int ehci_get_pid(EHCIqtd *qtd)
417 {
418 switch (get_field(qtd->token, QTD_TOKEN_PID)) {
419 case 0:
420 return USB_TOKEN_OUT;
421 case 1:
422 return USB_TOKEN_IN;
423 case 2:
424 return USB_TOKEN_SETUP;
425 default:
426 fprintf(stderr, "bad token\n");
427 return 0;
428 }
429 }
430
431 static bool ehci_verify_qh(EHCIQueue *q, EHCIqh *qh)
432 {
433 uint32_t devaddr = get_field(qh->epchar, QH_EPCHAR_DEVADDR);
434 uint32_t endp = get_field(qh->epchar, QH_EPCHAR_EP);
435 if ((devaddr != get_field(q->qh.epchar, QH_EPCHAR_DEVADDR)) ||
436 (endp != get_field(q->qh.epchar, QH_EPCHAR_EP)) ||
437 (qh->current_qtd != q->qh.current_qtd) ||
438 (q->async && qh->next_qtd != q->qh.next_qtd) ||
439 (memcmp(&qh->altnext_qtd, &q->qh.altnext_qtd,
440 7 * sizeof(uint32_t)) != 0) ||
441 (q->dev != NULL && q->dev->addr != devaddr)) {
442 return false;
443 } else {
444 return true;
445 }
446 }
447
448 static bool ehci_verify_qtd(EHCIPacket *p, EHCIqtd *qtd)
449 {
450 if (p->qtdaddr != p->queue->qtdaddr ||
451 (p->queue->async && !NLPTR_TBIT(p->qtd.next) &&
452 (p->qtd.next != qtd->next)) ||
453 (!NLPTR_TBIT(p->qtd.altnext) && (p->qtd.altnext != qtd->altnext)) ||
454 p->qtd.token != qtd->token ||
455 p->qtd.bufptr[0] != qtd->bufptr[0]) {
456 return false;
457 } else {
458 return true;
459 }
460 }
461
462 static bool ehci_verify_pid(EHCIQueue *q, EHCIqtd *qtd)
463 {
464 int ep = get_field(q->qh.epchar, QH_EPCHAR_EP);
465 int pid = ehci_get_pid(qtd);
466
467 /* Note the pid changing is normal for ep 0 (the control ep) */
468 if (q->last_pid && ep != 0 && pid != q->last_pid) {
469 return false;
470 } else {
471 return true;
472 }
473 }
474
475 /* Finish executing and writeback a packet outside of the regular
476 fetchqh -> fetchqtd -> execute -> writeback cycle */
477 static void ehci_writeback_async_complete_packet(EHCIPacket *p)
478 {
479 EHCIQueue *q = p->queue;
480 EHCIqtd qtd;
481 EHCIqh qh;
482 int state;
483
484 /* Verify the qh + qtd, like we do when going through fetchqh & fetchqtd */
485 get_dwords(q->ehci, NLPTR_GET(q->qhaddr),
486 (uint32_t *) &qh, sizeof(EHCIqh) >> 2);
487 get_dwords(q->ehci, NLPTR_GET(q->qtdaddr),
488 (uint32_t *) &qtd, sizeof(EHCIqtd) >> 2);
489 if (!ehci_verify_qh(q, &qh) || !ehci_verify_qtd(p, &qtd)) {
490 p->async = EHCI_ASYNC_INITIALIZED;
491 ehci_free_packet(p);
492 return;
493 }
494
495 state = ehci_get_state(q->ehci, q->async);
496 ehci_state_executing(q);
497 ehci_state_writeback(q); /* Frees the packet! */
498 if (!(q->qh.token & QTD_TOKEN_HALT)) {
499 ehci_state_advqueue(q);
500 }
501 ehci_set_state(q->ehci, q->async, state);
502 }
503
504 /* packet management */
505
506 static EHCIPacket *ehci_alloc_packet(EHCIQueue *q)
507 {
508 EHCIPacket *p;
509
510 p = g_new0(EHCIPacket, 1);
511 p->queue = q;
512 usb_packet_init(&p->packet);
513 QTAILQ_INSERT_TAIL(&q->packets, p, next);
514 trace_usb_ehci_packet_action(p->queue, p, "alloc");
515 return p;
516 }
517
518 static void ehci_free_packet(EHCIPacket *p)
519 {
520 if (p->async == EHCI_ASYNC_FINISHED &&
521 !(p->queue->qh.token & QTD_TOKEN_HALT)) {
522 ehci_writeback_async_complete_packet(p);
523 return;
524 }
525 trace_usb_ehci_packet_action(p->queue, p, "free");
526 if (p->async == EHCI_ASYNC_INFLIGHT) {
527 usb_cancel_packet(&p->packet);
528 }
529 if (p->async == EHCI_ASYNC_FINISHED &&
530 p->packet.status == USB_RET_SUCCESS) {
531 fprintf(stderr,
532 "EHCI: Dropping completed packet from halted %s ep %02X\n",
533 (p->pid == USB_TOKEN_IN) ? "in" : "out",
534 get_field(p->queue->qh.epchar, QH_EPCHAR_EP));
535 }
536 if (p->async != EHCI_ASYNC_NONE) {
537 usb_packet_unmap(&p->packet, &p->sgl);
538 qemu_sglist_destroy(&p->sgl);
539 }
540 QTAILQ_REMOVE(&p->queue->packets, p, next);
541 usb_packet_cleanup(&p->packet);
542 g_free(p);
543 }
544
545 /* queue management */
546
547 static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, uint32_t addr, int async)
548 {
549 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
550 EHCIQueue *q;
551
552 q = g_malloc0(sizeof(*q));
553 q->ehci = ehci;
554 q->qhaddr = addr;
555 q->async = async;
556 QTAILQ_INIT(&q->packets);
557 QTAILQ_INSERT_HEAD(head, q, next);
558 trace_usb_ehci_queue_action(q, "alloc");
559 return q;
560 }
561
562 static void ehci_queue_stopped(EHCIQueue *q)
563 {
564 int endp = get_field(q->qh.epchar, QH_EPCHAR_EP);
565
566 if (!q->last_pid || !q->dev) {
567 return;
568 }
569
570 usb_device_ep_stopped(q->dev, usb_ep_get(q->dev, q->last_pid, endp));
571 }
572
573 static int ehci_cancel_queue(EHCIQueue *q)
574 {
575 EHCIPacket *p;
576 int packets = 0;
577
578 p = QTAILQ_FIRST(&q->packets);
579 if (p == NULL) {
580 goto leave;
581 }
582
583 trace_usb_ehci_queue_action(q, "cancel");
584 do {
585 ehci_free_packet(p);
586 packets++;
587 } while ((p = QTAILQ_FIRST(&q->packets)) != NULL);
588
589 leave:
590 ehci_queue_stopped(q);
591 return packets;
592 }
593
594 static int ehci_reset_queue(EHCIQueue *q)
595 {
596 int packets;
597
598 trace_usb_ehci_queue_action(q, "reset");
599 packets = ehci_cancel_queue(q);
600 q->dev = NULL;
601 q->qtdaddr = 0;
602 q->last_pid = 0;
603 return packets;
604 }
605
606 static void ehci_free_queue(EHCIQueue *q, const char *warn)
607 {
608 EHCIQueueHead *head = q->async ? &q->ehci->aqueues : &q->ehci->pqueues;
609 int cancelled;
610
611 trace_usb_ehci_queue_action(q, "free");
612 cancelled = ehci_cancel_queue(q);
613 if (warn && cancelled > 0) {
614 ehci_trace_guest_bug(q->ehci, warn);
615 }
616 QTAILQ_REMOVE(head, q, next);
617 g_free(q);
618 }
619
620 static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr,
621 int async)
622 {
623 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
624 EHCIQueue *q;
625
626 QTAILQ_FOREACH(q, head, next) {
627 if (addr == q->qhaddr) {
628 return q;
629 }
630 }
631 return NULL;
632 }
633
634 static void ehci_queues_rip_unused(EHCIState *ehci, int async)
635 {
636 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
637 const char *warn = async ? "guest unlinked busy QH" : NULL;
638 uint64_t maxage = FRAME_TIMER_NS * ehci->maxframes * 4;
639 EHCIQueue *q, *tmp;
640
641 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
642 if (q->seen) {
643 q->seen = 0;
644 q->ts = ehci->last_run_ns;
645 continue;
646 }
647 if (ehci->last_run_ns < q->ts + maxage) {
648 continue;
649 }
650 ehci_free_queue(q, warn);
651 }
652 }
653
654 static void ehci_queues_rip_unseen(EHCIState *ehci, int async)
655 {
656 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
657 EHCIQueue *q, *tmp;
658
659 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
660 if (!q->seen) {
661 ehci_free_queue(q, NULL);
662 }
663 }
664 }
665
666 static void ehci_queues_rip_device(EHCIState *ehci, USBDevice *dev, int async)
667 {
668 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
669 EHCIQueue *q, *tmp;
670
671 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
672 if (q->dev != dev) {
673 continue;
674 }
675 ehci_free_queue(q, NULL);
676 }
677 }
678
679 static void ehci_queues_rip_all(EHCIState *ehci, int async)
680 {
681 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
682 const char *warn = async ? "guest stopped busy async schedule" : NULL;
683 EHCIQueue *q, *tmp;
684
685 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
686 ehci_free_queue(q, warn);
687 }
688 }
689
690 /* Attach or detach a device on root hub */
691
692 static void ehci_attach(USBPort *port)
693 {
694 EHCIState *s = port->opaque;
695 uint32_t *portsc = &s->portsc[port->index];
696 const char *owner = (*portsc & PORTSC_POWNER) ? "comp" : "ehci";
697
698 trace_usb_ehci_port_attach(port->index, owner, port->dev->product_desc);
699
700 if (*portsc & PORTSC_POWNER) {
701 USBPort *companion = s->companion_ports[port->index];
702 companion->dev = port->dev;
703 companion->ops->attach(companion);
704 return;
705 }
706
707 *portsc |= PORTSC_CONNECT;
708 *portsc |= PORTSC_CSC;
709
710 ehci_raise_irq(s, USBSTS_PCD);
711 }
712
713 static void ehci_detach(USBPort *port)
714 {
715 EHCIState *s = port->opaque;
716 uint32_t *portsc = &s->portsc[port->index];
717 const char *owner = (*portsc & PORTSC_POWNER) ? "comp" : "ehci";
718
719 trace_usb_ehci_port_detach(port->index, owner);
720
721 if (*portsc & PORTSC_POWNER) {
722 USBPort *companion = s->companion_ports[port->index];
723 companion->ops->detach(companion);
724 companion->dev = NULL;
725 /*
726 * EHCI spec 4.2.2: "When a disconnect occurs... On the event,
727 * the port ownership is returned immediately to the EHCI controller."
728 */
729 *portsc &= ~PORTSC_POWNER;
730 return;
731 }
732
733 ehci_queues_rip_device(s, port->dev, 0);
734 ehci_queues_rip_device(s, port->dev, 1);
735
736 *portsc &= ~(PORTSC_CONNECT|PORTSC_PED|PORTSC_SUSPEND);
737 *portsc |= PORTSC_CSC;
738
739 ehci_raise_irq(s, USBSTS_PCD);
740 }
741
742 static void ehci_child_detach(USBPort *port, USBDevice *child)
743 {
744 EHCIState *s = port->opaque;
745 uint32_t portsc = s->portsc[port->index];
746
747 if (portsc & PORTSC_POWNER) {
748 USBPort *companion = s->companion_ports[port->index];
749 companion->ops->child_detach(companion, child);
750 return;
751 }
752
753 ehci_queues_rip_device(s, child, 0);
754 ehci_queues_rip_device(s, child, 1);
755 }
756
757 static void ehci_wakeup(USBPort *port)
758 {
759 EHCIState *s = port->opaque;
760 uint32_t *portsc = &s->portsc[port->index];
761
762 if (*portsc & PORTSC_POWNER) {
763 USBPort *companion = s->companion_ports[port->index];
764 if (companion->ops->wakeup) {
765 companion->ops->wakeup(companion);
766 }
767 return;
768 }
769
770 if (*portsc & PORTSC_SUSPEND) {
771 trace_usb_ehci_port_wakeup(port->index);
772 *portsc |= PORTSC_FPRES;
773 ehci_raise_irq(s, USBSTS_PCD);
774 }
775
776 qemu_bh_schedule(s->async_bh);
777 }
778
779 static void ehci_register_companion(USBBus *bus, USBPort *ports[],
780 uint32_t portcount, uint32_t firstport,
781 Error **errp)
782 {
783 EHCIState *s = container_of(bus, EHCIState, bus);
784 uint32_t i;
785
786 if (firstport + portcount > NB_PORTS) {
787 error_setg(errp, "firstport must be between 0 and %u",
788 NB_PORTS - portcount);
789 return;
790 }
791
792 for (i = 0; i < portcount; i++) {
793 if (s->companion_ports[firstport + i]) {
794 error_setg(errp, "firstport %u asks for ports %u-%u,"
795 " but port %u has a companion assigned already",
796 firstport, firstport, firstport + portcount - 1,
797 firstport + i);
798 return;
799 }
800 }
801
802 for (i = 0; i < portcount; i++) {
803 s->companion_ports[firstport + i] = ports[i];
804 s->ports[firstport + i].speedmask |=
805 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL;
806 /* Ensure devs attached before the initial reset go to the companion */
807 s->portsc[firstport + i] = PORTSC_POWNER;
808 }
809
810 s->companion_count++;
811 s->caps[0x05] = (s->companion_count << 4) | portcount;
812 }
813
814 static void ehci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep,
815 unsigned int stream)
816 {
817 EHCIState *s = container_of(bus, EHCIState, bus);
818 uint32_t portsc = s->portsc[ep->dev->port->index];
819
820 if (portsc & PORTSC_POWNER) {
821 return;
822 }
823
824 s->periodic_sched_active = PERIODIC_ACTIVE;
825 qemu_bh_schedule(s->async_bh);
826 }
827
828 static USBDevice *ehci_find_device(EHCIState *ehci, uint8_t addr)
829 {
830 USBDevice *dev;
831 USBPort *port;
832 int i;
833
834 for (i = 0; i < NB_PORTS; i++) {
835 port = &ehci->ports[i];
836 if (!(ehci->portsc[i] & PORTSC_PED)) {
837 DPRINTF("Port %d not enabled\n", i);
838 continue;
839 }
840 dev = usb_find_device(port, addr);
841 if (dev != NULL) {
842 return dev;
843 }
844 }
845 return NULL;
846 }
847
848 /* 4.1 host controller initialization */
849 void ehci_reset(void *opaque)
850 {
851 EHCIState *s = opaque;
852 int i;
853 USBDevice *devs[NB_PORTS];
854
855 trace_usb_ehci_reset();
856
857 /*
858 * Do the detach before touching portsc, so that it correctly gets send to
859 * us or to our companion based on PORTSC_POWNER before the reset.
860 */
861 for(i = 0; i < NB_PORTS; i++) {
862 devs[i] = s->ports[i].dev;
863 if (devs[i] && devs[i]->attached) {
864 usb_detach(&s->ports[i]);
865 }
866 }
867
868 memset(&s->opreg, 0x00, sizeof(s->opreg));
869 memset(&s->portsc, 0x00, sizeof(s->portsc));
870
871 s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH;
872 s->usbsts = USBSTS_HALT;
873 s->usbsts_pending = 0;
874 s->usbsts_frindex = 0;
875 ehci_update_irq(s);
876
877 s->astate = EST_INACTIVE;
878 s->pstate = EST_INACTIVE;
879
880 for(i = 0; i < NB_PORTS; i++) {
881 if (s->companion_ports[i]) {
882 s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER;
883 } else {
884 s->portsc[i] = PORTSC_PPOWER;
885 }
886 if (devs[i] && devs[i]->attached) {
887 usb_attach(&s->ports[i]);
888 usb_device_reset(devs[i]);
889 }
890 }
891 ehci_queues_rip_all(s, 0);
892 ehci_queues_rip_all(s, 1);
893 timer_del(s->frame_timer);
894 qemu_bh_cancel(s->async_bh);
895 }
896
897 static uint64_t ehci_caps_read(void *ptr, hwaddr addr,
898 unsigned size)
899 {
900 EHCIState *s = ptr;
901 return s->caps[addr];
902 }
903
904 static void ehci_caps_write(void *ptr, hwaddr addr,
905 uint64_t val, unsigned size)
906 {
907 }
908
909 static uint64_t ehci_opreg_read(void *ptr, hwaddr addr,
910 unsigned size)
911 {
912 EHCIState *s = ptr;
913 uint32_t val;
914
915 switch (addr) {
916 case FRINDEX:
917 /* Round down to mult of 8, else it can go backwards on migration */
918 val = s->frindex & ~7;
919 break;
920 default:
921 val = s->opreg[addr >> 2];
922 }
923
924 trace_usb_ehci_opreg_read(addr + s->opregbase, addr2str(addr), val);
925 return val;
926 }
927
928 static uint64_t ehci_port_read(void *ptr, hwaddr addr,
929 unsigned size)
930 {
931 EHCIState *s = ptr;
932 uint32_t val;
933
934 val = s->portsc[addr >> 2];
935 trace_usb_ehci_portsc_read(addr + s->portscbase, addr >> 2, val);
936 return val;
937 }
938
939 static void handle_port_owner_write(EHCIState *s, int port, uint32_t owner)
940 {
941 USBDevice *dev = s->ports[port].dev;
942 uint32_t *portsc = &s->portsc[port];
943 uint32_t orig;
944
945 if (s->companion_ports[port] == NULL)
946 return;
947
948 owner = owner & PORTSC_POWNER;
949 orig = *portsc & PORTSC_POWNER;
950
951 if (!(owner ^ orig)) {
952 return;
953 }
954
955 if (dev && dev->attached) {
956 usb_detach(&s->ports[port]);
957 }
958
959 *portsc &= ~PORTSC_POWNER;
960 *portsc |= owner;
961
962 if (dev && dev->attached) {
963 usb_attach(&s->ports[port]);
964 }
965 }
966
967 static void ehci_port_write(void *ptr, hwaddr addr,
968 uint64_t val, unsigned size)
969 {
970 EHCIState *s = ptr;
971 int port = addr >> 2;
972 uint32_t *portsc = &s->portsc[port];
973 uint32_t old = *portsc;
974 USBDevice *dev = s->ports[port].dev;
975
976 trace_usb_ehci_portsc_write(addr + s->portscbase, addr >> 2, val);
977
978 /* Clear rwc bits */
979 *portsc &= ~(val & PORTSC_RWC_MASK);
980 /* The guest may clear, but not set the PED bit */
981 *portsc &= val | ~PORTSC_PED;
982 /* POWNER is masked out by RO_MASK as it is RO when we've no companion */
983 handle_port_owner_write(s, port, val);
984 /* And finally apply RO_MASK */
985 val &= PORTSC_RO_MASK;
986
987 if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) {
988 trace_usb_ehci_port_reset(port, 1);
989 }
990
991 if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) {
992 trace_usb_ehci_port_reset(port, 0);
993 if (dev && dev->attached) {
994 usb_port_reset(&s->ports[port]);
995 *portsc &= ~PORTSC_CSC;
996 }
997
998 /*
999 * Table 2.16 Set the enable bit(and enable bit change) to indicate
1000 * to SW that this port has a high speed device attached
1001 */
1002 if (dev && dev->attached && (dev->speedmask & USB_SPEED_MASK_HIGH)) {
1003 val |= PORTSC_PED;
1004 }
1005 }
1006
1007 if ((val & PORTSC_SUSPEND) && !(*portsc & PORTSC_SUSPEND)) {
1008 trace_usb_ehci_port_suspend(port);
1009 }
1010 if (!(val & PORTSC_FPRES) && (*portsc & PORTSC_FPRES)) {
1011 trace_usb_ehci_port_resume(port);
1012 val &= ~PORTSC_SUSPEND;
1013 }
1014
1015 *portsc &= ~PORTSC_RO_MASK;
1016 *portsc |= val;
1017 trace_usb_ehci_portsc_change(addr + s->portscbase, addr >> 2, *portsc, old);
1018 }
1019
1020 static void ehci_opreg_write(void *ptr, hwaddr addr,
1021 uint64_t val, unsigned size)
1022 {
1023 EHCIState *s = ptr;
1024 uint32_t *mmio = s->opreg + (addr >> 2);
1025 uint32_t old = *mmio;
1026 int i;
1027
1028 trace_usb_ehci_opreg_write(addr + s->opregbase, addr2str(addr), val);
1029
1030 switch (addr) {
1031 case USBCMD:
1032 if (val & USBCMD_HCRESET) {
1033 ehci_reset(s);
1034 val = s->usbcmd;
1035 break;
1036 }
1037
1038 /* not supporting dynamic frame list size at the moment */
1039 if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) {
1040 fprintf(stderr, "attempt to set frame list size -- value %d\n",
1041 (int)val & USBCMD_FLS);
1042 val &= ~USBCMD_FLS;
1043 }
1044
1045 if (val & USBCMD_IAAD) {
1046 /*
1047 * Process IAAD immediately, otherwise the Linux IAAD watchdog may
1048 * trigger and re-use a qh without us seeing the unlink.
1049 */
1050 s->async_stepdown = 0;
1051 qemu_bh_schedule(s->async_bh);
1052 trace_usb_ehci_doorbell_ring();
1053 }
1054
1055 if (((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & val) !=
1056 ((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & s->usbcmd)) {
1057 if (s->pstate == EST_INACTIVE) {
1058 SET_LAST_RUN_CLOCK(s);
1059 }
1060 s->usbcmd = val; /* Set usbcmd for ehci_update_halt() */
1061 ehci_update_halt(s);
1062 s->async_stepdown = 0;
1063 qemu_bh_schedule(s->async_bh);
1064 }
1065 break;
1066
1067 case USBSTS:
1068 val &= USBSTS_RO_MASK; // bits 6 through 31 are RO
1069 ehci_clear_usbsts(s, val); // bits 0 through 5 are R/WC
1070 val = s->usbsts;
1071 ehci_update_irq(s);
1072 break;
1073
1074 case USBINTR:
1075 val &= USBINTR_MASK;
1076 if (ehci_enabled(s) && (USBSTS_FLR & val)) {
1077 qemu_bh_schedule(s->async_bh);
1078 }
1079 break;
1080
1081 case FRINDEX:
1082 val &= 0x00003fff; /* frindex is 14bits */
1083 s->usbsts_frindex = val;
1084 break;
1085
1086 case CONFIGFLAG:
1087 val &= 0x1;
1088 if (val) {
1089 for(i = 0; i < NB_PORTS; i++)
1090 handle_port_owner_write(s, i, 0);
1091 }
1092 break;
1093
1094 case PERIODICLISTBASE:
1095 if (ehci_periodic_enabled(s)) {
1096 fprintf(stderr,
1097 "ehci: PERIODIC list base register set while periodic schedule\n"
1098 " is enabled and HC is enabled\n");
1099 }
1100 break;
1101
1102 case ASYNCLISTADDR:
1103 if (ehci_async_enabled(s)) {
1104 fprintf(stderr,
1105 "ehci: ASYNC list address register set while async schedule\n"
1106 " is enabled and HC is enabled\n");
1107 }
1108 break;
1109 }
1110
1111 *mmio = val;
1112 trace_usb_ehci_opreg_change(addr + s->opregbase, addr2str(addr),
1113 *mmio, old);
1114 }
1115
1116 /*
1117 * Write the qh back to guest physical memory. This step isn't
1118 * in the EHCI spec but we need to do it since we don't share
1119 * physical memory with our guest VM.
1120 *
1121 * The first three dwords are read-only for the EHCI, so skip them
1122 * when writing back the qh.
1123 */
1124 static void ehci_flush_qh(EHCIQueue *q)
1125 {
1126 uint32_t *qh = (uint32_t *) &q->qh;
1127 uint32_t dwords = sizeof(EHCIqh) >> 2;
1128 uint32_t addr = NLPTR_GET(q->qhaddr);
1129
1130 put_dwords(q->ehci, addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3);
1131 }
1132
1133 // 4.10.2
1134
1135 static int ehci_qh_do_overlay(EHCIQueue *q)
1136 {
1137 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
1138 int i;
1139 int dtoggle;
1140 int ping;
1141 int eps;
1142 int reload;
1143
1144 assert(p != NULL);
1145 assert(p->qtdaddr == q->qtdaddr);
1146
1147 // remember values in fields to preserve in qh after overlay
1148
1149 dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE;
1150 ping = q->qh.token & QTD_TOKEN_PING;
1151
1152 q->qh.current_qtd = p->qtdaddr;
1153 q->qh.next_qtd = p->qtd.next;
1154 q->qh.altnext_qtd = p->qtd.altnext;
1155 q->qh.token = p->qtd.token;
1156
1157
1158 eps = get_field(q->qh.epchar, QH_EPCHAR_EPS);
1159 if (eps == EHCI_QH_EPS_HIGH) {
1160 q->qh.token &= ~QTD_TOKEN_PING;
1161 q->qh.token |= ping;
1162 }
1163
1164 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1165 set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
1166
1167 for (i = 0; i < 5; i++) {
1168 q->qh.bufptr[i] = p->qtd.bufptr[i];
1169 }
1170
1171 if (!(q->qh.epchar & QH_EPCHAR_DTC)) {
1172 // preserve QH DT bit
1173 q->qh.token &= ~QTD_TOKEN_DTOGGLE;
1174 q->qh.token |= dtoggle;
1175 }
1176
1177 q->qh.bufptr[1] &= ~BUFPTR_CPROGMASK_MASK;
1178 q->qh.bufptr[2] &= ~BUFPTR_FRAMETAG_MASK;
1179
1180 ehci_flush_qh(q);
1181
1182 return 0;
1183 }
1184
1185 static int ehci_init_transfer(EHCIPacket *p)
1186 {
1187 uint32_t cpage, offset, bytes, plen;
1188 dma_addr_t page;
1189
1190 cpage = get_field(p->qtd.token, QTD_TOKEN_CPAGE);
1191 bytes = get_field(p->qtd.token, QTD_TOKEN_TBYTES);
1192 offset = p->qtd.bufptr[0] & ~QTD_BUFPTR_MASK;
1193 qemu_sglist_init(&p->sgl, p->queue->ehci->device, 5, p->queue->ehci->as);
1194
1195 while (bytes > 0) {
1196 if (cpage > 4) {
1197 fprintf(stderr, "cpage out of range (%u)\n", cpage);
1198 qemu_sglist_destroy(&p->sgl);
1199 return -1;
1200 }
1201
1202 page = p->qtd.bufptr[cpage] & QTD_BUFPTR_MASK;
1203 page += offset;
1204 plen = bytes;
1205 if (plen > 4096 - offset) {
1206 plen = 4096 - offset;
1207 offset = 0;
1208 cpage++;
1209 }
1210
1211 qemu_sglist_add(&p->sgl, page, plen);
1212 bytes -= plen;
1213 }
1214 return 0;
1215 }
1216
1217 static void ehci_finish_transfer(EHCIQueue *q, int len)
1218 {
1219 uint32_t cpage, offset;
1220
1221 if (len > 0) {
1222 /* update cpage & offset */
1223 cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE);
1224 offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK;
1225
1226 offset += len;
1227 cpage += offset >> QTD_BUFPTR_SH;
1228 offset &= ~QTD_BUFPTR_MASK;
1229
1230 set_field(&q->qh.token, cpage, QTD_TOKEN_CPAGE);
1231 q->qh.bufptr[0] &= QTD_BUFPTR_MASK;
1232 q->qh.bufptr[0] |= offset;
1233 }
1234 }
1235
1236 static void ehci_async_complete_packet(USBPort *port, USBPacket *packet)
1237 {
1238 EHCIPacket *p;
1239 EHCIState *s = port->opaque;
1240 uint32_t portsc = s->portsc[port->index];
1241
1242 if (portsc & PORTSC_POWNER) {
1243 USBPort *companion = s->companion_ports[port->index];
1244 companion->ops->complete(companion, packet);
1245 return;
1246 }
1247
1248 p = container_of(packet, EHCIPacket, packet);
1249 assert(p->async == EHCI_ASYNC_INFLIGHT);
1250
1251 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) {
1252 trace_usb_ehci_packet_action(p->queue, p, "remove");
1253 ehci_free_packet(p);
1254 return;
1255 }
1256
1257 trace_usb_ehci_packet_action(p->queue, p, "wakeup");
1258 p->async = EHCI_ASYNC_FINISHED;
1259
1260 if (!p->queue->async) {
1261 s->periodic_sched_active = PERIODIC_ACTIVE;
1262 }
1263 qemu_bh_schedule(s->async_bh);
1264 }
1265
1266 static void ehci_execute_complete(EHCIQueue *q)
1267 {
1268 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
1269 uint32_t tbytes;
1270
1271 assert(p != NULL);
1272 assert(p->qtdaddr == q->qtdaddr);
1273 assert(p->async == EHCI_ASYNC_INITIALIZED ||
1274 p->async == EHCI_ASYNC_FINISHED);
1275
1276 DPRINTF("execute_complete: qhaddr 0x%x, next 0x%x, qtdaddr 0x%x, "
1277 "status %d, actual_length %d\n",
1278 q->qhaddr, q->qh.next, q->qtdaddr,
1279 p->packet.status, p->packet.actual_length);
1280
1281 switch (p->packet.status) {
1282 case USB_RET_SUCCESS:
1283 break;
1284 case USB_RET_IOERROR:
1285 case USB_RET_NODEV:
1286 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_XACTERR);
1287 set_field(&q->qh.token, 0, QTD_TOKEN_CERR);
1288 ehci_raise_irq(q->ehci, USBSTS_ERRINT);
1289 break;
1290 case USB_RET_STALL:
1291 q->qh.token |= QTD_TOKEN_HALT;
1292 ehci_raise_irq(q->ehci, USBSTS_ERRINT);
1293 break;
1294 case USB_RET_NAK:
1295 set_field(&q->qh.altnext_qtd, 0, QH_ALTNEXT_NAKCNT);
1296 return; /* We're not done yet with this transaction */
1297 case USB_RET_BABBLE:
1298 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE);
1299 ehci_raise_irq(q->ehci, USBSTS_ERRINT);
1300 break;
1301 default:
1302 /* should not be triggerable */
1303 fprintf(stderr, "USB invalid response %d\n", p->packet.status);
1304 g_assert_not_reached();
1305 }
1306
1307 /* TODO check 4.12 for splits */
1308 tbytes = get_field(q->qh.token, QTD_TOKEN_TBYTES);
1309 if (tbytes && p->pid == USB_TOKEN_IN) {
1310 tbytes -= p->packet.actual_length;
1311 if (tbytes) {
1312 /* 4.15.1.2 must raise int on a short input packet */
1313 ehci_raise_irq(q->ehci, USBSTS_INT);
1314 if (q->async) {
1315 q->ehci->int_req_by_async = true;
1316 }
1317 }
1318 } else {
1319 tbytes = 0;
1320 }
1321 DPRINTF("updating tbytes to %d\n", tbytes);
1322 set_field(&q->qh.token, tbytes, QTD_TOKEN_TBYTES);
1323
1324 ehci_finish_transfer(q, p->packet.actual_length);
1325 usb_packet_unmap(&p->packet, &p->sgl);
1326 qemu_sglist_destroy(&p->sgl);
1327 p->async = EHCI_ASYNC_NONE;
1328
1329 q->qh.token ^= QTD_TOKEN_DTOGGLE;
1330 q->qh.token &= ~QTD_TOKEN_ACTIVE;
1331
1332 if (q->qh.token & QTD_TOKEN_IOC) {
1333 ehci_raise_irq(q->ehci, USBSTS_INT);
1334 if (q->async) {
1335 q->ehci->int_req_by_async = true;
1336 }
1337 }
1338 }
1339
1340 /* 4.10.3 returns "again" */
1341 static int ehci_execute(EHCIPacket *p, const char *action)
1342 {
1343 USBEndpoint *ep;
1344 int endp;
1345 bool spd;
1346
1347 assert(p->async == EHCI_ASYNC_NONE ||
1348 p->async == EHCI_ASYNC_INITIALIZED);
1349
1350 if (!(p->qtd.token & QTD_TOKEN_ACTIVE)) {
1351 fprintf(stderr, "Attempting to execute inactive qtd\n");
1352 return -1;
1353 }
1354
1355 if (get_field(p->qtd.token, QTD_TOKEN_TBYTES) > BUFF_SIZE) {
1356 ehci_trace_guest_bug(p->queue->ehci,
1357 "guest requested more bytes than allowed");
1358 return -1;
1359 }
1360
1361 if (!ehci_verify_pid(p->queue, &p->qtd)) {
1362 ehci_queue_stopped(p->queue); /* Mark the ep in the prev dir stopped */
1363 }
1364 p->pid = ehci_get_pid(&p->qtd);
1365 p->queue->last_pid = p->pid;
1366 endp = get_field(p->queue->qh.epchar, QH_EPCHAR_EP);
1367 ep = usb_ep_get(p->queue->dev, p->pid, endp);
1368
1369 if (p->async == EHCI_ASYNC_NONE) {
1370 if (ehci_init_transfer(p) != 0) {
1371 return -1;
1372 }
1373
1374 spd = (p->pid == USB_TOKEN_IN && NLPTR_TBIT(p->qtd.altnext) == 0);
1375 usb_packet_setup(&p->packet, p->pid, ep, 0, p->qtdaddr, spd,
1376 (p->qtd.token & QTD_TOKEN_IOC) != 0);
1377 if (usb_packet_map(&p->packet, &p->sgl)) {
1378 qemu_sglist_destroy(&p->sgl);
1379 return -1;
1380 }
1381 p->async = EHCI_ASYNC_INITIALIZED;
1382 }
1383
1384 trace_usb_ehci_packet_action(p->queue, p, action);
1385 usb_handle_packet(p->queue->dev, &p->packet);
1386 DPRINTF("submit: qh 0x%x next 0x%x qtd 0x%x pid 0x%x len %zd endp 0x%x "
1387 "status %d actual_length %d\n", p->queue->qhaddr, p->qtd.next,
1388 p->qtdaddr, p->pid, p->packet.iov.size, endp, p->packet.status,
1389 p->packet.actual_length);
1390
1391 if (p->packet.actual_length > BUFF_SIZE) {
1392 fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n");
1393 return -1;
1394 }
1395
1396 return 1;
1397 }
1398
1399 /* 4.7.2
1400 */
1401
1402 static int ehci_process_itd(EHCIState *ehci,
1403 EHCIitd *itd,
1404 uint32_t addr)
1405 {
1406 USBDevice *dev;
1407 USBEndpoint *ep;
1408 uint32_t i, len, pid, dir, devaddr, endp;
1409 uint32_t pg, off, ptr1, ptr2, max, mult;
1410
1411 ehci->periodic_sched_active = PERIODIC_ACTIVE;
1412
1413 dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION);
1414 devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR);
1415 endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP);
1416 max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT);
1417 mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT);
1418
1419 for(i = 0; i < 8; i++) {
1420 if (itd->transact[i] & ITD_XACT_ACTIVE) {
1421 pg = get_field(itd->transact[i], ITD_XACT_PGSEL);
1422 off = itd->transact[i] & ITD_XACT_OFFSET_MASK;
1423 len = get_field(itd->transact[i], ITD_XACT_LENGTH);
1424
1425 if (len > max * mult) {
1426 len = max * mult;
1427 }
1428 if (len > BUFF_SIZE || pg > 6) {
1429 return -1;
1430 }
1431
1432 ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK);
1433 qemu_sglist_init(&ehci->isgl, ehci->device, 2, ehci->as);
1434 if (off + len > 4096) {
1435 /* transfer crosses page border */
1436 if (pg == 6) {
1437 qemu_sglist_destroy(&ehci->isgl);
1438 return -1; /* avoid page pg + 1 */
1439 }
1440 ptr2 = (itd->bufptr[pg + 1] & ITD_BUFPTR_MASK);
1441 uint32_t len2 = off + len - 4096;
1442 uint32_t len1 = len - len2;
1443 qemu_sglist_add(&ehci->isgl, ptr1 + off, len1);
1444 qemu_sglist_add(&ehci->isgl, ptr2, len2);
1445 } else {
1446 qemu_sglist_add(&ehci->isgl, ptr1 + off, len);
1447 }
1448
1449 dev = ehci_find_device(ehci, devaddr);
1450 if (dev == NULL) {
1451 ehci_trace_guest_bug(ehci, "no device found");
1452 ehci->ipacket.status = USB_RET_NODEV;
1453 ehci->ipacket.actual_length = 0;
1454 } else {
1455 pid = dir ? USB_TOKEN_IN : USB_TOKEN_OUT;
1456 ep = usb_ep_get(dev, pid, endp);
1457 if (ep && ep->type == USB_ENDPOINT_XFER_ISOC) {
1458 usb_packet_setup(&ehci->ipacket, pid, ep, 0, addr, false,
1459 (itd->transact[i] & ITD_XACT_IOC) != 0);
1460 if (usb_packet_map(&ehci->ipacket, &ehci->isgl)) {
1461 qemu_sglist_destroy(&ehci->isgl);
1462 return -1;
1463 }
1464 usb_handle_packet(dev, &ehci->ipacket);
1465 usb_packet_unmap(&ehci->ipacket, &ehci->isgl);
1466 } else {
1467 DPRINTF("ISOCH: attempt to address non-iso endpoint\n");
1468 ehci->ipacket.status = USB_RET_NAK;
1469 ehci->ipacket.actual_length = 0;
1470 }
1471 }
1472 qemu_sglist_destroy(&ehci->isgl);
1473
1474 switch (ehci->ipacket.status) {
1475 case USB_RET_SUCCESS:
1476 break;
1477 default:
1478 fprintf(stderr, "Unexpected iso usb result: %d\n",
1479 ehci->ipacket.status);
1480 /* Fall through */
1481 case USB_RET_IOERROR:
1482 case USB_RET_NODEV:
1483 /* 3.3.2: XACTERR is only allowed on IN transactions */
1484 if (dir) {
1485 itd->transact[i] |= ITD_XACT_XACTERR;
1486 ehci_raise_irq(ehci, USBSTS_ERRINT);
1487 }
1488 break;
1489 case USB_RET_BABBLE:
1490 itd->transact[i] |= ITD_XACT_BABBLE;
1491 ehci_raise_irq(ehci, USBSTS_ERRINT);
1492 break;
1493 case USB_RET_NAK:
1494 /* no data for us, so do a zero-length transfer */
1495 ehci->ipacket.actual_length = 0;
1496 break;
1497 }
1498 if (!dir) {
1499 set_field(&itd->transact[i], len - ehci->ipacket.actual_length,
1500 ITD_XACT_LENGTH); /* OUT */
1501 } else {
1502 set_field(&itd->transact[i], ehci->ipacket.actual_length,
1503 ITD_XACT_LENGTH); /* IN */
1504 }
1505 if (itd->transact[i] & ITD_XACT_IOC) {
1506 ehci_raise_irq(ehci, USBSTS_INT);
1507 }
1508 itd->transact[i] &= ~ITD_XACT_ACTIVE;
1509 }
1510 }
1511 return 0;
1512 }
1513
1514
1515 /* This state is the entry point for asynchronous schedule
1516 * processing. Entry here constitutes a EHCI start event state (4.8.5)
1517 */
1518 static int ehci_state_waitlisthead(EHCIState *ehci, int async)
1519 {
1520 EHCIqh qh;
1521 int i = 0;
1522 int again = 0;
1523 uint32_t entry = ehci->asynclistaddr;
1524
1525 /* set reclamation flag at start event (4.8.6) */
1526 if (async) {
1527 ehci_set_usbsts(ehci, USBSTS_REC);
1528 }
1529
1530 ehci_queues_rip_unused(ehci, async);
1531
1532 /* Find the head of the list (4.9.1.1) */
1533 for(i = 0; i < MAX_QH; i++) {
1534 if (get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &qh,
1535 sizeof(EHCIqh) >> 2) < 0) {
1536 return 0;
1537 }
1538 ehci_trace_qh(NULL, NLPTR_GET(entry), &qh);
1539
1540 if (qh.epchar & QH_EPCHAR_H) {
1541 if (async) {
1542 entry |= (NLPTR_TYPE_QH << 1);
1543 }
1544
1545 ehci_set_fetch_addr(ehci, async, entry);
1546 ehci_set_state(ehci, async, EST_FETCHENTRY);
1547 again = 1;
1548 goto out;
1549 }
1550
1551 entry = qh.next;
1552 if (entry == ehci->asynclistaddr) {
1553 break;
1554 }
1555 }
1556
1557 /* no head found for list. */
1558
1559 ehci_set_state(ehci, async, EST_ACTIVE);
1560
1561 out:
1562 return again;
1563 }
1564
1565
1566 /* This state is the entry point for periodic schedule processing as
1567 * well as being a continuation state for async processing.
1568 */
1569 static int ehci_state_fetchentry(EHCIState *ehci, int async)
1570 {
1571 int again = 0;
1572 uint32_t entry = ehci_get_fetch_addr(ehci, async);
1573
1574 if (NLPTR_TBIT(entry)) {
1575 ehci_set_state(ehci, async, EST_ACTIVE);
1576 goto out;
1577 }
1578
1579 /* section 4.8, only QH in async schedule */
1580 if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) {
1581 fprintf(stderr, "non queue head request in async schedule\n");
1582 return -1;
1583 }
1584
1585 switch (NLPTR_TYPE_GET(entry)) {
1586 case NLPTR_TYPE_QH:
1587 ehci_set_state(ehci, async, EST_FETCHQH);
1588 again = 1;
1589 break;
1590
1591 case NLPTR_TYPE_ITD:
1592 ehci_set_state(ehci, async, EST_FETCHITD);
1593 again = 1;
1594 break;
1595
1596 case NLPTR_TYPE_STITD:
1597 ehci_set_state(ehci, async, EST_FETCHSITD);
1598 again = 1;
1599 break;
1600
1601 default:
1602 /* TODO: handle FSTN type */
1603 fprintf(stderr, "FETCHENTRY: entry at %X is of type %u "
1604 "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry));
1605 return -1;
1606 }
1607
1608 out:
1609 return again;
1610 }
1611
1612 static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async)
1613 {
1614 uint32_t entry;
1615 EHCIQueue *q;
1616 EHCIqh qh;
1617
1618 entry = ehci_get_fetch_addr(ehci, async);
1619 q = ehci_find_queue_by_qh(ehci, entry, async);
1620 if (q == NULL) {
1621 q = ehci_alloc_queue(ehci, entry, async);
1622 }
1623
1624 q->seen++;
1625 if (q->seen > 1) {
1626 /* we are going in circles -- stop processing */
1627 ehci_set_state(ehci, async, EST_ACTIVE);
1628 q = NULL;
1629 goto out;
1630 }
1631
1632 if (get_dwords(ehci, NLPTR_GET(q->qhaddr),
1633 (uint32_t *) &qh, sizeof(EHCIqh) >> 2) < 0) {
1634 q = NULL;
1635 goto out;
1636 }
1637 ehci_trace_qh(q, NLPTR_GET(q->qhaddr), &qh);
1638
1639 /*
1640 * The overlay area of the qh should never be changed by the guest,
1641 * except when idle, in which case the reset is a nop.
1642 */
1643 if (!ehci_verify_qh(q, &qh)) {
1644 if (ehci_reset_queue(q) > 0) {
1645 ehci_trace_guest_bug(ehci, "guest updated active QH");
1646 }
1647 }
1648 q->qh = qh;
1649
1650 q->transact_ctr = get_field(q->qh.epcap, QH_EPCAP_MULT);
1651 if (q->transact_ctr == 0) { /* Guest bug in some versions of windows */
1652 q->transact_ctr = 4;
1653 }
1654
1655 if (q->dev == NULL) {
1656 q->dev = ehci_find_device(q->ehci,
1657 get_field(q->qh.epchar, QH_EPCHAR_DEVADDR));
1658 }
1659
1660 if (async && (q->qh.epchar & QH_EPCHAR_H)) {
1661
1662 /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */
1663 if (ehci->usbsts & USBSTS_REC) {
1664 ehci_clear_usbsts(ehci, USBSTS_REC);
1665 } else {
1666 DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset"
1667 " - done processing\n", q->qhaddr);
1668 ehci_set_state(ehci, async, EST_ACTIVE);
1669 q = NULL;
1670 goto out;
1671 }
1672 }
1673
1674 #if EHCI_DEBUG
1675 if (q->qhaddr != q->qh.next) {
1676 DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
1677 q->qhaddr,
1678 q->qh.epchar & QH_EPCHAR_H,
1679 q->qh.token & QTD_TOKEN_HALT,
1680 q->qh.token & QTD_TOKEN_ACTIVE,
1681 q->qh.next);
1682 }
1683 #endif
1684
1685 if (q->qh.token & QTD_TOKEN_HALT) {
1686 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1687
1688 } else if ((q->qh.token & QTD_TOKEN_ACTIVE) &&
1689 (NLPTR_TBIT(q->qh.current_qtd) == 0) &&
1690 (q->qh.current_qtd != 0)) {
1691 q->qtdaddr = q->qh.current_qtd;
1692 ehci_set_state(ehci, async, EST_FETCHQTD);
1693
1694 } else {
1695 /* EHCI spec version 1.0 Section 4.10.2 */
1696 ehci_set_state(ehci, async, EST_ADVANCEQUEUE);
1697 }
1698
1699 out:
1700 return q;
1701 }
1702
1703 static int ehci_state_fetchitd(EHCIState *ehci, int async)
1704 {
1705 uint32_t entry;
1706 EHCIitd itd;
1707
1708 assert(!async);
1709 entry = ehci_get_fetch_addr(ehci, async);
1710
1711 if (get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd,
1712 sizeof(EHCIitd) >> 2) < 0) {
1713 return -1;
1714 }
1715 ehci_trace_itd(ehci, entry, &itd);
1716
1717 if (ehci_process_itd(ehci, &itd, entry) != 0) {
1718 return -1;
1719 }
1720
1721 put_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd,
1722 sizeof(EHCIitd) >> 2);
1723 ehci_set_fetch_addr(ehci, async, itd.next);
1724 ehci_set_state(ehci, async, EST_FETCHENTRY);
1725
1726 return 1;
1727 }
1728
1729 static int ehci_state_fetchsitd(EHCIState *ehci, int async)
1730 {
1731 uint32_t entry;
1732 EHCIsitd sitd;
1733
1734 assert(!async);
1735 entry = ehci_get_fetch_addr(ehci, async);
1736
1737 if (get_dwords(ehci, NLPTR_GET(entry), (uint32_t *)&sitd,
1738 sizeof(EHCIsitd) >> 2) < 0) {
1739 return 0;
1740 }
1741 ehci_trace_sitd(ehci, entry, &sitd);
1742
1743 if (!(sitd.results & SITD_RESULTS_ACTIVE)) {
1744 /* siTD is not active, nothing to do */;
1745 } else {
1746 /* TODO: split transfers are not implemented */
1747 warn_report("Skipping active siTD");
1748 }
1749
1750 ehci_set_fetch_addr(ehci, async, sitd.next);
1751 ehci_set_state(ehci, async, EST_FETCHENTRY);
1752 return 1;
1753 }
1754
1755 /* Section 4.10.2 - paragraph 3 */
1756 static int ehci_state_advqueue(EHCIQueue *q)
1757 {
1758 #if 0
1759 /* TO-DO: 4.10.2 - paragraph 2
1760 * if I-bit is set to 1 and QH is not active
1761 * go to horizontal QH
1762 */
1763 if (I-bit set) {
1764 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1765 goto out;
1766 }
1767 #endif
1768
1769 /*
1770 * want data and alt-next qTD is valid
1771 */
1772 if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) &&
1773 (NLPTR_TBIT(q->qh.altnext_qtd) == 0)) {
1774 q->qtdaddr = q->qh.altnext_qtd;
1775 ehci_set_state(q->ehci, q->async, EST_FETCHQTD);
1776
1777 /*
1778 * next qTD is valid
1779 */
1780 } else if (NLPTR_TBIT(q->qh.next_qtd) == 0) {
1781 q->qtdaddr = q->qh.next_qtd;
1782 ehci_set_state(q->ehci, q->async, EST_FETCHQTD);
1783
1784 /*
1785 * no valid qTD, try next QH
1786 */
1787 } else {
1788 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1789 }
1790
1791 return 1;
1792 }
1793
1794 /* Section 4.10.2 - paragraph 4 */
1795 static int ehci_state_fetchqtd(EHCIQueue *q)
1796 {
1797 EHCIqtd qtd;
1798 EHCIPacket *p;
1799 int again = 1;
1800 uint32_t addr;
1801
1802 addr = NLPTR_GET(q->qtdaddr);
1803 if (get_dwords(q->ehci, addr + 8, &qtd.token, 1) < 0) {
1804 return 0;
1805 }
1806 barrier();
1807 if (get_dwords(q->ehci, addr + 0, &qtd.next, 1) < 0 ||
1808 get_dwords(q->ehci, addr + 4, &qtd.altnext, 1) < 0 ||
1809 get_dwords(q->ehci, addr + 12, qtd.bufptr,
1810 ARRAY_SIZE(qtd.bufptr)) < 0) {
1811 return 0;
1812 }
1813 ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), &qtd);
1814
1815 p = QTAILQ_FIRST(&q->packets);
1816 if (p != NULL) {
1817 if (!ehci_verify_qtd(p, &qtd)) {
1818 ehci_cancel_queue(q);
1819 if (qtd.token & QTD_TOKEN_ACTIVE) {
1820 ehci_trace_guest_bug(q->ehci, "guest updated active qTD");
1821 }
1822 p = NULL;
1823 } else {
1824 p->qtd = qtd;
1825 ehci_qh_do_overlay(q);
1826 }
1827 }
1828
1829 if (!(qtd.token & QTD_TOKEN_ACTIVE)) {
1830 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1831 } else if (p != NULL) {
1832 switch (p->async) {
1833 case EHCI_ASYNC_NONE:
1834 case EHCI_ASYNC_INITIALIZED:
1835 /* Not yet executed (MULT), or previously nacked (int) packet */
1836 ehci_set_state(q->ehci, q->async, EST_EXECUTE);
1837 break;
1838 case EHCI_ASYNC_INFLIGHT:
1839 /* Check if the guest has added new tds to the queue */
1840 again = ehci_fill_queue(QTAILQ_LAST(&q->packets));
1841 /* Unfinished async handled packet, go horizontal */
1842 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1843 break;
1844 case EHCI_ASYNC_FINISHED:
1845 /* Complete executing of the packet */
1846 ehci_set_state(q->ehci, q->async, EST_EXECUTING);
1847 break;
1848 }
1849 } else if (q->dev == NULL) {
1850 ehci_trace_guest_bug(q->ehci, "no device attached to queue");
1851 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1852 } else {
1853 p = ehci_alloc_packet(q);
1854 p->qtdaddr = q->qtdaddr;
1855 p->qtd = qtd;
1856 ehci_set_state(q->ehci, q->async, EST_EXECUTE);
1857 }
1858
1859 return again;
1860 }
1861
1862 static int ehci_state_horizqh(EHCIQueue *q)
1863 {
1864 int again = 0;
1865
1866 if (ehci_get_fetch_addr(q->ehci, q->async) != q->qh.next) {
1867 ehci_set_fetch_addr(q->ehci, q->async, q->qh.next);
1868 ehci_set_state(q->ehci, q->async, EST_FETCHENTRY);
1869 again = 1;
1870 } else {
1871 ehci_set_state(q->ehci, q->async, EST_ACTIVE);
1872 }
1873
1874 return again;
1875 }
1876
1877 /* Returns "again" */
1878 static int ehci_fill_queue(EHCIPacket *p)
1879 {
1880 USBEndpoint *ep = p->packet.ep;
1881 EHCIQueue *q = p->queue;
1882 EHCIqtd qtd = p->qtd;
1883 uint32_t qtdaddr;
1884
1885 for (;;) {
1886 if (NLPTR_TBIT(qtd.next) != 0) {
1887 break;
1888 }
1889 qtdaddr = qtd.next;
1890 /*
1891 * Detect circular td lists, Windows creates these, counting on the
1892 * active bit going low after execution to make the queue stop.
1893 */
1894 QTAILQ_FOREACH(p, &q->packets, next) {
1895 if (p->qtdaddr == qtdaddr) {
1896 goto leave;
1897 }
1898 }
1899 if (get_dwords(q->ehci, NLPTR_GET(qtdaddr),
1900 (uint32_t *) &qtd, sizeof(EHCIqtd) >> 2) < 0) {
1901 return -1;
1902 }
1903 ehci_trace_qtd(q, NLPTR_GET(qtdaddr), &qtd);
1904 if (!(qtd.token & QTD_TOKEN_ACTIVE)) {
1905 break;
1906 }
1907 if (!ehci_verify_pid(q, &qtd)) {
1908 ehci_trace_guest_bug(q->ehci, "guest queued token with wrong pid");
1909 break;
1910 }
1911 p = ehci_alloc_packet(q);
1912 p->qtdaddr = qtdaddr;
1913 p->qtd = qtd;
1914 if (ehci_execute(p, "queue") == -1) {
1915 return -1;
1916 }
1917 assert(p->packet.status == USB_RET_ASYNC);
1918 p->async = EHCI_ASYNC_INFLIGHT;
1919 }
1920 leave:
1921 usb_device_flush_ep_queue(ep->dev, ep);
1922 return 1;
1923 }
1924
1925 static int ehci_state_execute(EHCIQueue *q)
1926 {
1927 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
1928 int again = 0;
1929
1930 assert(p != NULL);
1931 assert(p->qtdaddr == q->qtdaddr);
1932
1933 if (ehci_qh_do_overlay(q) != 0) {
1934 return -1;
1935 }
1936
1937 // TODO verify enough time remains in the uframe as in 4.4.1.1
1938 // TODO write back ptr to async list when done or out of time
1939
1940 /* 4.10.3, bottom of page 82, go horizontal on transaction counter == 0 */
1941 if (!q->async && q->transact_ctr == 0) {
1942 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1943 again = 1;
1944 goto out;
1945 }
1946
1947 if (q->async) {
1948 ehci_set_usbsts(q->ehci, USBSTS_REC);
1949 }
1950
1951 again = ehci_execute(p, "process");
1952 if (again == -1) {
1953 goto out;
1954 }
1955 if (p->packet.status == USB_RET_ASYNC) {
1956 ehci_flush_qh(q);
1957 trace_usb_ehci_packet_action(p->queue, p, "async");
1958 p->async = EHCI_ASYNC_INFLIGHT;
1959 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1960 if (q->async) {
1961 again = ehci_fill_queue(p);
1962 } else {
1963 again = 1;
1964 }
1965 goto out;
1966 }
1967
1968 ehci_set_state(q->ehci, q->async, EST_EXECUTING);
1969 again = 1;
1970
1971 out:
1972 return again;
1973 }
1974
1975 static int ehci_state_executing(EHCIQueue *q)
1976 {
1977 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
1978
1979 assert(p != NULL);
1980 assert(p->qtdaddr == q->qtdaddr);
1981
1982 ehci_execute_complete(q);
1983
1984 /* 4.10.3 */
1985 if (!q->async && q->transact_ctr > 0) {
1986 q->transact_ctr--;
1987 }
1988
1989 /* 4.10.5 */
1990 if (p->packet.status == USB_RET_NAK) {
1991 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1992 } else {
1993 ehci_set_state(q->ehci, q->async, EST_WRITEBACK);
1994 }
1995
1996 ehci_flush_qh(q);
1997 return 1;
1998 }
1999
2000
2001 static int ehci_state_writeback(EHCIQueue *q)
2002 {
2003 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
2004 uint32_t *qtd, addr;
2005 int again = 0;
2006
2007 /* Write back the QTD from the QH area */
2008 assert(p != NULL);
2009 assert(p->qtdaddr == q->qtdaddr);
2010
2011 ehci_trace_qtd(q, NLPTR_GET(p->qtdaddr), (EHCIqtd *) &q->qh.next_qtd);
2012 qtd = (uint32_t *) &q->qh.next_qtd;
2013 addr = NLPTR_GET(p->qtdaddr);
2014 /* First write back the offset */
2015 put_dwords(q->ehci, addr + 3 * sizeof(uint32_t), qtd + 3, 1);
2016 /* Then write back the token, clearing the 'active' bit */
2017 put_dwords(q->ehci, addr + 2 * sizeof(uint32_t), qtd + 2, 1);
2018 ehci_free_packet(p);
2019
2020 /*
2021 * EHCI specs say go horizontal here.
2022 *
2023 * We can also advance the queue here for performance reasons. We
2024 * need to take care to only take that shortcut in case we've
2025 * processed the qtd just written back without errors, i.e. halt
2026 * bit is clear.
2027 */
2028 if (q->qh.token & QTD_TOKEN_HALT) {
2029 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
2030 again = 1;
2031 } else {
2032 ehci_set_state(q->ehci, q->async, EST_ADVANCEQUEUE);
2033 again = 1;
2034 }
2035 return again;
2036 }
2037
2038 /*
2039 * This is the state machine that is common to both async and periodic
2040 */
2041
2042 static void ehci_advance_state(EHCIState *ehci, int async)
2043 {
2044 EHCIQueue *q = NULL;
2045 int itd_count = 0;
2046 int again;
2047
2048 do {
2049 switch(ehci_get_state(ehci, async)) {
2050 case EST_WAITLISTHEAD:
2051 again = ehci_state_waitlisthead(ehci, async);
2052 break;
2053
2054 case EST_FETCHENTRY:
2055 again = ehci_state_fetchentry(ehci, async);
2056 break;
2057
2058 case EST_FETCHQH:
2059 q = ehci_state_fetchqh(ehci, async);
2060 if (q != NULL) {
2061 assert(q->async == async);
2062 again = 1;
2063 } else {
2064 again = 0;
2065 }
2066 break;
2067
2068 case EST_FETCHITD:
2069 again = ehci_state_fetchitd(ehci, async);
2070 itd_count++;
2071 break;
2072
2073 case EST_FETCHSITD:
2074 again = ehci_state_fetchsitd(ehci, async);
2075 itd_count++;
2076 break;
2077
2078 case EST_ADVANCEQUEUE:
2079 assert(q != NULL);
2080 again = ehci_state_advqueue(q);
2081 break;
2082
2083 case EST_FETCHQTD:
2084 assert(q != NULL);
2085 again = ehci_state_fetchqtd(q);
2086 break;
2087
2088 case EST_HORIZONTALQH:
2089 assert(q != NULL);
2090 again = ehci_state_horizqh(q);
2091 break;
2092
2093 case EST_EXECUTE:
2094 assert(q != NULL);
2095 again = ehci_state_execute(q);
2096 if (async) {
2097 ehci->async_stepdown = 0;
2098 }
2099 break;
2100
2101 case EST_EXECUTING:
2102 assert(q != NULL);
2103 if (async) {
2104 ehci->async_stepdown = 0;
2105 }
2106 again = ehci_state_executing(q);
2107 break;
2108
2109 case EST_WRITEBACK:
2110 assert(q != NULL);
2111 again = ehci_state_writeback(q);
2112 if (!async) {
2113 ehci->periodic_sched_active = PERIODIC_ACTIVE;
2114 }
2115 break;
2116
2117 default:
2118 fprintf(stderr, "Bad state!\n");
2119 g_assert_not_reached();
2120 }
2121
2122 if (again < 0 || itd_count > 16) {
2123 /* TODO: notify guest (raise HSE irq?) */
2124 fprintf(stderr, "processing error - resetting ehci HC\n");
2125 ehci_reset(ehci);
2126 again = 0;
2127 }
2128 }
2129 while (again);
2130 }
2131
2132 static void ehci_advance_async_state(EHCIState *ehci)
2133 {
2134 const int async = 1;
2135
2136 switch(ehci_get_state(ehci, async)) {
2137 case EST_INACTIVE:
2138 if (!ehci_async_enabled(ehci)) {
2139 break;
2140 }
2141 ehci_set_state(ehci, async, EST_ACTIVE);
2142 // No break, fall through to ACTIVE
2143
2144 case EST_ACTIVE:
2145 if (!ehci_async_enabled(ehci)) {
2146 ehci_queues_rip_all(ehci, async);
2147 ehci_set_state(ehci, async, EST_INACTIVE);
2148 break;
2149 }
2150
2151 /* make sure guest has acknowledged the doorbell interrupt */
2152 /* TO-DO: is this really needed? */
2153 if (ehci->usbsts & USBSTS_IAA) {
2154 DPRINTF("IAA status bit still set.\n");
2155 break;
2156 }
2157
2158 /* check that address register has been set */
2159 if (ehci->asynclistaddr == 0) {
2160 break;
2161 }
2162
2163 ehci_set_state(ehci, async, EST_WAITLISTHEAD);
2164 ehci_advance_state(ehci, async);
2165
2166 /* If the doorbell is set, the guest wants to make a change to the
2167 * schedule. The host controller needs to release cached data.
2168 * (section 4.8.2)
2169 */
2170 if (ehci->usbcmd & USBCMD_IAAD) {
2171 /* Remove all unseen qhs from the async qhs queue */
2172 ehci_queues_rip_unseen(ehci, async);
2173 trace_usb_ehci_doorbell_ack();
2174 ehci->usbcmd &= ~USBCMD_IAAD;
2175 ehci_raise_irq(ehci, USBSTS_IAA);
2176 }
2177 break;
2178
2179 default:
2180 /* this should only be due to a developer mistake */
2181 fprintf(stderr, "ehci: Bad asynchronous state %d. "
2182 "Resetting to active\n", ehci->astate);
2183 g_assert_not_reached();
2184 }
2185 }
2186
2187 static void ehci_advance_periodic_state(EHCIState *ehci)
2188 {
2189 uint32_t entry;
2190 uint32_t list;
2191 const int async = 0;
2192
2193 // 4.6
2194
2195 switch(ehci_get_state(ehci, async)) {
2196 case EST_INACTIVE:
2197 if (!(ehci->frindex & 7) && ehci_periodic_enabled(ehci)) {
2198 ehci_set_state(ehci, async, EST_ACTIVE);
2199 // No break, fall through to ACTIVE
2200 } else
2201 break;
2202
2203 case EST_ACTIVE:
2204 if (!(ehci->frindex & 7) && !ehci_periodic_enabled(ehci)) {
2205 ehci_queues_rip_all(ehci, async);
2206 ehci_set_state(ehci, async, EST_INACTIVE);
2207 break;
2208 }
2209
2210 list = ehci->periodiclistbase & 0xfffff000;
2211 /* check that register has been set */
2212 if (list == 0) {
2213 break;
2214 }
2215 list |= ((ehci->frindex & 0x1ff8) >> 1);
2216
2217 if (get_dwords(ehci, list, &entry, 1) < 0) {
2218 break;
2219 }
2220
2221 DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n",
2222 ehci->frindex / 8, list, entry);
2223 ehci_set_fetch_addr(ehci, async,entry);
2224 ehci_set_state(ehci, async, EST_FETCHENTRY);
2225 ehci_advance_state(ehci, async);
2226 ehci_queues_rip_unused(ehci, async);
2227 break;
2228
2229 default:
2230 /* this should only be due to a developer mistake */
2231 fprintf(stderr, "ehci: Bad periodic state %d. "
2232 "Resetting to active\n", ehci->pstate);
2233 g_assert_not_reached();
2234 }
2235 }
2236
2237 static void ehci_update_frindex(EHCIState *ehci, int uframes)
2238 {
2239 if (!ehci_enabled(ehci) && ehci->pstate == EST_INACTIVE) {
2240 return;
2241 }
2242
2243 /* Generate FLR interrupt if frame index rolls over 0x2000 */
2244 if ((ehci->frindex % 0x2000) + uframes >= 0x2000) {
2245 ehci_raise_irq(ehci, USBSTS_FLR);
2246 }
2247
2248 /* How many times will frindex roll over 0x4000 with this frame count?
2249 * usbsts_frindex is decremented by 0x4000 on rollover until it reaches 0
2250 */
2251 int rollovers = (ehci->frindex + uframes) / 0x4000;
2252 if (rollovers > 0) {
2253 if (ehci->usbsts_frindex >= (rollovers * 0x4000)) {
2254 ehci->usbsts_frindex -= 0x4000 * rollovers;
2255 } else {
2256 ehci->usbsts_frindex = 0;
2257 }
2258 }
2259
2260 ehci->frindex = (ehci->frindex + uframes) % 0x4000;
2261 }
2262
2263 static void ehci_work_bh(void *opaque)
2264 {
2265 EHCIState *ehci = opaque;
2266 int need_timer = 0;
2267 int64_t expire_time, t_now;
2268 uint64_t ns_elapsed;
2269 uint64_t uframes, skipped_uframes;
2270 int i;
2271
2272 if (ehci->working) {
2273 return;
2274 }
2275 ehci->working = true;
2276
2277 t_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
2278 ns_elapsed = t_now - ehci->last_run_ns;
2279 uframes = ns_elapsed / UFRAME_TIMER_NS;
2280
2281 if (ehci_periodic_enabled(ehci) || ehci->pstate != EST_INACTIVE) {
2282 need_timer++;
2283
2284 if (uframes > (ehci->maxframes * 8)) {
2285 skipped_uframes = uframes - (ehci->maxframes * 8);
2286 ehci_update_frindex(ehci, skipped_uframes);
2287 ehci->last_run_ns += UFRAME_TIMER_NS * skipped_uframes;
2288 uframes -= skipped_uframes;
2289 DPRINTF("WARNING - EHCI skipped %d uframes\n", skipped_uframes);
2290 }
2291
2292 for (i = 0; i < uframes; i++) {
2293 /*
2294 * If we're running behind schedule, we should not catch up
2295 * too fast, as that will make some guests unhappy:
2296 * 1) We must process a minimum of MIN_UFR_PER_TICK frames,
2297 * otherwise we will never catch up
2298 * 2) Process frames until the guest has requested an irq (IOC)
2299 */
2300 if (i >= MIN_UFR_PER_TICK) {
2301 ehci_commit_irq(ehci);
2302 if ((ehci->usbsts & USBINTR_MASK) & ehci->usbintr) {
2303 break;
2304 }
2305 }
2306 if (ehci->periodic_sched_active) {
2307 ehci->periodic_sched_active--;
2308 }
2309 ehci_update_frindex(ehci, 1);
2310 if ((ehci->frindex & 7) == 0) {
2311 ehci_advance_periodic_state(ehci);
2312 }
2313 ehci->last_run_ns += UFRAME_TIMER_NS;
2314 }
2315 } else {
2316 ehci->periodic_sched_active = 0;
2317 ehci_update_frindex(ehci, uframes);
2318 ehci->last_run_ns += UFRAME_TIMER_NS * uframes;
2319 }
2320
2321 if (ehci->periodic_sched_active) {
2322 ehci->async_stepdown = 0;
2323 } else if (ehci->async_stepdown < ehci->maxframes / 2) {
2324 ehci->async_stepdown++;
2325 }
2326
2327 /* Async is not inside loop since it executes everything it can once
2328 * called
2329 */
2330 if (ehci_async_enabled(ehci) || ehci->astate != EST_INACTIVE) {
2331 need_timer++;
2332 ehci_advance_async_state(ehci);
2333 }
2334
2335 ehci_commit_irq(ehci);
2336 if (ehci->usbsts_pending) {
2337 need_timer++;
2338 ehci->async_stepdown = 0;
2339 }
2340
2341 if (ehci_enabled(ehci) && (ehci->usbintr & USBSTS_FLR)) {
2342 need_timer++;
2343 }
2344
2345 if (need_timer) {
2346 /* If we've raised int, we speed up the timer, so that we quickly
2347 * notice any new packets queued up in response */
2348 if (ehci->int_req_by_async && (ehci->usbsts & USBSTS_INT)) {
2349 expire_time = t_now +
2350 NANOSECONDS_PER_SECOND / (FRAME_TIMER_FREQ * 4);
2351 ehci->int_req_by_async = false;
2352 } else {
2353 expire_time = t_now + (NANOSECONDS_PER_SECOND
2354 * (ehci->async_stepdown+1) / FRAME_TIMER_FREQ);
2355 }
2356 timer_mod(ehci->frame_timer, expire_time);
2357 }
2358
2359 ehci->working = false;
2360 }
2361
2362 static void ehci_work_timer(void *opaque)
2363 {
2364 EHCIState *ehci = opaque;
2365
2366 qemu_bh_schedule(ehci->async_bh);
2367 }
2368
2369 static const MemoryRegionOps ehci_mmio_caps_ops = {
2370 .read = ehci_caps_read,
2371 .write = ehci_caps_write,
2372 .valid.min_access_size = 1,
2373 .valid.max_access_size = 4,
2374 .impl.min_access_size = 1,
2375 .impl.max_access_size = 1,
2376 .endianness = DEVICE_LITTLE_ENDIAN,
2377 };
2378
2379 static const MemoryRegionOps ehci_mmio_opreg_ops = {
2380 .read = ehci_opreg_read,
2381 .write = ehci_opreg_write,
2382 .valid.min_access_size = 4,
2383 .valid.max_access_size = 4,
2384 .endianness = DEVICE_LITTLE_ENDIAN,
2385 };
2386
2387 static const MemoryRegionOps ehci_mmio_port_ops = {
2388 .read = ehci_port_read,
2389 .write = ehci_port_write,
2390 .valid.min_access_size = 4,
2391 .valid.max_access_size = 4,
2392 .endianness = DEVICE_LITTLE_ENDIAN,
2393 };
2394
2395 static USBPortOps ehci_port_ops = {
2396 .attach = ehci_attach,
2397 .detach = ehci_detach,
2398 .child_detach = ehci_child_detach,
2399 .wakeup = ehci_wakeup,
2400 .complete = ehci_async_complete_packet,
2401 };
2402
2403 static USBBusOps ehci_bus_ops_companion = {
2404 .register_companion = ehci_register_companion,
2405 .wakeup_endpoint = ehci_wakeup_endpoint,
2406 };
2407 static USBBusOps ehci_bus_ops_standalone = {
2408 .wakeup_endpoint = ehci_wakeup_endpoint,
2409 };
2410
2411 static int usb_ehci_pre_save(void *opaque)
2412 {
2413 EHCIState *ehci = opaque;
2414 uint32_t new_frindex;
2415
2416 /* Round down frindex to a multiple of 8 for migration compatibility */
2417 new_frindex = ehci->frindex & ~7;
2418 ehci->last_run_ns -= (ehci->frindex - new_frindex) * UFRAME_TIMER_NS;
2419 ehci->frindex = new_frindex;
2420
2421 return 0;
2422 }
2423
2424 static int usb_ehci_post_load(void *opaque, int version_id)
2425 {
2426 EHCIState *s = opaque;
2427 int i;
2428
2429 for (i = 0; i < NB_PORTS; i++) {
2430 USBPort *companion = s->companion_ports[i];
2431 if (companion == NULL) {
2432 continue;
2433 }
2434 if (s->portsc[i] & PORTSC_POWNER) {
2435 companion->dev = s->ports[i].dev;
2436 } else {
2437 companion->dev = NULL;
2438 }
2439 }
2440
2441 return 0;
2442 }
2443
2444 static void usb_ehci_vm_state_change(void *opaque, bool running, RunState state)
2445 {
2446 EHCIState *ehci = opaque;
2447
2448 /*
2449 * We don't migrate the EHCIQueue-s, instead we rebuild them for the
2450 * schedule in guest memory. We must do the rebuilt ASAP, so that
2451 * USB-devices which have async handled packages have a packet in the
2452 * ep queue to match the completion with.
2453 */
2454 if (state == RUN_STATE_RUNNING) {
2455 ehci_advance_async_state(ehci);
2456 }
2457
2458 /*
2459 * The schedule rebuilt from guest memory could cause the migration dest
2460 * to miss a QH unlink, and fail to cancel packets, since the unlinked QH
2461 * will never have existed on the destination. Therefore we must flush the
2462 * async schedule on savevm to catch any not yet noticed unlinks.
2463 */
2464 if (state == RUN_STATE_SAVE_VM) {
2465 ehci_advance_async_state(ehci);
2466 ehci_queues_rip_unseen(ehci, 1);
2467 }
2468 }
2469
2470 const VMStateDescription vmstate_ehci = {
2471 .name = "ehci-core",
2472 .version_id = 2,
2473 .minimum_version_id = 1,
2474 .pre_save = usb_ehci_pre_save,
2475 .post_load = usb_ehci_post_load,
2476 .fields = (VMStateField[]) {
2477 /* mmio registers */
2478 VMSTATE_UINT32(usbcmd, EHCIState),
2479 VMSTATE_UINT32(usbsts, EHCIState),
2480 VMSTATE_UINT32_V(usbsts_pending, EHCIState, 2),
2481 VMSTATE_UINT32_V(usbsts_frindex, EHCIState, 2),
2482 VMSTATE_UINT32(usbintr, EHCIState),
2483 VMSTATE_UINT32(frindex, EHCIState),
2484 VMSTATE_UINT32(ctrldssegment, EHCIState),
2485 VMSTATE_UINT32(periodiclistbase, EHCIState),
2486 VMSTATE_UINT32(asynclistaddr, EHCIState),
2487 VMSTATE_UINT32(configflag, EHCIState),
2488 VMSTATE_UINT32(portsc[0], EHCIState),
2489 VMSTATE_UINT32(portsc[1], EHCIState),
2490 VMSTATE_UINT32(portsc[2], EHCIState),
2491 VMSTATE_UINT32(portsc[3], EHCIState),
2492 VMSTATE_UINT32(portsc[4], EHCIState),
2493 VMSTATE_UINT32(portsc[5], EHCIState),
2494 /* frame timer */
2495 VMSTATE_TIMER_PTR(frame_timer, EHCIState),
2496 VMSTATE_UINT64(last_run_ns, EHCIState),
2497 VMSTATE_UINT32(async_stepdown, EHCIState),
2498 /* schedule state */
2499 VMSTATE_UINT32(astate, EHCIState),
2500 VMSTATE_UINT32(pstate, EHCIState),
2501 VMSTATE_UINT32(a_fetch_addr, EHCIState),
2502 VMSTATE_UINT32(p_fetch_addr, EHCIState),
2503 VMSTATE_END_OF_LIST()
2504 }
2505 };
2506
2507 void usb_ehci_realize(EHCIState *s, DeviceState *dev, Error **errp)
2508 {
2509 int i;
2510
2511 if (s->portnr > NB_PORTS) {
2512 error_setg(errp, "Too many ports! Max. port number is %d.",
2513 NB_PORTS);
2514 return;
2515 }
2516 if (s->maxframes < 8 || s->maxframes > 512) {
2517 error_setg(errp, "maxframes %d out if range (8 .. 512)",
2518 s->maxframes);
2519 return;
2520 }
2521
2522 memory_region_add_subregion(&s->mem, s->capsbase, &s->mem_caps);
2523 memory_region_add_subregion(&s->mem, s->opregbase, &s->mem_opreg);
2524 memory_region_add_subregion(&s->mem, s->opregbase + s->portscbase,
2525 &s->mem_ports);
2526
2527 usb_bus_new(&s->bus, sizeof(s->bus), s->companion_enable ?
2528 &ehci_bus_ops_companion : &ehci_bus_ops_standalone, dev);
2529 for (i = 0; i < s->portnr; i++) {
2530 usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops,
2531 USB_SPEED_MASK_HIGH);
2532 s->ports[i].dev = 0;
2533 }
2534
2535 s->frame_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, ehci_work_timer, s);
2536 s->async_bh = qemu_bh_new_guarded(ehci_work_bh, s,
2537 &dev->mem_reentrancy_guard);
2538 s->device = dev;
2539
2540 s->vmstate = qemu_add_vm_change_state_handler(usb_ehci_vm_state_change, s);
2541 }
2542
2543 void usb_ehci_unrealize(EHCIState *s, DeviceState *dev)
2544 {
2545 trace_usb_ehci_unrealize();
2546
2547 if (s->frame_timer) {
2548 timer_free(s->frame_timer);
2549 s->frame_timer = NULL;
2550 }
2551 if (s->async_bh) {
2552 qemu_bh_delete(s->async_bh);
2553 }
2554
2555 ehci_queues_rip_all(s, 0);
2556 ehci_queues_rip_all(s, 1);
2557
2558 memory_region_del_subregion(&s->mem, &s->mem_caps);
2559 memory_region_del_subregion(&s->mem, &s->mem_opreg);
2560 memory_region_del_subregion(&s->mem, &s->mem_ports);
2561
2562 usb_bus_release(&s->bus);
2563
2564 if (s->vmstate) {
2565 qemu_del_vm_change_state_handler(s->vmstate);
2566 }
2567 }
2568
2569 void usb_ehci_init(EHCIState *s, DeviceState *dev)
2570 {
2571 /* 2.2 host controller interface version */
2572 s->caps[0x00] = (uint8_t)(s->opregbase - s->capsbase);
2573 s->caps[0x01] = 0x00;
2574 s->caps[0x02] = 0x00;
2575 s->caps[0x03] = 0x01; /* HC version */
2576 s->caps[0x04] = s->portnr; /* Number of downstream ports */
2577 s->caps[0x05] = 0x00; /* No companion ports at present */
2578 s->caps[0x06] = 0x00;
2579 s->caps[0x07] = 0x00;
2580 s->caps[0x08] = 0x80; /* We can cache whole frame, no 64-bit */
2581 s->caps[0x0a] = 0x00;
2582 s->caps[0x0b] = 0x00;
2583
2584 QTAILQ_INIT(&s->aqueues);
2585 QTAILQ_INIT(&s->pqueues);
2586 usb_packet_init(&s->ipacket);
2587
2588 memory_region_init(&s->mem, OBJECT(dev), "ehci", MMIO_SIZE);
2589 memory_region_init_io(&s->mem_caps, OBJECT(dev), &ehci_mmio_caps_ops, s,
2590 "capabilities", CAPA_SIZE);
2591 memory_region_init_io(&s->mem_opreg, OBJECT(dev), &ehci_mmio_opreg_ops, s,
2592 "operational", s->portscbase);
2593 memory_region_init_io(&s->mem_ports, OBJECT(dev), &ehci_mmio_port_ops, s,
2594 "ports", 4 * s->portnr);
2595 }
2596
2597 void usb_ehci_finalize(EHCIState *s)
2598 {
2599 usb_packet_cleanup(&s->ipacket);
2600 }
2601
2602 /*
2603 * vim: expandtab ts=4
2604 */
Random patches