ppc/pnv: Drop pnv_is_power9() and pnv_is_power10() helpers
[qemu/kevin.git] / include / hw / ppc / ppc4xx.h
blob7d822590513d224034b6e8ee34b89f875c882cfc
1 /*
2 * QEMU PowerPC 4xx emulation shared definitions
4 * Copyright (c) 2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
25 #ifndef PPC4XX_H
26 #define PPC4XX_H
28 #include "hw/ppc/ppc.h"
29 #include "exec/memory.h"
31 /* PowerPC 4xx core initialization */
32 PowerPCCPU *ppc4xx_init(const char *cpu_model,
33 clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
34 uint32_t sysclk);
36 /* PowerPC 4xx universal interrupt controller */
37 enum {
38 PPCUIC_OUTPUT_INT = 0,
39 PPCUIC_OUTPUT_CINT = 1,
40 PPCUIC_OUTPUT_NB,
42 qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs,
43 uint32_t dcr_base, int has_ssr, int has_vr);
45 ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
46 MemoryRegion ram_memories[],
47 hwaddr ram_bases[],
48 hwaddr ram_sizes[],
49 const ram_addr_t sdram_bank_sizes[]);
51 void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
52 MemoryRegion ram_memories[],
53 hwaddr *ram_bases,
54 hwaddr *ram_sizes,
55 int do_init);
57 void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
58 qemu_irq irqs[4]);
60 #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
62 #endif /* PPC4XX_H */