2 * QEMU PowerPC XIVE interrupt controller model
4 * Copyright (c) 2017-2019, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #ifndef PPC_PNV_XIVE_H
11 #define PPC_PNV_XIVE_H
13 #include "hw/ppc/xive.h"
17 #define TYPE_PNV_XIVE "pnv-xive"
18 #define PNV_XIVE(obj) OBJECT_CHECK(PnvXive, (obj), TYPE_PNV_XIVE)
20 #define XIVE_BLOCK_MAX 16
22 #define XIVE_TABLE_BLK_MAX 16 /* Block Scope Table (0-15) */
23 #define XIVE_TABLE_MIG_MAX 16 /* Migration Register Table (1-15) */
24 #define XIVE_TABLE_VDT_MAX 16 /* VDT Domain Table (0-15) */
25 #define XIVE_TABLE_EDT_MAX 64 /* EDT Domain Table (0-63) */
27 typedef struct PnvXive
{
28 XiveRouter parent_obj
;
33 /* XSCOM addresses giving access to the controller registers */
34 MemoryRegion xscom_regs
;
36 /* Main MMIO regions that can be configured by FW */
38 MemoryRegion ic_reg_mmio
;
39 MemoryRegion ic_notify_mmio
;
40 MemoryRegion ic_lsi_mmio
;
41 MemoryRegion tm_indirect_mmio
;
47 * IPI and END address spaces modeling the EDT segmentation in the
51 MemoryRegion ipi_mmio
;
52 MemoryRegion ipi_edt_mmio
;
55 MemoryRegion end_mmio
;
56 MemoryRegion end_edt_mmio
;
58 /* Shortcut values for the Main MMIO regions */
68 /* Our XIVE source objects for IPIs and ENDs */
69 XiveSource ipi_source
;
70 XiveENDSource end_source
;
72 /* Interrupt controller registers */
76 * Virtual Structure Descriptor tables : EAT, SBE, ENDT, NVTT, IRQ
77 * These are in a SRAM protected by ECC.
79 uint64_t vsds
[5][XIVE_BLOCK_MAX
];
81 /* Translation tables */
82 uint64_t blk
[XIVE_TABLE_BLK_MAX
];
83 uint64_t mig
[XIVE_TABLE_MIG_MAX
];
84 uint64_t vdt
[XIVE_TABLE_VDT_MAX
];
85 uint64_t edt
[XIVE_TABLE_EDT_MAX
];
88 void pnv_xive_pic_print_info(PnvXive
*xive
, Monitor
*mon
);
90 #endif /* PPC_PNV_XIVE_H */