2 * ARM Nested Vectored Interrupt Controller
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
9 * The ARMv7M System controller is fairly tightly tied in with the
10 * NVIC. Much of that is also implemented here.
13 #include "qemu/osdep.h"
14 #include "qapi/error.h"
15 #include "qemu-common.h"
17 #include "hw/sysbus.h"
18 #include "qemu/timer.h"
19 #include "hw/arm/arm.h"
20 #include "hw/intc/armv7m_nvic.h"
21 #include "target/arm/cpu.h"
22 #include "exec/exec-all.h"
26 /* IRQ number counting:
28 * the num-irq property counts the number of external IRQ lines
30 * NVICState::num_irq counts the total number of exceptions
31 * (external IRQs, the 15 internal exceptions including reset,
32 * and one for the unused exception number 0).
34 * NVIC_MAX_IRQ is the highest permitted number of external IRQ lines.
36 * NVIC_MAX_VECTORS is the highest permitted number of exceptions.
38 * Iterating through all exceptions should typically be done with
39 * for (i = 1; i < s->num_irq; i++) to avoid the unused slot 0.
41 * The external qemu_irq lines are the NVIC's external IRQ lines,
42 * so line 0 is exception 16.
44 * In the terminology of the architecture manual, "interrupts" are
45 * a subcategory of exception referring to the external interrupts
46 * (which are exception numbers NVIC_FIRST_IRQ and upward).
47 * For historical reasons QEMU tends to use "interrupt" and
48 * "exception" more or less interchangeably.
50 #define NVIC_FIRST_IRQ 16
51 #define NVIC_MAX_IRQ (NVIC_MAX_VECTORS - NVIC_FIRST_IRQ)
53 /* Effective running priority of the CPU when no exception is active
54 * (higher than the highest possible priority value)
56 #define NVIC_NOEXC_PRIO 0x100
58 static const uint8_t nvic_id
[] = {
59 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
62 static int nvic_pending_prio(NVICState
*s
)
64 /* return the priority of the current pending interrupt,
65 * or NVIC_NOEXC_PRIO if no interrupt is pending
67 return s
->vectpending
? s
->vectors
[s
->vectpending
].prio
: NVIC_NOEXC_PRIO
;
70 /* Return the value of the ISCR RETTOBASE bit:
71 * 1 if there is exactly one active exception
72 * 0 if there is more than one active exception
73 * UNKNOWN if there are no active exceptions (we choose 1,
74 * which matches the choice Cortex-M3 is documented as making).
76 * NB: some versions of the documentation talk about this
77 * counting "active exceptions other than the one shown by IPSR";
78 * this is only different in the obscure corner case where guest
79 * code has manually deactivated an exception and is about
80 * to fail an exception-return integrity check. The definition
81 * above is the one from the v8M ARM ARM and is also in line
82 * with the behaviour documented for the Cortex-M3.
84 static bool nvic_rettobase(NVICState
*s
)
88 for (irq
= ARMV7M_EXCP_RESET
; irq
< s
->num_irq
; irq
++) {
89 if (s
->vectors
[irq
].active
) {
100 /* Return the value of the ISCR ISRPENDING bit:
101 * 1 if an external interrupt is pending
102 * 0 if no external interrupt is pending
104 static bool nvic_isrpending(NVICState
*s
)
108 /* We can shortcut if the highest priority pending interrupt
109 * happens to be external or if there is nothing pending.
111 if (s
->vectpending
> NVIC_FIRST_IRQ
) {
114 if (s
->vectpending
== 0) {
118 for (irq
= NVIC_FIRST_IRQ
; irq
< s
->num_irq
; irq
++) {
119 if (s
->vectors
[irq
].pending
) {
126 /* Return a mask word which clears the subpriority bits from
127 * a priority value for an M-profile exception, leaving only
128 * the group priority.
130 static inline uint32_t nvic_gprio_mask(NVICState
*s
)
132 return ~0U << (s
->prigroup
+ 1);
135 /* Recompute vectpending and exception_prio */
136 static void nvic_recompute_state(NVICState
*s
)
139 int pend_prio
= NVIC_NOEXC_PRIO
;
140 int active_prio
= NVIC_NOEXC_PRIO
;
143 for (i
= 1; i
< s
->num_irq
; i
++) {
144 VecInfo
*vec
= &s
->vectors
[i
];
146 if (vec
->enabled
&& vec
->pending
&& vec
->prio
< pend_prio
) {
147 pend_prio
= vec
->prio
;
150 if (vec
->active
&& vec
->prio
< active_prio
) {
151 active_prio
= vec
->prio
;
155 s
->vectpending
= pend_irq
;
156 s
->exception_prio
= active_prio
& nvic_gprio_mask(s
);
158 trace_nvic_recompute_state(s
->vectpending
, s
->exception_prio
);
161 /* Return the current execution priority of the CPU
162 * (equivalent to the pseudocode ExecutionPriority function).
163 * This is a value between -2 (NMI priority) and NVIC_NOEXC_PRIO.
165 static inline int nvic_exec_prio(NVICState
*s
)
167 CPUARMState
*env
= &s
->cpu
->env
;
170 if (env
->v7m
.faultmask
[env
->v7m
.secure
]) {
172 } else if (env
->v7m
.primask
[env
->v7m
.secure
]) {
174 } else if (env
->v7m
.basepri
[env
->v7m
.secure
] > 0) {
175 running
= env
->v7m
.basepri
[env
->v7m
.secure
] & nvic_gprio_mask(s
);
177 running
= NVIC_NOEXC_PRIO
; /* lower than any possible priority */
179 /* consider priority of active handler */
180 return MIN(running
, s
->exception_prio
);
183 bool armv7m_nvic_can_take_pending_exception(void *opaque
)
185 NVICState
*s
= opaque
;
187 return nvic_exec_prio(s
) > nvic_pending_prio(s
);
190 int armv7m_nvic_raw_execution_priority(void *opaque
)
192 NVICState
*s
= opaque
;
194 return s
->exception_prio
;
197 /* caller must call nvic_irq_update() after this */
198 static void set_prio(NVICState
*s
, unsigned irq
, uint8_t prio
)
200 assert(irq
> ARMV7M_EXCP_NMI
); /* only use for configurable prios */
201 assert(irq
< s
->num_irq
);
203 s
->vectors
[irq
].prio
= prio
;
205 trace_nvic_set_prio(irq
, prio
);
208 /* Recompute state and assert irq line accordingly.
209 * Must be called after changes to:
210 * vec->active, vec->enabled, vec->pending or vec->prio for any vector
213 static void nvic_irq_update(NVICState
*s
)
218 nvic_recompute_state(s
);
219 pend_prio
= nvic_pending_prio(s
);
221 /* Raise NVIC output if this IRQ would be taken, except that we
222 * ignore the effects of the BASEPRI, FAULTMASK and PRIMASK (which
223 * will be checked for in arm_v7m_cpu_exec_interrupt()); changes
224 * to those CPU registers don't cause us to recalculate the NVIC
227 lvl
= (pend_prio
< s
->exception_prio
);
228 trace_nvic_irq_update(s
->vectpending
, pend_prio
, s
->exception_prio
, lvl
);
229 qemu_set_irq(s
->excpout
, lvl
);
232 static void armv7m_nvic_clear_pending(void *opaque
, int irq
)
234 NVICState
*s
= (NVICState
*)opaque
;
237 assert(irq
> ARMV7M_EXCP_RESET
&& irq
< s
->num_irq
);
239 vec
= &s
->vectors
[irq
];
240 trace_nvic_clear_pending(irq
, vec
->enabled
, vec
->prio
);
247 void armv7m_nvic_set_pending(void *opaque
, int irq
)
249 NVICState
*s
= (NVICState
*)opaque
;
252 assert(irq
> ARMV7M_EXCP_RESET
&& irq
< s
->num_irq
);
254 vec
= &s
->vectors
[irq
];
255 trace_nvic_set_pending(irq
, vec
->enabled
, vec
->prio
);
258 if (irq
>= ARMV7M_EXCP_HARD
&& irq
< ARMV7M_EXCP_PENDSV
) {
259 /* If a synchronous exception is pending then it may be
260 * escalated to HardFault if:
261 * * it is equal or lower priority to current execution
263 * (ie we need to take it immediately but we can't do so).
264 * Asynchronous exceptions (and interrupts) simply remain pending.
266 * For QEMU, we don't have any imprecise (asynchronous) faults,
267 * so we can assume that PREFETCH_ABORT and DATA_ABORT are always
269 * Debug exceptions are awkward because only Debug exceptions
270 * resulting from the BKPT instruction should be escalated,
271 * but we don't currently implement any Debug exceptions other
272 * than those that result from BKPT, so we treat all debug exceptions
273 * as needing escalation.
275 * This all means we can identify whether to escalate based only on
276 * the exception number and don't (yet) need the caller to explicitly
277 * tell us whether this exception is synchronous or not.
279 int running
= nvic_exec_prio(s
);
280 bool escalate
= false;
282 if (vec
->prio
>= running
) {
283 trace_nvic_escalate_prio(irq
, vec
->prio
, running
);
285 } else if (!vec
->enabled
) {
286 trace_nvic_escalate_disabled(irq
);
292 /* We want to escalate to HardFault but we can't take a
293 * synchronous HardFault at this point either. This is a
294 * Lockup condition due to a guest bug. We don't model
295 * Lockup, so report via cpu_abort() instead.
297 cpu_abort(&s
->cpu
->parent_obj
,
298 "Lockup: can't escalate %d to HardFault "
299 "(current priority %d)\n", irq
, running
);
302 /* We can do the escalation, so we take HardFault instead */
303 irq
= ARMV7M_EXCP_HARD
;
304 vec
= &s
->vectors
[irq
];
305 s
->cpu
->env
.v7m
.hfsr
|= R_V7M_HFSR_FORCED_MASK
;
315 /* Make pending IRQ active. */
316 void armv7m_nvic_acknowledge_irq(void *opaque
)
318 NVICState
*s
= (NVICState
*)opaque
;
319 CPUARMState
*env
= &s
->cpu
->env
;
320 const int pending
= s
->vectpending
;
321 const int running
= nvic_exec_prio(s
);
325 assert(pending
> ARMV7M_EXCP_RESET
&& pending
< s
->num_irq
);
327 vec
= &s
->vectors
[pending
];
329 assert(vec
->enabled
);
330 assert(vec
->pending
);
332 pendgroupprio
= vec
->prio
& nvic_gprio_mask(s
);
333 assert(pendgroupprio
< running
);
335 trace_nvic_acknowledge_irq(pending
, vec
->prio
);
340 env
->v7m
.exception
= s
->vectpending
;
345 int armv7m_nvic_complete_irq(void *opaque
, int irq
)
347 NVICState
*s
= (NVICState
*)opaque
;
351 assert(irq
> ARMV7M_EXCP_RESET
&& irq
< s
->num_irq
);
353 vec
= &s
->vectors
[irq
];
355 trace_nvic_complete_irq(irq
);
358 /* Tell the caller this was an illegal exception return */
362 ret
= nvic_rettobase(s
);
366 /* Re-pend the exception if it's still held high; only
367 * happens for extenal IRQs
369 assert(irq
>= NVIC_FIRST_IRQ
);
378 /* callback when external interrupt line is changed */
379 static void set_irq_level(void *opaque
, int n
, int level
)
381 NVICState
*s
= opaque
;
386 assert(n
>= NVIC_FIRST_IRQ
&& n
< s
->num_irq
);
388 trace_nvic_set_irq_level(n
, level
);
390 /* The pending status of an external interrupt is
391 * latched on rising edge and exception handler return.
393 * Pulsing the IRQ will always run the handler
394 * once, and the handler will re-run until the
395 * level is low when the handler completes.
397 vec
= &s
->vectors
[n
];
398 if (level
!= vec
->level
) {
401 armv7m_nvic_set_pending(s
, n
);
406 static uint32_t nvic_readl(NVICState
*s
, uint32_t offset
, MemTxAttrs attrs
)
408 ARMCPU
*cpu
= s
->cpu
;
412 case 4: /* Interrupt Control Type. */
413 return ((s
->num_irq
- NVIC_FIRST_IRQ
) / 32) - 1;
414 case 0xd00: /* CPUID Base. */
416 case 0xd04: /* Interrupt Control State. */
418 val
= cpu
->env
.v7m
.exception
;
420 val
|= (s
->vectpending
& 0xff) << 12;
421 /* ISRPENDING - set if any external IRQ is pending */
422 if (nvic_isrpending(s
)) {
425 /* RETTOBASE - set if only one handler is active */
426 if (nvic_rettobase(s
)) {
430 if (s
->vectors
[ARMV7M_EXCP_SYSTICK
].pending
) {
434 if (s
->vectors
[ARMV7M_EXCP_PENDSV
].pending
) {
438 if (s
->vectors
[ARMV7M_EXCP_NMI
].pending
) {
441 /* ISRPREEMPT not implemented */
443 case 0xd08: /* Vector Table Offset. */
444 return cpu
->env
.v7m
.vecbase
[attrs
.secure
];
445 case 0xd0c: /* Application Interrupt/Reset Control. */
446 return 0xfa050000 | (s
->prigroup
<< 8);
447 case 0xd10: /* System Control. */
448 /* TODO: Implement SLEEPONEXIT. */
450 case 0xd14: /* Configuration Control. */
451 /* The BFHFNMIGN bit is the only non-banked bit; we
452 * keep it in the non-secure copy of the register.
454 val
= cpu
->env
.v7m
.ccr
[attrs
.secure
];
455 val
|= cpu
->env
.v7m
.ccr
[M_REG_NS
] & R_V7M_CCR_BFHFNMIGN_MASK
;
457 case 0xd24: /* System Handler Status. */
459 if (s
->vectors
[ARMV7M_EXCP_MEM
].active
) {
462 if (s
->vectors
[ARMV7M_EXCP_BUS
].active
) {
465 if (s
->vectors
[ARMV7M_EXCP_USAGE
].active
) {
468 if (s
->vectors
[ARMV7M_EXCP_SVC
].active
) {
471 if (s
->vectors
[ARMV7M_EXCP_DEBUG
].active
) {
474 if (s
->vectors
[ARMV7M_EXCP_PENDSV
].active
) {
477 if (s
->vectors
[ARMV7M_EXCP_SYSTICK
].active
) {
480 if (s
->vectors
[ARMV7M_EXCP_USAGE
].pending
) {
483 if (s
->vectors
[ARMV7M_EXCP_MEM
].pending
) {
486 if (s
->vectors
[ARMV7M_EXCP_BUS
].pending
) {
489 if (s
->vectors
[ARMV7M_EXCP_SVC
].pending
) {
492 if (s
->vectors
[ARMV7M_EXCP_MEM
].enabled
) {
495 if (s
->vectors
[ARMV7M_EXCP_BUS
].enabled
) {
498 if (s
->vectors
[ARMV7M_EXCP_USAGE
].enabled
) {
502 case 0xd28: /* Configurable Fault Status. */
503 /* The BFSR bits [15:8] are shared between security states
504 * and we store them in the NS copy
506 val
= cpu
->env
.v7m
.cfsr
[attrs
.secure
];
507 val
|= cpu
->env
.v7m
.cfsr
[M_REG_NS
] & R_V7M_CFSR_BFSR_MASK
;
509 case 0xd2c: /* Hard Fault Status. */
510 return cpu
->env
.v7m
.hfsr
;
511 case 0xd30: /* Debug Fault Status. */
512 return cpu
->env
.v7m
.dfsr
;
513 case 0xd34: /* MMFAR MemManage Fault Address */
514 return cpu
->env
.v7m
.mmfar
[attrs
.secure
];
515 case 0xd38: /* Bus Fault Address. */
516 return cpu
->env
.v7m
.bfar
;
517 case 0xd3c: /* Aux Fault Status. */
518 /* TODO: Implement fault status registers. */
519 qemu_log_mask(LOG_UNIMP
,
520 "Aux Fault status registers unimplemented\n");
522 case 0xd40: /* PFR0. */
524 case 0xd44: /* PRF1. */
526 case 0xd48: /* DFR0. */
528 case 0xd4c: /* AFR0. */
530 case 0xd50: /* MMFR0. */
532 case 0xd54: /* MMFR1. */
534 case 0xd58: /* MMFR2. */
536 case 0xd5c: /* MMFR3. */
538 case 0xd60: /* ISAR0. */
540 case 0xd64: /* ISAR1. */
542 case 0xd68: /* ISAR2. */
544 case 0xd6c: /* ISAR3. */
546 case 0xd70: /* ISAR4. */
548 /* TODO: Implement debug registers. */
549 case 0xd90: /* MPU_TYPE */
550 /* Unified MPU; if the MPU is not present this value is zero */
551 return cpu
->pmsav7_dregion
<< 8;
553 case 0xd94: /* MPU_CTRL */
554 return cpu
->env
.v7m
.mpu_ctrl
[attrs
.secure
];
555 case 0xd98: /* MPU_RNR */
556 return cpu
->env
.pmsav7
.rnr
[attrs
.secure
];
557 case 0xd9c: /* MPU_RBAR */
558 case 0xda4: /* MPU_RBAR_A1 */
559 case 0xdac: /* MPU_RBAR_A2 */
560 case 0xdb4: /* MPU_RBAR_A3 */
562 int region
= cpu
->env
.pmsav7
.rnr
[attrs
.secure
];
564 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
565 /* PMSAv8M handling of the aliases is different from v7M:
566 * aliases A1, A2, A3 override the low two bits of the region
567 * number in MPU_RNR, and there is no 'region' field in the
570 int aliasno
= (offset
- 0xd9c) / 8; /* 0..3 */
572 region
= deposit32(region
, 0, 2, aliasno
);
574 if (region
>= cpu
->pmsav7_dregion
) {
577 return cpu
->env
.pmsav8
.rbar
[attrs
.secure
][region
];
580 if (region
>= cpu
->pmsav7_dregion
) {
583 return (cpu
->env
.pmsav7
.drbar
[region
] & 0x1f) | (region
& 0xf);
585 case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */
586 case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */
587 case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */
588 case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */
590 int region
= cpu
->env
.pmsav7
.rnr
[attrs
.secure
];
592 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
593 /* PMSAv8M handling of the aliases is different from v7M:
594 * aliases A1, A2, A3 override the low two bits of the region
597 int aliasno
= (offset
- 0xda0) / 8; /* 0..3 */
599 region
= deposit32(region
, 0, 2, aliasno
);
601 if (region
>= cpu
->pmsav7_dregion
) {
604 return cpu
->env
.pmsav8
.rlar
[attrs
.secure
][region
];
607 if (region
>= cpu
->pmsav7_dregion
) {
610 return ((cpu
->env
.pmsav7
.dracr
[region
] & 0xffff) << 16) |
611 (cpu
->env
.pmsav7
.drsr
[region
] & 0xffff);
613 case 0xdc0: /* MPU_MAIR0 */
614 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
617 return cpu
->env
.pmsav8
.mair0
[attrs
.secure
];
618 case 0xdc4: /* MPU_MAIR1 */
619 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
622 return cpu
->env
.pmsav8
.mair1
[attrs
.secure
];
625 qemu_log_mask(LOG_GUEST_ERROR
, "NVIC: Bad read offset 0x%x\n", offset
);
630 static void nvic_writel(NVICState
*s
, uint32_t offset
, uint32_t value
,
633 ARMCPU
*cpu
= s
->cpu
;
636 case 0xd04: /* Interrupt Control State. */
637 if (value
& (1 << 31)) {
638 armv7m_nvic_set_pending(s
, ARMV7M_EXCP_NMI
);
640 if (value
& (1 << 28)) {
641 armv7m_nvic_set_pending(s
, ARMV7M_EXCP_PENDSV
);
642 } else if (value
& (1 << 27)) {
643 armv7m_nvic_clear_pending(s
, ARMV7M_EXCP_PENDSV
);
645 if (value
& (1 << 26)) {
646 armv7m_nvic_set_pending(s
, ARMV7M_EXCP_SYSTICK
);
647 } else if (value
& (1 << 25)) {
648 armv7m_nvic_clear_pending(s
, ARMV7M_EXCP_SYSTICK
);
651 case 0xd08: /* Vector Table Offset. */
652 cpu
->env
.v7m
.vecbase
[attrs
.secure
] = value
& 0xffffff80;
654 case 0xd0c: /* Application Interrupt/Reset Control. */
655 if ((value
>> 16) == 0x05fa) {
657 qemu_irq_pulse(s
->sysresetreq
);
660 qemu_log_mask(LOG_GUEST_ERROR
,
661 "Setting VECTCLRACTIVE when not in DEBUG mode "
662 "is UNPREDICTABLE\n");
665 qemu_log_mask(LOG_GUEST_ERROR
,
666 "Setting VECTRESET when not in DEBUG mode "
667 "is UNPREDICTABLE\n");
669 s
->prigroup
= extract32(value
, 8, 3);
673 case 0xd10: /* System Control. */
674 /* TODO: Implement control registers. */
675 qemu_log_mask(LOG_UNIMP
, "NVIC: SCR unimplemented\n");
677 case 0xd14: /* Configuration Control. */
678 /* Enforce RAZ/WI on reserved and must-RAZ/WI bits */
679 value
&= (R_V7M_CCR_STKALIGN_MASK
|
680 R_V7M_CCR_BFHFNMIGN_MASK
|
681 R_V7M_CCR_DIV_0_TRP_MASK
|
682 R_V7M_CCR_UNALIGN_TRP_MASK
|
683 R_V7M_CCR_USERSETMPEND_MASK
|
684 R_V7M_CCR_NONBASETHRDENA_MASK
);
686 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
687 /* v8M makes NONBASETHRDENA and STKALIGN be RES1 */
688 value
|= R_V7M_CCR_NONBASETHRDENA_MASK
689 | R_V7M_CCR_STKALIGN_MASK
;
692 /* the BFHFNMIGN bit is not banked; keep that in the NS copy */
693 cpu
->env
.v7m
.ccr
[M_REG_NS
] =
694 (cpu
->env
.v7m
.ccr
[M_REG_NS
] & ~R_V7M_CCR_BFHFNMIGN_MASK
)
695 | (value
& R_V7M_CCR_BFHFNMIGN_MASK
);
696 value
&= ~R_V7M_CCR_BFHFNMIGN_MASK
;
699 cpu
->env
.v7m
.ccr
[attrs
.secure
] = value
;
701 case 0xd24: /* System Handler Control. */
702 s
->vectors
[ARMV7M_EXCP_MEM
].active
= (value
& (1 << 0)) != 0;
703 s
->vectors
[ARMV7M_EXCP_BUS
].active
= (value
& (1 << 1)) != 0;
704 s
->vectors
[ARMV7M_EXCP_USAGE
].active
= (value
& (1 << 3)) != 0;
705 s
->vectors
[ARMV7M_EXCP_SVC
].active
= (value
& (1 << 7)) != 0;
706 s
->vectors
[ARMV7M_EXCP_DEBUG
].active
= (value
& (1 << 8)) != 0;
707 s
->vectors
[ARMV7M_EXCP_PENDSV
].active
= (value
& (1 << 10)) != 0;
708 s
->vectors
[ARMV7M_EXCP_SYSTICK
].active
= (value
& (1 << 11)) != 0;
709 s
->vectors
[ARMV7M_EXCP_USAGE
].pending
= (value
& (1 << 12)) != 0;
710 s
->vectors
[ARMV7M_EXCP_MEM
].pending
= (value
& (1 << 13)) != 0;
711 s
->vectors
[ARMV7M_EXCP_BUS
].pending
= (value
& (1 << 14)) != 0;
712 s
->vectors
[ARMV7M_EXCP_SVC
].pending
= (value
& (1 << 15)) != 0;
713 s
->vectors
[ARMV7M_EXCP_MEM
].enabled
= (value
& (1 << 16)) != 0;
714 s
->vectors
[ARMV7M_EXCP_BUS
].enabled
= (value
& (1 << 17)) != 0;
715 s
->vectors
[ARMV7M_EXCP_USAGE
].enabled
= (value
& (1 << 18)) != 0;
718 case 0xd28: /* Configurable Fault Status. */
719 cpu
->env
.v7m
.cfsr
[attrs
.secure
] &= ~value
; /* W1C */
721 /* The BFSR bits [15:8] are shared between security states
722 * and we store them in the NS copy.
724 cpu
->env
.v7m
.cfsr
[M_REG_NS
] &= ~(value
& R_V7M_CFSR_BFSR_MASK
);
727 case 0xd2c: /* Hard Fault Status. */
728 cpu
->env
.v7m
.hfsr
&= ~value
; /* W1C */
730 case 0xd30: /* Debug Fault Status. */
731 cpu
->env
.v7m
.dfsr
&= ~value
; /* W1C */
733 case 0xd34: /* Mem Manage Address. */
734 cpu
->env
.v7m
.mmfar
[attrs
.secure
] = value
;
736 case 0xd38: /* Bus Fault Address. */
737 cpu
->env
.v7m
.bfar
= value
;
739 case 0xd3c: /* Aux Fault Status. */
740 qemu_log_mask(LOG_UNIMP
,
741 "NVIC: Aux fault status registers unimplemented\n");
743 case 0xd90: /* MPU_TYPE */
745 case 0xd94: /* MPU_CTRL */
747 (R_V7M_MPU_CTRL_HFNMIENA_MASK
| R_V7M_MPU_CTRL_ENABLE_MASK
))
748 == R_V7M_MPU_CTRL_HFNMIENA_MASK
) {
749 qemu_log_mask(LOG_GUEST_ERROR
, "MPU_CTRL: HFNMIENA and !ENABLE is "
752 cpu
->env
.v7m
.mpu_ctrl
[attrs
.secure
]
753 = value
& (R_V7M_MPU_CTRL_ENABLE_MASK
|
754 R_V7M_MPU_CTRL_HFNMIENA_MASK
|
755 R_V7M_MPU_CTRL_PRIVDEFENA_MASK
);
758 case 0xd98: /* MPU_RNR */
759 if (value
>= cpu
->pmsav7_dregion
) {
760 qemu_log_mask(LOG_GUEST_ERROR
, "MPU region out of range %"
761 PRIu32
"/%" PRIu32
"\n",
762 value
, cpu
->pmsav7_dregion
);
764 cpu
->env
.pmsav7
.rnr
[attrs
.secure
] = value
;
767 case 0xd9c: /* MPU_RBAR */
768 case 0xda4: /* MPU_RBAR_A1 */
769 case 0xdac: /* MPU_RBAR_A2 */
770 case 0xdb4: /* MPU_RBAR_A3 */
774 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
775 /* PMSAv8M handling of the aliases is different from v7M:
776 * aliases A1, A2, A3 override the low two bits of the region
777 * number in MPU_RNR, and there is no 'region' field in the
780 int aliasno
= (offset
- 0xd9c) / 8; /* 0..3 */
782 region
= cpu
->env
.pmsav7
.rnr
[attrs
.secure
];
784 region
= deposit32(region
, 0, 2, aliasno
);
786 if (region
>= cpu
->pmsav7_dregion
) {
789 cpu
->env
.pmsav8
.rbar
[attrs
.secure
][region
] = value
;
794 if (value
& (1 << 4)) {
795 /* VALID bit means use the region number specified in this
796 * value and also update MPU_RNR.REGION with that value.
798 region
= extract32(value
, 0, 4);
799 if (region
>= cpu
->pmsav7_dregion
) {
800 qemu_log_mask(LOG_GUEST_ERROR
,
801 "MPU region out of range %u/%" PRIu32
"\n",
802 region
, cpu
->pmsav7_dregion
);
805 cpu
->env
.pmsav7
.rnr
[attrs
.secure
] = region
;
807 region
= cpu
->env
.pmsav7
.rnr
[attrs
.secure
];
810 if (region
>= cpu
->pmsav7_dregion
) {
814 cpu
->env
.pmsav7
.drbar
[region
] = value
& ~0x1f;
818 case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */
819 case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */
820 case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */
821 case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */
823 int region
= cpu
->env
.pmsav7
.rnr
[attrs
.secure
];
825 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
826 /* PMSAv8M handling of the aliases is different from v7M:
827 * aliases A1, A2, A3 override the low two bits of the region
830 int aliasno
= (offset
- 0xd9c) / 8; /* 0..3 */
832 region
= cpu
->env
.pmsav7
.rnr
[attrs
.secure
];
834 region
= deposit32(region
, 0, 2, aliasno
);
836 if (region
>= cpu
->pmsav7_dregion
) {
839 cpu
->env
.pmsav8
.rlar
[attrs
.secure
][region
] = value
;
844 if (region
>= cpu
->pmsav7_dregion
) {
848 cpu
->env
.pmsav7
.drsr
[region
] = value
& 0xff3f;
849 cpu
->env
.pmsav7
.dracr
[region
] = (value
>> 16) & 0x173f;
853 case 0xdc0: /* MPU_MAIR0 */
854 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
857 if (cpu
->pmsav7_dregion
) {
858 /* Register is RES0 if no MPU regions are implemented */
859 cpu
->env
.pmsav8
.mair0
[attrs
.secure
] = value
;
861 /* We don't need to do anything else because memory attributes
862 * only affect cacheability, and we don't implement caching.
865 case 0xdc4: /* MPU_MAIR1 */
866 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
869 if (cpu
->pmsav7_dregion
) {
870 /* Register is RES0 if no MPU regions are implemented */
871 cpu
->env
.pmsav8
.mair1
[attrs
.secure
] = value
;
873 /* We don't need to do anything else because memory attributes
874 * only affect cacheability, and we don't implement caching.
877 case 0xf00: /* Software Triggered Interrupt Register */
879 int excnum
= (value
& 0x1ff) + NVIC_FIRST_IRQ
;
880 if (excnum
< s
->num_irq
) {
881 armv7m_nvic_set_pending(s
, excnum
);
887 qemu_log_mask(LOG_GUEST_ERROR
,
888 "NVIC: Bad write offset 0x%x\n", offset
);
892 static bool nvic_user_access_ok(NVICState
*s
, hwaddr offset
, MemTxAttrs attrs
)
894 /* Return true if unprivileged access to this register is permitted. */
896 case 0xf00: /* STIR: accessible only if CCR.USERSETMPEND permits */
897 /* For access via STIR_NS it is the NS CCR.USERSETMPEND that
898 * controls access even though the CPU is in Secure state (I_QDKX).
900 return s
->cpu
->env
.v7m
.ccr
[attrs
.secure
] & R_V7M_CCR_USERSETMPEND_MASK
;
902 /* All other user accesses cause a BusFault unconditionally */
907 static MemTxResult
nvic_sysreg_read(void *opaque
, hwaddr addr
,
908 uint64_t *data
, unsigned size
,
911 NVICState
*s
= (NVICState
*)opaque
;
912 uint32_t offset
= addr
;
913 unsigned i
, startvec
, end
;
916 if (attrs
.user
&& !nvic_user_access_ok(s
, addr
, attrs
)) {
917 /* Generate BusFault for unprivileged accesses */
922 /* reads of set and clear both return the status */
923 case 0x100 ... 0x13f: /* NVIC Set enable */
926 case 0x180 ... 0x1bf: /* NVIC Clear enable */
928 startvec
= offset
- 0x180 + NVIC_FIRST_IRQ
; /* vector # */
930 for (i
= 0, end
= size
* 8; i
< end
&& startvec
+ i
< s
->num_irq
; i
++) {
931 if (s
->vectors
[startvec
+ i
].enabled
) {
936 case 0x200 ... 0x23f: /* NVIC Set pend */
939 case 0x280 ... 0x2bf: /* NVIC Clear pend */
941 startvec
= offset
- 0x280 + NVIC_FIRST_IRQ
; /* vector # */
942 for (i
= 0, end
= size
* 8; i
< end
&& startvec
+ i
< s
->num_irq
; i
++) {
943 if (s
->vectors
[startvec
+ i
].pending
) {
948 case 0x300 ... 0x33f: /* NVIC Active */
950 startvec
= offset
- 0x300 + NVIC_FIRST_IRQ
; /* vector # */
952 for (i
= 0, end
= size
* 8; i
< end
&& startvec
+ i
< s
->num_irq
; i
++) {
953 if (s
->vectors
[startvec
+ i
].active
) {
958 case 0x400 ... 0x5ef: /* NVIC Priority */
960 startvec
= offset
- 0x400 + NVIC_FIRST_IRQ
; /* vector # */
962 for (i
= 0; i
< size
&& startvec
+ i
< s
->num_irq
; i
++) {
963 val
|= s
->vectors
[startvec
+ i
].prio
<< (8 * i
);
966 case 0xd18 ... 0xd23: /* System Handler Priority. */
968 for (i
= 0; i
< size
; i
++) {
969 val
|= s
->vectors
[(offset
- 0xd14) + i
].prio
<< (i
* 8);
972 case 0xfe0 ... 0xfff: /* ID. */
976 val
= nvic_id
[(offset
- 0xfe0) >> 2];
981 val
= nvic_readl(s
, offset
, attrs
);
983 qemu_log_mask(LOG_GUEST_ERROR
,
984 "NVIC: Bad read of size %d at offset 0x%x\n",
990 trace_nvic_sysreg_read(addr
, val
, size
);
995 static MemTxResult
nvic_sysreg_write(void *opaque
, hwaddr addr
,
996 uint64_t value
, unsigned size
,
999 NVICState
*s
= (NVICState
*)opaque
;
1000 uint32_t offset
= addr
;
1001 unsigned i
, startvec
, end
;
1002 unsigned setval
= 0;
1004 trace_nvic_sysreg_write(addr
, value
, size
);
1006 if (attrs
.user
&& !nvic_user_access_ok(s
, addr
, attrs
)) {
1007 /* Generate BusFault for unprivileged accesses */
1012 case 0x100 ... 0x13f: /* NVIC Set enable */
1016 case 0x180 ... 0x1bf: /* NVIC Clear enable */
1017 startvec
= 8 * (offset
- 0x180) + NVIC_FIRST_IRQ
;
1019 for (i
= 0, end
= size
* 8; i
< end
&& startvec
+ i
< s
->num_irq
; i
++) {
1020 if (value
& (1 << i
)) {
1021 s
->vectors
[startvec
+ i
].enabled
= setval
;
1026 case 0x200 ... 0x23f: /* NVIC Set pend */
1027 /* the special logic in armv7m_nvic_set_pending()
1028 * is not needed since IRQs are never escalated
1033 case 0x280 ... 0x2bf: /* NVIC Clear pend */
1034 startvec
= 8 * (offset
- 0x280) + NVIC_FIRST_IRQ
; /* vector # */
1036 for (i
= 0, end
= size
* 8; i
< end
&& startvec
+ i
< s
->num_irq
; i
++) {
1037 if (value
& (1 << i
)) {
1038 s
->vectors
[startvec
+ i
].pending
= setval
;
1043 case 0x300 ... 0x33f: /* NVIC Active */
1044 return MEMTX_OK
; /* R/O */
1045 case 0x400 ... 0x5ef: /* NVIC Priority */
1046 startvec
= 8 * (offset
- 0x400) + NVIC_FIRST_IRQ
; /* vector # */
1048 for (i
= 0; i
< size
&& startvec
+ i
< s
->num_irq
; i
++) {
1049 set_prio(s
, startvec
+ i
, (value
>> (i
* 8)) & 0xff);
1053 case 0xd18 ... 0xd23: /* System Handler Priority. */
1054 for (i
= 0; i
< size
; i
++) {
1055 unsigned hdlidx
= (offset
- 0xd14) + i
;
1056 set_prio(s
, hdlidx
, (value
>> (i
* 8)) & 0xff);
1062 nvic_writel(s
, offset
, value
, attrs
);
1065 qemu_log_mask(LOG_GUEST_ERROR
,
1066 "NVIC: Bad write of size %d at offset 0x%x\n", size
, offset
);
1067 /* This is UNPREDICTABLE; treat as RAZ/WI */
1071 static const MemoryRegionOps nvic_sysreg_ops
= {
1072 .read_with_attrs
= nvic_sysreg_read
,
1073 .write_with_attrs
= nvic_sysreg_write
,
1074 .endianness
= DEVICE_NATIVE_ENDIAN
,
1077 static MemTxResult
nvic_sysreg_ns_write(void *opaque
, hwaddr addr
,
1078 uint64_t value
, unsigned size
,
1082 /* S accesses to the alias act like NS accesses to the real region */
1084 return nvic_sysreg_write(opaque
, addr
, value
, size
, attrs
);
1086 /* NS attrs are RAZ/WI for privileged, and BusFault for user */
1094 static MemTxResult
nvic_sysreg_ns_read(void *opaque
, hwaddr addr
,
1095 uint64_t *data
, unsigned size
,
1099 /* S accesses to the alias act like NS accesses to the real region */
1101 return nvic_sysreg_read(opaque
, addr
, data
, size
, attrs
);
1103 /* NS attrs are RAZ/WI for privileged, and BusFault for user */
1112 static const MemoryRegionOps nvic_sysreg_ns_ops
= {
1113 .read_with_attrs
= nvic_sysreg_ns_read
,
1114 .write_with_attrs
= nvic_sysreg_ns_write
,
1115 .endianness
= DEVICE_NATIVE_ENDIAN
,
1118 static int nvic_post_load(void *opaque
, int version_id
)
1120 NVICState
*s
= opaque
;
1123 /* Check for out of range priority settings */
1124 if (s
->vectors
[ARMV7M_EXCP_RESET
].prio
!= -3 ||
1125 s
->vectors
[ARMV7M_EXCP_NMI
].prio
!= -2 ||
1126 s
->vectors
[ARMV7M_EXCP_HARD
].prio
!= -1) {
1129 for (i
= ARMV7M_EXCP_MEM
; i
< s
->num_irq
; i
++) {
1130 if (s
->vectors
[i
].prio
& ~0xff) {
1135 nvic_recompute_state(s
);
1140 static const VMStateDescription vmstate_VecInfo
= {
1141 .name
= "armv7m_nvic_info",
1143 .minimum_version_id
= 1,
1144 .fields
= (VMStateField
[]) {
1145 VMSTATE_INT16(prio
, VecInfo
),
1146 VMSTATE_UINT8(enabled
, VecInfo
),
1147 VMSTATE_UINT8(pending
, VecInfo
),
1148 VMSTATE_UINT8(active
, VecInfo
),
1149 VMSTATE_UINT8(level
, VecInfo
),
1150 VMSTATE_END_OF_LIST()
1154 static const VMStateDescription vmstate_nvic
= {
1155 .name
= "armv7m_nvic",
1157 .minimum_version_id
= 4,
1158 .post_load
= &nvic_post_load
,
1159 .fields
= (VMStateField
[]) {
1160 VMSTATE_STRUCT_ARRAY(vectors
, NVICState
, NVIC_MAX_VECTORS
, 1,
1161 vmstate_VecInfo
, VecInfo
),
1162 VMSTATE_UINT32(prigroup
, NVICState
),
1163 VMSTATE_END_OF_LIST()
1167 static Property props_nvic
[] = {
1168 /* Number of external IRQ lines (so excluding the 16 internal exceptions) */
1169 DEFINE_PROP_UINT32("num-irq", NVICState
, num_irq
, 64),
1170 DEFINE_PROP_END_OF_LIST()
1173 static void armv7m_nvic_reset(DeviceState
*dev
)
1175 NVICState
*s
= NVIC(dev
);
1177 s
->vectors
[ARMV7M_EXCP_NMI
].enabled
= 1;
1178 s
->vectors
[ARMV7M_EXCP_HARD
].enabled
= 1;
1179 /* MEM, BUS, and USAGE are enabled through
1180 * the System Handler Control register
1182 s
->vectors
[ARMV7M_EXCP_SVC
].enabled
= 1;
1183 s
->vectors
[ARMV7M_EXCP_DEBUG
].enabled
= 1;
1184 s
->vectors
[ARMV7M_EXCP_PENDSV
].enabled
= 1;
1185 s
->vectors
[ARMV7M_EXCP_SYSTICK
].enabled
= 1;
1187 s
->vectors
[ARMV7M_EXCP_RESET
].prio
= -3;
1188 s
->vectors
[ARMV7M_EXCP_NMI
].prio
= -2;
1189 s
->vectors
[ARMV7M_EXCP_HARD
].prio
= -1;
1191 /* Strictly speaking the reset handler should be enabled.
1192 * However, we don't simulate soft resets through the NVIC,
1193 * and the reset vector should never be pended.
1194 * So we leave it disabled to catch logic errors.
1197 s
->exception_prio
= NVIC_NOEXC_PRIO
;
1201 static void nvic_systick_trigger(void *opaque
, int n
, int level
)
1203 NVICState
*s
= opaque
;
1206 /* SysTick just asked us to pend its exception.
1207 * (This is different from an external interrupt line's
1210 armv7m_nvic_set_pending(s
, ARMV7M_EXCP_SYSTICK
);
1214 static void armv7m_nvic_realize(DeviceState
*dev
, Error
**errp
)
1216 NVICState
*s
= NVIC(dev
);
1217 SysBusDevice
*systick_sbd
;
1221 s
->cpu
= ARM_CPU(qemu_get_cpu(0));
1224 if (s
->num_irq
> NVIC_MAX_IRQ
) {
1225 error_setg(errp
, "num-irq %d exceeds NVIC maximum", s
->num_irq
);
1229 qdev_init_gpio_in(dev
, set_irq_level
, s
->num_irq
);
1231 /* include space for internal exception vectors */
1232 s
->num_irq
+= NVIC_FIRST_IRQ
;
1234 object_property_set_bool(OBJECT(&s
->systick
), true, "realized", &err
);
1236 error_propagate(errp
, err
);
1239 systick_sbd
= SYS_BUS_DEVICE(&s
->systick
);
1240 sysbus_connect_irq(systick_sbd
, 0,
1241 qdev_get_gpio_in_named(dev
, "systick-trigger", 0));
1243 /* The NVIC and System Control Space (SCS) starts at 0xe000e000
1244 * and looks like this:
1246 * 0x010 - 0xff - systick
1247 * 0x100..0x7ec - NVIC
1248 * 0x7f0..0xcff - Reserved
1249 * 0xd00..0xd3c - SCS registers
1250 * 0xd40..0xeff - Reserved or Not implemented
1253 * Some registers within this space are banked between security states.
1254 * In v8M there is a second range 0xe002e000..0xe002efff which is the
1255 * NonSecure alias SCS; secure accesses to this behave like NS accesses
1256 * to the main SCS range, and non-secure accesses (including when
1257 * the security extension is not implemented) are RAZ/WI.
1258 * Note that both the main SCS range and the alias range are defined
1259 * to be exempt from memory attribution (R_BLJT) and so the memory
1260 * transaction attribute always matches the current CPU security
1261 * state (attrs.secure == env->v7m.secure). In the nvic_sysreg_ns_ops
1262 * wrappers we change attrs.secure to indicate the NS access; so
1263 * generally code determining which banked register to use should
1264 * use attrs.secure; code determining actual behaviour of the system
1265 * should use env->v7m.secure.
1267 regionlen
= arm_feature(&s
->cpu
->env
, ARM_FEATURE_V8
) ? 0x21000 : 0x1000;
1268 memory_region_init(&s
->container
, OBJECT(s
), "nvic", regionlen
);
1269 /* The system register region goes at the bottom of the priority
1270 * stack as it covers the whole page.
1272 memory_region_init_io(&s
->sysregmem
, OBJECT(s
), &nvic_sysreg_ops
, s
,
1273 "nvic_sysregs", 0x1000);
1274 memory_region_add_subregion(&s
->container
, 0, &s
->sysregmem
);
1275 memory_region_add_subregion_overlap(&s
->container
, 0x10,
1276 sysbus_mmio_get_region(systick_sbd
, 0),
1279 if (arm_feature(&s
->cpu
->env
, ARM_FEATURE_V8
)) {
1280 memory_region_init_io(&s
->sysreg_ns_mem
, OBJECT(s
),
1281 &nvic_sysreg_ns_ops
, s
,
1282 "nvic_sysregs_ns", 0x1000);
1283 memory_region_add_subregion(&s
->container
, 0x20000, &s
->sysreg_ns_mem
);
1286 sysbus_init_mmio(SYS_BUS_DEVICE(dev
), &s
->container
);
1289 static void armv7m_nvic_instance_init(Object
*obj
)
1291 /* We have a different default value for the num-irq property
1292 * than our superclass. This function runs after qdev init
1293 * has set the defaults from the Property array and before
1294 * any user-specified property setting, so just modify the
1295 * value in the GICState struct.
1297 DeviceState
*dev
= DEVICE(obj
);
1298 NVICState
*nvic
= NVIC(obj
);
1299 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
1301 object_initialize(&nvic
->systick
, sizeof(nvic
->systick
), TYPE_SYSTICK
);
1302 qdev_set_parent_bus(DEVICE(&nvic
->systick
), sysbus_get_default());
1304 sysbus_init_irq(sbd
, &nvic
->excpout
);
1305 qdev_init_gpio_out_named(dev
, &nvic
->sysresetreq
, "SYSRESETREQ", 1);
1306 qdev_init_gpio_in_named(dev
, nvic_systick_trigger
, "systick-trigger", 1);
1309 static void armv7m_nvic_class_init(ObjectClass
*klass
, void *data
)
1311 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1313 dc
->vmsd
= &vmstate_nvic
;
1314 dc
->props
= props_nvic
;
1315 dc
->reset
= armv7m_nvic_reset
;
1316 dc
->realize
= armv7m_nvic_realize
;
1319 static const TypeInfo armv7m_nvic_info
= {
1321 .parent
= TYPE_SYS_BUS_DEVICE
,
1322 .instance_init
= armv7m_nvic_instance_init
,
1323 .instance_size
= sizeof(NVICState
),
1324 .class_init
= armv7m_nvic_class_init
,
1325 .class_size
= sizeof(SysBusDeviceClass
),
1328 static void armv7m_nvic_register_types(void)
1330 type_register_static(&armv7m_nvic_info
);
1333 type_init(armv7m_nvic_register_types
)