target-tricore/helper.c

   1 /*
   2  *  Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
   3  *
   4  * This library is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU Lesser General Public
   6  * License as published by the Free Software Foundation; either
   7  * version 2 of the License, or (at your option) any later version.
   8  *
   9  * This library is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * Lesser General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU Lesser General Public
  15  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <stdarg.h>
  19 #include <stdlib.h>
  20 #include <stdio.h>
  21 #include <string.h>
  22 #include <inttypes.h>
  23
  24 #include "cpu.h"
  25
  26 enum {
  27     TLBRET_DIRTY = -4,
  28     TLBRET_INVALID = -3,
  29     TLBRET_NOMATCH = -2,
  30     TLBRET_BADADDR = -1,
  31     TLBRET_MATCH = 0
  32 };
  33
  34 #if defined(CONFIG_SOFTMMU)
  35 static int get_physical_address(CPUTriCoreState *env, hwaddr *physical,
  36                                 int *prot, target_ulong address,
  37                                 int rw, int access_type)
  38 {
  39     int ret = TLBRET_MATCH;
  40
  41     *physical = address & 0xFFFFFFFF;
  42     *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
  43
  44     return ret;
  45 }
  46 #endif
  47
  48 /* TODO: Add exeption support*/
  49 static void raise_mmu_exception(CPUTriCoreState *env, target_ulong address,
  50                                 int rw, int tlb_error)
  51 {
  52 }
  53
  54 int cpu_tricore_handle_mmu_fault(CPUState *cs, target_ulong address,
  55                                  int rw, int mmu_idx)
  56 {
  57     TriCoreCPU *cpu = TRICORE_CPU(cs);
  58     CPUTriCoreState *env = &cpu->env;
  59     hwaddr physical;
  60     int prot;
  61     int access_type;
  62     int ret = 0;
  63
  64     rw &= 1;
  65     access_type = ACCESS_INT;
  66     ret = get_physical_address(env, &physical, &prot,
  67                                address, rw, access_type);
  68     qemu_log("%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_plx
  69              " prot %d\n", __func__, address, ret, physical, prot);
  70
  71     if (ret == TLBRET_MATCH) {
  72         tlb_set_page(cs, address & TARGET_PAGE_MASK,
  73                      physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
  74                      mmu_idx, TARGET_PAGE_SIZE);
  75         ret = 0;
  76     } else if (ret < 0) {
  77         raise_mmu_exception(env, address, rw, ret);
  78         ret = 1;
  79     }
  80
  81     return ret;
  82 }
  83
  84 TriCoreCPU *cpu_tricore_init(const char *cpu_model)
  85 {
  86     return TRICORE_CPU(cpu_generic_init(TYPE_TRICORE_CPU, cpu_model));
  87 }
  88
  89 static void tricore_cpu_list_entry(gpointer data, gpointer user_data)
  90 {
  91     ObjectClass *oc = data;
  92     CPUListState *s = user_data;
  93     const char *typename;
  94     char *name;
  95
  96     typename = object_class_get_name(oc);
  97     name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_TRICORE_CPU));
  98     (*s->cpu_fprintf)(s->file, "  %s\n",
  99                       name);
 100     g_free(name);
 101 }
 102
 103 void tricore_cpu_list(FILE *f, fprintf_function cpu_fprintf)
 104 {
 105     CPUListState s = {
 106         .file = f,
 107         .cpu_fprintf = cpu_fprintf,
 108     };
 109     GSList *list;
 110
 111     list = object_class_get_list(TYPE_TRICORE_CPU, false);
 112     (*cpu_fprintf)(f, "Available CPUs:\n");
 113     g_slist_foreach(list, tricore_cpu_list_entry, &s);
 114     g_slist_free(list);
 115 }
 116
 117 uint32_t psw_read(CPUTriCoreState *env)
 118 {
 119     /* clear all USB bits */
 120     env->PSW &= 0xffffff;
 121     /* now set them from the cache */
 122     env->PSW |= ((env->PSW_USB_C != 0) << 31);
 123     env->PSW |= ((env->PSW_USB_V   & (1 << 31))  >> 1);
 124     env->PSW |= ((env->PSW_USB_SV  & (1 << 31))  >> 2);
 125     env->PSW |= ((env->PSW_USB_AV  & (1 << 31))  >> 3);
 126     env->PSW |= ((env->PSW_USB_SAV & (1 << 31))  >> 4);
 127
 128     return env->PSW;
 129 }
 130
 131 void psw_write(CPUTriCoreState *env, uint32_t val)
 132 {
 133     env->PSW_USB_C = (val & MASK_USB_C);
 134     env->PSW_USB_V = (val & MASK_USB_V << 1);
 135     env->PSW_USB_SV = (val & MASK_USB_SV << 2);
 136     env->PSW_USB_AV = ((val & MASK_USB_AV) << 3);
 137     env->PSW_USB_SAV = ((val & MASK_USB_SAV) << 4);
 138     env->PSW = val;
 139 }