2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 /* define it to use liveness analysis (better code) */
26 #define USE_TCG_OPTIMIZATIONS
28 #include "qemu/osdep.h"
30 /* Define to jump the ELF file used to communicate with GDB. */
33 #include "qemu/cutils.h"
34 #include "qemu/host-utils.h"
35 #include "qemu/timer.h"
37 /* Note: the long term plan is to reduce the dependencies on the QEMU
38 CPU definitions. Currently they are used for qemu_ld/st
40 #define NO_CPU_IO_DEFS
43 #include "exec/cpu-common.h"
44 #include "exec/exec-all.h"
48 #if UINTPTR_MAX == UINT32_MAX
49 # define ELF_CLASS ELFCLASS32
51 # define ELF_CLASS ELFCLASS64
53 #ifdef HOST_WORDS_BIGENDIAN
54 # define ELF_DATA ELFDATA2MSB
56 # define ELF_DATA ELFDATA2LSB
62 /* Forward declarations for functions declared in tcg-target.inc.c and
64 static void tcg_target_init(TCGContext
*s
);
65 static const TCGTargetOpDef
*tcg_target_op_def(TCGOpcode
);
66 static void tcg_target_qemu_prologue(TCGContext
*s
);
67 static void patch_reloc(tcg_insn_unit
*code_ptr
, int type
,
68 intptr_t value
, intptr_t addend
);
70 /* The CIE and FDE header definitions will be common to all hosts. */
72 uint32_t len
__attribute__((aligned((sizeof(void *)))));
78 uint8_t return_column
;
81 typedef struct QEMU_PACKED
{
82 uint32_t len
__attribute__((aligned((sizeof(void *)))));
86 } DebugFrameFDEHeader
;
88 typedef struct QEMU_PACKED
{
90 DebugFrameFDEHeader fde
;
93 static void tcg_register_jit_int(void *buf
, size_t size
,
94 const void *debug_frame
,
95 size_t debug_frame_size
)
96 __attribute__((unused
));
98 /* Forward declarations for functions declared and used in tcg-target.inc.c. */
99 static const char *target_parse_constraint(TCGArgConstraint
*ct
,
100 const char *ct_str
, TCGType type
);
101 static void tcg_out_ld(TCGContext
*s
, TCGType type
, TCGReg ret
, TCGReg arg1
,
103 static void tcg_out_mov(TCGContext
*s
, TCGType type
, TCGReg ret
, TCGReg arg
);
104 static void tcg_out_movi(TCGContext
*s
, TCGType type
,
105 TCGReg ret
, tcg_target_long arg
);
106 static void tcg_out_op(TCGContext
*s
, TCGOpcode opc
, const TCGArg
*args
,
107 const int *const_args
);
108 static void tcg_out_st(TCGContext
*s
, TCGType type
, TCGReg arg
, TCGReg arg1
,
110 static bool tcg_out_sti(TCGContext
*s
, TCGType type
, TCGArg val
,
111 TCGReg base
, intptr_t ofs
);
112 static void tcg_out_call(TCGContext
*s
, tcg_insn_unit
*target
);
113 static int tcg_target_const_match(tcg_target_long val
, TCGType type
,
114 const TCGArgConstraint
*arg_ct
);
115 #ifdef TCG_TARGET_NEED_LDST_LABELS
116 static bool tcg_out_ldst_finalize(TCGContext
*s
);
119 static TCGRegSet tcg_target_available_regs
[2];
120 static TCGRegSet tcg_target_call_clobber_regs
;
122 #if TCG_TARGET_INSN_UNIT_SIZE == 1
123 static __attribute__((unused
)) inline void tcg_out8(TCGContext
*s
, uint8_t v
)
128 static __attribute__((unused
)) inline void tcg_patch8(tcg_insn_unit
*p
,
135 #if TCG_TARGET_INSN_UNIT_SIZE <= 2
136 static __attribute__((unused
)) inline void tcg_out16(TCGContext
*s
, uint16_t v
)
138 if (TCG_TARGET_INSN_UNIT_SIZE
== 2) {
141 tcg_insn_unit
*p
= s
->code_ptr
;
142 memcpy(p
, &v
, sizeof(v
));
143 s
->code_ptr
= p
+ (2 / TCG_TARGET_INSN_UNIT_SIZE
);
147 static __attribute__((unused
)) inline void tcg_patch16(tcg_insn_unit
*p
,
150 if (TCG_TARGET_INSN_UNIT_SIZE
== 2) {
153 memcpy(p
, &v
, sizeof(v
));
158 #if TCG_TARGET_INSN_UNIT_SIZE <= 4
159 static __attribute__((unused
)) inline void tcg_out32(TCGContext
*s
, uint32_t v
)
161 if (TCG_TARGET_INSN_UNIT_SIZE
== 4) {
164 tcg_insn_unit
*p
= s
->code_ptr
;
165 memcpy(p
, &v
, sizeof(v
));
166 s
->code_ptr
= p
+ (4 / TCG_TARGET_INSN_UNIT_SIZE
);
170 static __attribute__((unused
)) inline void tcg_patch32(tcg_insn_unit
*p
,
173 if (TCG_TARGET_INSN_UNIT_SIZE
== 4) {
176 memcpy(p
, &v
, sizeof(v
));
181 #if TCG_TARGET_INSN_UNIT_SIZE <= 8
182 static __attribute__((unused
)) inline void tcg_out64(TCGContext
*s
, uint64_t v
)
184 if (TCG_TARGET_INSN_UNIT_SIZE
== 8) {
187 tcg_insn_unit
*p
= s
->code_ptr
;
188 memcpy(p
, &v
, sizeof(v
));
189 s
->code_ptr
= p
+ (8 / TCG_TARGET_INSN_UNIT_SIZE
);
193 static __attribute__((unused
)) inline void tcg_patch64(tcg_insn_unit
*p
,
196 if (TCG_TARGET_INSN_UNIT_SIZE
== 8) {
199 memcpy(p
, &v
, sizeof(v
));
204 /* label relocation processing */
206 static void tcg_out_reloc(TCGContext
*s
, tcg_insn_unit
*code_ptr
, int type
,
207 TCGLabel
*l
, intptr_t addend
)
212 /* FIXME: This may break relocations on RISC targets that
213 modify instruction fields in place. The caller may not have
214 written the initial value. */
215 patch_reloc(code_ptr
, type
, l
->u
.value
, addend
);
217 /* add a new relocation entry */
218 r
= tcg_malloc(sizeof(TCGRelocation
));
222 r
->next
= l
->u
.first_reloc
;
223 l
->u
.first_reloc
= r
;
227 static void tcg_out_label(TCGContext
*s
, TCGLabel
*l
, tcg_insn_unit
*ptr
)
229 intptr_t value
= (intptr_t)ptr
;
232 tcg_debug_assert(!l
->has_value
);
234 for (r
= l
->u
.first_reloc
; r
!= NULL
; r
= r
->next
) {
235 patch_reloc(r
->ptr
, r
->type
, value
, r
->addend
);
239 l
->u
.value_ptr
= ptr
;
242 TCGLabel
*gen_new_label(void)
244 TCGContext
*s
= &tcg_ctx
;
245 TCGLabel
*l
= tcg_malloc(sizeof(TCGLabel
));
254 #include "tcg-target.inc.c"
256 /* pool based memory allocation */
257 void *tcg_malloc_internal(TCGContext
*s
, int size
)
262 if (size
> TCG_POOL_CHUNK_SIZE
) {
263 /* big malloc: insert a new pool (XXX: could optimize) */
264 p
= g_malloc(sizeof(TCGPool
) + size
);
266 p
->next
= s
->pool_first_large
;
267 s
->pool_first_large
= p
;
278 pool_size
= TCG_POOL_CHUNK_SIZE
;
279 p
= g_malloc(sizeof(TCGPool
) + pool_size
);
283 s
->pool_current
->next
= p
;
292 s
->pool_cur
= p
->data
+ size
;
293 s
->pool_end
= p
->data
+ p
->size
;
297 void tcg_pool_reset(TCGContext
*s
)
300 for (p
= s
->pool_first_large
; p
; p
= t
) {
304 s
->pool_first_large
= NULL
;
305 s
->pool_cur
= s
->pool_end
= NULL
;
306 s
->pool_current
= NULL
;
309 typedef struct TCGHelperInfo
{
316 #include "exec/helper-proto.h"
318 static const TCGHelperInfo all_helpers
[] = {
319 #include "exec/helper-tcg.h"
322 static int indirect_reg_alloc_order
[ARRAY_SIZE(tcg_target_reg_alloc_order
)];
323 static void process_op_defs(TCGContext
*s
);
325 void tcg_context_init(TCGContext
*s
)
327 int op
, total_args
, n
, i
;
329 TCGArgConstraint
*args_ct
;
331 GHashTable
*helper_table
;
333 memset(s
, 0, sizeof(*s
));
336 /* Count total number of arguments and allocate the corresponding
339 for(op
= 0; op
< NB_OPS
; op
++) {
340 def
= &tcg_op_defs
[op
];
341 n
= def
->nb_iargs
+ def
->nb_oargs
;
345 args_ct
= g_malloc(sizeof(TCGArgConstraint
) * total_args
);
346 sorted_args
= g_malloc(sizeof(int) * total_args
);
348 for(op
= 0; op
< NB_OPS
; op
++) {
349 def
= &tcg_op_defs
[op
];
350 def
->args_ct
= args_ct
;
351 def
->sorted_args
= sorted_args
;
352 n
= def
->nb_iargs
+ def
->nb_oargs
;
357 /* Register helpers. */
358 /* Use g_direct_hash/equal for direct pointer comparisons on func. */
359 s
->helpers
= helper_table
= g_hash_table_new(NULL
, NULL
);
361 for (i
= 0; i
< ARRAY_SIZE(all_helpers
); ++i
) {
362 g_hash_table_insert(helper_table
, (gpointer
)all_helpers
[i
].func
,
363 (gpointer
)&all_helpers
[i
]);
369 /* Reverse the order of the saved registers, assuming they're all at
370 the start of tcg_target_reg_alloc_order. */
371 for (n
= 0; n
< ARRAY_SIZE(tcg_target_reg_alloc_order
); ++n
) {
372 int r
= tcg_target_reg_alloc_order
[n
];
373 if (tcg_regset_test_reg(tcg_target_call_clobber_regs
, r
)) {
377 for (i
= 0; i
< n
; ++i
) {
378 indirect_reg_alloc_order
[i
] = tcg_target_reg_alloc_order
[n
- 1 - i
];
380 for (; i
< ARRAY_SIZE(tcg_target_reg_alloc_order
); ++i
) {
381 indirect_reg_alloc_order
[i
] = tcg_target_reg_alloc_order
[i
];
386 * Allocate TBs right before their corresponding translated code, making
387 * sure that TBs and code are on different cache lines.
389 TranslationBlock
*tcg_tb_alloc(TCGContext
*s
)
391 uintptr_t align
= qemu_icache_linesize
;
392 TranslationBlock
*tb
;
395 tb
= (void *)ROUND_UP((uintptr_t)s
->code_gen_ptr
, align
);
396 next
= (void *)ROUND_UP((uintptr_t)(tb
+ 1), align
);
398 if (unlikely(next
> s
->code_gen_highwater
)) {
401 s
->code_gen_ptr
= next
;
402 s
->data_gen_ptr
= NULL
;
406 void tcg_prologue_init(TCGContext
*s
)
408 size_t prologue_size
, total_size
;
411 /* Put the prologue at the beginning of code_gen_buffer. */
412 buf0
= s
->code_gen_buffer
;
415 s
->code_gen_prologue
= buf0
;
417 /* Generate the prologue. */
418 tcg_target_qemu_prologue(s
);
420 flush_icache_range((uintptr_t)buf0
, (uintptr_t)buf1
);
422 /* Deduct the prologue from the buffer. */
423 prologue_size
= tcg_current_code_size(s
);
424 s
->code_gen_ptr
= buf1
;
425 s
->code_gen_buffer
= buf1
;
427 total_size
= s
->code_gen_buffer_size
- prologue_size
;
428 s
->code_gen_buffer_size
= total_size
;
430 /* Compute a high-water mark, at which we voluntarily flush the buffer
431 and start over. The size here is arbitrary, significantly larger
432 than we expect the code generation for any one opcode to require. */
433 s
->code_gen_highwater
= s
->code_gen_buffer
+ (total_size
- 1024);
435 tcg_register_jit(s
->code_gen_buffer
, total_size
);
438 if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM
)) {
440 qemu_log("PROLOGUE: [size=%zu]\n", prologue_size
);
441 log_disas(buf0
, prologue_size
);
448 /* Assert that goto_ptr is implemented completely. */
449 if (TCG_TARGET_HAS_goto_ptr
) {
450 tcg_debug_assert(s
->code_gen_epilogue
!= NULL
);
454 void tcg_func_start(TCGContext
*s
)
457 s
->nb_temps
= s
->nb_globals
;
459 /* No temps have been previously allocated for size or locality. */
460 memset(s
->free_temps
, 0, sizeof(s
->free_temps
));
463 s
->current_frame_offset
= s
->frame_start
;
465 #ifdef CONFIG_DEBUG_TCG
466 s
->goto_tb_issue_mask
= 0;
469 s
->gen_op_buf
[0].next
= 1;
470 s
->gen_op_buf
[0].prev
= 0;
471 s
->gen_next_op_idx
= 1;
472 s
->gen_next_parm_idx
= 0;
475 static inline int temp_idx(TCGContext
*s
, TCGTemp
*ts
)
477 ptrdiff_t n
= ts
- s
->temps
;
478 tcg_debug_assert(n
>= 0 && n
< s
->nb_temps
);
482 static inline TCGTemp
*tcg_temp_alloc(TCGContext
*s
)
484 int n
= s
->nb_temps
++;
485 tcg_debug_assert(n
< TCG_MAX_TEMPS
);
486 return memset(&s
->temps
[n
], 0, sizeof(TCGTemp
));
489 static inline TCGTemp
*tcg_global_alloc(TCGContext
*s
)
491 tcg_debug_assert(s
->nb_globals
== s
->nb_temps
);
493 return tcg_temp_alloc(s
);
496 static int tcg_global_reg_new_internal(TCGContext
*s
, TCGType type
,
497 TCGReg reg
, const char *name
)
501 if (TCG_TARGET_REG_BITS
== 32 && type
!= TCG_TYPE_I32
) {
505 ts
= tcg_global_alloc(s
);
506 ts
->base_type
= type
;
511 tcg_regset_set_reg(s
->reserved_regs
, reg
);
513 return temp_idx(s
, ts
);
516 void tcg_set_frame(TCGContext
*s
, TCGReg reg
, intptr_t start
, intptr_t size
)
519 s
->frame_start
= start
;
520 s
->frame_end
= start
+ size
;
521 idx
= tcg_global_reg_new_internal(s
, TCG_TYPE_PTR
, reg
, "_frame");
522 s
->frame_temp
= &s
->temps
[idx
];
525 TCGv_i32
tcg_global_reg_new_i32(TCGReg reg
, const char *name
)
527 TCGContext
*s
= &tcg_ctx
;
530 if (tcg_regset_test_reg(s
->reserved_regs
, reg
)) {
533 idx
= tcg_global_reg_new_internal(s
, TCG_TYPE_I32
, reg
, name
);
534 return MAKE_TCGV_I32(idx
);
537 TCGv_i64
tcg_global_reg_new_i64(TCGReg reg
, const char *name
)
539 TCGContext
*s
= &tcg_ctx
;
542 if (tcg_regset_test_reg(s
->reserved_regs
, reg
)) {
545 idx
= tcg_global_reg_new_internal(s
, TCG_TYPE_I64
, reg
, name
);
546 return MAKE_TCGV_I64(idx
);
549 int tcg_global_mem_new_internal(TCGType type
, TCGv_ptr base
,
550 intptr_t offset
, const char *name
)
552 TCGContext
*s
= &tcg_ctx
;
553 TCGTemp
*base_ts
= &s
->temps
[GET_TCGV_PTR(base
)];
554 TCGTemp
*ts
= tcg_global_alloc(s
);
555 int indirect_reg
= 0, bigendian
= 0;
556 #ifdef HOST_WORDS_BIGENDIAN
560 if (!base_ts
->fixed_reg
) {
561 /* We do not support double-indirect registers. */
562 tcg_debug_assert(!base_ts
->indirect_reg
);
563 base_ts
->indirect_base
= 1;
564 s
->nb_indirects
+= (TCG_TARGET_REG_BITS
== 32 && type
== TCG_TYPE_I64
569 if (TCG_TARGET_REG_BITS
== 32 && type
== TCG_TYPE_I64
) {
570 TCGTemp
*ts2
= tcg_global_alloc(s
);
573 ts
->base_type
= TCG_TYPE_I64
;
574 ts
->type
= TCG_TYPE_I32
;
575 ts
->indirect_reg
= indirect_reg
;
576 ts
->mem_allocated
= 1;
577 ts
->mem_base
= base_ts
;
578 ts
->mem_offset
= offset
+ bigendian
* 4;
579 pstrcpy(buf
, sizeof(buf
), name
);
580 pstrcat(buf
, sizeof(buf
), "_0");
581 ts
->name
= strdup(buf
);
583 tcg_debug_assert(ts2
== ts
+ 1);
584 ts2
->base_type
= TCG_TYPE_I64
;
585 ts2
->type
= TCG_TYPE_I32
;
586 ts2
->indirect_reg
= indirect_reg
;
587 ts2
->mem_allocated
= 1;
588 ts2
->mem_base
= base_ts
;
589 ts2
->mem_offset
= offset
+ (1 - bigendian
) * 4;
590 pstrcpy(buf
, sizeof(buf
), name
);
591 pstrcat(buf
, sizeof(buf
), "_1");
592 ts2
->name
= strdup(buf
);
594 ts
->base_type
= type
;
596 ts
->indirect_reg
= indirect_reg
;
597 ts
->mem_allocated
= 1;
598 ts
->mem_base
= base_ts
;
599 ts
->mem_offset
= offset
;
602 return temp_idx(s
, ts
);
605 static int tcg_temp_new_internal(TCGType type
, int temp_local
)
607 TCGContext
*s
= &tcg_ctx
;
611 k
= type
+ (temp_local
? TCG_TYPE_COUNT
: 0);
612 idx
= find_first_bit(s
->free_temps
[k
].l
, TCG_MAX_TEMPS
);
613 if (idx
< TCG_MAX_TEMPS
) {
614 /* There is already an available temp with the right type. */
615 clear_bit(idx
, s
->free_temps
[k
].l
);
618 ts
->temp_allocated
= 1;
619 tcg_debug_assert(ts
->base_type
== type
);
620 tcg_debug_assert(ts
->temp_local
== temp_local
);
622 ts
= tcg_temp_alloc(s
);
623 if (TCG_TARGET_REG_BITS
== 32 && type
== TCG_TYPE_I64
) {
624 TCGTemp
*ts2
= tcg_temp_alloc(s
);
626 ts
->base_type
= type
;
627 ts
->type
= TCG_TYPE_I32
;
628 ts
->temp_allocated
= 1;
629 ts
->temp_local
= temp_local
;
631 tcg_debug_assert(ts2
== ts
+ 1);
632 ts2
->base_type
= TCG_TYPE_I64
;
633 ts2
->type
= TCG_TYPE_I32
;
634 ts2
->temp_allocated
= 1;
635 ts2
->temp_local
= temp_local
;
637 ts
->base_type
= type
;
639 ts
->temp_allocated
= 1;
640 ts
->temp_local
= temp_local
;
642 idx
= temp_idx(s
, ts
);
645 #if defined(CONFIG_DEBUG_TCG)
651 TCGv_i32
tcg_temp_new_internal_i32(int temp_local
)
655 idx
= tcg_temp_new_internal(TCG_TYPE_I32
, temp_local
);
656 return MAKE_TCGV_I32(idx
);
659 TCGv_i64
tcg_temp_new_internal_i64(int temp_local
)
663 idx
= tcg_temp_new_internal(TCG_TYPE_I64
, temp_local
);
664 return MAKE_TCGV_I64(idx
);
667 static void tcg_temp_free_internal(int idx
)
669 TCGContext
*s
= &tcg_ctx
;
673 #if defined(CONFIG_DEBUG_TCG)
675 if (s
->temps_in_use
< 0) {
676 fprintf(stderr
, "More temporaries freed than allocated!\n");
680 tcg_debug_assert(idx
>= s
->nb_globals
&& idx
< s
->nb_temps
);
682 tcg_debug_assert(ts
->temp_allocated
!= 0);
683 ts
->temp_allocated
= 0;
685 k
= ts
->base_type
+ (ts
->temp_local
? TCG_TYPE_COUNT
: 0);
686 set_bit(idx
, s
->free_temps
[k
].l
);
689 void tcg_temp_free_i32(TCGv_i32 arg
)
691 tcg_temp_free_internal(GET_TCGV_I32(arg
));
694 void tcg_temp_free_i64(TCGv_i64 arg
)
696 tcg_temp_free_internal(GET_TCGV_I64(arg
));
699 TCGv_i32
tcg_const_i32(int32_t val
)
702 t0
= tcg_temp_new_i32();
703 tcg_gen_movi_i32(t0
, val
);
707 TCGv_i64
tcg_const_i64(int64_t val
)
710 t0
= tcg_temp_new_i64();
711 tcg_gen_movi_i64(t0
, val
);
715 TCGv_i32
tcg_const_local_i32(int32_t val
)
718 t0
= tcg_temp_local_new_i32();
719 tcg_gen_movi_i32(t0
, val
);
723 TCGv_i64
tcg_const_local_i64(int64_t val
)
726 t0
= tcg_temp_local_new_i64();
727 tcg_gen_movi_i64(t0
, val
);
731 #if defined(CONFIG_DEBUG_TCG)
732 void tcg_clear_temp_count(void)
734 TCGContext
*s
= &tcg_ctx
;
738 int tcg_check_temp_count(void)
740 TCGContext
*s
= &tcg_ctx
;
741 if (s
->temps_in_use
) {
742 /* Clear the count so that we don't give another
743 * warning immediately next time around.
752 /* Note: we convert the 64 bit args to 32 bit and do some alignment
753 and endian swap. Maybe it would be better to do the alignment
754 and endian swap in tcg_reg_alloc_call(). */
755 void tcg_gen_callN(TCGContext
*s
, void *func
, TCGArg ret
,
756 int nargs
, TCGArg
*args
)
758 int i
, real_args
, nb_rets
, pi
, pi_first
;
759 unsigned sizemask
, flags
;
762 info
= g_hash_table_lookup(s
->helpers
, (gpointer
)func
);
764 sizemask
= info
->sizemask
;
766 #if defined(__sparc__) && !defined(__arch64__) \
767 && !defined(CONFIG_TCG_INTERPRETER)
768 /* We have 64-bit values in one register, but need to pass as two
769 separate parameters. Split them. */
770 int orig_sizemask
= sizemask
;
771 int orig_nargs
= nargs
;
774 TCGV_UNUSED_I64(retl
);
775 TCGV_UNUSED_I64(reth
);
777 TCGArg
*split_args
= __builtin_alloca(sizeof(TCGArg
) * nargs
* 2);
778 for (i
= real_args
= 0; i
< nargs
; ++i
) {
779 int is_64bit
= sizemask
& (1 << (i
+1)*2);
781 TCGv_i64 orig
= MAKE_TCGV_I64(args
[i
]);
782 TCGv_i32 h
= tcg_temp_new_i32();
783 TCGv_i32 l
= tcg_temp_new_i32();
784 tcg_gen_extr_i64_i32(l
, h
, orig
);
785 split_args
[real_args
++] = GET_TCGV_I32(h
);
786 split_args
[real_args
++] = GET_TCGV_I32(l
);
788 split_args
[real_args
++] = args
[i
];
795 #elif defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS == 64
796 for (i
= 0; i
< nargs
; ++i
) {
797 int is_64bit
= sizemask
& (1 << (i
+1)*2);
798 int is_signed
= sizemask
& (2 << (i
+1)*2);
800 TCGv_i64 temp
= tcg_temp_new_i64();
801 TCGv_i64 orig
= MAKE_TCGV_I64(args
[i
]);
803 tcg_gen_ext32s_i64(temp
, orig
);
805 tcg_gen_ext32u_i64(temp
, orig
);
807 args
[i
] = GET_TCGV_I64(temp
);
810 #endif /* TCG_TARGET_EXTEND_ARGS */
812 pi_first
= pi
= s
->gen_next_parm_idx
;
813 if (ret
!= TCG_CALL_DUMMY_ARG
) {
814 #if defined(__sparc__) && !defined(__arch64__) \
815 && !defined(CONFIG_TCG_INTERPRETER)
816 if (orig_sizemask
& 1) {
817 /* The 32-bit ABI is going to return the 64-bit value in
818 the %o0/%o1 register pair. Prepare for this by using
819 two return temporaries, and reassemble below. */
820 retl
= tcg_temp_new_i64();
821 reth
= tcg_temp_new_i64();
822 s
->gen_opparam_buf
[pi
++] = GET_TCGV_I64(reth
);
823 s
->gen_opparam_buf
[pi
++] = GET_TCGV_I64(retl
);
826 s
->gen_opparam_buf
[pi
++] = ret
;
830 if (TCG_TARGET_REG_BITS
< 64 && (sizemask
& 1)) {
831 #ifdef HOST_WORDS_BIGENDIAN
832 s
->gen_opparam_buf
[pi
++] = ret
+ 1;
833 s
->gen_opparam_buf
[pi
++] = ret
;
835 s
->gen_opparam_buf
[pi
++] = ret
;
836 s
->gen_opparam_buf
[pi
++] = ret
+ 1;
840 s
->gen_opparam_buf
[pi
++] = ret
;
848 for (i
= 0; i
< nargs
; i
++) {
849 int is_64bit
= sizemask
& (1 << (i
+1)*2);
850 if (TCG_TARGET_REG_BITS
< 64 && is_64bit
) {
851 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
852 /* some targets want aligned 64 bit args */
854 s
->gen_opparam_buf
[pi
++] = TCG_CALL_DUMMY_ARG
;
858 /* If stack grows up, then we will be placing successive
859 arguments at lower addresses, which means we need to
860 reverse the order compared to how we would normally
861 treat either big or little-endian. For those arguments
862 that will wind up in registers, this still works for
863 HPPA (the only current STACK_GROWSUP target) since the
864 argument registers are *also* allocated in decreasing
865 order. If another such target is added, this logic may
866 have to get more complicated to differentiate between
867 stack arguments and register arguments. */
868 #if defined(HOST_WORDS_BIGENDIAN) != defined(TCG_TARGET_STACK_GROWSUP)
869 s
->gen_opparam_buf
[pi
++] = args
[i
] + 1;
870 s
->gen_opparam_buf
[pi
++] = args
[i
];
872 s
->gen_opparam_buf
[pi
++] = args
[i
];
873 s
->gen_opparam_buf
[pi
++] = args
[i
] + 1;
879 s
->gen_opparam_buf
[pi
++] = args
[i
];
882 s
->gen_opparam_buf
[pi
++] = (uintptr_t)func
;
883 s
->gen_opparam_buf
[pi
++] = flags
;
885 i
= s
->gen_next_op_idx
;
886 tcg_debug_assert(i
< OPC_BUF_SIZE
);
887 tcg_debug_assert(pi
<= OPPARAM_BUF_SIZE
);
889 /* Set links for sequential allocation during translation. */
890 s
->gen_op_buf
[i
] = (TCGOp
){
891 .opc
= INDEX_op_call
,
899 /* Make sure the calli field didn't overflow. */
900 tcg_debug_assert(s
->gen_op_buf
[i
].calli
== real_args
);
902 s
->gen_op_buf
[0].prev
= i
;
903 s
->gen_next_op_idx
= i
+ 1;
904 s
->gen_next_parm_idx
= pi
;
906 #if defined(__sparc__) && !defined(__arch64__) \
907 && !defined(CONFIG_TCG_INTERPRETER)
908 /* Free all of the parts we allocated above. */
909 for (i
= real_args
= 0; i
< orig_nargs
; ++i
) {
910 int is_64bit
= orig_sizemask
& (1 << (i
+1)*2);
912 TCGv_i32 h
= MAKE_TCGV_I32(args
[real_args
++]);
913 TCGv_i32 l
= MAKE_TCGV_I32(args
[real_args
++]);
914 tcg_temp_free_i32(h
);
915 tcg_temp_free_i32(l
);
920 if (orig_sizemask
& 1) {
921 /* The 32-bit ABI returned two 32-bit pieces. Re-assemble them.
922 Note that describing these as TCGv_i64 eliminates an unnecessary
923 zero-extension that tcg_gen_concat_i32_i64 would create. */
924 tcg_gen_concat32_i64(MAKE_TCGV_I64(ret
), retl
, reth
);
925 tcg_temp_free_i64(retl
);
926 tcg_temp_free_i64(reth
);
928 #elif defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS == 64
929 for (i
= 0; i
< nargs
; ++i
) {
930 int is_64bit
= sizemask
& (1 << (i
+1)*2);
932 TCGv_i64 temp
= MAKE_TCGV_I64(args
[i
]);
933 tcg_temp_free_i64(temp
);
936 #endif /* TCG_TARGET_EXTEND_ARGS */
939 static void tcg_reg_alloc_start(TCGContext
*s
)
943 for(i
= 0; i
< s
->nb_globals
; i
++) {
946 ts
->val_type
= TEMP_VAL_REG
;
948 ts
->val_type
= TEMP_VAL_MEM
;
951 for(i
= s
->nb_globals
; i
< s
->nb_temps
; i
++) {
953 if (ts
->temp_local
) {
954 ts
->val_type
= TEMP_VAL_MEM
;
956 ts
->val_type
= TEMP_VAL_DEAD
;
958 ts
->mem_allocated
= 0;
962 memset(s
->reg_to_temp
, 0, sizeof(s
->reg_to_temp
));
965 static char *tcg_get_arg_str_ptr(TCGContext
*s
, char *buf
, int buf_size
,
968 int idx
= temp_idx(s
, ts
);
970 if (idx
< s
->nb_globals
) {
971 pstrcpy(buf
, buf_size
, ts
->name
);
972 } else if (ts
->temp_local
) {
973 snprintf(buf
, buf_size
, "loc%d", idx
- s
->nb_globals
);
975 snprintf(buf
, buf_size
, "tmp%d", idx
- s
->nb_globals
);
980 static char *tcg_get_arg_str_idx(TCGContext
*s
, char *buf
,
981 int buf_size
, int idx
)
983 tcg_debug_assert(idx
>= 0 && idx
< s
->nb_temps
);
984 return tcg_get_arg_str_ptr(s
, buf
, buf_size
, &s
->temps
[idx
]);
987 /* Find helper name. */
988 static inline const char *tcg_find_helper(TCGContext
*s
, uintptr_t val
)
990 const char *ret
= NULL
;
992 TCGHelperInfo
*info
= g_hash_table_lookup(s
->helpers
, (gpointer
)val
);
1000 static const char * const cond_name
[] =
1002 [TCG_COND_NEVER
] = "never",
1003 [TCG_COND_ALWAYS
] = "always",
1004 [TCG_COND_EQ
] = "eq",
1005 [TCG_COND_NE
] = "ne",
1006 [TCG_COND_LT
] = "lt",
1007 [TCG_COND_GE
] = "ge",
1008 [TCG_COND_LE
] = "le",
1009 [TCG_COND_GT
] = "gt",
1010 [TCG_COND_LTU
] = "ltu",
1011 [TCG_COND_GEU
] = "geu",
1012 [TCG_COND_LEU
] = "leu",
1013 [TCG_COND_GTU
] = "gtu"
1016 static const char * const ldst_name
[] =
1032 static const char * const alignment_name
[(MO_AMASK
>> MO_ASHIFT
) + 1] = {
1034 [MO_UNALN
>> MO_ASHIFT
] = "un+",
1035 [MO_ALIGN
>> MO_ASHIFT
] = "",
1037 [MO_UNALN
>> MO_ASHIFT
] = "",
1038 [MO_ALIGN
>> MO_ASHIFT
] = "al+",
1040 [MO_ALIGN_2
>> MO_ASHIFT
] = "al2+",
1041 [MO_ALIGN_4
>> MO_ASHIFT
] = "al4+",
1042 [MO_ALIGN_8
>> MO_ASHIFT
] = "al8+",
1043 [MO_ALIGN_16
>> MO_ASHIFT
] = "al16+",
1044 [MO_ALIGN_32
>> MO_ASHIFT
] = "al32+",
1045 [MO_ALIGN_64
>> MO_ASHIFT
] = "al64+",
1048 void tcg_dump_ops(TCGContext
*s
)
1054 for (oi
= s
->gen_op_buf
[0].next
; oi
!= 0; oi
= op
->next
) {
1055 int i
, k
, nb_oargs
, nb_iargs
, nb_cargs
;
1056 const TCGOpDef
*def
;
1061 op
= &s
->gen_op_buf
[oi
];
1063 def
= &tcg_op_defs
[c
];
1064 args
= &s
->gen_opparam_buf
[op
->args
];
1066 if (c
== INDEX_op_insn_start
) {
1067 col
+= qemu_log("%s ----", oi
!= s
->gen_op_buf
[0].next
? "\n" : "");
1069 for (i
= 0; i
< TARGET_INSN_START_WORDS
; ++i
) {
1071 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
1072 a
= ((target_ulong
)args
[i
* 2 + 1] << 32) | args
[i
* 2];
1076 col
+= qemu_log(" " TARGET_FMT_lx
, a
);
1078 } else if (c
== INDEX_op_call
) {
1079 /* variable number of arguments */
1080 nb_oargs
= op
->callo
;
1081 nb_iargs
= op
->calli
;
1082 nb_cargs
= def
->nb_cargs
;
1084 /* function name, flags, out args */
1085 col
+= qemu_log(" %s %s,$0x%" TCG_PRIlx
",$%d", def
->name
,
1086 tcg_find_helper(s
, args
[nb_oargs
+ nb_iargs
]),
1087 args
[nb_oargs
+ nb_iargs
+ 1], nb_oargs
);
1088 for (i
= 0; i
< nb_oargs
; i
++) {
1089 col
+= qemu_log(",%s", tcg_get_arg_str_idx(s
, buf
, sizeof(buf
),
1092 for (i
= 0; i
< nb_iargs
; i
++) {
1093 TCGArg arg
= args
[nb_oargs
+ i
];
1094 const char *t
= "<dummy>";
1095 if (arg
!= TCG_CALL_DUMMY_ARG
) {
1096 t
= tcg_get_arg_str_idx(s
, buf
, sizeof(buf
), arg
);
1098 col
+= qemu_log(",%s", t
);
1101 col
+= qemu_log(" %s ", def
->name
);
1103 nb_oargs
= def
->nb_oargs
;
1104 nb_iargs
= def
->nb_iargs
;
1105 nb_cargs
= def
->nb_cargs
;
1108 for (i
= 0; i
< nb_oargs
; i
++) {
1110 col
+= qemu_log(",");
1112 col
+= qemu_log("%s", tcg_get_arg_str_idx(s
, buf
, sizeof(buf
),
1115 for (i
= 0; i
< nb_iargs
; i
++) {
1117 col
+= qemu_log(",");
1119 col
+= qemu_log("%s", tcg_get_arg_str_idx(s
, buf
, sizeof(buf
),
1123 case INDEX_op_brcond_i32
:
1124 case INDEX_op_setcond_i32
:
1125 case INDEX_op_movcond_i32
:
1126 case INDEX_op_brcond2_i32
:
1127 case INDEX_op_setcond2_i32
:
1128 case INDEX_op_brcond_i64
:
1129 case INDEX_op_setcond_i64
:
1130 case INDEX_op_movcond_i64
:
1131 if (args
[k
] < ARRAY_SIZE(cond_name
) && cond_name
[args
[k
]]) {
1132 col
+= qemu_log(",%s", cond_name
[args
[k
++]]);
1134 col
+= qemu_log(",$0x%" TCG_PRIlx
, args
[k
++]);
1138 case INDEX_op_qemu_ld_i32
:
1139 case INDEX_op_qemu_st_i32
:
1140 case INDEX_op_qemu_ld_i64
:
1141 case INDEX_op_qemu_st_i64
:
1143 TCGMemOpIdx oi
= args
[k
++];
1144 TCGMemOp op
= get_memop(oi
);
1145 unsigned ix
= get_mmuidx(oi
);
1147 if (op
& ~(MO_AMASK
| MO_BSWAP
| MO_SSIZE
)) {
1148 col
+= qemu_log(",$0x%x,%u", op
, ix
);
1150 const char *s_al
, *s_op
;
1151 s_al
= alignment_name
[(op
& MO_AMASK
) >> MO_ASHIFT
];
1152 s_op
= ldst_name
[op
& (MO_BSWAP
| MO_SSIZE
)];
1153 col
+= qemu_log(",%s%s,%u", s_al
, s_op
, ix
);
1163 case INDEX_op_set_label
:
1165 case INDEX_op_brcond_i32
:
1166 case INDEX_op_brcond_i64
:
1167 case INDEX_op_brcond2_i32
:
1168 col
+= qemu_log("%s$L%d", k
? "," : "", arg_label(args
[k
])->id
);
1174 for (; i
< nb_cargs
; i
++, k
++) {
1175 col
+= qemu_log("%s$0x%" TCG_PRIlx
, k
? "," : "", args
[k
]);
1179 unsigned life
= op
->life
;
1181 for (; col
< 48; ++col
) {
1182 putc(' ', qemu_logfile
);
1185 if (life
& (SYNC_ARG
* 3)) {
1187 for (i
= 0; i
< 2; ++i
) {
1188 if (life
& (SYNC_ARG
<< i
)) {
1196 for (i
= 0; life
; ++i
, life
>>= 1) {
1207 /* we give more priority to constraints with less registers */
1208 static int get_constraint_priority(const TCGOpDef
*def
, int k
)
1210 const TCGArgConstraint
*arg_ct
;
1213 arg_ct
= &def
->args_ct
[k
];
1214 if (arg_ct
->ct
& TCG_CT_ALIAS
) {
1215 /* an alias is equivalent to a single register */
1218 if (!(arg_ct
->ct
& TCG_CT_REG
))
1221 for(i
= 0; i
< TCG_TARGET_NB_REGS
; i
++) {
1222 if (tcg_regset_test_reg(arg_ct
->u
.regs
, i
))
1226 return TCG_TARGET_NB_REGS
- n
+ 1;
1229 /* sort from highest priority to lowest */
1230 static void sort_constraints(TCGOpDef
*def
, int start
, int n
)
1232 int i
, j
, p1
, p2
, tmp
;
1234 for(i
= 0; i
< n
; i
++)
1235 def
->sorted_args
[start
+ i
] = start
+ i
;
1238 for(i
= 0; i
< n
- 1; i
++) {
1239 for(j
= i
+ 1; j
< n
; j
++) {
1240 p1
= get_constraint_priority(def
, def
->sorted_args
[start
+ i
]);
1241 p2
= get_constraint_priority(def
, def
->sorted_args
[start
+ j
]);
1243 tmp
= def
->sorted_args
[start
+ i
];
1244 def
->sorted_args
[start
+ i
] = def
->sorted_args
[start
+ j
];
1245 def
->sorted_args
[start
+ j
] = tmp
;
1251 static void process_op_defs(TCGContext
*s
)
1255 for (op
= 0; op
< NB_OPS
; op
++) {
1256 TCGOpDef
*def
= &tcg_op_defs
[op
];
1257 const TCGTargetOpDef
*tdefs
;
1261 if (def
->flags
& TCG_OPF_NOT_PRESENT
) {
1265 nb_args
= def
->nb_iargs
+ def
->nb_oargs
;
1270 tdefs
= tcg_target_op_def(op
);
1271 /* Missing TCGTargetOpDef entry. */
1272 tcg_debug_assert(tdefs
!= NULL
);
1274 type
= (def
->flags
& TCG_OPF_64BIT
? TCG_TYPE_I64
: TCG_TYPE_I32
);
1275 for (i
= 0; i
< nb_args
; i
++) {
1276 const char *ct_str
= tdefs
->args_ct_str
[i
];
1277 /* Incomplete TCGTargetOpDef entry. */
1278 tcg_debug_assert(ct_str
!= NULL
);
1280 tcg_regset_clear(def
->args_ct
[i
].u
.regs
);
1281 def
->args_ct
[i
].ct
= 0;
1282 while (*ct_str
!= '\0') {
1286 int oarg
= *ct_str
- '0';
1287 tcg_debug_assert(ct_str
== tdefs
->args_ct_str
[i
]);
1288 tcg_debug_assert(oarg
< def
->nb_oargs
);
1289 tcg_debug_assert(def
->args_ct
[oarg
].ct
& TCG_CT_REG
);
1290 /* TCG_CT_ALIAS is for the output arguments.
1291 The input is tagged with TCG_CT_IALIAS. */
1292 def
->args_ct
[i
] = def
->args_ct
[oarg
];
1293 def
->args_ct
[oarg
].ct
|= TCG_CT_ALIAS
;
1294 def
->args_ct
[oarg
].alias_index
= i
;
1295 def
->args_ct
[i
].ct
|= TCG_CT_IALIAS
;
1296 def
->args_ct
[i
].alias_index
= oarg
;
1301 def
->args_ct
[i
].ct
|= TCG_CT_NEWREG
;
1305 def
->args_ct
[i
].ct
|= TCG_CT_CONST
;
1309 ct_str
= target_parse_constraint(&def
->args_ct
[i
],
1311 /* Typo in TCGTargetOpDef constraint. */
1312 tcg_debug_assert(ct_str
!= NULL
);
1317 /* TCGTargetOpDef entry with too much information? */
1318 tcg_debug_assert(i
== TCG_MAX_OP_ARGS
|| tdefs
->args_ct_str
[i
] == NULL
);
1320 /* sort the constraints (XXX: this is just an heuristic) */
1321 sort_constraints(def
, 0, def
->nb_oargs
);
1322 sort_constraints(def
, def
->nb_oargs
, def
->nb_iargs
);
1326 void tcg_op_remove(TCGContext
*s
, TCGOp
*op
)
1328 int next
= op
->next
;
1329 int prev
= op
->prev
;
1331 /* We should never attempt to remove the list terminator. */
1332 tcg_debug_assert(op
!= &s
->gen_op_buf
[0]);
1334 s
->gen_op_buf
[next
].prev
= prev
;
1335 s
->gen_op_buf
[prev
].next
= next
;
1337 memset(op
, 0, sizeof(*op
));
1339 #ifdef CONFIG_PROFILER
1344 TCGOp
*tcg_op_insert_before(TCGContext
*s
, TCGOp
*old_op
,
1345 TCGOpcode opc
, int nargs
)
1347 int oi
= s
->gen_next_op_idx
;
1348 int pi
= s
->gen_next_parm_idx
;
1349 int prev
= old_op
->prev
;
1350 int next
= old_op
- s
->gen_op_buf
;
1353 tcg_debug_assert(oi
< OPC_BUF_SIZE
);
1354 tcg_debug_assert(pi
+ nargs
<= OPPARAM_BUF_SIZE
);
1355 s
->gen_next_op_idx
= oi
+ 1;
1356 s
->gen_next_parm_idx
= pi
+ nargs
;
1358 new_op
= &s
->gen_op_buf
[oi
];
1365 s
->gen_op_buf
[prev
].next
= oi
;
1371 TCGOp
*tcg_op_insert_after(TCGContext
*s
, TCGOp
*old_op
,
1372 TCGOpcode opc
, int nargs
)
1374 int oi
= s
->gen_next_op_idx
;
1375 int pi
= s
->gen_next_parm_idx
;
1376 int prev
= old_op
- s
->gen_op_buf
;
1377 int next
= old_op
->next
;
1380 tcg_debug_assert(oi
< OPC_BUF_SIZE
);
1381 tcg_debug_assert(pi
+ nargs
<= OPPARAM_BUF_SIZE
);
1382 s
->gen_next_op_idx
= oi
+ 1;
1383 s
->gen_next_parm_idx
= pi
+ nargs
;
1385 new_op
= &s
->gen_op_buf
[oi
];
1392 s
->gen_op_buf
[next
].prev
= oi
;
1401 #define IS_DEAD_ARG(n) (arg_life & (DEAD_ARG << (n)))
1402 #define NEED_SYNC_ARG(n) (arg_life & (SYNC_ARG << (n)))
1404 /* liveness analysis: end of function: all temps are dead, and globals
1405 should be in memory. */
1406 static inline void tcg_la_func_end(TCGContext
*s
, uint8_t *temp_state
)
1408 memset(temp_state
, TS_DEAD
| TS_MEM
, s
->nb_globals
);
1409 memset(temp_state
+ s
->nb_globals
, TS_DEAD
, s
->nb_temps
- s
->nb_globals
);
1412 /* liveness analysis: end of basic block: all temps are dead, globals
1413 and local temps should be in memory. */
1414 static inline void tcg_la_bb_end(TCGContext
*s
, uint8_t *temp_state
)
1418 tcg_la_func_end(s
, temp_state
);
1419 for (i
= s
->nb_globals
, n
= s
->nb_temps
; i
< n
; i
++) {
1420 if (s
->temps
[i
].temp_local
) {
1421 temp_state
[i
] |= TS_MEM
;
1426 /* Liveness analysis : update the opc_arg_life array to tell if a
1427 given input arguments is dead. Instructions updating dead
1428 temporaries are removed. */
1429 static void liveness_pass_1(TCGContext
*s
, uint8_t *temp_state
)
1431 int nb_globals
= s
->nb_globals
;
1434 tcg_la_func_end(s
, temp_state
);
1436 for (oi
= s
->gen_op_buf
[0].prev
; oi
!= 0; oi
= oi_prev
) {
1437 int i
, nb_iargs
, nb_oargs
;
1438 TCGOpcode opc_new
, opc_new2
;
1440 TCGLifeData arg_life
= 0;
1443 TCGOp
* const op
= &s
->gen_op_buf
[oi
];
1444 TCGArg
* const args
= &s
->gen_opparam_buf
[op
->args
];
1445 TCGOpcode opc
= op
->opc
;
1446 const TCGOpDef
*def
= &tcg_op_defs
[opc
];
1455 nb_oargs
= op
->callo
;
1456 nb_iargs
= op
->calli
;
1457 call_flags
= args
[nb_oargs
+ nb_iargs
+ 1];
1459 /* pure functions can be removed if their result is unused */
1460 if (call_flags
& TCG_CALL_NO_SIDE_EFFECTS
) {
1461 for (i
= 0; i
< nb_oargs
; i
++) {
1463 if (temp_state
[arg
] != TS_DEAD
) {
1464 goto do_not_remove_call
;
1471 /* output args are dead */
1472 for (i
= 0; i
< nb_oargs
; i
++) {
1474 if (temp_state
[arg
] & TS_DEAD
) {
1475 arg_life
|= DEAD_ARG
<< i
;
1477 if (temp_state
[arg
] & TS_MEM
) {
1478 arg_life
|= SYNC_ARG
<< i
;
1480 temp_state
[arg
] = TS_DEAD
;
1483 if (!(call_flags
& (TCG_CALL_NO_WRITE_GLOBALS
|
1484 TCG_CALL_NO_READ_GLOBALS
))) {
1485 /* globals should go back to memory */
1486 memset(temp_state
, TS_DEAD
| TS_MEM
, nb_globals
);
1487 } else if (!(call_flags
& TCG_CALL_NO_READ_GLOBALS
)) {
1488 /* globals should be synced to memory */
1489 for (i
= 0; i
< nb_globals
; i
++) {
1490 temp_state
[i
] |= TS_MEM
;
1494 /* record arguments that die in this helper */
1495 for (i
= nb_oargs
; i
< nb_iargs
+ nb_oargs
; i
++) {
1497 if (arg
!= TCG_CALL_DUMMY_ARG
) {
1498 if (temp_state
[arg
] & TS_DEAD
) {
1499 arg_life
|= DEAD_ARG
<< i
;
1503 /* input arguments are live for preceding opcodes */
1504 for (i
= nb_oargs
; i
< nb_iargs
+ nb_oargs
; i
++) {
1506 if (arg
!= TCG_CALL_DUMMY_ARG
) {
1507 temp_state
[arg
] &= ~TS_DEAD
;
1513 case INDEX_op_insn_start
:
1515 case INDEX_op_discard
:
1516 /* mark the temporary as dead */
1517 temp_state
[args
[0]] = TS_DEAD
;
1520 case INDEX_op_add2_i32
:
1521 opc_new
= INDEX_op_add_i32
;
1523 case INDEX_op_sub2_i32
:
1524 opc_new
= INDEX_op_sub_i32
;
1526 case INDEX_op_add2_i64
:
1527 opc_new
= INDEX_op_add_i64
;
1529 case INDEX_op_sub2_i64
:
1530 opc_new
= INDEX_op_sub_i64
;
1534 /* Test if the high part of the operation is dead, but not
1535 the low part. The result can be optimized to a simple
1536 add or sub. This happens often for x86_64 guest when the
1537 cpu mode is set to 32 bit. */
1538 if (temp_state
[args
[1]] == TS_DEAD
) {
1539 if (temp_state
[args
[0]] == TS_DEAD
) {
1542 /* Replace the opcode and adjust the args in place,
1543 leaving 3 unused args at the end. */
1544 op
->opc
= opc
= opc_new
;
1547 /* Fall through and mark the single-word operation live. */
1553 case INDEX_op_mulu2_i32
:
1554 opc_new
= INDEX_op_mul_i32
;
1555 opc_new2
= INDEX_op_muluh_i32
;
1556 have_opc_new2
= TCG_TARGET_HAS_muluh_i32
;
1558 case INDEX_op_muls2_i32
:
1559 opc_new
= INDEX_op_mul_i32
;
1560 opc_new2
= INDEX_op_mulsh_i32
;
1561 have_opc_new2
= TCG_TARGET_HAS_mulsh_i32
;
1563 case INDEX_op_mulu2_i64
:
1564 opc_new
= INDEX_op_mul_i64
;
1565 opc_new2
= INDEX_op_muluh_i64
;
1566 have_opc_new2
= TCG_TARGET_HAS_muluh_i64
;
1568 case INDEX_op_muls2_i64
:
1569 opc_new
= INDEX_op_mul_i64
;
1570 opc_new2
= INDEX_op_mulsh_i64
;
1571 have_opc_new2
= TCG_TARGET_HAS_mulsh_i64
;
1576 if (temp_state
[args
[1]] == TS_DEAD
) {
1577 if (temp_state
[args
[0]] == TS_DEAD
) {
1578 /* Both parts of the operation are dead. */
1581 /* The high part of the operation is dead; generate the low. */
1582 op
->opc
= opc
= opc_new
;
1585 } else if (temp_state
[args
[0]] == TS_DEAD
&& have_opc_new2
) {
1586 /* The low part of the operation is dead; generate the high. */
1587 op
->opc
= opc
= opc_new2
;
1594 /* Mark the single-word operation live. */
1599 /* XXX: optimize by hardcoding common cases (e.g. triadic ops) */
1600 nb_iargs
= def
->nb_iargs
;
1601 nb_oargs
= def
->nb_oargs
;
1603 /* Test if the operation can be removed because all
1604 its outputs are dead. We assume that nb_oargs == 0
1605 implies side effects */
1606 if (!(def
->flags
& TCG_OPF_SIDE_EFFECTS
) && nb_oargs
!= 0) {
1607 for (i
= 0; i
< nb_oargs
; i
++) {
1608 if (temp_state
[args
[i
]] != TS_DEAD
) {
1613 tcg_op_remove(s
, op
);
1616 /* output args are dead */
1617 for (i
= 0; i
< nb_oargs
; i
++) {
1619 if (temp_state
[arg
] & TS_DEAD
) {
1620 arg_life
|= DEAD_ARG
<< i
;
1622 if (temp_state
[arg
] & TS_MEM
) {
1623 arg_life
|= SYNC_ARG
<< i
;
1625 temp_state
[arg
] = TS_DEAD
;
1628 /* if end of basic block, update */
1629 if (def
->flags
& TCG_OPF_BB_END
) {
1630 tcg_la_bb_end(s
, temp_state
);
1631 } else if (def
->flags
& TCG_OPF_SIDE_EFFECTS
) {
1632 /* globals should be synced to memory */
1633 for (i
= 0; i
< nb_globals
; i
++) {
1634 temp_state
[i
] |= TS_MEM
;
1638 /* record arguments that die in this opcode */
1639 for (i
= nb_oargs
; i
< nb_oargs
+ nb_iargs
; i
++) {
1641 if (temp_state
[arg
] & TS_DEAD
) {
1642 arg_life
|= DEAD_ARG
<< i
;
1645 /* input arguments are live for preceding opcodes */
1646 for (i
= nb_oargs
; i
< nb_oargs
+ nb_iargs
; i
++) {
1647 temp_state
[args
[i
]] &= ~TS_DEAD
;
1652 op
->life
= arg_life
;
1656 /* Liveness analysis: Convert indirect regs to direct temporaries. */
1657 static bool liveness_pass_2(TCGContext
*s
, uint8_t *temp_state
)
1659 int nb_globals
= s
->nb_globals
;
1662 bool changes
= false;
1664 dir_temps
= tcg_malloc(nb_globals
* sizeof(int16_t));
1665 memset(dir_temps
, 0, nb_globals
* sizeof(int16_t));
1667 /* Create a temporary for each indirect global. */
1668 for (i
= 0; i
< nb_globals
; ++i
) {
1669 TCGTemp
*its
= &s
->temps
[i
];
1670 if (its
->indirect_reg
) {
1671 TCGTemp
*dts
= tcg_temp_alloc(s
);
1672 dts
->type
= its
->type
;
1673 dts
->base_type
= its
->base_type
;
1674 dir_temps
[i
] = temp_idx(s
, dts
);
1678 memset(temp_state
, TS_DEAD
, nb_globals
);
1680 for (oi
= s
->gen_op_buf
[0].next
; oi
!= 0; oi
= oi_next
) {
1681 TCGOp
*op
= &s
->gen_op_buf
[oi
];
1682 TCGArg
*args
= &s
->gen_opparam_buf
[op
->args
];
1683 TCGOpcode opc
= op
->opc
;
1684 const TCGOpDef
*def
= &tcg_op_defs
[opc
];
1685 TCGLifeData arg_life
= op
->life
;
1686 int nb_iargs
, nb_oargs
, call_flags
;
1691 if (opc
== INDEX_op_call
) {
1692 nb_oargs
= op
->callo
;
1693 nb_iargs
= op
->calli
;
1694 call_flags
= args
[nb_oargs
+ nb_iargs
+ 1];
1696 nb_iargs
= def
->nb_iargs
;
1697 nb_oargs
= def
->nb_oargs
;
1699 /* Set flags similar to how calls require. */
1700 if (def
->flags
& TCG_OPF_BB_END
) {
1701 /* Like writing globals: save_globals */
1703 } else if (def
->flags
& TCG_OPF_SIDE_EFFECTS
) {
1704 /* Like reading globals: sync_globals */
1705 call_flags
= TCG_CALL_NO_WRITE_GLOBALS
;
1707 /* No effect on globals. */
1708 call_flags
= (TCG_CALL_NO_READ_GLOBALS
|
1709 TCG_CALL_NO_WRITE_GLOBALS
);
1713 /* Make sure that input arguments are available. */
1714 for (i
= nb_oargs
; i
< nb_iargs
+ nb_oargs
; i
++) {
1716 /* Note this unsigned test catches TCG_CALL_ARG_DUMMY too. */
1717 if (arg
< nb_globals
) {
1718 dir
= dir_temps
[arg
];
1719 if (dir
!= 0 && temp_state
[arg
] == TS_DEAD
) {
1720 TCGTemp
*its
= &s
->temps
[arg
];
1721 TCGOpcode lopc
= (its
->type
== TCG_TYPE_I32
1724 TCGOp
*lop
= tcg_op_insert_before(s
, op
, lopc
, 3);
1725 TCGArg
*largs
= &s
->gen_opparam_buf
[lop
->args
];
1728 largs
[1] = temp_idx(s
, its
->mem_base
);
1729 largs
[2] = its
->mem_offset
;
1731 /* Loaded, but synced with memory. */
1732 temp_state
[arg
] = TS_MEM
;
1737 /* Perform input replacement, and mark inputs that became dead.
1738 No action is required except keeping temp_state up to date
1739 so that we reload when needed. */
1740 for (i
= nb_oargs
; i
< nb_iargs
+ nb_oargs
; i
++) {
1742 if (arg
< nb_globals
) {
1743 dir
= dir_temps
[arg
];
1747 if (IS_DEAD_ARG(i
)) {
1748 temp_state
[arg
] = TS_DEAD
;
1754 /* Liveness analysis should ensure that the following are
1755 all correct, for call sites and basic block end points. */
1756 if (call_flags
& TCG_CALL_NO_READ_GLOBALS
) {
1758 } else if (call_flags
& TCG_CALL_NO_WRITE_GLOBALS
) {
1759 for (i
= 0; i
< nb_globals
; ++i
) {
1760 /* Liveness should see that globals are synced back,
1761 that is, either TS_DEAD or TS_MEM. */
1762 tcg_debug_assert(dir_temps
[i
] == 0
1763 || temp_state
[i
] != 0);
1766 for (i
= 0; i
< nb_globals
; ++i
) {
1767 /* Liveness should see that globals are saved back,
1768 that is, TS_DEAD, waiting to be reloaded. */
1769 tcg_debug_assert(dir_temps
[i
] == 0
1770 || temp_state
[i
] == TS_DEAD
);
1774 /* Outputs become available. */
1775 for (i
= 0; i
< nb_oargs
; i
++) {
1777 if (arg
>= nb_globals
) {
1780 dir
= dir_temps
[arg
];
1787 /* The output is now live and modified. */
1788 temp_state
[arg
] = 0;
1790 /* Sync outputs upon their last write. */
1791 if (NEED_SYNC_ARG(i
)) {
1792 TCGTemp
*its
= &s
->temps
[arg
];
1793 TCGOpcode sopc
= (its
->type
== TCG_TYPE_I32
1796 TCGOp
*sop
= tcg_op_insert_after(s
, op
, sopc
, 3);
1797 TCGArg
*sargs
= &s
->gen_opparam_buf
[sop
->args
];
1800 sargs
[1] = temp_idx(s
, its
->mem_base
);
1801 sargs
[2] = its
->mem_offset
;
1803 temp_state
[arg
] = TS_MEM
;
1805 /* Drop outputs that are dead. */
1806 if (IS_DEAD_ARG(i
)) {
1807 temp_state
[arg
] = TS_DEAD
;
1815 #ifdef CONFIG_DEBUG_TCG
1816 static void dump_regs(TCGContext
*s
)
1822 for(i
= 0; i
< s
->nb_temps
; i
++) {
1824 printf(" %10s: ", tcg_get_arg_str_idx(s
, buf
, sizeof(buf
), i
));
1825 switch(ts
->val_type
) {
1827 printf("%s", tcg_target_reg_names
[ts
->reg
]);
1830 printf("%d(%s)", (int)ts
->mem_offset
,
1831 tcg_target_reg_names
[ts
->mem_base
->reg
]);
1833 case TEMP_VAL_CONST
:
1834 printf("$0x%" TCG_PRIlx
, ts
->val
);
1846 for(i
= 0; i
< TCG_TARGET_NB_REGS
; i
++) {
1847 if (s
->reg_to_temp
[i
] != NULL
) {
1849 tcg_target_reg_names
[i
],
1850 tcg_get_arg_str_ptr(s
, buf
, sizeof(buf
), s
->reg_to_temp
[i
]));
1855 static void check_regs(TCGContext
*s
)
1862 for (reg
= 0; reg
< TCG_TARGET_NB_REGS
; reg
++) {
1863 ts
= s
->reg_to_temp
[reg
];
1865 if (ts
->val_type
!= TEMP_VAL_REG
|| ts
->reg
!= reg
) {
1866 printf("Inconsistency for register %s:\n",
1867 tcg_target_reg_names
[reg
]);
1872 for (k
= 0; k
< s
->nb_temps
; k
++) {
1874 if (ts
->val_type
== TEMP_VAL_REG
&& !ts
->fixed_reg
1875 && s
->reg_to_temp
[ts
->reg
] != ts
) {
1876 printf("Inconsistency for temp %s:\n",
1877 tcg_get_arg_str_ptr(s
, buf
, sizeof(buf
), ts
));
1879 printf("reg state:\n");
1887 static void temp_allocate_frame(TCGContext
*s
, int temp
)
1890 ts
= &s
->temps
[temp
];
1891 #if !(defined(__sparc__) && TCG_TARGET_REG_BITS == 64)
1892 /* Sparc64 stack is accessed with offset of 2047 */
1893 s
->current_frame_offset
= (s
->current_frame_offset
+
1894 (tcg_target_long
)sizeof(tcg_target_long
) - 1) &
1895 ~(sizeof(tcg_target_long
) - 1);
1897 if (s
->current_frame_offset
+ (tcg_target_long
)sizeof(tcg_target_long
) >
1901 ts
->mem_offset
= s
->current_frame_offset
;
1902 ts
->mem_base
= s
->frame_temp
;
1903 ts
->mem_allocated
= 1;
1904 s
->current_frame_offset
+= sizeof(tcg_target_long
);
1907 static void temp_load(TCGContext
*, TCGTemp
*, TCGRegSet
, TCGRegSet
);
1909 /* Mark a temporary as free or dead. If 'free_or_dead' is negative,
1910 mark it free; otherwise mark it dead. */
1911 static void temp_free_or_dead(TCGContext
*s
, TCGTemp
*ts
, int free_or_dead
)
1913 if (ts
->fixed_reg
) {
1916 if (ts
->val_type
== TEMP_VAL_REG
) {
1917 s
->reg_to_temp
[ts
->reg
] = NULL
;
1919 ts
->val_type
= (free_or_dead
< 0
1921 || temp_idx(s
, ts
) < s
->nb_globals
1922 ? TEMP_VAL_MEM
: TEMP_VAL_DEAD
);
1925 /* Mark a temporary as dead. */
1926 static inline void temp_dead(TCGContext
*s
, TCGTemp
*ts
)
1928 temp_free_or_dead(s
, ts
, 1);
1931 /* Sync a temporary to memory. 'allocated_regs' is used in case a temporary
1932 registers needs to be allocated to store a constant. If 'free_or_dead'
1933 is non-zero, subsequently release the temporary; if it is positive, the
1934 temp is dead; if it is negative, the temp is free. */
1935 static void temp_sync(TCGContext
*s
, TCGTemp
*ts
,
1936 TCGRegSet allocated_regs
, int free_or_dead
)
1938 if (ts
->fixed_reg
) {
1941 if (!ts
->mem_coherent
) {
1942 if (!ts
->mem_allocated
) {
1943 temp_allocate_frame(s
, temp_idx(s
, ts
));
1945 switch (ts
->val_type
) {
1946 case TEMP_VAL_CONST
:
1947 /* If we're going to free the temp immediately, then we won't
1948 require it later in a register, so attempt to store the
1949 constant to memory directly. */
1951 && tcg_out_sti(s
, ts
->type
, ts
->val
,
1952 ts
->mem_base
->reg
, ts
->mem_offset
)) {
1955 temp_load(s
, ts
, tcg_target_available_regs
[ts
->type
],
1960 tcg_out_st(s
, ts
->type
, ts
->reg
,
1961 ts
->mem_base
->reg
, ts
->mem_offset
);
1971 ts
->mem_coherent
= 1;
1974 temp_free_or_dead(s
, ts
, free_or_dead
);
1978 /* free register 'reg' by spilling the corresponding temporary if necessary */
1979 static void tcg_reg_free(TCGContext
*s
, TCGReg reg
, TCGRegSet allocated_regs
)
1981 TCGTemp
*ts
= s
->reg_to_temp
[reg
];
1983 temp_sync(s
, ts
, allocated_regs
, -1);
1987 /* Allocate a register belonging to reg1 & ~reg2 */
1988 static TCGReg
tcg_reg_alloc(TCGContext
*s
, TCGRegSet desired_regs
,
1989 TCGRegSet allocated_regs
, bool rev
)
1991 int i
, n
= ARRAY_SIZE(tcg_target_reg_alloc_order
);
1996 tcg_regset_andnot(reg_ct
, desired_regs
, allocated_regs
);
1997 order
= rev
? indirect_reg_alloc_order
: tcg_target_reg_alloc_order
;
1999 /* first try free registers */
2000 for(i
= 0; i
< n
; i
++) {
2002 if (tcg_regset_test_reg(reg_ct
, reg
) && s
->reg_to_temp
[reg
] == NULL
)
2006 /* XXX: do better spill choice */
2007 for(i
= 0; i
< n
; i
++) {
2009 if (tcg_regset_test_reg(reg_ct
, reg
)) {
2010 tcg_reg_free(s
, reg
, allocated_regs
);
2018 /* Make sure the temporary is in a register. If needed, allocate the register
2019 from DESIRED while avoiding ALLOCATED. */
2020 static void temp_load(TCGContext
*s
, TCGTemp
*ts
, TCGRegSet desired_regs
,
2021 TCGRegSet allocated_regs
)
2025 switch (ts
->val_type
) {
2028 case TEMP_VAL_CONST
:
2029 reg
= tcg_reg_alloc(s
, desired_regs
, allocated_regs
, ts
->indirect_base
);
2030 tcg_out_movi(s
, ts
->type
, reg
, ts
->val
);
2031 ts
->mem_coherent
= 0;
2034 reg
= tcg_reg_alloc(s
, desired_regs
, allocated_regs
, ts
->indirect_base
);
2035 tcg_out_ld(s
, ts
->type
, reg
, ts
->mem_base
->reg
, ts
->mem_offset
);
2036 ts
->mem_coherent
= 1;
2043 ts
->val_type
= TEMP_VAL_REG
;
2044 s
->reg_to_temp
[reg
] = ts
;
2047 /* Save a temporary to memory. 'allocated_regs' is used in case a
2048 temporary registers needs to be allocated to store a constant. */
2049 static void temp_save(TCGContext
*s
, TCGTemp
*ts
, TCGRegSet allocated_regs
)
2051 /* The liveness analysis already ensures that globals are back
2052 in memory. Keep an tcg_debug_assert for safety. */
2053 tcg_debug_assert(ts
->val_type
== TEMP_VAL_MEM
|| ts
->fixed_reg
);
2056 /* save globals to their canonical location and assume they can be
2057 modified be the following code. 'allocated_regs' is used in case a
2058 temporary registers needs to be allocated to store a constant. */
2059 static void save_globals(TCGContext
*s
, TCGRegSet allocated_regs
)
2063 for (i
= 0; i
< s
->nb_globals
; i
++) {
2064 temp_save(s
, &s
->temps
[i
], allocated_regs
);
2068 /* sync globals to their canonical location and assume they can be
2069 read by the following code. 'allocated_regs' is used in case a
2070 temporary registers needs to be allocated to store a constant. */
2071 static void sync_globals(TCGContext
*s
, TCGRegSet allocated_regs
)
2075 for (i
= 0; i
< s
->nb_globals
; i
++) {
2076 TCGTemp
*ts
= &s
->temps
[i
];
2077 tcg_debug_assert(ts
->val_type
!= TEMP_VAL_REG
2079 || ts
->mem_coherent
);
2083 /* at the end of a basic block, we assume all temporaries are dead and
2084 all globals are stored at their canonical location. */
2085 static void tcg_reg_alloc_bb_end(TCGContext
*s
, TCGRegSet allocated_regs
)
2089 for (i
= s
->nb_globals
; i
< s
->nb_temps
; i
++) {
2090 TCGTemp
*ts
= &s
->temps
[i
];
2091 if (ts
->temp_local
) {
2092 temp_save(s
, ts
, allocated_regs
);
2094 /* The liveness analysis already ensures that temps are dead.
2095 Keep an tcg_debug_assert for safety. */
2096 tcg_debug_assert(ts
->val_type
== TEMP_VAL_DEAD
);
2100 save_globals(s
, allocated_regs
);
2103 static void tcg_reg_alloc_do_movi(TCGContext
*s
, TCGTemp
*ots
,
2104 tcg_target_ulong val
, TCGLifeData arg_life
)
2106 if (ots
->fixed_reg
) {
2107 /* For fixed registers, we do not do any constant propagation. */
2108 tcg_out_movi(s
, ots
->type
, ots
->reg
, val
);
2112 /* The movi is not explicitly generated here. */
2113 if (ots
->val_type
== TEMP_VAL_REG
) {
2114 s
->reg_to_temp
[ots
->reg
] = NULL
;
2116 ots
->val_type
= TEMP_VAL_CONST
;
2118 ots
->mem_coherent
= 0;
2119 if (NEED_SYNC_ARG(0)) {
2120 temp_sync(s
, ots
, s
->reserved_regs
, IS_DEAD_ARG(0));
2121 } else if (IS_DEAD_ARG(0)) {
2126 static void tcg_reg_alloc_movi(TCGContext
*s
, const TCGArg
*args
,
2127 TCGLifeData arg_life
)
2129 TCGTemp
*ots
= &s
->temps
[args
[0]];
2130 tcg_target_ulong val
= args
[1];
2132 tcg_reg_alloc_do_movi(s
, ots
, val
, arg_life
);
2135 static void tcg_reg_alloc_mov(TCGContext
*s
, const TCGOpDef
*def
,
2136 const TCGArg
*args
, TCGLifeData arg_life
)
2138 TCGRegSet allocated_regs
;
2140 TCGType otype
, itype
;
2142 tcg_regset_set(allocated_regs
, s
->reserved_regs
);
2143 ots
= &s
->temps
[args
[0]];
2144 ts
= &s
->temps
[args
[1]];
2146 /* Note that otype != itype for no-op truncation. */
2150 if (ts
->val_type
== TEMP_VAL_CONST
) {
2151 /* propagate constant or generate sti */
2152 tcg_target_ulong val
= ts
->val
;
2153 if (IS_DEAD_ARG(1)) {
2156 tcg_reg_alloc_do_movi(s
, ots
, val
, arg_life
);
2160 /* If the source value is in memory we're going to be forced
2161 to have it in a register in order to perform the copy. Copy
2162 the SOURCE value into its own register first, that way we
2163 don't have to reload SOURCE the next time it is used. */
2164 if (ts
->val_type
== TEMP_VAL_MEM
) {
2165 temp_load(s
, ts
, tcg_target_available_regs
[itype
], allocated_regs
);
2168 tcg_debug_assert(ts
->val_type
== TEMP_VAL_REG
);
2169 if (IS_DEAD_ARG(0) && !ots
->fixed_reg
) {
2170 /* mov to a non-saved dead register makes no sense (even with
2171 liveness analysis disabled). */
2172 tcg_debug_assert(NEED_SYNC_ARG(0));
2173 if (!ots
->mem_allocated
) {
2174 temp_allocate_frame(s
, args
[0]);
2176 tcg_out_st(s
, otype
, ts
->reg
, ots
->mem_base
->reg
, ots
->mem_offset
);
2177 if (IS_DEAD_ARG(1)) {
2182 if (IS_DEAD_ARG(1) && !ts
->fixed_reg
&& !ots
->fixed_reg
) {
2183 /* the mov can be suppressed */
2184 if (ots
->val_type
== TEMP_VAL_REG
) {
2185 s
->reg_to_temp
[ots
->reg
] = NULL
;
2190 if (ots
->val_type
!= TEMP_VAL_REG
) {
2191 /* When allocating a new register, make sure to not spill the
2193 tcg_regset_set_reg(allocated_regs
, ts
->reg
);
2194 ots
->reg
= tcg_reg_alloc(s
, tcg_target_available_regs
[otype
],
2195 allocated_regs
, ots
->indirect_base
);
2197 tcg_out_mov(s
, otype
, ots
->reg
, ts
->reg
);
2199 ots
->val_type
= TEMP_VAL_REG
;
2200 ots
->mem_coherent
= 0;
2201 s
->reg_to_temp
[ots
->reg
] = ots
;
2202 if (NEED_SYNC_ARG(0)) {
2203 temp_sync(s
, ots
, allocated_regs
, 0);
2208 static void tcg_reg_alloc_op(TCGContext
*s
,
2209 const TCGOpDef
*def
, TCGOpcode opc
,
2210 const TCGArg
*args
, TCGLifeData arg_life
)
2212 TCGRegSet i_allocated_regs
;
2213 TCGRegSet o_allocated_regs
;
2214 int i
, k
, nb_iargs
, nb_oargs
;
2217 const TCGArgConstraint
*arg_ct
;
2219 TCGArg new_args
[TCG_MAX_OP_ARGS
];
2220 int const_args
[TCG_MAX_OP_ARGS
];
2222 nb_oargs
= def
->nb_oargs
;
2223 nb_iargs
= def
->nb_iargs
;
2225 /* copy constants */
2226 memcpy(new_args
+ nb_oargs
+ nb_iargs
,
2227 args
+ nb_oargs
+ nb_iargs
,
2228 sizeof(TCGArg
) * def
->nb_cargs
);
2230 tcg_regset_set(i_allocated_regs
, s
->reserved_regs
);
2231 tcg_regset_set(o_allocated_regs
, s
->reserved_regs
);
2233 /* satisfy input constraints */
2234 for(k
= 0; k
< nb_iargs
; k
++) {
2235 i
= def
->sorted_args
[nb_oargs
+ k
];
2237 arg_ct
= &def
->args_ct
[i
];
2238 ts
= &s
->temps
[arg
];
2240 if (ts
->val_type
== TEMP_VAL_CONST
2241 && tcg_target_const_match(ts
->val
, ts
->type
, arg_ct
)) {
2242 /* constant is OK for instruction */
2244 new_args
[i
] = ts
->val
;
2248 temp_load(s
, ts
, arg_ct
->u
.regs
, i_allocated_regs
);
2250 if (arg_ct
->ct
& TCG_CT_IALIAS
) {
2251 if (ts
->fixed_reg
) {
2252 /* if fixed register, we must allocate a new register
2253 if the alias is not the same register */
2254 if (arg
!= args
[arg_ct
->alias_index
])
2255 goto allocate_in_reg
;
2257 /* if the input is aliased to an output and if it is
2258 not dead after the instruction, we must allocate
2259 a new register and move it */
2260 if (!IS_DEAD_ARG(i
)) {
2261 goto allocate_in_reg
;
2263 /* check if the current register has already been allocated
2264 for another input aliased to an output */
2266 for (k2
= 0 ; k2
< k
; k2
++) {
2267 i2
= def
->sorted_args
[nb_oargs
+ k2
];
2268 if ((def
->args_ct
[i2
].ct
& TCG_CT_IALIAS
) &&
2269 (new_args
[i2
] == ts
->reg
)) {
2270 goto allocate_in_reg
;
2276 if (tcg_regset_test_reg(arg_ct
->u
.regs
, reg
)) {
2277 /* nothing to do : the constraint is satisfied */
2280 /* allocate a new register matching the constraint
2281 and move the temporary register into it */
2282 reg
= tcg_reg_alloc(s
, arg_ct
->u
.regs
, i_allocated_regs
,
2284 tcg_out_mov(s
, ts
->type
, reg
, ts
->reg
);
2288 tcg_regset_set_reg(i_allocated_regs
, reg
);
2292 /* mark dead temporaries and free the associated registers */
2293 for (i
= nb_oargs
; i
< nb_oargs
+ nb_iargs
; i
++) {
2294 if (IS_DEAD_ARG(i
)) {
2295 temp_dead(s
, &s
->temps
[args
[i
]]);
2299 if (def
->flags
& TCG_OPF_BB_END
) {
2300 tcg_reg_alloc_bb_end(s
, i_allocated_regs
);
2302 if (def
->flags
& TCG_OPF_CALL_CLOBBER
) {
2303 /* XXX: permit generic clobber register list ? */
2304 for (i
= 0; i
< TCG_TARGET_NB_REGS
; i
++) {
2305 if (tcg_regset_test_reg(tcg_target_call_clobber_regs
, i
)) {
2306 tcg_reg_free(s
, i
, i_allocated_regs
);
2310 if (def
->flags
& TCG_OPF_SIDE_EFFECTS
) {
2311 /* sync globals if the op has side effects and might trigger
2313 sync_globals(s
, i_allocated_regs
);
2316 /* satisfy the output constraints */
2317 for(k
= 0; k
< nb_oargs
; k
++) {
2318 i
= def
->sorted_args
[k
];
2320 arg_ct
= &def
->args_ct
[i
];
2321 ts
= &s
->temps
[arg
];
2322 if ((arg_ct
->ct
& TCG_CT_ALIAS
)
2323 && !const_args
[arg_ct
->alias_index
]) {
2324 reg
= new_args
[arg_ct
->alias_index
];
2325 } else if (arg_ct
->ct
& TCG_CT_NEWREG
) {
2326 reg
= tcg_reg_alloc(s
, arg_ct
->u
.regs
,
2327 i_allocated_regs
| o_allocated_regs
,
2330 /* if fixed register, we try to use it */
2332 if (ts
->fixed_reg
&&
2333 tcg_regset_test_reg(arg_ct
->u
.regs
, reg
)) {
2336 reg
= tcg_reg_alloc(s
, arg_ct
->u
.regs
, o_allocated_regs
,
2339 tcg_regset_set_reg(o_allocated_regs
, reg
);
2340 /* if a fixed register is used, then a move will be done afterwards */
2341 if (!ts
->fixed_reg
) {
2342 if (ts
->val_type
== TEMP_VAL_REG
) {
2343 s
->reg_to_temp
[ts
->reg
] = NULL
;
2345 ts
->val_type
= TEMP_VAL_REG
;
2347 /* temp value is modified, so the value kept in memory is
2348 potentially not the same */
2349 ts
->mem_coherent
= 0;
2350 s
->reg_to_temp
[reg
] = ts
;
2357 /* emit instruction */
2358 tcg_out_op(s
, opc
, new_args
, const_args
);
2360 /* move the outputs in the correct register if needed */
2361 for(i
= 0; i
< nb_oargs
; i
++) {
2362 ts
= &s
->temps
[args
[i
]];
2364 if (ts
->fixed_reg
&& ts
->reg
!= reg
) {
2365 tcg_out_mov(s
, ts
->type
, ts
->reg
, reg
);
2367 if (NEED_SYNC_ARG(i
)) {
2368 temp_sync(s
, ts
, o_allocated_regs
, IS_DEAD_ARG(i
));
2369 } else if (IS_DEAD_ARG(i
)) {
2375 #ifdef TCG_TARGET_STACK_GROWSUP
2376 #define STACK_DIR(x) (-(x))
2378 #define STACK_DIR(x) (x)
2381 static void tcg_reg_alloc_call(TCGContext
*s
, int nb_oargs
, int nb_iargs
,
2382 const TCGArg
* const args
, TCGLifeData arg_life
)
2384 int flags
, nb_regs
, i
;
2388 intptr_t stack_offset
;
2389 size_t call_stack_size
;
2390 tcg_insn_unit
*func_addr
;
2392 TCGRegSet allocated_regs
;
2394 func_addr
= (tcg_insn_unit
*)(intptr_t)args
[nb_oargs
+ nb_iargs
];
2395 flags
= args
[nb_oargs
+ nb_iargs
+ 1];
2397 nb_regs
= ARRAY_SIZE(tcg_target_call_iarg_regs
);
2398 if (nb_regs
> nb_iargs
) {
2402 /* assign stack slots first */
2403 call_stack_size
= (nb_iargs
- nb_regs
) * sizeof(tcg_target_long
);
2404 call_stack_size
= (call_stack_size
+ TCG_TARGET_STACK_ALIGN
- 1) &
2405 ~(TCG_TARGET_STACK_ALIGN
- 1);
2406 allocate_args
= (call_stack_size
> TCG_STATIC_CALL_ARGS_SIZE
);
2407 if (allocate_args
) {
2408 /* XXX: if more than TCG_STATIC_CALL_ARGS_SIZE is needed,
2409 preallocate call stack */
2413 stack_offset
= TCG_TARGET_CALL_STACK_OFFSET
;
2414 for(i
= nb_regs
; i
< nb_iargs
; i
++) {
2415 arg
= args
[nb_oargs
+ i
];
2416 #ifdef TCG_TARGET_STACK_GROWSUP
2417 stack_offset
-= sizeof(tcg_target_long
);
2419 if (arg
!= TCG_CALL_DUMMY_ARG
) {
2420 ts
= &s
->temps
[arg
];
2421 temp_load(s
, ts
, tcg_target_available_regs
[ts
->type
],
2423 tcg_out_st(s
, ts
->type
, ts
->reg
, TCG_REG_CALL_STACK
, stack_offset
);
2425 #ifndef TCG_TARGET_STACK_GROWSUP
2426 stack_offset
+= sizeof(tcg_target_long
);
2430 /* assign input registers */
2431 tcg_regset_set(allocated_regs
, s
->reserved_regs
);
2432 for(i
= 0; i
< nb_regs
; i
++) {
2433 arg
= args
[nb_oargs
+ i
];
2434 if (arg
!= TCG_CALL_DUMMY_ARG
) {
2435 ts
= &s
->temps
[arg
];
2436 reg
= tcg_target_call_iarg_regs
[i
];
2437 tcg_reg_free(s
, reg
, allocated_regs
);
2439 if (ts
->val_type
== TEMP_VAL_REG
) {
2440 if (ts
->reg
!= reg
) {
2441 tcg_out_mov(s
, ts
->type
, reg
, ts
->reg
);
2446 tcg_regset_clear(arg_set
);
2447 tcg_regset_set_reg(arg_set
, reg
);
2448 temp_load(s
, ts
, arg_set
, allocated_regs
);
2451 tcg_regset_set_reg(allocated_regs
, reg
);
2455 /* mark dead temporaries and free the associated registers */
2456 for(i
= nb_oargs
; i
< nb_iargs
+ nb_oargs
; i
++) {
2457 if (IS_DEAD_ARG(i
)) {
2458 temp_dead(s
, &s
->temps
[args
[i
]]);
2462 /* clobber call registers */
2463 for (i
= 0; i
< TCG_TARGET_NB_REGS
; i
++) {
2464 if (tcg_regset_test_reg(tcg_target_call_clobber_regs
, i
)) {
2465 tcg_reg_free(s
, i
, allocated_regs
);
2469 /* Save globals if they might be written by the helper, sync them if
2470 they might be read. */
2471 if (flags
& TCG_CALL_NO_READ_GLOBALS
) {
2473 } else if (flags
& TCG_CALL_NO_WRITE_GLOBALS
) {
2474 sync_globals(s
, allocated_regs
);
2476 save_globals(s
, allocated_regs
);
2479 tcg_out_call(s
, func_addr
);
2481 /* assign output registers and emit moves if needed */
2482 for(i
= 0; i
< nb_oargs
; i
++) {
2484 ts
= &s
->temps
[arg
];
2485 reg
= tcg_target_call_oarg_regs
[i
];
2486 tcg_debug_assert(s
->reg_to_temp
[reg
] == NULL
);
2488 if (ts
->fixed_reg
) {
2489 if (ts
->reg
!= reg
) {
2490 tcg_out_mov(s
, ts
->type
, ts
->reg
, reg
);
2493 if (ts
->val_type
== TEMP_VAL_REG
) {
2494 s
->reg_to_temp
[ts
->reg
] = NULL
;
2496 ts
->val_type
= TEMP_VAL_REG
;
2498 ts
->mem_coherent
= 0;
2499 s
->reg_to_temp
[reg
] = ts
;
2500 if (NEED_SYNC_ARG(i
)) {
2501 temp_sync(s
, ts
, allocated_regs
, IS_DEAD_ARG(i
));
2502 } else if (IS_DEAD_ARG(i
)) {
2509 #ifdef CONFIG_PROFILER
2511 static int64_t tcg_table_op_count
[NB_OPS
];
2513 void tcg_dump_op_count(FILE *f
, fprintf_function cpu_fprintf
)
2517 for (i
= 0; i
< NB_OPS
; i
++) {
2518 cpu_fprintf(f
, "%s %" PRId64
"\n", tcg_op_defs
[i
].name
,
2519 tcg_table_op_count
[i
]);
2523 void tcg_dump_op_count(FILE *f
, fprintf_function cpu_fprintf
)
2525 cpu_fprintf(f
, "[TCG profiler not compiled]\n");
2530 int tcg_gen_code(TCGContext
*s
, TranslationBlock
*tb
)
2532 int i
, oi
, oi_next
, num_insns
;
2534 #ifdef CONFIG_PROFILER
2538 n
= s
->gen_op_buf
[0].prev
+ 1;
2540 if (n
> s
->op_count_max
) {
2541 s
->op_count_max
= n
;
2546 if (n
> s
->temp_count_max
) {
2547 s
->temp_count_max
= n
;
2553 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
)
2554 && qemu_log_in_addr_range(tb
->pc
))) {
2563 #ifdef CONFIG_PROFILER
2564 s
->opt_time
-= profile_getclock();
2567 #ifdef USE_TCG_OPTIMIZATIONS
2571 #ifdef CONFIG_PROFILER
2572 s
->opt_time
+= profile_getclock();
2573 s
->la_time
-= profile_getclock();
2577 uint8_t *temp_state
= tcg_malloc(s
->nb_temps
+ s
->nb_indirects
);
2579 liveness_pass_1(s
, temp_state
);
2581 if (s
->nb_indirects
> 0) {
2583 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_IND
)
2584 && qemu_log_in_addr_range(tb
->pc
))) {
2586 qemu_log("OP before indirect lowering:\n");
2592 /* Replace indirect temps with direct temps. */
2593 if (liveness_pass_2(s
, temp_state
)) {
2594 /* If changes were made, re-run liveness. */
2595 liveness_pass_1(s
, temp_state
);
2600 #ifdef CONFIG_PROFILER
2601 s
->la_time
+= profile_getclock();
2605 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT
)
2606 && qemu_log_in_addr_range(tb
->pc
))) {
2608 qemu_log("OP after optimization and liveness analysis:\n");
2615 tcg_reg_alloc_start(s
);
2617 s
->code_buf
= tb
->tc_ptr
;
2618 s
->code_ptr
= tb
->tc_ptr
;
2620 #ifdef TCG_TARGET_NEED_LDST_LABELS
2621 s
->ldst_labels
= NULL
;
2623 #ifdef TCG_TARGET_NEED_POOL_LABELS
2624 s
->pool_labels
= NULL
;
2628 for (oi
= s
->gen_op_buf
[0].next
; oi
!= 0; oi
= oi_next
) {
2629 TCGOp
* const op
= &s
->gen_op_buf
[oi
];
2630 TCGArg
* const args
= &s
->gen_opparam_buf
[op
->args
];
2631 TCGOpcode opc
= op
->opc
;
2632 const TCGOpDef
*def
= &tcg_op_defs
[opc
];
2633 TCGLifeData arg_life
= op
->life
;
2636 #ifdef CONFIG_PROFILER
2637 tcg_table_op_count
[opc
]++;
2641 case INDEX_op_mov_i32
:
2642 case INDEX_op_mov_i64
:
2643 tcg_reg_alloc_mov(s
, def
, args
, arg_life
);
2645 case INDEX_op_movi_i32
:
2646 case INDEX_op_movi_i64
:
2647 tcg_reg_alloc_movi(s
, args
, arg_life
);
2649 case INDEX_op_insn_start
:
2650 if (num_insns
>= 0) {
2651 s
->gen_insn_end_off
[num_insns
] = tcg_current_code_size(s
);
2654 for (i
= 0; i
< TARGET_INSN_START_WORDS
; ++i
) {
2656 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
2657 a
= ((target_ulong
)args
[i
* 2 + 1] << 32) | args
[i
* 2];
2661 s
->gen_insn_data
[num_insns
][i
] = a
;
2664 case INDEX_op_discard
:
2665 temp_dead(s
, &s
->temps
[args
[0]]);
2667 case INDEX_op_set_label
:
2668 tcg_reg_alloc_bb_end(s
, s
->reserved_regs
);
2669 tcg_out_label(s
, arg_label(args
[0]), s
->code_ptr
);
2672 tcg_reg_alloc_call(s
, op
->callo
, op
->calli
, args
, arg_life
);
2675 /* Sanity check that we've not introduced any unhandled opcodes. */
2676 if (def
->flags
& TCG_OPF_NOT_PRESENT
) {
2679 /* Note: in order to speed up the code, it would be much
2680 faster to have specialized register allocator functions for
2681 some common argument patterns */
2682 tcg_reg_alloc_op(s
, def
, opc
, args
, arg_life
);
2685 #ifdef CONFIG_DEBUG_TCG
2688 /* Test for (pending) buffer overflow. The assumption is that any
2689 one operation beginning below the high water mark cannot overrun
2690 the buffer completely. Thus we can test for overflow after
2691 generating code without having to check during generation. */
2692 if (unlikely((void *)s
->code_ptr
> s
->code_gen_highwater
)) {
2696 tcg_debug_assert(num_insns
>= 0);
2697 s
->gen_insn_end_off
[num_insns
] = tcg_current_code_size(s
);
2699 /* Generate TB finalization at the end of block */
2700 #ifdef TCG_TARGET_NEED_LDST_LABELS
2701 if (!tcg_out_ldst_finalize(s
)) {
2705 #ifdef TCG_TARGET_NEED_POOL_LABELS
2706 if (!tcg_out_pool_finalize(s
)) {
2711 /* flush instruction cache */
2712 flush_icache_range((uintptr_t)s
->code_buf
, (uintptr_t)s
->code_ptr
);
2714 return tcg_current_code_size(s
);
2717 #ifdef CONFIG_PROFILER
2718 void tcg_dump_info(FILE *f
, fprintf_function cpu_fprintf
)
2720 TCGContext
*s
= &tcg_ctx
;
2721 int64_t tb_count
= s
->tb_count
;
2722 int64_t tb_div_count
= tb_count
? tb_count
: 1;
2723 int64_t tot
= s
->interm_time
+ s
->code_time
;
2725 cpu_fprintf(f
, "JIT cycles %" PRId64
" (%0.3f s at 2.4 GHz)\n",
2727 cpu_fprintf(f
, "translated TBs %" PRId64
" (aborted=%" PRId64
" %0.1f%%)\n",
2728 tb_count
, s
->tb_count1
- tb_count
,
2729 (double)(s
->tb_count1
- s
->tb_count
)
2730 / (s
->tb_count1
? s
->tb_count1
: 1) * 100.0);
2731 cpu_fprintf(f
, "avg ops/TB %0.1f max=%d\n",
2732 (double)s
->op_count
/ tb_div_count
, s
->op_count_max
);
2733 cpu_fprintf(f
, "deleted ops/TB %0.2f\n",
2734 (double)s
->del_op_count
/ tb_div_count
);
2735 cpu_fprintf(f
, "avg temps/TB %0.2f max=%d\n",
2736 (double)s
->temp_count
/ tb_div_count
, s
->temp_count_max
);
2737 cpu_fprintf(f
, "avg host code/TB %0.1f\n",
2738 (double)s
->code_out_len
/ tb_div_count
);
2739 cpu_fprintf(f
, "avg search data/TB %0.1f\n",
2740 (double)s
->search_out_len
/ tb_div_count
);
2742 cpu_fprintf(f
, "cycles/op %0.1f\n",
2743 s
->op_count
? (double)tot
/ s
->op_count
: 0);
2744 cpu_fprintf(f
, "cycles/in byte %0.1f\n",
2745 s
->code_in_len
? (double)tot
/ s
->code_in_len
: 0);
2746 cpu_fprintf(f
, "cycles/out byte %0.1f\n",
2747 s
->code_out_len
? (double)tot
/ s
->code_out_len
: 0);
2748 cpu_fprintf(f
, "cycles/search byte %0.1f\n",
2749 s
->search_out_len
? (double)tot
/ s
->search_out_len
: 0);
2753 cpu_fprintf(f
, " gen_interm time %0.1f%%\n",
2754 (double)s
->interm_time
/ tot
* 100.0);
2755 cpu_fprintf(f
, " gen_code time %0.1f%%\n",
2756 (double)s
->code_time
/ tot
* 100.0);
2757 cpu_fprintf(f
, "optim./code time %0.1f%%\n",
2758 (double)s
->opt_time
/ (s
->code_time
? s
->code_time
: 1)
2760 cpu_fprintf(f
, "liveness/code time %0.1f%%\n",
2761 (double)s
->la_time
/ (s
->code_time
? s
->code_time
: 1) * 100.0);
2762 cpu_fprintf(f
, "cpu_restore count %" PRId64
"\n",
2764 cpu_fprintf(f
, " avg cycles %0.1f\n",
2765 s
->restore_count
? (double)s
->restore_time
/ s
->restore_count
: 0);
2768 void tcg_dump_info(FILE *f
, fprintf_function cpu_fprintf
)
2770 cpu_fprintf(f
, "[TCG profiler not compiled]\n");
2774 #ifdef ELF_HOST_MACHINE
2775 /* In order to use this feature, the backend needs to do three things:
2777 (1) Define ELF_HOST_MACHINE to indicate both what value to
2778 put into the ELF image and to indicate support for the feature.
2780 (2) Define tcg_register_jit. This should create a buffer containing
2781 the contents of a .debug_frame section that describes the post-
2782 prologue unwind info for the tcg machine.
2784 (3) Call tcg_register_jit_int, with the constructed .debug_frame.
2787 /* Begin GDB interface. THE FOLLOWING MUST MATCH GDB DOCS. */
2794 struct jit_code_entry
{
2795 struct jit_code_entry
*next_entry
;
2796 struct jit_code_entry
*prev_entry
;
2797 const void *symfile_addr
;
2798 uint64_t symfile_size
;
2801 struct jit_descriptor
{
2803 uint32_t action_flag
;
2804 struct jit_code_entry
*relevant_entry
;
2805 struct jit_code_entry
*first_entry
;
2808 void __jit_debug_register_code(void) __attribute__((noinline
));
2809 void __jit_debug_register_code(void)
2814 /* Must statically initialize the version, because GDB may check
2815 the version before we can set it. */
2816 struct jit_descriptor __jit_debug_descriptor
= { 1, 0, 0, 0 };
2818 /* End GDB interface. */
2820 static int find_string(const char *strtab
, const char *str
)
2822 const char *p
= strtab
+ 1;
2825 if (strcmp(p
, str
) == 0) {
2832 static void tcg_register_jit_int(void *buf_ptr
, size_t buf_size
,
2833 const void *debug_frame
,
2834 size_t debug_frame_size
)
2836 struct __attribute__((packed
)) DebugInfo
{
2843 uintptr_t cu_low_pc
;
2844 uintptr_t cu_high_pc
;
2847 uintptr_t fn_low_pc
;
2848 uintptr_t fn_high_pc
;
2857 struct DebugInfo di
;
2862 struct ElfImage
*img
;
2864 static const struct ElfImage img_template
= {
2866 .e_ident
[EI_MAG0
] = ELFMAG0
,
2867 .e_ident
[EI_MAG1
] = ELFMAG1
,
2868 .e_ident
[EI_MAG2
] = ELFMAG2
,
2869 .e_ident
[EI_MAG3
] = ELFMAG3
,
2870 .e_ident
[EI_CLASS
] = ELF_CLASS
,
2871 .e_ident
[EI_DATA
] = ELF_DATA
,
2872 .e_ident
[EI_VERSION
] = EV_CURRENT
,
2874 .e_machine
= ELF_HOST_MACHINE
,
2875 .e_version
= EV_CURRENT
,
2876 .e_phoff
= offsetof(struct ElfImage
, phdr
),
2877 .e_shoff
= offsetof(struct ElfImage
, shdr
),
2878 .e_ehsize
= sizeof(ElfW(Shdr
)),
2879 .e_phentsize
= sizeof(ElfW(Phdr
)),
2881 .e_shentsize
= sizeof(ElfW(Shdr
)),
2882 .e_shnum
= ARRAY_SIZE(img
->shdr
),
2883 .e_shstrndx
= ARRAY_SIZE(img
->shdr
) - 1,
2884 #ifdef ELF_HOST_FLAGS
2885 .e_flags
= ELF_HOST_FLAGS
,
2888 .e_ident
[EI_OSABI
] = ELF_OSABI
,
2896 [0] = { .sh_type
= SHT_NULL
},
2897 /* Trick: The contents of code_gen_buffer are not present in
2898 this fake ELF file; that got allocated elsewhere. Therefore
2899 we mark .text as SHT_NOBITS (similar to .bss) so that readers
2900 will not look for contents. We can record any address. */
2902 .sh_type
= SHT_NOBITS
,
2903 .sh_flags
= SHF_EXECINSTR
| SHF_ALLOC
,
2905 [2] = { /* .debug_info */
2906 .sh_type
= SHT_PROGBITS
,
2907 .sh_offset
= offsetof(struct ElfImage
, di
),
2908 .sh_size
= sizeof(struct DebugInfo
),
2910 [3] = { /* .debug_abbrev */
2911 .sh_type
= SHT_PROGBITS
,
2912 .sh_offset
= offsetof(struct ElfImage
, da
),
2913 .sh_size
= sizeof(img
->da
),
2915 [4] = { /* .debug_frame */
2916 .sh_type
= SHT_PROGBITS
,
2917 .sh_offset
= sizeof(struct ElfImage
),
2919 [5] = { /* .symtab */
2920 .sh_type
= SHT_SYMTAB
,
2921 .sh_offset
= offsetof(struct ElfImage
, sym
),
2922 .sh_size
= sizeof(img
->sym
),
2924 .sh_link
= ARRAY_SIZE(img
->shdr
) - 1,
2925 .sh_entsize
= sizeof(ElfW(Sym
)),
2927 [6] = { /* .strtab */
2928 .sh_type
= SHT_STRTAB
,
2929 .sh_offset
= offsetof(struct ElfImage
, str
),
2930 .sh_size
= sizeof(img
->str
),
2934 [1] = { /* code_gen_buffer */
2935 .st_info
= ELF_ST_INFO(STB_GLOBAL
, STT_FUNC
),
2940 .len
= sizeof(struct DebugInfo
) - 4,
2942 .ptr_size
= sizeof(void *),
2944 .cu_lang
= 0x8001, /* DW_LANG_Mips_Assembler */
2946 .fn_name
= "code_gen_buffer"
2949 1, /* abbrev number (the cu) */
2950 0x11, 1, /* DW_TAG_compile_unit, has children */
2951 0x13, 0x5, /* DW_AT_language, DW_FORM_data2 */
2952 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */
2953 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */
2954 0, 0, /* end of abbrev */
2955 2, /* abbrev number (the fn) */
2956 0x2e, 0, /* DW_TAG_subprogram, no children */
2957 0x3, 0x8, /* DW_AT_name, DW_FORM_string */
2958 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */
2959 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */
2960 0, 0, /* end of abbrev */
2961 0 /* no more abbrev */
2963 .str
= "\0" ".text\0" ".debug_info\0" ".debug_abbrev\0"
2964 ".debug_frame\0" ".symtab\0" ".strtab\0" "code_gen_buffer",
2967 /* We only need a single jit entry; statically allocate it. */
2968 static struct jit_code_entry one_entry
;
2970 uintptr_t buf
= (uintptr_t)buf_ptr
;
2971 size_t img_size
= sizeof(struct ElfImage
) + debug_frame_size
;
2972 DebugFrameHeader
*dfh
;
2974 img
= g_malloc(img_size
);
2975 *img
= img_template
;
2977 img
->phdr
.p_vaddr
= buf
;
2978 img
->phdr
.p_paddr
= buf
;
2979 img
->phdr
.p_memsz
= buf_size
;
2981 img
->shdr
[1].sh_name
= find_string(img
->str
, ".text");
2982 img
->shdr
[1].sh_addr
= buf
;
2983 img
->shdr
[1].sh_size
= buf_size
;
2985 img
->shdr
[2].sh_name
= find_string(img
->str
, ".debug_info");
2986 img
->shdr
[3].sh_name
= find_string(img
->str
, ".debug_abbrev");
2988 img
->shdr
[4].sh_name
= find_string(img
->str
, ".debug_frame");
2989 img
->shdr
[4].sh_size
= debug_frame_size
;
2991 img
->shdr
[5].sh_name
= find_string(img
->str
, ".symtab");
2992 img
->shdr
[6].sh_name
= find_string(img
->str
, ".strtab");
2994 img
->sym
[1].st_name
= find_string(img
->str
, "code_gen_buffer");
2995 img
->sym
[1].st_value
= buf
;
2996 img
->sym
[1].st_size
= buf_size
;
2998 img
->di
.cu_low_pc
= buf
;
2999 img
->di
.cu_high_pc
= buf
+ buf_size
;
3000 img
->di
.fn_low_pc
= buf
;
3001 img
->di
.fn_high_pc
= buf
+ buf_size
;
3003 dfh
= (DebugFrameHeader
*)(img
+ 1);
3004 memcpy(dfh
, debug_frame
, debug_frame_size
);
3005 dfh
->fde
.func_start
= buf
;
3006 dfh
->fde
.func_len
= buf_size
;
3009 /* Enable this block to be able to debug the ELF image file creation.
3010 One can use readelf, objdump, or other inspection utilities. */
3012 FILE *f
= fopen("/tmp/qemu.jit", "w+b");
3014 if (fwrite(img
, img_size
, 1, f
) != img_size
) {
3015 /* Avoid stupid unused return value warning for fwrite. */
3022 one_entry
.symfile_addr
= img
;
3023 one_entry
.symfile_size
= img_size
;
3025 __jit_debug_descriptor
.action_flag
= JIT_REGISTER_FN
;
3026 __jit_debug_descriptor
.relevant_entry
= &one_entry
;
3027 __jit_debug_descriptor
.first_entry
= &one_entry
;
3028 __jit_debug_register_code();
3031 /* No support for the feature. Provide the entry point expected by exec.c,
3032 and implement the internal function we declared earlier. */
3034 static void tcg_register_jit_int(void *buf
, size_t size
,
3035 const void *debug_frame
,
3036 size_t debug_frame_size
)
3040 void tcg_register_jit(void *buf
, size_t buf_size
)
3043 #endif /* ELF_HOST_MACHINE */