2 * MIPS emulation helpers for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 #include "host-utils.h"
25 /*****************************************************************************/
26 /* Exceptions processing helpers */
28 void helper_raise_exception_err (uint32_t exception
, int error_code
)
31 if (exception
< 0x100)
32 qemu_log("%s: %d %d\n", __func__
, exception
, error_code
);
34 env
->exception_index
= exception
;
35 env
->error_code
= error_code
;
39 void helper_raise_exception (uint32_t exception
)
41 helper_raise_exception_err(exception
, 0);
44 void helper_interrupt_restart (void)
46 if (!(env
->CP0_Status
& (1 << CP0St_EXL
)) &&
47 !(env
->CP0_Status
& (1 << CP0St_ERL
)) &&
48 !(env
->hflags
& MIPS_HFLAG_DM
) &&
49 (env
->CP0_Status
& (1 << CP0St_IE
)) &&
50 (env
->CP0_Status
& env
->CP0_Cause
& CP0Ca_IP_mask
)) {
51 env
->CP0_Cause
&= ~(0x1f << CP0Ca_EC
);
52 helper_raise_exception(EXCP_EXT_INTERRUPT
);
56 #if !defined(CONFIG_USER_ONLY)
57 static void do_restore_state (void *pc_ptr
)
60 unsigned long pc
= (unsigned long) pc_ptr
;
64 cpu_restore_state (tb
, env
, pc
, NULL
);
69 #if defined(CONFIG_USER_ONLY)
70 #define HELPER_LD(name, insn, type) \
71 static inline type do_##name(target_ulong addr, int mem_idx) \
73 return (type) insn##_raw(addr); \
76 #define HELPER_LD(name, insn, type) \
77 static inline type do_##name(target_ulong addr, int mem_idx) \
81 case 0: return (type) insn##_kernel(addr); break; \
82 case 1: return (type) insn##_super(addr); break; \
84 case 2: return (type) insn##_user(addr); break; \
88 HELPER_LD(lbu
, ldub
, uint8_t)
89 HELPER_LD(lw
, ldl
, int32_t)
91 HELPER_LD(ld
, ldq
, int64_t)
95 #if defined(CONFIG_USER_ONLY)
96 #define HELPER_ST(name, insn, type) \
97 static inline void do_##name(target_ulong addr, type val, int mem_idx) \
99 insn##_raw(addr, val); \
102 #define HELPER_ST(name, insn, type) \
103 static inline void do_##name(target_ulong addr, type val, int mem_idx) \
107 case 0: insn##_kernel(addr, val); break; \
108 case 1: insn##_super(addr, val); break; \
110 case 2: insn##_user(addr, val); break; \
114 HELPER_ST(sb
, stb
, uint8_t)
115 HELPER_ST(sw
, stl
, uint32_t)
117 HELPER_ST(sd
, stq
, uint64_t)
121 target_ulong
helper_clo (target_ulong arg1
)
126 target_ulong
helper_clz (target_ulong arg1
)
131 #if defined(TARGET_MIPS64)
132 target_ulong
helper_dclo (target_ulong arg1
)
137 target_ulong
helper_dclz (target_ulong arg1
)
141 #endif /* TARGET_MIPS64 */
143 /* 64 bits arithmetic for 32 bits hosts */
144 static inline uint64_t get_HILO (void)
146 return ((uint64_t)(env
->active_tc
.HI
[0]) << 32) | (uint32_t)env
->active_tc
.LO
[0];
149 static inline void set_HILO (uint64_t HILO
)
151 env
->active_tc
.LO
[0] = (int32_t)HILO
;
152 env
->active_tc
.HI
[0] = (int32_t)(HILO
>> 32);
155 static inline void set_HIT0_LO (target_ulong arg1
, uint64_t HILO
)
157 env
->active_tc
.LO
[0] = (int32_t)(HILO
& 0xFFFFFFFF);
158 arg1
= env
->active_tc
.HI
[0] = (int32_t)(HILO
>> 32);
161 static inline void set_HI_LOT0 (target_ulong arg1
, uint64_t HILO
)
163 arg1
= env
->active_tc
.LO
[0] = (int32_t)(HILO
& 0xFFFFFFFF);
164 env
->active_tc
.HI
[0] = (int32_t)(HILO
>> 32);
167 /* Multiplication variants of the vr54xx. */
168 target_ulong
helper_muls (target_ulong arg1
, target_ulong arg2
)
170 set_HI_LOT0(arg1
, 0 - ((int64_t)(int32_t)arg1
* (int64_t)(int32_t)arg2
));
175 target_ulong
helper_mulsu (target_ulong arg1
, target_ulong arg2
)
177 set_HI_LOT0(arg1
, 0 - ((uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
));
182 target_ulong
helper_macc (target_ulong arg1
, target_ulong arg2
)
184 set_HI_LOT0(arg1
, ((int64_t)get_HILO()) + ((int64_t)(int32_t)arg1
* (int64_t)(int32_t)arg2
));
189 target_ulong
helper_macchi (target_ulong arg1
, target_ulong arg2
)
191 set_HIT0_LO(arg1
, ((int64_t)get_HILO()) + ((int64_t)(int32_t)arg1
* (int64_t)(int32_t)arg2
));
196 target_ulong
helper_maccu (target_ulong arg1
, target_ulong arg2
)
198 set_HI_LOT0(arg1
, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
));
203 target_ulong
helper_macchiu (target_ulong arg1
, target_ulong arg2
)
205 set_HIT0_LO(arg1
, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
));
210 target_ulong
helper_msac (target_ulong arg1
, target_ulong arg2
)
212 set_HI_LOT0(arg1
, ((int64_t)get_HILO()) - ((int64_t)(int32_t)arg1
* (int64_t)(int32_t)arg2
));
217 target_ulong
helper_msachi (target_ulong arg1
, target_ulong arg2
)
219 set_HIT0_LO(arg1
, ((int64_t)get_HILO()) - ((int64_t)(int32_t)arg1
* (int64_t)(int32_t)arg2
));
224 target_ulong
helper_msacu (target_ulong arg1
, target_ulong arg2
)
226 set_HI_LOT0(arg1
, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
));
231 target_ulong
helper_msachiu (target_ulong arg1
, target_ulong arg2
)
233 set_HIT0_LO(arg1
, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
));
238 target_ulong
helper_mulhi (target_ulong arg1
, target_ulong arg2
)
240 set_HIT0_LO(arg1
, (int64_t)(int32_t)arg1
* (int64_t)(int32_t)arg2
);
245 target_ulong
helper_mulhiu (target_ulong arg1
, target_ulong arg2
)
247 set_HIT0_LO(arg1
, (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
252 target_ulong
helper_mulshi (target_ulong arg1
, target_ulong arg2
)
254 set_HIT0_LO(arg1
, 0 - ((int64_t)(int32_t)arg1
* (int64_t)(int32_t)arg2
));
259 target_ulong
helper_mulshiu (target_ulong arg1
, target_ulong arg2
)
261 set_HIT0_LO(arg1
, 0 - ((uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
));
267 void helper_dmult (target_ulong arg1
, target_ulong arg2
)
269 muls64(&(env
->active_tc
.LO
[0]), &(env
->active_tc
.HI
[0]), arg1
, arg2
);
272 void helper_dmultu (target_ulong arg1
, target_ulong arg2
)
274 mulu64(&(env
->active_tc
.LO
[0]), &(env
->active_tc
.HI
[0]), arg1
, arg2
);
278 #ifndef CONFIG_USER_ONLY
280 static inline target_phys_addr_t
do_translate_address(target_ulong address
, int rw
)
282 target_phys_addr_t lladdr
;
284 lladdr
= cpu_mips_translate_address(env
, address
, rw
);
286 if (lladdr
== -1LL) {
293 #define HELPER_LD_ATOMIC(name, insn) \
294 target_ulong helper_##name(target_ulong arg, int mem_idx) \
296 env->lladdr = do_translate_address(arg, 0); \
297 env->llval = do_##insn(arg, mem_idx); \
300 HELPER_LD_ATOMIC(ll
, lw
)
302 HELPER_LD_ATOMIC(lld
, ld
)
304 #undef HELPER_LD_ATOMIC
306 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \
307 target_ulong helper_##name(target_ulong arg1, target_ulong arg2, int mem_idx) \
311 if (arg2 & almask) { \
312 env->CP0_BadVAddr = arg2; \
313 helper_raise_exception(EXCP_AdES); \
315 if (do_translate_address(arg2, 1) == env->lladdr) { \
316 tmp = do_##ld_insn(arg2, mem_idx); \
317 if (tmp == env->llval) { \
318 do_##st_insn(arg2, arg1, mem_idx); \
324 HELPER_ST_ATOMIC(sc
, lw
, sw
, 0x3)
326 HELPER_ST_ATOMIC(scd
, ld
, sd
, 0x7)
328 #undef HELPER_ST_ATOMIC
331 #ifdef TARGET_WORDS_BIGENDIAN
332 #define GET_LMASK(v) ((v) & 3)
333 #define GET_OFFSET(addr, offset) (addr + (offset))
335 #define GET_LMASK(v) (((v) & 3) ^ 3)
336 #define GET_OFFSET(addr, offset) (addr - (offset))
339 target_ulong
helper_lwl(target_ulong arg1
, target_ulong arg2
, int mem_idx
)
343 tmp
= do_lbu(arg2
, mem_idx
);
344 arg1
= (arg1
& 0x00FFFFFF) | (tmp
<< 24);
346 if (GET_LMASK(arg2
) <= 2) {
347 tmp
= do_lbu(GET_OFFSET(arg2
, 1), mem_idx
);
348 arg1
= (arg1
& 0xFF00FFFF) | (tmp
<< 16);
351 if (GET_LMASK(arg2
) <= 1) {
352 tmp
= do_lbu(GET_OFFSET(arg2
, 2), mem_idx
);
353 arg1
= (arg1
& 0xFFFF00FF) | (tmp
<< 8);
356 if (GET_LMASK(arg2
) == 0) {
357 tmp
= do_lbu(GET_OFFSET(arg2
, 3), mem_idx
);
358 arg1
= (arg1
& 0xFFFFFF00) | tmp
;
360 return (int32_t)arg1
;
363 target_ulong
helper_lwr(target_ulong arg1
, target_ulong arg2
, int mem_idx
)
367 tmp
= do_lbu(arg2
, mem_idx
);
368 arg1
= (arg1
& 0xFFFFFF00) | tmp
;
370 if (GET_LMASK(arg2
) >= 1) {
371 tmp
= do_lbu(GET_OFFSET(arg2
, -1), mem_idx
);
372 arg1
= (arg1
& 0xFFFF00FF) | (tmp
<< 8);
375 if (GET_LMASK(arg2
) >= 2) {
376 tmp
= do_lbu(GET_OFFSET(arg2
, -2), mem_idx
);
377 arg1
= (arg1
& 0xFF00FFFF) | (tmp
<< 16);
380 if (GET_LMASK(arg2
) == 3) {
381 tmp
= do_lbu(GET_OFFSET(arg2
, -3), mem_idx
);
382 arg1
= (arg1
& 0x00FFFFFF) | (tmp
<< 24);
384 return (int32_t)arg1
;
387 void helper_swl(target_ulong arg1
, target_ulong arg2
, int mem_idx
)
389 do_sb(arg2
, (uint8_t)(arg1
>> 24), mem_idx
);
391 if (GET_LMASK(arg2
) <= 2)
392 do_sb(GET_OFFSET(arg2
, 1), (uint8_t)(arg1
>> 16), mem_idx
);
394 if (GET_LMASK(arg2
) <= 1)
395 do_sb(GET_OFFSET(arg2
, 2), (uint8_t)(arg1
>> 8), mem_idx
);
397 if (GET_LMASK(arg2
) == 0)
398 do_sb(GET_OFFSET(arg2
, 3), (uint8_t)arg1
, mem_idx
);
401 void helper_swr(target_ulong arg1
, target_ulong arg2
, int mem_idx
)
403 do_sb(arg2
, (uint8_t)arg1
, mem_idx
);
405 if (GET_LMASK(arg2
) >= 1)
406 do_sb(GET_OFFSET(arg2
, -1), (uint8_t)(arg1
>> 8), mem_idx
);
408 if (GET_LMASK(arg2
) >= 2)
409 do_sb(GET_OFFSET(arg2
, -2), (uint8_t)(arg1
>> 16), mem_idx
);
411 if (GET_LMASK(arg2
) == 3)
412 do_sb(GET_OFFSET(arg2
, -3), (uint8_t)(arg1
>> 24), mem_idx
);
415 #if defined(TARGET_MIPS64)
416 /* "half" load and stores. We must do the memory access inline,
417 or fault handling won't work. */
419 #ifdef TARGET_WORDS_BIGENDIAN
420 #define GET_LMASK64(v) ((v) & 7)
422 #define GET_LMASK64(v) (((v) & 7) ^ 7)
425 target_ulong
helper_ldl(target_ulong arg1
, target_ulong arg2
, int mem_idx
)
429 tmp
= do_lbu(arg2
, mem_idx
);
430 arg1
= (arg1
& 0x00FFFFFFFFFFFFFFULL
) | (tmp
<< 56);
432 if (GET_LMASK64(arg2
) <= 6) {
433 tmp
= do_lbu(GET_OFFSET(arg2
, 1), mem_idx
);
434 arg1
= (arg1
& 0xFF00FFFFFFFFFFFFULL
) | (tmp
<< 48);
437 if (GET_LMASK64(arg2
) <= 5) {
438 tmp
= do_lbu(GET_OFFSET(arg2
, 2), mem_idx
);
439 arg1
= (arg1
& 0xFFFF00FFFFFFFFFFULL
) | (tmp
<< 40);
442 if (GET_LMASK64(arg2
) <= 4) {
443 tmp
= do_lbu(GET_OFFSET(arg2
, 3), mem_idx
);
444 arg1
= (arg1
& 0xFFFFFF00FFFFFFFFULL
) | (tmp
<< 32);
447 if (GET_LMASK64(arg2
) <= 3) {
448 tmp
= do_lbu(GET_OFFSET(arg2
, 4), mem_idx
);
449 arg1
= (arg1
& 0xFFFFFFFF00FFFFFFULL
) | (tmp
<< 24);
452 if (GET_LMASK64(arg2
) <= 2) {
453 tmp
= do_lbu(GET_OFFSET(arg2
, 5), mem_idx
);
454 arg1
= (arg1
& 0xFFFFFFFFFF00FFFFULL
) | (tmp
<< 16);
457 if (GET_LMASK64(arg2
) <= 1) {
458 tmp
= do_lbu(GET_OFFSET(arg2
, 6), mem_idx
);
459 arg1
= (arg1
& 0xFFFFFFFFFFFF00FFULL
) | (tmp
<< 8);
462 if (GET_LMASK64(arg2
) == 0) {
463 tmp
= do_lbu(GET_OFFSET(arg2
, 7), mem_idx
);
464 arg1
= (arg1
& 0xFFFFFFFFFFFFFF00ULL
) | tmp
;
470 target_ulong
helper_ldr(target_ulong arg1
, target_ulong arg2
, int mem_idx
)
474 tmp
= do_lbu(arg2
, mem_idx
);
475 arg1
= (arg1
& 0xFFFFFFFFFFFFFF00ULL
) | tmp
;
477 if (GET_LMASK64(arg2
) >= 1) {
478 tmp
= do_lbu(GET_OFFSET(arg2
, -1), mem_idx
);
479 arg1
= (arg1
& 0xFFFFFFFFFFFF00FFULL
) | (tmp
<< 8);
482 if (GET_LMASK64(arg2
) >= 2) {
483 tmp
= do_lbu(GET_OFFSET(arg2
, -2), mem_idx
);
484 arg1
= (arg1
& 0xFFFFFFFFFF00FFFFULL
) | (tmp
<< 16);
487 if (GET_LMASK64(arg2
) >= 3) {
488 tmp
= do_lbu(GET_OFFSET(arg2
, -3), mem_idx
);
489 arg1
= (arg1
& 0xFFFFFFFF00FFFFFFULL
) | (tmp
<< 24);
492 if (GET_LMASK64(arg2
) >= 4) {
493 tmp
= do_lbu(GET_OFFSET(arg2
, -4), mem_idx
);
494 arg1
= (arg1
& 0xFFFFFF00FFFFFFFFULL
) | (tmp
<< 32);
497 if (GET_LMASK64(arg2
) >= 5) {
498 tmp
= do_lbu(GET_OFFSET(arg2
, -5), mem_idx
);
499 arg1
= (arg1
& 0xFFFF00FFFFFFFFFFULL
) | (tmp
<< 40);
502 if (GET_LMASK64(arg2
) >= 6) {
503 tmp
= do_lbu(GET_OFFSET(arg2
, -6), mem_idx
);
504 arg1
= (arg1
& 0xFF00FFFFFFFFFFFFULL
) | (tmp
<< 48);
507 if (GET_LMASK64(arg2
) == 7) {
508 tmp
= do_lbu(GET_OFFSET(arg2
, -7), mem_idx
);
509 arg1
= (arg1
& 0x00FFFFFFFFFFFFFFULL
) | (tmp
<< 56);
515 void helper_sdl(target_ulong arg1
, target_ulong arg2
, int mem_idx
)
517 do_sb(arg2
, (uint8_t)(arg1
>> 56), mem_idx
);
519 if (GET_LMASK64(arg2
) <= 6)
520 do_sb(GET_OFFSET(arg2
, 1), (uint8_t)(arg1
>> 48), mem_idx
);
522 if (GET_LMASK64(arg2
) <= 5)
523 do_sb(GET_OFFSET(arg2
, 2), (uint8_t)(arg1
>> 40), mem_idx
);
525 if (GET_LMASK64(arg2
) <= 4)
526 do_sb(GET_OFFSET(arg2
, 3), (uint8_t)(arg1
>> 32), mem_idx
);
528 if (GET_LMASK64(arg2
) <= 3)
529 do_sb(GET_OFFSET(arg2
, 4), (uint8_t)(arg1
>> 24), mem_idx
);
531 if (GET_LMASK64(arg2
) <= 2)
532 do_sb(GET_OFFSET(arg2
, 5), (uint8_t)(arg1
>> 16), mem_idx
);
534 if (GET_LMASK64(arg2
) <= 1)
535 do_sb(GET_OFFSET(arg2
, 6), (uint8_t)(arg1
>> 8), mem_idx
);
537 if (GET_LMASK64(arg2
) <= 0)
538 do_sb(GET_OFFSET(arg2
, 7), (uint8_t)arg1
, mem_idx
);
541 void helper_sdr(target_ulong arg1
, target_ulong arg2
, int mem_idx
)
543 do_sb(arg2
, (uint8_t)arg1
, mem_idx
);
545 if (GET_LMASK64(arg2
) >= 1)
546 do_sb(GET_OFFSET(arg2
, -1), (uint8_t)(arg1
>> 8), mem_idx
);
548 if (GET_LMASK64(arg2
) >= 2)
549 do_sb(GET_OFFSET(arg2
, -2), (uint8_t)(arg1
>> 16), mem_idx
);
551 if (GET_LMASK64(arg2
) >= 3)
552 do_sb(GET_OFFSET(arg2
, -3), (uint8_t)(arg1
>> 24), mem_idx
);
554 if (GET_LMASK64(arg2
) >= 4)
555 do_sb(GET_OFFSET(arg2
, -4), (uint8_t)(arg1
>> 32), mem_idx
);
557 if (GET_LMASK64(arg2
) >= 5)
558 do_sb(GET_OFFSET(arg2
, -5), (uint8_t)(arg1
>> 40), mem_idx
);
560 if (GET_LMASK64(arg2
) >= 6)
561 do_sb(GET_OFFSET(arg2
, -6), (uint8_t)(arg1
>> 48), mem_idx
);
563 if (GET_LMASK64(arg2
) == 7)
564 do_sb(GET_OFFSET(arg2
, -7), (uint8_t)(arg1
>> 56), mem_idx
);
566 #endif /* TARGET_MIPS64 */
568 #ifndef CONFIG_USER_ONLY
570 target_ulong
helper_mfc0_mvpcontrol (void)
572 return env
->mvp
->CP0_MVPControl
;
575 target_ulong
helper_mfc0_mvpconf0 (void)
577 return env
->mvp
->CP0_MVPConf0
;
580 target_ulong
helper_mfc0_mvpconf1 (void)
582 return env
->mvp
->CP0_MVPConf1
;
585 target_ulong
helper_mfc0_random (void)
587 return (int32_t)cpu_mips_get_random(env
);
590 target_ulong
helper_mfc0_tcstatus (void)
592 return env
->active_tc
.CP0_TCStatus
;
595 target_ulong
helper_mftc0_tcstatus(void)
597 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
599 if (other_tc
== env
->current_tc
)
600 return env
->active_tc
.CP0_TCStatus
;
602 return env
->tcs
[other_tc
].CP0_TCStatus
;
605 target_ulong
helper_mfc0_tcbind (void)
607 return env
->active_tc
.CP0_TCBind
;
610 target_ulong
helper_mftc0_tcbind(void)
612 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
614 if (other_tc
== env
->current_tc
)
615 return env
->active_tc
.CP0_TCBind
;
617 return env
->tcs
[other_tc
].CP0_TCBind
;
620 target_ulong
helper_mfc0_tcrestart (void)
622 return env
->active_tc
.PC
;
625 target_ulong
helper_mftc0_tcrestart(void)
627 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
629 if (other_tc
== env
->current_tc
)
630 return env
->active_tc
.PC
;
632 return env
->tcs
[other_tc
].PC
;
635 target_ulong
helper_mfc0_tchalt (void)
637 return env
->active_tc
.CP0_TCHalt
;
640 target_ulong
helper_mftc0_tchalt(void)
642 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
644 if (other_tc
== env
->current_tc
)
645 return env
->active_tc
.CP0_TCHalt
;
647 return env
->tcs
[other_tc
].CP0_TCHalt
;
650 target_ulong
helper_mfc0_tccontext (void)
652 return env
->active_tc
.CP0_TCContext
;
655 target_ulong
helper_mftc0_tccontext(void)
657 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
659 if (other_tc
== env
->current_tc
)
660 return env
->active_tc
.CP0_TCContext
;
662 return env
->tcs
[other_tc
].CP0_TCContext
;
665 target_ulong
helper_mfc0_tcschedule (void)
667 return env
->active_tc
.CP0_TCSchedule
;
670 target_ulong
helper_mftc0_tcschedule(void)
672 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
674 if (other_tc
== env
->current_tc
)
675 return env
->active_tc
.CP0_TCSchedule
;
677 return env
->tcs
[other_tc
].CP0_TCSchedule
;
680 target_ulong
helper_mfc0_tcschefback (void)
682 return env
->active_tc
.CP0_TCScheFBack
;
685 target_ulong
helper_mftc0_tcschefback(void)
687 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
689 if (other_tc
== env
->current_tc
)
690 return env
->active_tc
.CP0_TCScheFBack
;
692 return env
->tcs
[other_tc
].CP0_TCScheFBack
;
695 target_ulong
helper_mfc0_count (void)
697 return (int32_t)cpu_mips_get_count(env
);
700 target_ulong
helper_mftc0_entryhi(void)
702 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
705 if (other_tc
== env
->current_tc
)
706 tcstatus
= env
->active_tc
.CP0_TCStatus
;
708 tcstatus
= env
->tcs
[other_tc
].CP0_TCStatus
;
710 return (env
->CP0_EntryHi
& ~0xff) | (tcstatus
& 0xff);
713 target_ulong
helper_mftc0_status(void)
715 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
719 if (other_tc
== env
->current_tc
)
720 tcstatus
= env
->active_tc
.CP0_TCStatus
;
722 tcstatus
= env
->tcs
[other_tc
].CP0_TCStatus
;
724 t0
= env
->CP0_Status
& ~0xf1000018;
725 t0
|= tcstatus
& (0xf << CP0TCSt_TCU0
);
726 t0
|= (tcstatus
& (1 << CP0TCSt_TMX
)) >> (CP0TCSt_TMX
- CP0St_MX
);
727 t0
|= (tcstatus
& (0x3 << CP0TCSt_TKSU
)) >> (CP0TCSt_TKSU
- CP0St_KSU
);
732 target_ulong
helper_mfc0_lladdr (void)
734 return (int32_t)(env
->lladdr
>> env
->CP0_LLAddr_shift
);
737 target_ulong
helper_mfc0_watchlo (uint32_t sel
)
739 return (int32_t)env
->CP0_WatchLo
[sel
];
742 target_ulong
helper_mfc0_watchhi (uint32_t sel
)
744 return env
->CP0_WatchHi
[sel
];
747 target_ulong
helper_mfc0_debug (void)
749 target_ulong t0
= env
->CP0_Debug
;
750 if (env
->hflags
& MIPS_HFLAG_DM
)
756 target_ulong
helper_mftc0_debug(void)
758 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
761 if (other_tc
== env
->current_tc
)
762 tcstatus
= env
->active_tc
.CP0_Debug_tcstatus
;
764 tcstatus
= env
->tcs
[other_tc
].CP0_Debug_tcstatus
;
766 /* XXX: Might be wrong, check with EJTAG spec. */
767 return (env
->CP0_Debug
& ~((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
))) |
768 (tcstatus
& ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
)));
771 #if defined(TARGET_MIPS64)
772 target_ulong
helper_dmfc0_tcrestart (void)
774 return env
->active_tc
.PC
;
777 target_ulong
helper_dmfc0_tchalt (void)
779 return env
->active_tc
.CP0_TCHalt
;
782 target_ulong
helper_dmfc0_tccontext (void)
784 return env
->active_tc
.CP0_TCContext
;
787 target_ulong
helper_dmfc0_tcschedule (void)
789 return env
->active_tc
.CP0_TCSchedule
;
792 target_ulong
helper_dmfc0_tcschefback (void)
794 return env
->active_tc
.CP0_TCScheFBack
;
797 target_ulong
helper_dmfc0_lladdr (void)
799 return env
->lladdr
>> env
->CP0_LLAddr_shift
;
802 target_ulong
helper_dmfc0_watchlo (uint32_t sel
)
804 return env
->CP0_WatchLo
[sel
];
806 #endif /* TARGET_MIPS64 */
808 void helper_mtc0_index (target_ulong arg1
)
811 unsigned int tmp
= env
->tlb
->nb_tlb
;
817 env
->CP0_Index
= (env
->CP0_Index
& 0x80000000) | (arg1
& (num
- 1));
820 void helper_mtc0_mvpcontrol (target_ulong arg1
)
825 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
))
826 mask
|= (1 << CP0MVPCo_CPA
) | (1 << CP0MVPCo_VPC
) |
828 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
829 mask
|= (1 << CP0MVPCo_STLB
);
830 newval
= (env
->mvp
->CP0_MVPControl
& ~mask
) | (arg1
& mask
);
832 // TODO: Enable/disable shared TLB, enable/disable VPEs.
834 env
->mvp
->CP0_MVPControl
= newval
;
837 void helper_mtc0_vpecontrol (target_ulong arg1
)
842 mask
= (1 << CP0VPECo_YSI
) | (1 << CP0VPECo_GSI
) |
843 (1 << CP0VPECo_TE
) | (0xff << CP0VPECo_TargTC
);
844 newval
= (env
->CP0_VPEControl
& ~mask
) | (arg1
& mask
);
846 /* Yield scheduler intercept not implemented. */
847 /* Gating storage scheduler intercept not implemented. */
849 // TODO: Enable/disable TCs.
851 env
->CP0_VPEControl
= newval
;
854 void helper_mtc0_vpeconf0 (target_ulong arg1
)
859 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) {
860 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_VPA
))
861 mask
|= (0xff << CP0VPEC0_XTC
);
862 mask
|= (1 << CP0VPEC0_MVP
) | (1 << CP0VPEC0_VPA
);
864 newval
= (env
->CP0_VPEConf0
& ~mask
) | (arg1
& mask
);
866 // TODO: TC exclusive handling due to ERL/EXL.
868 env
->CP0_VPEConf0
= newval
;
871 void helper_mtc0_vpeconf1 (target_ulong arg1
)
876 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
877 mask
|= (0xff << CP0VPEC1_NCX
) | (0xff << CP0VPEC1_NCP2
) |
878 (0xff << CP0VPEC1_NCP1
);
879 newval
= (env
->CP0_VPEConf1
& ~mask
) | (arg1
& mask
);
881 /* UDI not implemented. */
882 /* CP2 not implemented. */
884 // TODO: Handle FPU (CP1) binding.
886 env
->CP0_VPEConf1
= newval
;
889 void helper_mtc0_yqmask (target_ulong arg1
)
891 /* Yield qualifier inputs not implemented. */
892 env
->CP0_YQMask
= 0x00000000;
895 void helper_mtc0_vpeopt (target_ulong arg1
)
897 env
->CP0_VPEOpt
= arg1
& 0x0000ffff;
900 void helper_mtc0_entrylo0 (target_ulong arg1
)
902 /* Large physaddr (PABITS) not implemented */
903 /* 1k pages not implemented */
904 env
->CP0_EntryLo0
= arg1
& 0x3FFFFFFF;
907 void helper_mtc0_tcstatus (target_ulong arg1
)
909 uint32_t mask
= env
->CP0_TCStatus_rw_bitmask
;
912 newval
= (env
->active_tc
.CP0_TCStatus
& ~mask
) | (arg1
& mask
);
914 // TODO: Sync with CP0_Status.
916 env
->active_tc
.CP0_TCStatus
= newval
;
919 void helper_mttc0_tcstatus (target_ulong arg1
)
921 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
923 // TODO: Sync with CP0_Status.
925 if (other_tc
== env
->current_tc
)
926 env
->active_tc
.CP0_TCStatus
= arg1
;
928 env
->tcs
[other_tc
].CP0_TCStatus
= arg1
;
931 void helper_mtc0_tcbind (target_ulong arg1
)
933 uint32_t mask
= (1 << CP0TCBd_TBE
);
936 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
937 mask
|= (1 << CP0TCBd_CurVPE
);
938 newval
= (env
->active_tc
.CP0_TCBind
& ~mask
) | (arg1
& mask
);
939 env
->active_tc
.CP0_TCBind
= newval
;
942 void helper_mttc0_tcbind (target_ulong arg1
)
944 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
945 uint32_t mask
= (1 << CP0TCBd_TBE
);
948 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
949 mask
|= (1 << CP0TCBd_CurVPE
);
950 if (other_tc
== env
->current_tc
) {
951 newval
= (env
->active_tc
.CP0_TCBind
& ~mask
) | (arg1
& mask
);
952 env
->active_tc
.CP0_TCBind
= newval
;
954 newval
= (env
->tcs
[other_tc
].CP0_TCBind
& ~mask
) | (arg1
& mask
);
955 env
->tcs
[other_tc
].CP0_TCBind
= newval
;
959 void helper_mtc0_tcrestart (target_ulong arg1
)
961 env
->active_tc
.PC
= arg1
;
962 env
->active_tc
.CP0_TCStatus
&= ~(1 << CP0TCSt_TDS
);
964 /* MIPS16 not implemented. */
967 void helper_mttc0_tcrestart (target_ulong arg1
)
969 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
971 if (other_tc
== env
->current_tc
) {
972 env
->active_tc
.PC
= arg1
;
973 env
->active_tc
.CP0_TCStatus
&= ~(1 << CP0TCSt_TDS
);
975 /* MIPS16 not implemented. */
977 env
->tcs
[other_tc
].PC
= arg1
;
978 env
->tcs
[other_tc
].CP0_TCStatus
&= ~(1 << CP0TCSt_TDS
);
980 /* MIPS16 not implemented. */
984 void helper_mtc0_tchalt (target_ulong arg1
)
986 env
->active_tc
.CP0_TCHalt
= arg1
& 0x1;
988 // TODO: Halt TC / Restart (if allocated+active) TC.
991 void helper_mttc0_tchalt (target_ulong arg1
)
993 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
995 // TODO: Halt TC / Restart (if allocated+active) TC.
997 if (other_tc
== env
->current_tc
)
998 env
->active_tc
.CP0_TCHalt
= arg1
;
1000 env
->tcs
[other_tc
].CP0_TCHalt
= arg1
;
1003 void helper_mtc0_tccontext (target_ulong arg1
)
1005 env
->active_tc
.CP0_TCContext
= arg1
;
1008 void helper_mttc0_tccontext (target_ulong arg1
)
1010 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1012 if (other_tc
== env
->current_tc
)
1013 env
->active_tc
.CP0_TCContext
= arg1
;
1015 env
->tcs
[other_tc
].CP0_TCContext
= arg1
;
1018 void helper_mtc0_tcschedule (target_ulong arg1
)
1020 env
->active_tc
.CP0_TCSchedule
= arg1
;
1023 void helper_mttc0_tcschedule (target_ulong arg1
)
1025 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1027 if (other_tc
== env
->current_tc
)
1028 env
->active_tc
.CP0_TCSchedule
= arg1
;
1030 env
->tcs
[other_tc
].CP0_TCSchedule
= arg1
;
1033 void helper_mtc0_tcschefback (target_ulong arg1
)
1035 env
->active_tc
.CP0_TCScheFBack
= arg1
;
1038 void helper_mttc0_tcschefback (target_ulong arg1
)
1040 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1042 if (other_tc
== env
->current_tc
)
1043 env
->active_tc
.CP0_TCScheFBack
= arg1
;
1045 env
->tcs
[other_tc
].CP0_TCScheFBack
= arg1
;
1048 void helper_mtc0_entrylo1 (target_ulong arg1
)
1050 /* Large physaddr (PABITS) not implemented */
1051 /* 1k pages not implemented */
1052 env
->CP0_EntryLo1
= arg1
& 0x3FFFFFFF;
1055 void helper_mtc0_context (target_ulong arg1
)
1057 env
->CP0_Context
= (env
->CP0_Context
& 0x007FFFFF) | (arg1
& ~0x007FFFFF);
1060 void helper_mtc0_pagemask (target_ulong arg1
)
1062 /* 1k pages not implemented */
1063 env
->CP0_PageMask
= arg1
& (0x1FFFFFFF & (TARGET_PAGE_MASK
<< 1));
1066 void helper_mtc0_pagegrain (target_ulong arg1
)
1068 /* SmartMIPS not implemented */
1069 /* Large physaddr (PABITS) not implemented */
1070 /* 1k pages not implemented */
1071 env
->CP0_PageGrain
= 0;
1074 void helper_mtc0_wired (target_ulong arg1
)
1076 env
->CP0_Wired
= arg1
% env
->tlb
->nb_tlb
;
1079 void helper_mtc0_srsconf0 (target_ulong arg1
)
1081 env
->CP0_SRSConf0
|= arg1
& env
->CP0_SRSConf0_rw_bitmask
;
1084 void helper_mtc0_srsconf1 (target_ulong arg1
)
1086 env
->CP0_SRSConf1
|= arg1
& env
->CP0_SRSConf1_rw_bitmask
;
1089 void helper_mtc0_srsconf2 (target_ulong arg1
)
1091 env
->CP0_SRSConf2
|= arg1
& env
->CP0_SRSConf2_rw_bitmask
;
1094 void helper_mtc0_srsconf3 (target_ulong arg1
)
1096 env
->CP0_SRSConf3
|= arg1
& env
->CP0_SRSConf3_rw_bitmask
;
1099 void helper_mtc0_srsconf4 (target_ulong arg1
)
1101 env
->CP0_SRSConf4
|= arg1
& env
->CP0_SRSConf4_rw_bitmask
;
1104 void helper_mtc0_hwrena (target_ulong arg1
)
1106 env
->CP0_HWREna
= arg1
& 0x0000000F;
1109 void helper_mtc0_count (target_ulong arg1
)
1111 cpu_mips_store_count(env
, arg1
);
1114 void helper_mtc0_entryhi (target_ulong arg1
)
1116 target_ulong old
, val
;
1118 /* 1k pages not implemented */
1119 val
= arg1
& ((TARGET_PAGE_MASK
<< 1) | 0xFF);
1120 #if defined(TARGET_MIPS64)
1121 val
&= env
->SEGMask
;
1123 old
= env
->CP0_EntryHi
;
1124 env
->CP0_EntryHi
= val
;
1125 if (env
->CP0_Config3
& (1 << CP0C3_MT
)) {
1126 uint32_t tcst
= env
->active_tc
.CP0_TCStatus
& ~0xff;
1127 env
->active_tc
.CP0_TCStatus
= tcst
| (val
& 0xff);
1129 /* If the ASID changes, flush qemu's TLB. */
1130 if ((old
& 0xFF) != (val
& 0xFF))
1131 cpu_mips_tlb_flush(env
, 1);
1134 void helper_mttc0_entryhi(target_ulong arg1
)
1136 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1139 env
->CP0_EntryHi
= (env
->CP0_EntryHi
& 0xff) | (arg1
& ~0xff);
1140 if (other_tc
== env
->current_tc
) {
1141 tcstatus
= (env
->active_tc
.CP0_TCStatus
& ~0xff) | (arg1
& 0xff);
1142 env
->active_tc
.CP0_TCStatus
= tcstatus
;
1144 tcstatus
= (env
->tcs
[other_tc
].CP0_TCStatus
& ~0xff) | (arg1
& 0xff);
1145 env
->tcs
[other_tc
].CP0_TCStatus
= tcstatus
;
1149 void helper_mtc0_compare (target_ulong arg1
)
1151 cpu_mips_store_compare(env
, arg1
);
1154 void helper_mtc0_status (target_ulong arg1
)
1157 uint32_t mask
= env
->CP0_Status_rw_bitmask
;
1160 old
= env
->CP0_Status
;
1161 env
->CP0_Status
= (env
->CP0_Status
& ~mask
) | val
;
1162 compute_hflags(env
);
1163 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
1164 qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1165 old
, old
& env
->CP0_Cause
& CP0Ca_IP_mask
,
1166 val
, val
& env
->CP0_Cause
& CP0Ca_IP_mask
,
1168 switch (env
->hflags
& MIPS_HFLAG_KSU
) {
1169 case MIPS_HFLAG_UM
: qemu_log(", UM\n"); break;
1170 case MIPS_HFLAG_SM
: qemu_log(", SM\n"); break;
1171 case MIPS_HFLAG_KM
: qemu_log("\n"); break;
1172 default: cpu_abort(env
, "Invalid MMU mode!\n"); break;
1175 cpu_mips_update_irq(env
);
1178 void helper_mttc0_status(target_ulong arg1
)
1180 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1181 int32_t tcstatus
= env
->tcs
[other_tc
].CP0_TCStatus
;
1183 env
->CP0_Status
= arg1
& ~0xf1000018;
1184 tcstatus
= (tcstatus
& ~(0xf << CP0TCSt_TCU0
)) | (arg1
& (0xf << CP0St_CU0
));
1185 tcstatus
= (tcstatus
& ~(1 << CP0TCSt_TMX
)) | ((arg1
& (1 << CP0St_MX
)) << (CP0TCSt_TMX
- CP0St_MX
));
1186 tcstatus
= (tcstatus
& ~(0x3 << CP0TCSt_TKSU
)) | ((arg1
& (0x3 << CP0St_KSU
)) << (CP0TCSt_TKSU
- CP0St_KSU
));
1187 if (other_tc
== env
->current_tc
)
1188 env
->active_tc
.CP0_TCStatus
= tcstatus
;
1190 env
->tcs
[other_tc
].CP0_TCStatus
= tcstatus
;
1193 void helper_mtc0_intctl (target_ulong arg1
)
1195 /* vectored interrupts not implemented, no performance counters. */
1196 env
->CP0_IntCtl
= (env
->CP0_IntCtl
& ~0x000002e0) | (arg1
& 0x000002e0);
1199 void helper_mtc0_srsctl (target_ulong arg1
)
1201 uint32_t mask
= (0xf << CP0SRSCtl_ESS
) | (0xf << CP0SRSCtl_PSS
);
1202 env
->CP0_SRSCtl
= (env
->CP0_SRSCtl
& ~mask
) | (arg1
& mask
);
1205 void helper_mtc0_cause (target_ulong arg1
)
1207 uint32_t mask
= 0x00C00300;
1208 uint32_t old
= env
->CP0_Cause
;
1210 if (env
->insn_flags
& ISA_MIPS32R2
)
1211 mask
|= 1 << CP0Ca_DC
;
1213 env
->CP0_Cause
= (env
->CP0_Cause
& ~mask
) | (arg1
& mask
);
1215 if ((old
^ env
->CP0_Cause
) & (1 << CP0Ca_DC
)) {
1216 if (env
->CP0_Cause
& (1 << CP0Ca_DC
))
1217 cpu_mips_stop_count(env
);
1219 cpu_mips_start_count(env
);
1222 /* Handle the software interrupt as an hardware one, as they
1224 if (arg1
& CP0Ca_IP_mask
) {
1225 cpu_mips_update_irq(env
);
1229 void helper_mtc0_ebase (target_ulong arg1
)
1231 /* vectored interrupts not implemented */
1232 /* Multi-CPU not implemented */
1233 env
->CP0_EBase
= 0x80000000 | (arg1
& 0x3FFFF000);
1236 void helper_mtc0_config0 (target_ulong arg1
)
1238 env
->CP0_Config0
= (env
->CP0_Config0
& 0x81FFFFF8) | (arg1
& 0x00000007);
1241 void helper_mtc0_config2 (target_ulong arg1
)
1243 /* tertiary/secondary caches not implemented */
1244 env
->CP0_Config2
= (env
->CP0_Config2
& 0x8FFF0FFF);
1247 void helper_mtc0_lladdr (target_ulong arg1
)
1249 target_long mask
= env
->CP0_LLAddr_rw_bitmask
;
1250 arg1
= arg1
<< env
->CP0_LLAddr_shift
;
1251 env
->lladdr
= (env
->lladdr
& ~mask
) | (arg1
& mask
);
1254 void helper_mtc0_watchlo (target_ulong arg1
, uint32_t sel
)
1256 /* Watch exceptions for instructions, data loads, data stores
1258 env
->CP0_WatchLo
[sel
] = (arg1
& ~0x7);
1261 void helper_mtc0_watchhi (target_ulong arg1
, uint32_t sel
)
1263 env
->CP0_WatchHi
[sel
] = (arg1
& 0x40FF0FF8);
1264 env
->CP0_WatchHi
[sel
] &= ~(env
->CP0_WatchHi
[sel
] & arg1
& 0x7);
1267 void helper_mtc0_xcontext (target_ulong arg1
)
1269 target_ulong mask
= (1ULL << (env
->SEGBITS
- 7)) - 1;
1270 env
->CP0_XContext
= (env
->CP0_XContext
& mask
) | (arg1
& ~mask
);
1273 void helper_mtc0_framemask (target_ulong arg1
)
1275 env
->CP0_Framemask
= arg1
; /* XXX */
1278 void helper_mtc0_debug (target_ulong arg1
)
1280 env
->CP0_Debug
= (env
->CP0_Debug
& 0x8C03FC1F) | (arg1
& 0x13300120);
1281 if (arg1
& (1 << CP0DB_DM
))
1282 env
->hflags
|= MIPS_HFLAG_DM
;
1284 env
->hflags
&= ~MIPS_HFLAG_DM
;
1287 void helper_mttc0_debug(target_ulong arg1
)
1289 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1290 uint32_t val
= arg1
& ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
));
1292 /* XXX: Might be wrong, check with EJTAG spec. */
1293 if (other_tc
== env
->current_tc
)
1294 env
->active_tc
.CP0_Debug_tcstatus
= val
;
1296 env
->tcs
[other_tc
].CP0_Debug_tcstatus
= val
;
1297 env
->CP0_Debug
= (env
->CP0_Debug
& ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
))) |
1298 (arg1
& ~((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
)));
1301 void helper_mtc0_performance0 (target_ulong arg1
)
1303 env
->CP0_Performance0
= arg1
& 0x000007ff;
1306 void helper_mtc0_taglo (target_ulong arg1
)
1308 env
->CP0_TagLo
= arg1
& 0xFFFFFCF6;
1311 void helper_mtc0_datalo (target_ulong arg1
)
1313 env
->CP0_DataLo
= arg1
; /* XXX */
1316 void helper_mtc0_taghi (target_ulong arg1
)
1318 env
->CP0_TagHi
= arg1
; /* XXX */
1321 void helper_mtc0_datahi (target_ulong arg1
)
1323 env
->CP0_DataHi
= arg1
; /* XXX */
1326 /* MIPS MT functions */
1327 target_ulong
helper_mftgpr(uint32_t sel
)
1329 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1331 if (other_tc
== env
->current_tc
)
1332 return env
->active_tc
.gpr
[sel
];
1334 return env
->tcs
[other_tc
].gpr
[sel
];
1337 target_ulong
helper_mftlo(uint32_t sel
)
1339 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1341 if (other_tc
== env
->current_tc
)
1342 return env
->active_tc
.LO
[sel
];
1344 return env
->tcs
[other_tc
].LO
[sel
];
1347 target_ulong
helper_mfthi(uint32_t sel
)
1349 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1351 if (other_tc
== env
->current_tc
)
1352 return env
->active_tc
.HI
[sel
];
1354 return env
->tcs
[other_tc
].HI
[sel
];
1357 target_ulong
helper_mftacx(uint32_t sel
)
1359 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1361 if (other_tc
== env
->current_tc
)
1362 return env
->active_tc
.ACX
[sel
];
1364 return env
->tcs
[other_tc
].ACX
[sel
];
1367 target_ulong
helper_mftdsp(void)
1369 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1371 if (other_tc
== env
->current_tc
)
1372 return env
->active_tc
.DSPControl
;
1374 return env
->tcs
[other_tc
].DSPControl
;
1377 void helper_mttgpr(target_ulong arg1
, uint32_t sel
)
1379 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1381 if (other_tc
== env
->current_tc
)
1382 env
->active_tc
.gpr
[sel
] = arg1
;
1384 env
->tcs
[other_tc
].gpr
[sel
] = arg1
;
1387 void helper_mttlo(target_ulong arg1
, uint32_t sel
)
1389 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1391 if (other_tc
== env
->current_tc
)
1392 env
->active_tc
.LO
[sel
] = arg1
;
1394 env
->tcs
[other_tc
].LO
[sel
] = arg1
;
1397 void helper_mtthi(target_ulong arg1
, uint32_t sel
)
1399 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1401 if (other_tc
== env
->current_tc
)
1402 env
->active_tc
.HI
[sel
] = arg1
;
1404 env
->tcs
[other_tc
].HI
[sel
] = arg1
;
1407 void helper_mttacx(target_ulong arg1
, uint32_t sel
)
1409 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1411 if (other_tc
== env
->current_tc
)
1412 env
->active_tc
.ACX
[sel
] = arg1
;
1414 env
->tcs
[other_tc
].ACX
[sel
] = arg1
;
1417 void helper_mttdsp(target_ulong arg1
)
1419 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1421 if (other_tc
== env
->current_tc
)
1422 env
->active_tc
.DSPControl
= arg1
;
1424 env
->tcs
[other_tc
].DSPControl
= arg1
;
1427 /* MIPS MT functions */
1428 target_ulong
helper_dmt(target_ulong arg1
)
1437 target_ulong
helper_emt(target_ulong arg1
)
1446 target_ulong
helper_dvpe(target_ulong arg1
)
1455 target_ulong
helper_evpe(target_ulong arg1
)
1463 #endif /* !CONFIG_USER_ONLY */
1465 void helper_fork(target_ulong arg1
, target_ulong arg2
)
1467 // arg1 = rt, arg2 = rs
1469 // TODO: store to TC register
1472 target_ulong
helper_yield(target_ulong arg1
)
1475 /* No scheduling policy implemented. */
1477 if (env
->CP0_VPEControl
& (1 << CP0VPECo_YSI
) &&
1478 env
->active_tc
.CP0_TCStatus
& (1 << CP0TCSt_DT
)) {
1479 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
1480 env
->CP0_VPEControl
|= 4 << CP0VPECo_EXCPT
;
1481 helper_raise_exception(EXCP_THREAD
);
1484 } else if (arg1
== 0) {
1485 if (0 /* TODO: TC underflow */) {
1486 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
1487 helper_raise_exception(EXCP_THREAD
);
1489 // TODO: Deallocate TC
1491 } else if (arg1
> 0) {
1492 /* Yield qualifier inputs not implemented. */
1493 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
1494 env
->CP0_VPEControl
|= 2 << CP0VPECo_EXCPT
;
1495 helper_raise_exception(EXCP_THREAD
);
1497 return env
->CP0_YQMask
;
1500 #ifndef CONFIG_USER_ONLY
1501 /* TLB management */
1502 void cpu_mips_tlb_flush (CPUState
*env
, int flush_global
)
1504 /* Flush qemu's TLB and discard all shadowed entries. */
1505 tlb_flush (env
, flush_global
);
1506 env
->tlb
->tlb_in_use
= env
->tlb
->nb_tlb
;
1509 static void r4k_mips_tlb_flush_extra (CPUState
*env
, int first
)
1511 /* Discard entries from env->tlb[first] onwards. */
1512 while (env
->tlb
->tlb_in_use
> first
) {
1513 r4k_invalidate_tlb(env
, --env
->tlb
->tlb_in_use
, 0);
1517 static void r4k_fill_tlb (int idx
)
1521 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1522 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
1523 tlb
->VPN
= env
->CP0_EntryHi
& (TARGET_PAGE_MASK
<< 1);
1524 #if defined(TARGET_MIPS64)
1525 tlb
->VPN
&= env
->SEGMask
;
1527 tlb
->ASID
= env
->CP0_EntryHi
& 0xFF;
1528 tlb
->PageMask
= env
->CP0_PageMask
;
1529 tlb
->G
= env
->CP0_EntryLo0
& env
->CP0_EntryLo1
& 1;
1530 tlb
->V0
= (env
->CP0_EntryLo0
& 2) != 0;
1531 tlb
->D0
= (env
->CP0_EntryLo0
& 4) != 0;
1532 tlb
->C0
= (env
->CP0_EntryLo0
>> 3) & 0x7;
1533 tlb
->PFN
[0] = (env
->CP0_EntryLo0
>> 6) << 12;
1534 tlb
->V1
= (env
->CP0_EntryLo1
& 2) != 0;
1535 tlb
->D1
= (env
->CP0_EntryLo1
& 4) != 0;
1536 tlb
->C1
= (env
->CP0_EntryLo1
>> 3) & 0x7;
1537 tlb
->PFN
[1] = (env
->CP0_EntryLo1
>> 6) << 12;
1540 void r4k_helper_tlbwi (void)
1544 idx
= (env
->CP0_Index
& ~0x80000000) % env
->tlb
->nb_tlb
;
1546 /* Discard cached TLB entries. We could avoid doing this if the
1547 tlbwi is just upgrading access permissions on the current entry;
1548 that might be a further win. */
1549 r4k_mips_tlb_flush_extra (env
, env
->tlb
->nb_tlb
);
1551 r4k_invalidate_tlb(env
, idx
, 0);
1555 void r4k_helper_tlbwr (void)
1557 int r
= cpu_mips_get_random(env
);
1559 r4k_invalidate_tlb(env
, r
, 1);
1563 void r4k_helper_tlbp (void)
1572 ASID
= env
->CP0_EntryHi
& 0xFF;
1573 for (i
= 0; i
< env
->tlb
->nb_tlb
; i
++) {
1574 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[i
];
1575 /* 1k pages are not supported. */
1576 mask
= tlb
->PageMask
| ~(TARGET_PAGE_MASK
<< 1);
1577 tag
= env
->CP0_EntryHi
& ~mask
;
1578 VPN
= tlb
->VPN
& ~mask
;
1579 /* Check ASID, virtual page number & size */
1580 if ((tlb
->G
== 1 || tlb
->ASID
== ASID
) && VPN
== tag
) {
1586 if (i
== env
->tlb
->nb_tlb
) {
1587 /* No match. Discard any shadow entries, if any of them match. */
1588 for (i
= env
->tlb
->nb_tlb
; i
< env
->tlb
->tlb_in_use
; i
++) {
1589 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[i
];
1590 /* 1k pages are not supported. */
1591 mask
= tlb
->PageMask
| ~(TARGET_PAGE_MASK
<< 1);
1592 tag
= env
->CP0_EntryHi
& ~mask
;
1593 VPN
= tlb
->VPN
& ~mask
;
1594 /* Check ASID, virtual page number & size */
1595 if ((tlb
->G
== 1 || tlb
->ASID
== ASID
) && VPN
== tag
) {
1596 r4k_mips_tlb_flush_extra (env
, i
);
1601 env
->CP0_Index
|= 0x80000000;
1605 void r4k_helper_tlbr (void)
1611 ASID
= env
->CP0_EntryHi
& 0xFF;
1612 idx
= (env
->CP0_Index
& ~0x80000000) % env
->tlb
->nb_tlb
;
1613 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
1615 /* If this will change the current ASID, flush qemu's TLB. */
1616 if (ASID
!= tlb
->ASID
)
1617 cpu_mips_tlb_flush (env
, 1);
1619 r4k_mips_tlb_flush_extra(env
, env
->tlb
->nb_tlb
);
1621 env
->CP0_EntryHi
= tlb
->VPN
| tlb
->ASID
;
1622 env
->CP0_PageMask
= tlb
->PageMask
;
1623 env
->CP0_EntryLo0
= tlb
->G
| (tlb
->V0
<< 1) | (tlb
->D0
<< 2) |
1624 (tlb
->C0
<< 3) | (tlb
->PFN
[0] >> 6);
1625 env
->CP0_EntryLo1
= tlb
->G
| (tlb
->V1
<< 1) | (tlb
->D1
<< 2) |
1626 (tlb
->C1
<< 3) | (tlb
->PFN
[1] >> 6);
1629 void helper_tlbwi(void)
1631 env
->tlb
->helper_tlbwi();
1634 void helper_tlbwr(void)
1636 env
->tlb
->helper_tlbwr();
1639 void helper_tlbp(void)
1641 env
->tlb
->helper_tlbp();
1644 void helper_tlbr(void)
1646 env
->tlb
->helper_tlbr();
1650 target_ulong
helper_di (void)
1652 target_ulong t0
= env
->CP0_Status
;
1654 env
->CP0_Status
= t0
& ~(1 << CP0St_IE
);
1655 cpu_mips_update_irq(env
);
1660 target_ulong
helper_ei (void)
1662 target_ulong t0
= env
->CP0_Status
;
1664 env
->CP0_Status
= t0
| (1 << CP0St_IE
);
1665 cpu_mips_update_irq(env
);
1670 static void debug_pre_eret (void)
1672 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
1673 qemu_log("ERET: PC " TARGET_FMT_lx
" EPC " TARGET_FMT_lx
,
1674 env
->active_tc
.PC
, env
->CP0_EPC
);
1675 if (env
->CP0_Status
& (1 << CP0St_ERL
))
1676 qemu_log(" ErrorEPC " TARGET_FMT_lx
, env
->CP0_ErrorEPC
);
1677 if (env
->hflags
& MIPS_HFLAG_DM
)
1678 qemu_log(" DEPC " TARGET_FMT_lx
, env
->CP0_DEPC
);
1683 static void debug_post_eret (void)
1685 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
1686 qemu_log(" => PC " TARGET_FMT_lx
" EPC " TARGET_FMT_lx
,
1687 env
->active_tc
.PC
, env
->CP0_EPC
);
1688 if (env
->CP0_Status
& (1 << CP0St_ERL
))
1689 qemu_log(" ErrorEPC " TARGET_FMT_lx
, env
->CP0_ErrorEPC
);
1690 if (env
->hflags
& MIPS_HFLAG_DM
)
1691 qemu_log(" DEPC " TARGET_FMT_lx
, env
->CP0_DEPC
);
1692 switch (env
->hflags
& MIPS_HFLAG_KSU
) {
1693 case MIPS_HFLAG_UM
: qemu_log(", UM\n"); break;
1694 case MIPS_HFLAG_SM
: qemu_log(", SM\n"); break;
1695 case MIPS_HFLAG_KM
: qemu_log("\n"); break;
1696 default: cpu_abort(env
, "Invalid MMU mode!\n"); break;
1701 static void set_pc (target_ulong error_pc
)
1703 env
->active_tc
.PC
= error_pc
& ~(target_ulong
)1;
1705 env
->hflags
|= MIPS_HFLAG_M16
;
1707 env
->hflags
&= ~(MIPS_HFLAG_M16
);
1711 void helper_eret (void)
1714 if (env
->CP0_Status
& (1 << CP0St_ERL
)) {
1715 set_pc(env
->CP0_ErrorEPC
);
1716 env
->CP0_Status
&= ~(1 << CP0St_ERL
);
1718 set_pc(env
->CP0_EPC
);
1719 env
->CP0_Status
&= ~(1 << CP0St_EXL
);
1721 compute_hflags(env
);
1726 void helper_deret (void)
1729 set_pc(env
->CP0_DEPC
);
1731 env
->hflags
&= MIPS_HFLAG_DM
;
1732 compute_hflags(env
);
1736 #endif /* !CONFIG_USER_ONLY */
1738 target_ulong
helper_rdhwr_cpunum(void)
1740 if ((env
->hflags
& MIPS_HFLAG_CP0
) ||
1741 (env
->CP0_HWREna
& (1 << 0)))
1742 return env
->CP0_EBase
& 0x3ff;
1744 helper_raise_exception(EXCP_RI
);
1749 target_ulong
helper_rdhwr_synci_step(void)
1751 if ((env
->hflags
& MIPS_HFLAG_CP0
) ||
1752 (env
->CP0_HWREna
& (1 << 1)))
1753 return env
->SYNCI_Step
;
1755 helper_raise_exception(EXCP_RI
);
1760 target_ulong
helper_rdhwr_cc(void)
1762 if ((env
->hflags
& MIPS_HFLAG_CP0
) ||
1763 (env
->CP0_HWREna
& (1 << 2)))
1764 return env
->CP0_Count
;
1766 helper_raise_exception(EXCP_RI
);
1771 target_ulong
helper_rdhwr_ccres(void)
1773 if ((env
->hflags
& MIPS_HFLAG_CP0
) ||
1774 (env
->CP0_HWREna
& (1 << 3)))
1777 helper_raise_exception(EXCP_RI
);
1782 void helper_pmon (int function
)
1786 case 2: /* TODO: char inbyte(int waitflag); */
1787 if (env
->active_tc
.gpr
[4] == 0)
1788 env
->active_tc
.gpr
[2] = -1;
1790 case 11: /* TODO: char inbyte (void); */
1791 env
->active_tc
.gpr
[2] = -1;
1795 printf("%c", (char)(env
->active_tc
.gpr
[4] & 0xFF));
1801 unsigned char *fmt
= (void *)(unsigned long)env
->active_tc
.gpr
[4];
1808 void helper_wait (void)
1811 helper_raise_exception(EXCP_HLT
);
1814 #if !defined(CONFIG_USER_ONLY)
1816 static void do_unaligned_access (target_ulong addr
, int is_write
, int is_user
, void *retaddr
);
1818 #define MMUSUFFIX _mmu
1819 #define ALIGNED_ONLY
1822 #include "softmmu_template.h"
1825 #include "softmmu_template.h"
1828 #include "softmmu_template.h"
1831 #include "softmmu_template.h"
1833 static void do_unaligned_access (target_ulong addr
, int is_write
, int is_user
, void *retaddr
)
1835 env
->CP0_BadVAddr
= addr
;
1836 do_restore_state (retaddr
);
1837 helper_raise_exception ((is_write
== 1) ? EXCP_AdES
: EXCP_AdEL
);
1840 void tlb_fill (target_ulong addr
, int is_write
, int mmu_idx
, void *retaddr
)
1842 TranslationBlock
*tb
;
1843 CPUState
*saved_env
;
1847 /* XXX: hack to restore env in all cases, even if not called from
1850 env
= cpu_single_env
;
1851 ret
= cpu_mips_handle_mmu_fault(env
, addr
, is_write
, mmu_idx
, 1);
1854 /* now we have a real cpu fault */
1855 pc
= (unsigned long)retaddr
;
1856 tb
= tb_find_pc(pc
);
1858 /* the PC is inside the translated code. It means that we have
1859 a virtual CPU fault */
1860 cpu_restore_state(tb
, env
, pc
, NULL
);
1863 helper_raise_exception_err(env
->exception_index
, env
->error_code
);
1868 void do_unassigned_access(target_phys_addr_t addr
, int is_write
, int is_exec
,
1869 int unused
, int size
)
1872 helper_raise_exception(EXCP_IBE
);
1874 helper_raise_exception(EXCP_DBE
);
1876 #endif /* !CONFIG_USER_ONLY */
1878 /* Complex FPU operations which may need stack space. */
1880 #define FLOAT_ONE32 make_float32(0x3f8 << 20)
1881 #define FLOAT_ONE64 make_float64(0x3ffULL << 52)
1882 #define FLOAT_TWO32 make_float32(1 << 30)
1883 #define FLOAT_TWO64 make_float64(1ULL << 62)
1884 #define FLOAT_QNAN32 0x7fbfffff
1885 #define FLOAT_QNAN64 0x7ff7ffffffffffffULL
1886 #define FLOAT_SNAN32 0x7fffffff
1887 #define FLOAT_SNAN64 0x7fffffffffffffffULL
1889 /* convert MIPS rounding mode in FCR31 to IEEE library */
1890 static unsigned int ieee_rm
[] = {
1891 float_round_nearest_even
,
1892 float_round_to_zero
,
1897 #define RESTORE_ROUNDING_MODE \
1898 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
1900 #define RESTORE_FLUSH_MODE \
1901 set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0, &env->active_fpu.fp_status);
1903 target_ulong
helper_cfc1 (uint32_t reg
)
1909 arg1
= (int32_t)env
->active_fpu
.fcr0
;
1912 arg1
= ((env
->active_fpu
.fcr31
>> 24) & 0xfe) | ((env
->active_fpu
.fcr31
>> 23) & 0x1);
1915 arg1
= env
->active_fpu
.fcr31
& 0x0003f07c;
1918 arg1
= (env
->active_fpu
.fcr31
& 0x00000f83) | ((env
->active_fpu
.fcr31
>> 22) & 0x4);
1921 arg1
= (int32_t)env
->active_fpu
.fcr31
;
1928 void helper_ctc1 (target_ulong arg1
, uint32_t reg
)
1932 if (arg1
& 0xffffff00)
1934 env
->active_fpu
.fcr31
= (env
->active_fpu
.fcr31
& 0x017fffff) | ((arg1
& 0xfe) << 24) |
1935 ((arg1
& 0x1) << 23);
1938 if (arg1
& 0x007c0000)
1940 env
->active_fpu
.fcr31
= (env
->active_fpu
.fcr31
& 0xfffc0f83) | (arg1
& 0x0003f07c);
1943 if (arg1
& 0x007c0000)
1945 env
->active_fpu
.fcr31
= (env
->active_fpu
.fcr31
& 0xfefff07c) | (arg1
& 0x00000f83) |
1946 ((arg1
& 0x4) << 22);
1949 if (arg1
& 0x007c0000)
1951 env
->active_fpu
.fcr31
= arg1
;
1956 /* set rounding mode */
1957 RESTORE_ROUNDING_MODE
;
1958 /* set flush-to-zero mode */
1960 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
1961 if ((GET_FP_ENABLE(env
->active_fpu
.fcr31
) | 0x20) & GET_FP_CAUSE(env
->active_fpu
.fcr31
))
1962 helper_raise_exception(EXCP_FPE
);
1965 static inline char ieee_ex_to_mips(char xcpt
)
1967 return (xcpt
& float_flag_inexact
) >> 5 |
1968 (xcpt
& float_flag_underflow
) >> 3 |
1969 (xcpt
& float_flag_overflow
) >> 1 |
1970 (xcpt
& float_flag_divbyzero
) << 1 |
1971 (xcpt
& float_flag_invalid
) << 4;
1974 static inline char mips_ex_to_ieee(char xcpt
)
1976 return (xcpt
& FP_INEXACT
) << 5 |
1977 (xcpt
& FP_UNDERFLOW
) << 3 |
1978 (xcpt
& FP_OVERFLOW
) << 1 |
1979 (xcpt
& FP_DIV0
) >> 1 |
1980 (xcpt
& FP_INVALID
) >> 4;
1983 static inline void update_fcr31(void)
1985 int tmp
= ieee_ex_to_mips(get_float_exception_flags(&env
->active_fpu
.fp_status
));
1987 SET_FP_CAUSE(env
->active_fpu
.fcr31
, tmp
);
1988 if (GET_FP_ENABLE(env
->active_fpu
.fcr31
) & tmp
)
1989 helper_raise_exception(EXCP_FPE
);
1991 UPDATE_FP_FLAGS(env
->active_fpu
.fcr31
, tmp
);
1995 Single precition routines have a "s" suffix, double precision a
1996 "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
1997 paired single lower "pl", paired single upper "pu". */
1999 /* unary operations, modifying fp status */
2000 uint64_t helper_float_sqrt_d(uint64_t fdt0
)
2002 return float64_sqrt(fdt0
, &env
->active_fpu
.fp_status
);
2005 uint32_t helper_float_sqrt_s(uint32_t fst0
)
2007 return float32_sqrt(fst0
, &env
->active_fpu
.fp_status
);
2010 uint64_t helper_float_cvtd_s(uint32_t fst0
)
2014 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2015 fdt2
= float32_to_float64(fst0
, &env
->active_fpu
.fp_status
);
2020 uint64_t helper_float_cvtd_w(uint32_t wt0
)
2024 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2025 fdt2
= int32_to_float64(wt0
, &env
->active_fpu
.fp_status
);
2030 uint64_t helper_float_cvtd_l(uint64_t dt0
)
2034 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2035 fdt2
= int64_to_float64(dt0
, &env
->active_fpu
.fp_status
);
2040 uint64_t helper_float_cvtl_d(uint64_t fdt0
)
2044 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2045 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
2047 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
2052 uint64_t helper_float_cvtl_s(uint32_t fst0
)
2056 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2057 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
2059 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
2064 uint64_t helper_float_cvtps_pw(uint64_t dt0
)
2069 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2070 fst2
= int32_to_float32(dt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
2071 fsth2
= int32_to_float32(dt0
>> 32, &env
->active_fpu
.fp_status
);
2073 return ((uint64_t)fsth2
<< 32) | fst2
;
2076 uint64_t helper_float_cvtpw_ps(uint64_t fdt0
)
2081 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2082 wt2
= float32_to_int32(fdt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
2083 wth2
= float32_to_int32(fdt0
>> 32, &env
->active_fpu
.fp_status
);
2085 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
)) {
2087 wth2
= FLOAT_SNAN32
;
2089 return ((uint64_t)wth2
<< 32) | wt2
;
2092 uint32_t helper_float_cvts_d(uint64_t fdt0
)
2096 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2097 fst2
= float64_to_float32(fdt0
, &env
->active_fpu
.fp_status
);
2102 uint32_t helper_float_cvts_w(uint32_t wt0
)
2106 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2107 fst2
= int32_to_float32(wt0
, &env
->active_fpu
.fp_status
);
2112 uint32_t helper_float_cvts_l(uint64_t dt0
)
2116 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2117 fst2
= int64_to_float32(dt0
, &env
->active_fpu
.fp_status
);
2122 uint32_t helper_float_cvts_pl(uint32_t wt0
)
2126 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2132 uint32_t helper_float_cvts_pu(uint32_t wth0
)
2136 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2142 uint32_t helper_float_cvtw_s(uint32_t fst0
)
2146 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2147 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
2149 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
2154 uint32_t helper_float_cvtw_d(uint64_t fdt0
)
2158 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2159 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
2161 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
2166 uint64_t helper_float_roundl_d(uint64_t fdt0
)
2170 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
2171 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
2172 RESTORE_ROUNDING_MODE
;
2174 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
2179 uint64_t helper_float_roundl_s(uint32_t fst0
)
2183 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
2184 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
2185 RESTORE_ROUNDING_MODE
;
2187 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
2192 uint32_t helper_float_roundw_d(uint64_t fdt0
)
2196 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
2197 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
2198 RESTORE_ROUNDING_MODE
;
2200 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
2205 uint32_t helper_float_roundw_s(uint32_t fst0
)
2209 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
2210 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
2211 RESTORE_ROUNDING_MODE
;
2213 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
2218 uint64_t helper_float_truncl_d(uint64_t fdt0
)
2222 dt2
= float64_to_int64_round_to_zero(fdt0
, &env
->active_fpu
.fp_status
);
2224 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
2229 uint64_t helper_float_truncl_s(uint32_t fst0
)
2233 dt2
= float32_to_int64_round_to_zero(fst0
, &env
->active_fpu
.fp_status
);
2235 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
2240 uint32_t helper_float_truncw_d(uint64_t fdt0
)
2244 wt2
= float64_to_int32_round_to_zero(fdt0
, &env
->active_fpu
.fp_status
);
2246 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
2251 uint32_t helper_float_truncw_s(uint32_t fst0
)
2255 wt2
= float32_to_int32_round_to_zero(fst0
, &env
->active_fpu
.fp_status
);
2257 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
2262 uint64_t helper_float_ceill_d(uint64_t fdt0
)
2266 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
2267 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
2268 RESTORE_ROUNDING_MODE
;
2270 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
2275 uint64_t helper_float_ceill_s(uint32_t fst0
)
2279 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
2280 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
2281 RESTORE_ROUNDING_MODE
;
2283 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
2288 uint32_t helper_float_ceilw_d(uint64_t fdt0
)
2292 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
2293 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
2294 RESTORE_ROUNDING_MODE
;
2296 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
2301 uint32_t helper_float_ceilw_s(uint32_t fst0
)
2305 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
2306 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
2307 RESTORE_ROUNDING_MODE
;
2309 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
2314 uint64_t helper_float_floorl_d(uint64_t fdt0
)
2318 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
2319 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
2320 RESTORE_ROUNDING_MODE
;
2322 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
2327 uint64_t helper_float_floorl_s(uint32_t fst0
)
2331 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
2332 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
2333 RESTORE_ROUNDING_MODE
;
2335 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
2340 uint32_t helper_float_floorw_d(uint64_t fdt0
)
2344 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
2345 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
2346 RESTORE_ROUNDING_MODE
;
2348 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
2353 uint32_t helper_float_floorw_s(uint32_t fst0
)
2357 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
2358 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
2359 RESTORE_ROUNDING_MODE
;
2361 if (GET_FP_CAUSE(env
->active_fpu
.fcr31
) & (FP_OVERFLOW
| FP_INVALID
))
2366 /* unary operations, not modifying fp status */
2367 #define FLOAT_UNOP(name) \
2368 uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
2370 return float64_ ## name(fdt0); \
2372 uint32_t helper_float_ ## name ## _s(uint32_t fst0) \
2374 return float32_ ## name(fst0); \
2376 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \
2381 wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
2382 wth0 = float32_ ## name(fdt0 >> 32); \
2383 return ((uint64_t)wth0 << 32) | wt0; \
2389 /* MIPS specific unary operations */
2390 uint64_t helper_float_recip_d(uint64_t fdt0
)
2394 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2395 fdt2
= float64_div(FLOAT_ONE64
, fdt0
, &env
->active_fpu
.fp_status
);
2400 uint32_t helper_float_recip_s(uint32_t fst0
)
2404 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2405 fst2
= float32_div(FLOAT_ONE32
, fst0
, &env
->active_fpu
.fp_status
);
2410 uint64_t helper_float_rsqrt_d(uint64_t fdt0
)
2414 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2415 fdt2
= float64_sqrt(fdt0
, &env
->active_fpu
.fp_status
);
2416 fdt2
= float64_div(FLOAT_ONE64
, fdt2
, &env
->active_fpu
.fp_status
);
2421 uint32_t helper_float_rsqrt_s(uint32_t fst0
)
2425 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2426 fst2
= float32_sqrt(fst0
, &env
->active_fpu
.fp_status
);
2427 fst2
= float32_div(FLOAT_ONE32
, fst2
, &env
->active_fpu
.fp_status
);
2432 uint64_t helper_float_recip1_d(uint64_t fdt0
)
2436 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2437 fdt2
= float64_div(FLOAT_ONE64
, fdt0
, &env
->active_fpu
.fp_status
);
2442 uint32_t helper_float_recip1_s(uint32_t fst0
)
2446 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2447 fst2
= float32_div(FLOAT_ONE32
, fst0
, &env
->active_fpu
.fp_status
);
2452 uint64_t helper_float_recip1_ps(uint64_t fdt0
)
2457 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2458 fst2
= float32_div(FLOAT_ONE32
, fdt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
2459 fsth2
= float32_div(FLOAT_ONE32
, fdt0
>> 32, &env
->active_fpu
.fp_status
);
2461 return ((uint64_t)fsth2
<< 32) | fst2
;
2464 uint64_t helper_float_rsqrt1_d(uint64_t fdt0
)
2468 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2469 fdt2
= float64_sqrt(fdt0
, &env
->active_fpu
.fp_status
);
2470 fdt2
= float64_div(FLOAT_ONE64
, fdt2
, &env
->active_fpu
.fp_status
);
2475 uint32_t helper_float_rsqrt1_s(uint32_t fst0
)
2479 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2480 fst2
= float32_sqrt(fst0
, &env
->active_fpu
.fp_status
);
2481 fst2
= float32_div(FLOAT_ONE32
, fst2
, &env
->active_fpu
.fp_status
);
2486 uint64_t helper_float_rsqrt1_ps(uint64_t fdt0
)
2491 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2492 fst2
= float32_sqrt(fdt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
2493 fsth2
= float32_sqrt(fdt0
>> 32, &env
->active_fpu
.fp_status
);
2494 fst2
= float32_div(FLOAT_ONE32
, fst2
, &env
->active_fpu
.fp_status
);
2495 fsth2
= float32_div(FLOAT_ONE32
, fsth2
, &env
->active_fpu
.fp_status
);
2497 return ((uint64_t)fsth2
<< 32) | fst2
;
2500 #define FLOAT_OP(name, p) void helper_float_##name##_##p(void)
2502 /* binary operations */
2503 #define FLOAT_BINOP(name) \
2504 uint64_t helper_float_ ## name ## _d(uint64_t fdt0, uint64_t fdt1) \
2508 set_float_exception_flags(0, &env->active_fpu.fp_status); \
2509 dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
2511 if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \
2512 dt2 = FLOAT_QNAN64; \
2516 uint32_t helper_float_ ## name ## _s(uint32_t fst0, uint32_t fst1) \
2520 set_float_exception_flags(0, &env->active_fpu.fp_status); \
2521 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
2523 if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \
2524 wt2 = FLOAT_QNAN32; \
2528 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0, uint64_t fdt1) \
2530 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2531 uint32_t fsth0 = fdt0 >> 32; \
2532 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
2533 uint32_t fsth1 = fdt1 >> 32; \
2537 set_float_exception_flags(0, &env->active_fpu.fp_status); \
2538 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
2539 wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
2541 if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) { \
2542 wt2 = FLOAT_QNAN32; \
2543 wth2 = FLOAT_QNAN32; \
2545 return ((uint64_t)wth2 << 32) | wt2; \
2554 /* ternary operations */
2555 #define FLOAT_TERNOP(name1, name2) \
2556 uint64_t helper_float_ ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \
2559 fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \
2560 return float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \
2563 uint32_t helper_float_ ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \
2566 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2567 return float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
2570 uint64_t helper_float_ ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1, \
2573 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2574 uint32_t fsth0 = fdt0 >> 32; \
2575 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
2576 uint32_t fsth1 = fdt1 >> 32; \
2577 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
2578 uint32_t fsth2 = fdt2 >> 32; \
2580 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2581 fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \
2582 fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
2583 fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \
2584 return ((uint64_t)fsth2 << 32) | fst2; \
2587 FLOAT_TERNOP(mul
, add
)
2588 FLOAT_TERNOP(mul
, sub
)
2591 /* negated ternary operations */
2592 #define FLOAT_NTERNOP(name1, name2) \
2593 uint64_t helper_float_n ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \
2596 fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \
2597 fdt2 = float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \
2598 return float64_chs(fdt2); \
2601 uint32_t helper_float_n ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \
2604 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2605 fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
2606 return float32_chs(fst2); \
2609 uint64_t helper_float_n ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1,\
2612 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2613 uint32_t fsth0 = fdt0 >> 32; \
2614 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
2615 uint32_t fsth1 = fdt1 >> 32; \
2616 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
2617 uint32_t fsth2 = fdt2 >> 32; \
2619 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2620 fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \
2621 fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
2622 fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \
2623 fst2 = float32_chs(fst2); \
2624 fsth2 = float32_chs(fsth2); \
2625 return ((uint64_t)fsth2 << 32) | fst2; \
2628 FLOAT_NTERNOP(mul
, add
)
2629 FLOAT_NTERNOP(mul
, sub
)
2630 #undef FLOAT_NTERNOP
2632 /* MIPS specific binary operations */
2633 uint64_t helper_float_recip2_d(uint64_t fdt0
, uint64_t fdt2
)
2635 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2636 fdt2
= float64_mul(fdt0
, fdt2
, &env
->active_fpu
.fp_status
);
2637 fdt2
= float64_chs(float64_sub(fdt2
, FLOAT_ONE64
, &env
->active_fpu
.fp_status
));
2642 uint32_t helper_float_recip2_s(uint32_t fst0
, uint32_t fst2
)
2644 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2645 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
2646 fst2
= float32_chs(float32_sub(fst2
, FLOAT_ONE32
, &env
->active_fpu
.fp_status
));
2651 uint64_t helper_float_recip2_ps(uint64_t fdt0
, uint64_t fdt2
)
2653 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
2654 uint32_t fsth0
= fdt0
>> 32;
2655 uint32_t fst2
= fdt2
& 0XFFFFFFFF;
2656 uint32_t fsth2
= fdt2
>> 32;
2658 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2659 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
2660 fsth2
= float32_mul(fsth0
, fsth2
, &env
->active_fpu
.fp_status
);
2661 fst2
= float32_chs(float32_sub(fst2
, FLOAT_ONE32
, &env
->active_fpu
.fp_status
));
2662 fsth2
= float32_chs(float32_sub(fsth2
, FLOAT_ONE32
, &env
->active_fpu
.fp_status
));
2664 return ((uint64_t)fsth2
<< 32) | fst2
;
2667 uint64_t helper_float_rsqrt2_d(uint64_t fdt0
, uint64_t fdt2
)
2669 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2670 fdt2
= float64_mul(fdt0
, fdt2
, &env
->active_fpu
.fp_status
);
2671 fdt2
= float64_sub(fdt2
, FLOAT_ONE64
, &env
->active_fpu
.fp_status
);
2672 fdt2
= float64_chs(float64_div(fdt2
, FLOAT_TWO64
, &env
->active_fpu
.fp_status
));
2677 uint32_t helper_float_rsqrt2_s(uint32_t fst0
, uint32_t fst2
)
2679 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2680 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
2681 fst2
= float32_sub(fst2
, FLOAT_ONE32
, &env
->active_fpu
.fp_status
);
2682 fst2
= float32_chs(float32_div(fst2
, FLOAT_TWO32
, &env
->active_fpu
.fp_status
));
2687 uint64_t helper_float_rsqrt2_ps(uint64_t fdt0
, uint64_t fdt2
)
2689 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
2690 uint32_t fsth0
= fdt0
>> 32;
2691 uint32_t fst2
= fdt2
& 0XFFFFFFFF;
2692 uint32_t fsth2
= fdt2
>> 32;
2694 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2695 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
2696 fsth2
= float32_mul(fsth0
, fsth2
, &env
->active_fpu
.fp_status
);
2697 fst2
= float32_sub(fst2
, FLOAT_ONE32
, &env
->active_fpu
.fp_status
);
2698 fsth2
= float32_sub(fsth2
, FLOAT_ONE32
, &env
->active_fpu
.fp_status
);
2699 fst2
= float32_chs(float32_div(fst2
, FLOAT_TWO32
, &env
->active_fpu
.fp_status
));
2700 fsth2
= float32_chs(float32_div(fsth2
, FLOAT_TWO32
, &env
->active_fpu
.fp_status
));
2702 return ((uint64_t)fsth2
<< 32) | fst2
;
2705 uint64_t helper_float_addr_ps(uint64_t fdt0
, uint64_t fdt1
)
2707 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
2708 uint32_t fsth0
= fdt0
>> 32;
2709 uint32_t fst1
= fdt1
& 0XFFFFFFFF;
2710 uint32_t fsth1
= fdt1
>> 32;
2714 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2715 fst2
= float32_add (fst0
, fsth0
, &env
->active_fpu
.fp_status
);
2716 fsth2
= float32_add (fst1
, fsth1
, &env
->active_fpu
.fp_status
);
2718 return ((uint64_t)fsth2
<< 32) | fst2
;
2721 uint64_t helper_float_mulr_ps(uint64_t fdt0
, uint64_t fdt1
)
2723 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
2724 uint32_t fsth0
= fdt0
>> 32;
2725 uint32_t fst1
= fdt1
& 0XFFFFFFFF;
2726 uint32_t fsth1
= fdt1
>> 32;
2730 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2731 fst2
= float32_mul (fst0
, fsth0
, &env
->active_fpu
.fp_status
);
2732 fsth2
= float32_mul (fst1
, fsth1
, &env
->active_fpu
.fp_status
);
2734 return ((uint64_t)fsth2
<< 32) | fst2
;
2737 /* compare operations */
2738 #define FOP_COND_D(op, cond) \
2739 void helper_cmp_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
2744 SET_FP_COND(cc, env->active_fpu); \
2746 CLEAR_FP_COND(cc, env->active_fpu); \
2748 void helper_cmpabs_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
2751 fdt0 = float64_abs(fdt0); \
2752 fdt1 = float64_abs(fdt1); \
2756 SET_FP_COND(cc, env->active_fpu); \
2758 CLEAR_FP_COND(cc, env->active_fpu); \
2761 static int float64_is_unordered(int sig
, float64 a
, float64 b STATUS_PARAM
)
2763 if (float64_is_signaling_nan(a
) ||
2764 float64_is_signaling_nan(b
) ||
2765 (sig
&& (float64_is_nan(a
) || float64_is_nan(b
)))) {
2766 float_raise(float_flag_invalid
, status
);
2768 } else if (float64_is_nan(a
) || float64_is_nan(b
)) {
2775 /* NOTE: the comma operator will make "cond" to eval to false,
2776 * but float*_is_unordered() is still called. */
2777 FOP_COND_D(f
, (float64_is_unordered(0, fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
2778 FOP_COND_D(un
, float64_is_unordered(0, fdt1
, fdt0
, &env
->active_fpu
.fp_status
))
2779 FOP_COND_D(eq
, !float64_is_unordered(0, fdt1
, fdt0
, &env
->active_fpu
.fp_status
) && float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
2780 FOP_COND_D(ueq
, float64_is_unordered(0, fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
2781 FOP_COND_D(olt
, !float64_is_unordered(0, fdt1
, fdt0
, &env
->active_fpu
.fp_status
) && float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
2782 FOP_COND_D(ult
, float64_is_unordered(0, fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
2783 FOP_COND_D(ole
, !float64_is_unordered(0, fdt1
, fdt0
, &env
->active_fpu
.fp_status
) && float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
2784 FOP_COND_D(ule
, float64_is_unordered(0, fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
2785 /* NOTE: the comma operator will make "cond" to eval to false,
2786 * but float*_is_unordered() is still called. */
2787 FOP_COND_D(sf
, (float64_is_unordered(1, fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
2788 FOP_COND_D(ngle
,float64_is_unordered(1, fdt1
, fdt0
, &env
->active_fpu
.fp_status
))
2789 FOP_COND_D(seq
, !float64_is_unordered(1, fdt1
, fdt0
, &env
->active_fpu
.fp_status
) && float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
2790 FOP_COND_D(ngl
, float64_is_unordered(1, fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
2791 FOP_COND_D(lt
, !float64_is_unordered(1, fdt1
, fdt0
, &env
->active_fpu
.fp_status
) && float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
2792 FOP_COND_D(nge
, float64_is_unordered(1, fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
2793 FOP_COND_D(le
, !float64_is_unordered(1, fdt1
, fdt0
, &env
->active_fpu
.fp_status
) && float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
2794 FOP_COND_D(ngt
, float64_is_unordered(1, fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
2796 #define FOP_COND_S(op, cond) \
2797 void helper_cmp_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \
2802 SET_FP_COND(cc, env->active_fpu); \
2804 CLEAR_FP_COND(cc, env->active_fpu); \
2806 void helper_cmpabs_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \
2809 fst0 = float32_abs(fst0); \
2810 fst1 = float32_abs(fst1); \
2814 SET_FP_COND(cc, env->active_fpu); \
2816 CLEAR_FP_COND(cc, env->active_fpu); \
2819 static flag
float32_is_unordered(int sig
, float32 a
, float32 b STATUS_PARAM
)
2821 if (float32_is_signaling_nan(a
) ||
2822 float32_is_signaling_nan(b
) ||
2823 (sig
&& (float32_is_nan(a
) || float32_is_nan(b
)))) {
2824 float_raise(float_flag_invalid
, status
);
2826 } else if (float32_is_nan(a
) || float32_is_nan(b
)) {
2833 /* NOTE: the comma operator will make "cond" to eval to false,
2834 * but float*_is_unordered() is still called. */
2835 FOP_COND_S(f
, (float32_is_unordered(0, fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
2836 FOP_COND_S(un
, float32_is_unordered(0, fst1
, fst0
, &env
->active_fpu
.fp_status
))
2837 FOP_COND_S(eq
, !float32_is_unordered(0, fst1
, fst0
, &env
->active_fpu
.fp_status
) && float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
))
2838 FOP_COND_S(ueq
, float32_is_unordered(0, fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
))
2839 FOP_COND_S(olt
, !float32_is_unordered(0, fst1
, fst0
, &env
->active_fpu
.fp_status
) && float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
))
2840 FOP_COND_S(ult
, float32_is_unordered(0, fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
))
2841 FOP_COND_S(ole
, !float32_is_unordered(0, fst1
, fst0
, &env
->active_fpu
.fp_status
) && float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
))
2842 FOP_COND_S(ule
, float32_is_unordered(0, fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
))
2843 /* NOTE: the comma operator will make "cond" to eval to false,
2844 * but float*_is_unordered() is still called. */
2845 FOP_COND_S(sf
, (float32_is_unordered(1, fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
2846 FOP_COND_S(ngle
,float32_is_unordered(1, fst1
, fst0
, &env
->active_fpu
.fp_status
))
2847 FOP_COND_S(seq
, !float32_is_unordered(1, fst1
, fst0
, &env
->active_fpu
.fp_status
) && float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
))
2848 FOP_COND_S(ngl
, float32_is_unordered(1, fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
))
2849 FOP_COND_S(lt
, !float32_is_unordered(1, fst1
, fst0
, &env
->active_fpu
.fp_status
) && float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
))
2850 FOP_COND_S(nge
, float32_is_unordered(1, fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
))
2851 FOP_COND_S(le
, !float32_is_unordered(1, fst1
, fst0
, &env
->active_fpu
.fp_status
) && float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
))
2852 FOP_COND_S(ngt
, float32_is_unordered(1, fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
))
2854 #define FOP_COND_PS(op, condl, condh) \
2855 void helper_cmp_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
2857 uint32_t fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
2858 uint32_t fsth0 = float32_abs(fdt0 >> 32); \
2859 uint32_t fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
2860 uint32_t fsth1 = float32_abs(fdt1 >> 32); \
2866 SET_FP_COND(cc, env->active_fpu); \
2868 CLEAR_FP_COND(cc, env->active_fpu); \
2870 SET_FP_COND(cc + 1, env->active_fpu); \
2872 CLEAR_FP_COND(cc + 1, env->active_fpu); \
2874 void helper_cmpabs_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
2876 uint32_t fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
2877 uint32_t fsth0 = float32_abs(fdt0 >> 32); \
2878 uint32_t fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
2879 uint32_t fsth1 = float32_abs(fdt1 >> 32); \
2885 SET_FP_COND(cc, env->active_fpu); \
2887 CLEAR_FP_COND(cc, env->active_fpu); \
2889 SET_FP_COND(cc + 1, env->active_fpu); \
2891 CLEAR_FP_COND(cc + 1, env->active_fpu); \
2894 /* NOTE: the comma operator will make "cond" to eval to false,
2895 * but float*_is_unordered() is still called. */
2896 FOP_COND_PS(f
, (float32_is_unordered(0, fst1
, fst0
, &env
->active_fpu
.fp_status
), 0),
2897 (float32_is_unordered(0, fsth1
, fsth0
, &env
->active_fpu
.fp_status
), 0))
2898 FOP_COND_PS(un
, float32_is_unordered(0, fst1
, fst0
, &env
->active_fpu
.fp_status
),
2899 float32_is_unordered(0, fsth1
, fsth0
, &env
->active_fpu
.fp_status
))
2900 FOP_COND_PS(eq
, !float32_is_unordered(0, fst1
, fst0
, &env
->active_fpu
.fp_status
) && float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
),
2901 !float32_is_unordered(0, fsth1
, fsth0
, &env
->active_fpu
.fp_status
) && float32_eq(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
2902 FOP_COND_PS(ueq
, float32_is_unordered(0, fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
),
2903 float32_is_unordered(0, fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_eq(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
2904 FOP_COND_PS(olt
, !float32_is_unordered(0, fst1
, fst0
, &env
->active_fpu
.fp_status
) && float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
),
2905 !float32_is_unordered(0, fsth1
, fsth0
, &env
->active_fpu
.fp_status
) && float32_lt(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
2906 FOP_COND_PS(ult
, float32_is_unordered(0, fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
),
2907 float32_is_unordered(0, fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_lt(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
2908 FOP_COND_PS(ole
, !float32_is_unordered(0, fst1
, fst0
, &env
->active_fpu
.fp_status
) && float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
),
2909 !float32_is_unordered(0, fsth1
, fsth0
, &env
->active_fpu
.fp_status
) && float32_le(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
2910 FOP_COND_PS(ule
, float32_is_unordered(0, fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
),
2911 float32_is_unordered(0, fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_le(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
2912 /* NOTE: the comma operator will make "cond" to eval to false,
2913 * but float*_is_unordered() is still called. */
2914 FOP_COND_PS(sf
, (float32_is_unordered(1, fst1
, fst0
, &env
->active_fpu
.fp_status
), 0),
2915 (float32_is_unordered(1, fsth1
, fsth0
, &env
->active_fpu
.fp_status
), 0))
2916 FOP_COND_PS(ngle
,float32_is_unordered(1, fst1
, fst0
, &env
->active_fpu
.fp_status
),
2917 float32_is_unordered(1, fsth1
, fsth0
, &env
->active_fpu
.fp_status
))
2918 FOP_COND_PS(seq
, !float32_is_unordered(1, fst1
, fst0
, &env
->active_fpu
.fp_status
) && float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
),
2919 !float32_is_unordered(1, fsth1
, fsth0
, &env
->active_fpu
.fp_status
) && float32_eq(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
2920 FOP_COND_PS(ngl
, float32_is_unordered(1, fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
),
2921 float32_is_unordered(1, fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_eq(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
2922 FOP_COND_PS(lt
, !float32_is_unordered(1, fst1
, fst0
, &env
->active_fpu
.fp_status
) && float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
),
2923 !float32_is_unordered(1, fsth1
, fsth0
, &env
->active_fpu
.fp_status
) && float32_lt(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
2924 FOP_COND_PS(nge
, float32_is_unordered(1, fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
),
2925 float32_is_unordered(1, fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_lt(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
2926 FOP_COND_PS(le
, !float32_is_unordered(1, fst1
, fst0
, &env
->active_fpu
.fp_status
) && float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
),
2927 !float32_is_unordered(1, fsth1
, fsth0
, &env
->active_fpu
.fp_status
) && float32_le(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
2928 FOP_COND_PS(ngt
, float32_is_unordered(1, fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
),
2929 float32_is_unordered(1, fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_le(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))