target-arm/cpu.h

   1 /*
   2  * ARM virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef CPU_ARM_H
  20 #define CPU_ARM_H
  21
  22 #define TARGET_LONG_BITS 32
  23
  24 #define ELF_MACHINE     EM_ARM
  25
  26 #define CPUState struct CPUARMState
  27
  28 #include "config.h"
  29 #include "qemu-common.h"
  30 #include "cpu-defs.h"
  31
  32 #include "softfloat.h"
  33
  34 #define TARGET_HAS_ICE 1
  35
  36 #define EXCP_UDEF            1   /* undefined instruction */
  37 #define EXCP_SWI             2   /* software interrupt */
  38 #define EXCP_PREFETCH_ABORT  3
  39 #define EXCP_DATA_ABORT      4
  40 #define EXCP_IRQ             5
  41 #define EXCP_FIQ             6
  42 #define EXCP_BKPT            7
  43 #define EXCP_EXCEPTION_EXIT  8   /* Return from v7M exception.  */
  44 #define EXCP_KERNEL_TRAP     9   /* Jumped to kernel code page.  */
  45 #define EXCP_STREX          10
  46
  47 #define ARMV7M_EXCP_RESET   1
  48 #define ARMV7M_EXCP_NMI     2
  49 #define ARMV7M_EXCP_HARD    3
  50 #define ARMV7M_EXCP_MEM     4
  51 #define ARMV7M_EXCP_BUS     5
  52 #define ARMV7M_EXCP_USAGE   6
  53 #define ARMV7M_EXCP_SVC     11
  54 #define ARMV7M_EXCP_DEBUG   12
  55 #define ARMV7M_EXCP_PENDSV  14
  56 #define ARMV7M_EXCP_SYSTICK 15
  57
  58 /* ARM-specific interrupt pending bits.  */
  59 #define CPU_INTERRUPT_FIQ   CPU_INTERRUPT_TGT_EXT_1
  60
  61
  62 typedef void ARMWriteCPFunc(void *opaque, int cp_info,
  63                             int srcreg, int operand, uint32_t value);
  64 typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
  65                                int dstreg, int operand);
  66
  67 struct arm_boot_info;
  68
  69 #define NB_MMU_MODES 2
  70
  71 /* We currently assume float and double are IEEE single and double
  72    precision respectively.
  73    Doing runtime conversions is tricky because VFP registers may contain
  74    integer values (eg. as the result of a FTOSI instruction).
  75    s<2n> maps to the least significant half of d<n>
  76    s<2n+1> maps to the most significant half of d<n>
  77  */
  78
  79 typedef struct CPUARMState {
  80     /* Regs for current mode.  */
  81     uint32_t regs[16];
  82     /* Frequently accessed CPSR bits are stored separately for efficiently.
  83        This contains all the other bits.  Use cpsr_{read,write} to access
  84        the whole CPSR.  */
  85     uint32_t uncached_cpsr;
  86     uint32_t spsr;
  87
  88     /* Banked registers.  */
  89     uint32_t banked_spsr[6];
  90     uint32_t banked_r13[6];
  91     uint32_t banked_r14[6];
  92
  93     /* These hold r8-r12.  */
  94     uint32_t usr_regs[5];
  95     uint32_t fiq_regs[5];
  96
  97     /* cpsr flag cache for faster execution */
  98     uint32_t CF; /* 0 or 1 */
  99     uint32_t VF; /* V is the bit 31. All other bits are undefined */
 100     uint32_t NF; /* N is bit 31. All other bits are undefined.  */
 101     uint32_t ZF; /* Z set if zero.  */
 102     uint32_t QF; /* 0 or 1 */
 103     uint32_t GE; /* cpsr[19:16] */
 104     uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
 105     uint32_t condexec_bits; /* IT bits.  cpsr[15:10,26:25].  */
 106
 107     /* System control coprocessor (cp15) */
 108     struct {
 109         uint32_t c0_cpuid;
 110         uint32_t c0_cachetype;
 111         uint32_t c0_ccsid[16]; /* Cache size.  */
 112         uint32_t c0_clid; /* Cache level.  */
 113         uint32_t c0_cssel; /* Cache size selection.  */
 114         uint32_t c0_c1[8]; /* Feature registers.  */
 115         uint32_t c0_c2[8]; /* Instruction set registers.  */
 116         uint32_t c1_sys; /* System control register.  */
 117         uint32_t c1_coproc; /* Coprocessor access register.  */
 118         uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
 119         uint32_t c2_base0; /* MMU translation table base 0.  */
 120         uint32_t c2_base1; /* MMU translation table base 1.  */
 121         uint32_t c2_control; /* MMU translation table base control.  */
 122         uint32_t c2_mask; /* MMU translation table base selection mask.  */
 123         uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
 124         uint32_t c2_data; /* MPU data cachable bits.  */
 125         uint32_t c2_insn; /* MPU instruction cachable bits.  */
 126         uint32_t c3; /* MMU domain access control register
 127                         MPU write buffer control.  */
 128         uint32_t c5_insn; /* Fault status registers.  */
 129         uint32_t c5_data;
 130         uint32_t c6_region[8]; /* MPU base/size registers.  */
 131         uint32_t c6_insn; /* Fault address registers.  */
 132         uint32_t c6_data;
 133         uint32_t c7_par;  /* Translation result. */
 134         uint32_t c9_insn; /* Cache lockdown registers.  */
 135         uint32_t c9_data;
 136         uint32_t c9_pmcr; /* performance monitor control register */
 137         uint32_t c9_pmcnten; /* perf monitor counter enables */
 138         uint32_t c9_pmovsr; /* perf monitor overflow status */
 139         uint32_t c9_pmxevtyper; /* perf monitor event type */
 140         uint32_t c9_pmuserenr; /* perf monitor user enable */
 141         uint32_t c9_pminten; /* perf monitor interrupt enables */
 142         uint32_t c13_fcse; /* FCSE PID.  */
 143         uint32_t c13_context; /* Context ID.  */
 144         uint32_t c13_tls1; /* User RW Thread register.  */
 145         uint32_t c13_tls2; /* User RO Thread register.  */
 146         uint32_t c13_tls3; /* Privileged Thread register.  */
 147         uint32_t c15_cpar; /* XScale Coprocessor Access Register */
 148         uint32_t c15_ticonfig; /* TI925T configuration byte.  */
 149         uint32_t c15_i_max; /* Maximum D-cache dirty line index.  */
 150         uint32_t c15_i_min; /* Minimum D-cache dirty line index.  */
 151         uint32_t c15_threadid; /* TI debugger thread-ID.  */
 152         uint32_t c15_config_base_address; /* SCU base address.  */
 153         uint32_t c15_diagnostic; /* diagnostic register */
 154         uint32_t c15_power_diagnostic;
 155         uint32_t c15_power_control; /* power control */
 156     } cp15;
 157
 158     struct {
 159         uint32_t other_sp;
 160         uint32_t vecbase;
 161         uint32_t basepri;
 162         uint32_t control;
 163         int current_sp;
 164         int exception;
 165         int pending_exception;
 166     } v7m;
 167
 168     /* Thumb-2 EE state.  */
 169     uint32_t teecr;
 170     uint32_t teehbr;
 171
 172     /* Internal CPU feature flags.  */
 173     uint32_t features;
 174
 175     /* VFP coprocessor state.  */
 176     struct {
 177         float64 regs[32];
 178
 179         uint32_t xregs[16];
 180         /* We store these fpcsr fields separately for convenience.  */
 181         int vec_len;
 182         int vec_stride;
 183
 184         /* scratch space when Tn are not sufficient.  */
 185         uint32_t scratch[8];
 186
 187         /* fp_status is the "normal" fp status. standard_fp_status retains
 188          * values corresponding to the ARM "Standard FPSCR Value", ie
 189          * default-NaN, flush-to-zero, round-to-nearest and is used by
 190          * any operations (generally Neon) which the architecture defines
 191          * as controlled by the standard FPSCR value rather than the FPSCR.
 192          *
 193          * To avoid having to transfer exception bits around, we simply
 194          * say that the FPSCR cumulative exception flags are the logical
 195          * OR of the flags in the two fp statuses. This relies on the
 196          * only thing which needs to read the exception flags being
 197          * an explicit FPSCR read.
 198          */
 199         float_status fp_status;
 200         float_status standard_fp_status;
 201     } vfp;
 202     uint32_t exclusive_addr;
 203     uint32_t exclusive_val;
 204     uint32_t exclusive_high;
 205 #if defined(CONFIG_USER_ONLY)
 206     uint32_t exclusive_test;
 207     uint32_t exclusive_info;
 208 #endif
 209
 210     /* iwMMXt coprocessor state.  */
 211     struct {
 212         uint64_t regs[16];
 213         uint64_t val;
 214
 215         uint32_t cregs[16];
 216     } iwmmxt;
 217
 218 #if defined(CONFIG_USER_ONLY)
 219     /* For usermode syscall translation.  */
 220     int eabi;
 221 #endif
 222
 223     CPU_COMMON
 224
 225     /* These fields after the common ones so they are preserved on reset.  */
 226
 227     /* Coprocessor IO used by peripherals */
 228     struct {
 229         ARMReadCPFunc *cp_read;
 230         ARMWriteCPFunc *cp_write;
 231         void *opaque;
 232     } cp[15];
 233     void *nvic;
 234     const struct arm_boot_info *boot_info;
 235 } CPUARMState;
 236
 237 CPUARMState *cpu_arm_init(const char *cpu_model);
 238 void arm_translate_init(void);
 239 int cpu_arm_exec(CPUARMState *s);
 240 void cpu_arm_close(CPUARMState *s);
 241 void do_interrupt(CPUARMState *);
 242 void switch_mode(CPUARMState *, int);
 243 uint32_t do_arm_semihosting(CPUARMState *env);
 244
 245 /* you can call this signal handler from your SIGBUS and SIGSEGV
 246    signal handlers to inform the virtual CPU of exceptions. non zero
 247    is returned if the signal was handled by the virtual CPU.  */
 248 int cpu_arm_signal_handler(int host_signum, void *pinfo,
 249                            void *puc);
 250 int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
 251                               int mmu_idx);
 252 #define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault
 253
 254 static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls)
 255 {
 256   env->cp15.c13_tls2 = newtls;
 257 }
 258
 259 #define CPSR_M (0x1f)
 260 #define CPSR_T (1 << 5)
 261 #define CPSR_F (1 << 6)
 262 #define CPSR_I (1 << 7)
 263 #define CPSR_A (1 << 8)
 264 #define CPSR_E (1 << 9)
 265 #define CPSR_IT_2_7 (0xfc00)
 266 #define CPSR_GE (0xf << 16)
 267 #define CPSR_RESERVED (0xf << 20)
 268 #define CPSR_J (1 << 24)
 269 #define CPSR_IT_0_1 (3 << 25)
 270 #define CPSR_Q (1 << 27)
 271 #define CPSR_V (1 << 28)
 272 #define CPSR_C (1 << 29)
 273 #define CPSR_Z (1 << 30)
 274 #define CPSR_N (1 << 31)
 275 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
 276
 277 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
 278 #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV)
 279 /* Bits writable in user mode.  */
 280 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
 281 /* Execution state bits.  MRS read as zero, MSR writes ignored.  */
 282 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)
 283
 284 /* Return the current CPSR value.  */
 285 uint32_t cpsr_read(CPUARMState *env);
 286 /* Set the CPSR.  Note that some bits of mask must be all-set or all-clear.  */
 287 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
 288
 289 /* Return the current xPSR value.  */
 290 static inline uint32_t xpsr_read(CPUARMState *env)
 291 {
 292     int ZF;
 293     ZF = (env->ZF == 0);
 294     return (env->NF & 0x80000000) | (ZF << 30)
 295         | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
 296         | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
 297         | ((env->condexec_bits & 0xfc) << 8)
 298         | env->v7m.exception;
 299 }
 300
 301 /* Set the xPSR.  Note that some bits of mask must be all-set or all-clear.  */
 302 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
 303 {
 304     if (mask & CPSR_NZCV) {
 305         env->ZF = (~val) & CPSR_Z;
 306         env->NF = val;
 307         env->CF = (val >> 29) & 1;
 308         env->VF = (val << 3) & 0x80000000;
 309     }
 310     if (mask & CPSR_Q)
 311         env->QF = ((val & CPSR_Q) != 0);
 312     if (mask & (1 << 24))
 313         env->thumb = ((val & (1 << 24)) != 0);
 314     if (mask & CPSR_IT_0_1) {
 315         env->condexec_bits &= ~3;
 316         env->condexec_bits |= (val >> 25) & 3;
 317     }
 318     if (mask & CPSR_IT_2_7) {
 319         env->condexec_bits &= 3;
 320         env->condexec_bits |= (val >> 8) & 0xfc;
 321     }
 322     if (mask & 0x1ff) {
 323         env->v7m.exception = val & 0x1ff;
 324     }
 325 }
 326
 327 /* Return the current FPSCR value.  */
 328 uint32_t vfp_get_fpscr(CPUARMState *env);
 329 void vfp_set_fpscr(CPUARMState *env, uint32_t val);
 330
 331 enum arm_cpu_mode {
 332   ARM_CPU_MODE_USR = 0x10,
 333   ARM_CPU_MODE_FIQ = 0x11,
 334   ARM_CPU_MODE_IRQ = 0x12,
 335   ARM_CPU_MODE_SVC = 0x13,
 336   ARM_CPU_MODE_ABT = 0x17,
 337   ARM_CPU_MODE_UND = 0x1b,
 338   ARM_CPU_MODE_SYS = 0x1f
 339 };
 340
 341 /* VFP system registers.  */
 342 #define ARM_VFP_FPSID   0
 343 #define ARM_VFP_FPSCR   1
 344 #define ARM_VFP_MVFR1   6
 345 #define ARM_VFP_MVFR0   7
 346 #define ARM_VFP_FPEXC   8
 347 #define ARM_VFP_FPINST  9
 348 #define ARM_VFP_FPINST2 10
 349
 350 /* iwMMXt coprocessor control registers.  */
 351 #define ARM_IWMMXT_wCID         0
 352 #define ARM_IWMMXT_wCon         1
 353 #define ARM_IWMMXT_wCSSF        2
 354 #define ARM_IWMMXT_wCASF        3
 355 #define ARM_IWMMXT_wCGR0        8
 356 #define ARM_IWMMXT_wCGR1        9
 357 #define ARM_IWMMXT_wCGR2        10
 358 #define ARM_IWMMXT_wCGR3        11
 359
 360 enum arm_features {
 361     ARM_FEATURE_VFP,
 362     ARM_FEATURE_AUXCR,  /* ARM1026 Auxiliary control register.  */
 363     ARM_FEATURE_XSCALE, /* Intel XScale extensions.  */
 364     ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension.  */
 365     ARM_FEATURE_V6,
 366     ARM_FEATURE_V6K,
 367     ARM_FEATURE_V7,
 368     ARM_FEATURE_THUMB2,
 369     ARM_FEATURE_MPU,    /* Only has Memory Protection Unit, not full MMU.  */
 370     ARM_FEATURE_VFP3,
 371     ARM_FEATURE_VFP_FP16,
 372     ARM_FEATURE_NEON,
 373     ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */
 374     ARM_FEATURE_M, /* Microcontroller profile.  */
 375     ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling.  */
 376     ARM_FEATURE_THUMB2EE,
 377     ARM_FEATURE_V7MP,    /* v7 Multiprocessing Extensions */
 378     ARM_FEATURE_V4T,
 379     ARM_FEATURE_V5,
 380     ARM_FEATURE_STRONGARM,
 381     ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
 382     ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */
 383     ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */
 384 };
 385
 386 static inline int arm_feature(CPUARMState *env, int feature)
 387 {
 388     return (env->features & (1u << feature)) != 0;
 389 }
 390
 391 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 392
 393 /* Interface between CPU and Interrupt controller.  */
 394 void armv7m_nvic_set_pending(void *opaque, int irq);
 395 int armv7m_nvic_acknowledge_irq(void *opaque);
 396 void armv7m_nvic_complete_irq(void *opaque, int irq);
 397
 398 void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
 399                        ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
 400                        void *opaque);
 401
 402 /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
 403    Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
 404    conventional cores (ie. Application or Realtime profile).  */
 405
 406 #define IS_M(env) arm_feature(env, ARM_FEATURE_M)
 407 #define ARM_CPUID(env) (env->cp15.c0_cpuid)
 408
 409 #define ARM_CPUID_ARM1026     0x4106a262
 410 #define ARM_CPUID_ARM926      0x41069265
 411 #define ARM_CPUID_ARM946      0x41059461
 412 #define ARM_CPUID_TI915T      0x54029152
 413 #define ARM_CPUID_TI925T      0x54029252
 414 #define ARM_CPUID_SA1100      0x4401A11B
 415 #define ARM_CPUID_SA1110      0x6901B119
 416 #define ARM_CPUID_PXA250      0x69052100
 417 #define ARM_CPUID_PXA255      0x69052d00
 418 #define ARM_CPUID_PXA260      0x69052903
 419 #define ARM_CPUID_PXA261      0x69052d05
 420 #define ARM_CPUID_PXA262      0x69052d06
 421 #define ARM_CPUID_PXA270      0x69054110
 422 #define ARM_CPUID_PXA270_A0   0x69054110
 423 #define ARM_CPUID_PXA270_A1   0x69054111
 424 #define ARM_CPUID_PXA270_B0   0x69054112
 425 #define ARM_CPUID_PXA270_B1   0x69054113
 426 #define ARM_CPUID_PXA270_C0   0x69054114
 427 #define ARM_CPUID_PXA270_C5   0x69054117
 428 #define ARM_CPUID_ARM1136     0x4117b363
 429 #define ARM_CPUID_ARM1136_R2  0x4107b362
 430 #define ARM_CPUID_ARM1176     0x410fb767
 431 #define ARM_CPUID_ARM11MPCORE 0x410fb022
 432 #define ARM_CPUID_CORTEXA8    0x410fc080
 433 #define ARM_CPUID_CORTEXA9    0x410fc090
 434 #define ARM_CPUID_CORTEXM3    0x410fc231
 435 #define ARM_CPUID_ANY         0xffffffff
 436
 437 #if defined(CONFIG_USER_ONLY)
 438 #define TARGET_PAGE_BITS 12
 439 #else
 440 /* The ARM MMU allows 1k pages.  */
 441 /* ??? Linux doesn't actually use these, and they're deprecated in recent
 442    architecture revisions.  Maybe a configure option to disable them.  */
 443 #define TARGET_PAGE_BITS 10
 444 #endif
 445
 446 #define TARGET_PHYS_ADDR_SPACE_BITS 32
 447 #define TARGET_VIRT_ADDR_SPACE_BITS 32
 448
 449 #define cpu_init cpu_arm_init
 450 #define cpu_exec cpu_arm_exec
 451 #define cpu_gen_code cpu_arm_gen_code
 452 #define cpu_signal_handler cpu_arm_signal_handler
 453 #define cpu_list arm_cpu_list
 454
 455 #define CPU_SAVE_VERSION 5
 456
 457 /* MMU modes definitions */
 458 #define MMU_MODE0_SUFFIX _kernel
 459 #define MMU_MODE1_SUFFIX _user
 460 #define MMU_USER_IDX 1
 461 static inline int cpu_mmu_index (CPUState *env)
 462 {
 463     return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
 464 }
 465
 466 #if defined(CONFIG_USER_ONLY)
 467 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
 468 {
 469     if (newsp)
 470         env->regs[13] = newsp;
 471     env->regs[0] = 0;
 472 }
 473 #endif
 474
 475 #include "cpu-all.h"
 476
 477 /* Bit usage in the TB flags field: */
 478 #define ARM_TBFLAG_THUMB_SHIFT      0
 479 #define ARM_TBFLAG_THUMB_MASK       (1 << ARM_TBFLAG_THUMB_SHIFT)
 480 #define ARM_TBFLAG_VECLEN_SHIFT     1
 481 #define ARM_TBFLAG_VECLEN_MASK      (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
 482 #define ARM_TBFLAG_VECSTRIDE_SHIFT  4
 483 #define ARM_TBFLAG_VECSTRIDE_MASK   (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
 484 #define ARM_TBFLAG_PRIV_SHIFT       6
 485 #define ARM_TBFLAG_PRIV_MASK        (1 << ARM_TBFLAG_PRIV_SHIFT)
 486 #define ARM_TBFLAG_VFPEN_SHIFT      7
 487 #define ARM_TBFLAG_VFPEN_MASK       (1 << ARM_TBFLAG_VFPEN_SHIFT)
 488 #define ARM_TBFLAG_CONDEXEC_SHIFT   8
 489 #define ARM_TBFLAG_CONDEXEC_MASK    (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
 490 /* Bits 31..16 are currently unused. */
 491
 492 /* some convenience accessor macros */
 493 #define ARM_TBFLAG_THUMB(F) \
 494     (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
 495 #define ARM_TBFLAG_VECLEN(F) \
 496     (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
 497 #define ARM_TBFLAG_VECSTRIDE(F) \
 498     (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
 499 #define ARM_TBFLAG_PRIV(F) \
 500     (((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT)
 501 #define ARM_TBFLAG_VFPEN(F) \
 502     (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
 503 #define ARM_TBFLAG_CONDEXEC(F) \
 504     (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
 505
 506 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
 507                                         target_ulong *cs_base, int *flags)
 508 {
 509     int privmode;
 510     *pc = env->regs[15];
 511     *cs_base = 0;
 512     *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
 513         | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
 514         | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
 515         | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT);
 516     if (arm_feature(env, ARM_FEATURE_M)) {
 517         privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1));
 518     } else {
 519         privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR;
 520     }
 521     if (privmode) {
 522         *flags |= ARM_TBFLAG_PRIV_MASK;
 523     }
 524     if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
 525         *flags |= ARM_TBFLAG_VFPEN_MASK;
 526     }
 527 }
 528
 529 static inline bool cpu_has_work(CPUState *env)
 530 {
 531     return env->interrupt_request &
 532         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
 533 }
 534
 535 #include "exec-all.h"
 536
 537 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
 538 {
 539     env->regs[15] = tb->pc;
 540 }
 541
 542 #endif