hw/isa/piix4.c

   1 /*
   2  * QEMU PIIX4 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  * Copyright (c) 2018 Hervé Poussineau
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "qapi/error.h"
  28 #include "hw/irq.h"
  29 #include "hw/southbridge/piix.h"
  30 #include "hw/pci/pci.h"
  31 #include "hw/isa/isa.h"
  32 #include "hw/intc/i8259.h"
  33 #include "hw/dma/i8257.h"
  34 #include "hw/timer/i8254.h"
  35 #include "hw/rtc/mc146818rtc.h"
  36 #include "hw/ide/pci.h"
  37 #include "migration/vmstate.h"
  38 #include "sysemu/reset.h"
  39 #include "sysemu/runstate.h"
  40 #include "qom/object.h"
  41
  42 PCIDevice *piix4_dev;
  43
  44 struct PIIX4State {
  45     PCIDevice dev;
  46     qemu_irq cpu_intr;
  47     qemu_irq *isa;
  48     qemu_irq i8259[ISA_NUM_IRQS];
  49
  50     RTCState rtc;
  51     /* Reset Control Register */
  52     MemoryRegion rcr_mem;
  53     uint8_t rcr;
  54 };
  55
  56 OBJECT_DECLARE_SIMPLE_TYPE(PIIX4State, PIIX4_PCI_DEVICE)
  57
  58 static void piix4_set_irq(void *opaque, int irq_num, int level)
  59 {
  60     int i, pic_irq, pic_level;
  61     qemu_irq *pic = opaque;
  62     PCIBus *bus = pci_get_bus(piix4_dev);
  63
  64     /* now we change the pic irq level according to the piix irq mappings */
  65     /* XXX: optimize */
  66     pic_irq = piix4_dev->config[PIIX_PIRQCA + irq_num];
  67     if (pic_irq < 16) {
  68         /* The pic level is the logical OR of all the PCI irqs mapped to it. */
  69         pic_level = 0;
  70         for (i = 0; i < 4; i++) {
  71             if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) {
  72                 pic_level |= pci_bus_get_irq_level(bus, i);
  73             }
  74         }
  75         qemu_set_irq(pic[pic_irq], pic_level);
  76     }
  77 }
  78
  79 static void piix4_isa_reset(DeviceState *dev)
  80 {
  81     PIIX4State *d = PIIX4_PCI_DEVICE(dev);
  82     uint8_t *pci_conf = d->dev.config;
  83
  84     pci_conf[0x04] = 0x07; // master, memory and I/O
  85     pci_conf[0x05] = 0x00;
  86     pci_conf[0x06] = 0x00;
  87     pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
  88     pci_conf[0x4c] = 0x4d;
  89     pci_conf[0x4e] = 0x03;
  90     pci_conf[0x4f] = 0x00;
  91     pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10
  92     pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10
  93     pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11
  94     pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11
  95     pci_conf[0x69] = 0x02;
  96     pci_conf[0x70] = 0x80;
  97     pci_conf[0x76] = 0x0c;
  98     pci_conf[0x77] = 0x0c;
  99     pci_conf[0x78] = 0x02;
 100     pci_conf[0x79] = 0x00;
 101     pci_conf[0x80] = 0x00;
 102     pci_conf[0x82] = 0x00;
 103     pci_conf[0xa0] = 0x08;
 104     pci_conf[0xa2] = 0x00;
 105     pci_conf[0xa3] = 0x00;
 106     pci_conf[0xa4] = 0x00;
 107     pci_conf[0xa5] = 0x00;
 108     pci_conf[0xa6] = 0x00;
 109     pci_conf[0xa7] = 0x00;
 110     pci_conf[0xa8] = 0x0f;
 111     pci_conf[0xaa] = 0x00;
 112     pci_conf[0xab] = 0x00;
 113     pci_conf[0xac] = 0x00;
 114     pci_conf[0xae] = 0x00;
 115 }
 116
 117 static int piix4_ide_post_load(void *opaque, int version_id)
 118 {
 119     PIIX4State *s = opaque;
 120
 121     if (version_id == 2) {
 122         s->rcr = 0;
 123     }
 124
 125     return 0;
 126 }
 127
 128 static const VMStateDescription vmstate_piix4 = {
 129     .name = "PIIX4",
 130     .version_id = 3,
 131     .minimum_version_id = 2,
 132     .post_load = piix4_ide_post_load,
 133     .fields = (VMStateField[]) {
 134         VMSTATE_PCI_DEVICE(dev, PIIX4State),
 135         VMSTATE_UINT8_V(rcr, PIIX4State, 3),
 136         VMSTATE_END_OF_LIST()
 137     }
 138 };
 139
 140 static void piix4_request_i8259_irq(void *opaque, int irq, int level)
 141 {
 142     PIIX4State *s = opaque;
 143     qemu_set_irq(s->cpu_intr, level);
 144 }
 145
 146 static void piix4_set_i8259_irq(void *opaque, int irq, int level)
 147 {
 148     PIIX4State *s = opaque;
 149     qemu_set_irq(s->isa[irq], level);
 150 }
 151
 152 static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
 153                             unsigned int len)
 154 {
 155     PIIX4State *s = opaque;
 156
 157     if (val & 4) {
 158         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 159         return;
 160     }
 161
 162     s->rcr = val & 2; /* keep System Reset type only */
 163 }
 164
 165 static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len)
 166 {
 167     PIIX4State *s = opaque;
 168
 169     return s->rcr;
 170 }
 171
 172 static const MemoryRegionOps piix4_rcr_ops = {
 173     .read = piix4_rcr_read,
 174     .write = piix4_rcr_write,
 175     .endianness = DEVICE_LITTLE_ENDIAN,
 176     .impl = {
 177         .min_access_size = 1,
 178         .max_access_size = 1,
 179     },
 180 };
 181
 182 static void piix4_realize(PCIDevice *dev, Error **errp)
 183 {
 184     PIIX4State *s = PIIX4_PCI_DEVICE(dev);
 185     ISABus *isa_bus;
 186     qemu_irq *i8259_out_irq;
 187
 188     isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev),
 189                           pci_address_space_io(dev), errp);
 190     if (!isa_bus) {
 191         return;
 192     }
 193
 194     qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq,
 195                             "isa", ISA_NUM_IRQS);
 196     qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr,
 197                              "intr", 1);
 198
 199     memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
 200                           "reset-control", 1);
 201     memory_region_add_subregion_overlap(pci_address_space_io(dev),
 202                                         PIIX_RCR_IOPORT, &s->rcr_mem, 1);
 203
 204     /* initialize i8259 pic */
 205     i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1);
 206     s->isa = i8259_init(isa_bus, *i8259_out_irq);
 207
 208     /* initialize ISA irqs */
 209     isa_bus_irqs(isa_bus, s->isa);
 210
 211     /* initialize pit */
 212     i8254_pit_init(isa_bus, 0x40, 0, NULL);
 213
 214     /* DMA */
 215     i8257_dma_init(isa_bus, 0);
 216
 217     /* RTC */
 218     qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000);
 219     if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) {
 220         return;
 221     }
 222     isa_init_irq(ISA_DEVICE(&s->rtc), &s->rtc.irq, RTC_ISA_IRQ);
 223
 224     piix4_dev = dev;
 225 }
 226
 227 static void piix4_init(Object *obj)
 228 {
 229     PIIX4State *s = PIIX4_PCI_DEVICE(obj);
 230
 231     object_initialize(&s->rtc, sizeof(s->rtc), TYPE_MC146818_RTC);
 232 }
 233
 234 static void piix4_class_init(ObjectClass *klass, void *data)
 235 {
 236     DeviceClass *dc = DEVICE_CLASS(klass);
 237     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 238
 239     k->realize = piix4_realize;
 240     k->vendor_id = PCI_VENDOR_ID_INTEL;
 241     k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0;
 242     k->class_id = PCI_CLASS_BRIDGE_ISA;
 243     dc->reset = piix4_isa_reset;
 244     dc->desc = "ISA bridge";
 245     dc->vmsd = &vmstate_piix4;
 246     /*
 247      * Reason: part of PIIX4 southbridge, needs to be wired up,
 248      * e.g. by mips_malta_init()
 249      */
 250     dc->user_creatable = false;
 251     dc->hotpluggable = false;
 252 }
 253
 254 static const TypeInfo piix4_info = {
 255     .name          = TYPE_PIIX4_PCI_DEVICE,
 256     .parent        = TYPE_PCI_DEVICE,
 257     .instance_size = sizeof(PIIX4State),
 258     .instance_init = piix4_init,
 259     .class_init    = piix4_class_init,
 260     .interfaces = (InterfaceInfo[]) {
 261         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 262         { },
 263     },
 264 };
 265
 266 static void piix4_register_types(void)
 267 {
 268     type_register_static(&piix4_info);
 269 }
 270
 271 type_init(piix4_register_types)
 272
 273 static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
 274 {
 275     int slot;
 276
 277     slot = PCI_SLOT(pci_dev->devfn);
 278
 279     switch (slot) {
 280     /* PIIX4 USB */
 281     case 10:
 282         return 3;
 283     /* AMD 79C973 Ethernet */
 284     case 11:
 285         return 1;
 286     /* Crystal 4281 Sound */
 287     case 12:
 288         return 2;
 289     /* PCI slot 1 to 4 */
 290     case 18 ... 21:
 291         return ((slot - 18) + irq_num) & 0x03;
 292     /* Unknown device, don't do any translation */
 293     default:
 294         return irq_num;
 295     }
 296 }
 297
 298 DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus)
 299 {
 300     PIIX4State *s;
 301     PCIDevice *pci;
 302     DeviceState *dev;
 303     int devfn = PCI_DEVFN(10, 0);
 304
 305     pci = pci_create_simple_multifunction(pci_bus, devfn,  true,
 306                                           TYPE_PIIX4_PCI_DEVICE);
 307     dev = DEVICE(pci);
 308     s = PIIX4_PCI_DEVICE(pci);
 309     if (isa_bus) {
 310         *isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
 311     }
 312
 313     pci = pci_create_simple(pci_bus, devfn + 1, "piix4-ide");
 314     pci_ide_create_devs(pci);
 315
 316     pci_create_simple(pci_bus, devfn + 2, "piix4-usb-uhci");
 317     if (smbus) {
 318         *smbus = piix4_pm_init(pci_bus, devfn + 3, 0x1100,
 319                                qdev_get_gpio_in_named(dev, "isa", 9),
 320                                NULL, 0, NULL);
 321     }
 322
 323     pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s->i8259, 4);
 324
 325     for (int i = 0; i < ISA_NUM_IRQS; i++) {
 326         s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
 327     }
 328
 329     return dev;
 330 }