2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu-timer.h"
28 #include "sparc32_dma.h"
33 #include "firmware_abi.h"
39 #include "empty_slot.h"
40 #include "qdev-addr.h"
47 * Sun4m architecture was used in the following machines:
49 * SPARCserver 6xxMP/xx
50 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
51 * SPARCclassic X (4/10)
52 * SPARCstation LX/ZX (4/30)
53 * SPARCstation Voyager
54 * SPARCstation 10/xx, SPARCserver 10/xx
55 * SPARCstation 5, SPARCserver 5
56 * SPARCstation 20/xx, SPARCserver 20
59 * Sun4d architecture was used in the following machines:
64 * Sun4c architecture was used in the following machines:
65 * SPARCstation 1/1+, SPARCserver 1/1+
71 * See for example: http://www.sunhelp.org/faq/sunref1.html
74 #define KERNEL_LOAD_ADDR 0x00004000
75 #define CMDLINE_ADDR 0x007ff000
76 #define INITRD_LOAD_ADDR 0x00800000
77 #define PROM_SIZE_MAX (1024 * 1024)
78 #define PROM_VADDR 0xffd00000
79 #define PROM_FILENAME "openbios-sparc32"
80 #define CFG_ADDR 0xd00000510ULL
81 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
87 #define ESCC_CLOCK 4915200
90 target_phys_addr_t iommu_base
, iommu_pad_base
, iommu_pad_len
, slavio_base
;
91 target_phys_addr_t intctl_base
, counter_base
, nvram_base
, ms_kb_base
;
92 target_phys_addr_t serial_base
, fd_base
;
93 target_phys_addr_t afx_base
, idreg_base
, dma_base
, esp_base
, le_base
;
94 target_phys_addr_t tcx_base
, cs_base
, apc_base
, aux1_base
, aux2_base
;
95 target_phys_addr_t bpp_base
, dbri_base
, sx_base
;
97 target_phys_addr_t reg_base
, vram_base
;
99 target_phys_addr_t ecc_base
;
101 const char * const default_cpu_model
;
102 uint32_t ecc_version
;
103 uint32_t iommu_version
;
105 uint8_t nvram_machine_id
;
108 #define MAX_IOUNITS 5
111 target_phys_addr_t iounit_bases
[MAX_IOUNITS
], slavio_base
;
112 target_phys_addr_t counter_base
, nvram_base
, ms_kb_base
;
113 target_phys_addr_t serial_base
;
114 target_phys_addr_t espdma_base
, esp_base
;
115 target_phys_addr_t ledma_base
, le_base
;
116 target_phys_addr_t tcx_base
;
117 target_phys_addr_t sbi_base
;
119 const char * const default_cpu_model
;
120 uint32_t iounit_version
;
122 uint8_t nvram_machine_id
;
126 target_phys_addr_t iommu_base
, slavio_base
;
127 target_phys_addr_t intctl_base
, counter_base
, nvram_base
, ms_kb_base
;
128 target_phys_addr_t serial_base
, fd_base
;
129 target_phys_addr_t idreg_base
, dma_base
, esp_base
, le_base
;
130 target_phys_addr_t tcx_base
, aux1_base
;
132 const char * const default_cpu_model
;
133 uint32_t iommu_version
;
135 uint8_t nvram_machine_id
;
138 int DMA_get_channel_mode (int nchan
)
142 int DMA_read_memory (int nchan
, void *buf
, int pos
, int size
)
146 int DMA_write_memory (int nchan
, void *buf
, int pos
, int size
)
150 void DMA_hold_DREQ (int nchan
) {}
151 void DMA_release_DREQ (int nchan
) {}
152 void DMA_schedule(int nchan
) {}
154 void DMA_init(int high_page_enable
, qemu_irq
*cpu_request_exit
)
158 void DMA_register_channel (int nchan
,
159 DMA_transfer_handler transfer_handler
,
164 static int fw_cfg_boot_set(void *opaque
, const char *boot_device
)
166 fw_cfg_add_i16(opaque
, FW_CFG_BOOT_DEVICE
, boot_device
[0]);
170 static void nvram_init(M48t59State
*nvram
, uint8_t *macaddr
,
171 const char *cmdline
, const char *boot_devices
,
172 ram_addr_t RAM_size
, uint32_t kernel_size
,
173 int width
, int height
, int depth
,
174 int nvram_machine_id
, const char *arch
)
178 uint8_t image
[0x1ff0];
179 struct OpenBIOS_nvpart_v1
*part_header
;
181 memset(image
, '\0', sizeof(image
));
185 // OpenBIOS nvram variables
186 // Variable partition
187 part_header
= (struct OpenBIOS_nvpart_v1
*)&image
[start
];
188 part_header
->signature
= OPENBIOS_PART_SYSTEM
;
189 pstrcpy(part_header
->name
, sizeof(part_header
->name
), "system");
191 end
= start
+ sizeof(struct OpenBIOS_nvpart_v1
);
192 for (i
= 0; i
< nb_prom_envs
; i
++)
193 end
= OpenBIOS_set_var(image
, end
, prom_envs
[i
]);
198 end
= start
+ ((end
- start
+ 15) & ~15);
199 OpenBIOS_finish_partition(part_header
, end
- start
);
203 part_header
= (struct OpenBIOS_nvpart_v1
*)&image
[start
];
204 part_header
->signature
= OPENBIOS_PART_FREE
;
205 pstrcpy(part_header
->name
, sizeof(part_header
->name
), "free");
208 OpenBIOS_finish_partition(part_header
, end
- start
);
210 Sun_init_header((struct Sun_nvram
*)&image
[0x1fd8], macaddr
,
213 for (i
= 0; i
< sizeof(image
); i
++)
214 m48t59_write(nvram
, i
, image
[i
]);
217 static DeviceState
*slavio_intctl
;
219 void sun4m_pic_info(Monitor
*mon
)
222 slavio_pic_info(mon
, slavio_intctl
);
225 void sun4m_irq_info(Monitor
*mon
)
228 slavio_irq_info(mon
, slavio_intctl
);
231 void cpu_check_irqs(CPUSPARCState
*env
)
233 if (env
->pil_in
&& (env
->interrupt_index
== 0 ||
234 (env
->interrupt_index
& ~15) == TT_EXTINT
)) {
237 for (i
= 15; i
> 0; i
--) {
238 if (env
->pil_in
& (1 << i
)) {
239 int old_interrupt
= env
->interrupt_index
;
241 env
->interrupt_index
= TT_EXTINT
| i
;
242 if (old_interrupt
!= env
->interrupt_index
) {
243 trace_sun4m_cpu_interrupt(i
);
244 cpu_interrupt(env
, CPU_INTERRUPT_HARD
);
249 } else if (!env
->pil_in
&& (env
->interrupt_index
& ~15) == TT_EXTINT
) {
250 trace_sun4m_cpu_reset_interrupt(env
->interrupt_index
& 15);
251 env
->interrupt_index
= 0;
252 cpu_reset_interrupt(env
, CPU_INTERRUPT_HARD
);
256 static void cpu_kick_irq(CPUSPARCState
*env
)
263 static void cpu_set_irq(void *opaque
, int irq
, int level
)
265 CPUSPARCState
*env
= opaque
;
268 trace_sun4m_cpu_set_irq_raise(irq
);
269 env
->pil_in
|= 1 << irq
;
272 trace_sun4m_cpu_set_irq_lower(irq
);
273 env
->pil_in
&= ~(1 << irq
);
278 static void dummy_cpu_set_irq(void *opaque
, int irq
, int level
)
282 static void main_cpu_reset(void *opaque
)
284 CPUSPARCState
*env
= opaque
;
286 cpu_state_reset(env
);
290 static void secondary_cpu_reset(void *opaque
)
292 CPUSPARCState
*env
= opaque
;
294 cpu_state_reset(env
);
298 static void cpu_halt_signal(void *opaque
, int irq
, int level
)
300 if (level
&& cpu_single_env
)
301 cpu_interrupt(cpu_single_env
, CPU_INTERRUPT_HALT
);
304 static uint64_t translate_kernel_address(void *opaque
, uint64_t addr
)
306 return addr
- 0xf0000000ULL
;
309 static unsigned long sun4m_load_kernel(const char *kernel_filename
,
310 const char *initrd_filename
,
315 long initrd_size
, kernel_size
;
318 linux_boot
= (kernel_filename
!= NULL
);
329 kernel_size
= load_elf(kernel_filename
, translate_kernel_address
, NULL
,
330 NULL
, NULL
, NULL
, 1, ELF_MACHINE
, 0);
332 kernel_size
= load_aout(kernel_filename
, KERNEL_LOAD_ADDR
,
333 RAM_size
- KERNEL_LOAD_ADDR
, bswap_needed
,
336 kernel_size
= load_image_targphys(kernel_filename
,
338 RAM_size
- KERNEL_LOAD_ADDR
);
339 if (kernel_size
< 0) {
340 fprintf(stderr
, "qemu: could not load kernel '%s'\n",
347 if (initrd_filename
) {
348 initrd_size
= load_image_targphys(initrd_filename
,
350 RAM_size
- INITRD_LOAD_ADDR
);
351 if (initrd_size
< 0) {
352 fprintf(stderr
, "qemu: could not load initial ram disk '%s'\n",
357 if (initrd_size
> 0) {
358 for (i
= 0; i
< 64 * TARGET_PAGE_SIZE
; i
+= TARGET_PAGE_SIZE
) {
359 ptr
= rom_ptr(KERNEL_LOAD_ADDR
+ i
);
360 if (ldl_p(ptr
) == 0x48647253) { // HdrS
361 stl_p(ptr
+ 16, INITRD_LOAD_ADDR
);
362 stl_p(ptr
+ 20, initrd_size
);
371 static void *iommu_init(target_phys_addr_t addr
, uint32_t version
, qemu_irq irq
)
376 dev
= qdev_create(NULL
, "iommu");
377 qdev_prop_set_uint32(dev
, "version", version
);
378 qdev_init_nofail(dev
);
379 s
= sysbus_from_qdev(dev
);
380 sysbus_connect_irq(s
, 0, irq
);
381 sysbus_mmio_map(s
, 0, addr
);
386 static void *sparc32_dma_init(target_phys_addr_t daddr
, qemu_irq parent_irq
,
387 void *iommu
, qemu_irq
*dev_irq
, int is_ledma
)
392 dev
= qdev_create(NULL
, "sparc32_dma");
393 qdev_prop_set_ptr(dev
, "iommu_opaque", iommu
);
394 qdev_prop_set_uint32(dev
, "is_ledma", is_ledma
);
395 qdev_init_nofail(dev
);
396 s
= sysbus_from_qdev(dev
);
397 sysbus_connect_irq(s
, 0, parent_irq
);
398 *dev_irq
= qdev_get_gpio_in(dev
, 0);
399 sysbus_mmio_map(s
, 0, daddr
);
404 static void lance_init(NICInfo
*nd
, target_phys_addr_t leaddr
,
405 void *dma_opaque
, qemu_irq irq
)
411 qemu_check_nic_model(&nd_table
[0], "lance");
413 dev
= qdev_create(NULL
, "lance");
414 qdev_set_nic_properties(dev
, nd
);
415 qdev_prop_set_ptr(dev
, "dma", dma_opaque
);
416 qdev_init_nofail(dev
);
417 s
= sysbus_from_qdev(dev
);
418 sysbus_mmio_map(s
, 0, leaddr
);
419 sysbus_connect_irq(s
, 0, irq
);
420 reset
= qdev_get_gpio_in(dev
, 0);
421 qdev_connect_gpio_out(dma_opaque
, 0, reset
);
424 static DeviceState
*slavio_intctl_init(target_phys_addr_t addr
,
425 target_phys_addr_t addrg
,
426 qemu_irq
**parent_irq
)
432 dev
= qdev_create(NULL
, "slavio_intctl");
433 qdev_init_nofail(dev
);
435 s
= sysbus_from_qdev(dev
);
437 for (i
= 0; i
< MAX_CPUS
; i
++) {
438 for (j
= 0; j
< MAX_PILS
; j
++) {
439 sysbus_connect_irq(s
, i
* MAX_PILS
+ j
, parent_irq
[i
][j
]);
442 sysbus_mmio_map(s
, 0, addrg
);
443 for (i
= 0; i
< MAX_CPUS
; i
++) {
444 sysbus_mmio_map(s
, i
+ 1, addr
+ i
* TARGET_PAGE_SIZE
);
450 #define SYS_TIMER_OFFSET 0x10000ULL
451 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
453 static void slavio_timer_init_all(target_phys_addr_t addr
, qemu_irq master_irq
,
454 qemu_irq
*cpu_irqs
, unsigned int num_cpus
)
460 dev
= qdev_create(NULL
, "slavio_timer");
461 qdev_prop_set_uint32(dev
, "num_cpus", num_cpus
);
462 qdev_init_nofail(dev
);
463 s
= sysbus_from_qdev(dev
);
464 sysbus_connect_irq(s
, 0, master_irq
);
465 sysbus_mmio_map(s
, 0, addr
+ SYS_TIMER_OFFSET
);
467 for (i
= 0; i
< MAX_CPUS
; i
++) {
468 sysbus_mmio_map(s
, i
+ 1, addr
+ (target_phys_addr_t
)CPU_TIMER_OFFSET(i
));
469 sysbus_connect_irq(s
, i
+ 1, cpu_irqs
[i
]);
473 #define MISC_LEDS 0x01600000
474 #define MISC_CFG 0x01800000
475 #define MISC_DIAG 0x01a00000
476 #define MISC_MDM 0x01b00000
477 #define MISC_SYS 0x01f00000
479 static void slavio_misc_init(target_phys_addr_t base
,
480 target_phys_addr_t aux1_base
,
481 target_phys_addr_t aux2_base
, qemu_irq irq
,
487 dev
= qdev_create(NULL
, "slavio_misc");
488 qdev_init_nofail(dev
);
489 s
= sysbus_from_qdev(dev
);
491 /* 8 bit registers */
493 sysbus_mmio_map(s
, 0, base
+ MISC_CFG
);
495 sysbus_mmio_map(s
, 1, base
+ MISC_DIAG
);
497 sysbus_mmio_map(s
, 2, base
+ MISC_MDM
);
498 /* 16 bit registers */
499 /* ss600mp diag LEDs */
500 sysbus_mmio_map(s
, 3, base
+ MISC_LEDS
);
501 /* 32 bit registers */
503 sysbus_mmio_map(s
, 4, base
+ MISC_SYS
);
506 /* AUX 1 (Misc System Functions) */
507 sysbus_mmio_map(s
, 5, aux1_base
);
510 /* AUX 2 (Software Powerdown Control) */
511 sysbus_mmio_map(s
, 6, aux2_base
);
513 sysbus_connect_irq(s
, 0, irq
);
514 sysbus_connect_irq(s
, 1, fdc_tc
);
515 qemu_system_powerdown
= qdev_get_gpio_in(dev
, 0);
518 static void ecc_init(target_phys_addr_t base
, qemu_irq irq
, uint32_t version
)
523 dev
= qdev_create(NULL
, "eccmemctl");
524 qdev_prop_set_uint32(dev
, "version", version
);
525 qdev_init_nofail(dev
);
526 s
= sysbus_from_qdev(dev
);
527 sysbus_connect_irq(s
, 0, irq
);
528 sysbus_mmio_map(s
, 0, base
);
529 if (version
== 0) { // SS-600MP only
530 sysbus_mmio_map(s
, 1, base
+ 0x1000);
534 static void apc_init(target_phys_addr_t power_base
, qemu_irq cpu_halt
)
539 dev
= qdev_create(NULL
, "apc");
540 qdev_init_nofail(dev
);
541 s
= sysbus_from_qdev(dev
);
542 /* Power management (APC) XXX: not a Slavio device */
543 sysbus_mmio_map(s
, 0, power_base
);
544 sysbus_connect_irq(s
, 0, cpu_halt
);
547 static void tcx_init(target_phys_addr_t addr
, int vram_size
, int width
,
548 int height
, int depth
)
553 dev
= qdev_create(NULL
, "SUNW,tcx");
554 qdev_prop_set_taddr(dev
, "addr", addr
);
555 qdev_prop_set_uint32(dev
, "vram_size", vram_size
);
556 qdev_prop_set_uint16(dev
, "width", width
);
557 qdev_prop_set_uint16(dev
, "height", height
);
558 qdev_prop_set_uint16(dev
, "depth", depth
);
559 qdev_init_nofail(dev
);
560 s
= sysbus_from_qdev(dev
);
562 sysbus_mmio_map(s
, 0, addr
+ 0x00800000ULL
);
564 sysbus_mmio_map(s
, 1, addr
+ 0x00200000ULL
);
566 sysbus_mmio_map(s
, 2, addr
+ 0x00700000ULL
);
567 /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
568 sysbus_mmio_map(s
, 3, addr
+ 0x00301000ULL
);
571 sysbus_mmio_map(s
, 4, addr
+ 0x02000000ULL
);
573 sysbus_mmio_map(s
, 5, addr
+ 0x0a000000ULL
);
575 /* THC 8 bit (dummy) */
576 sysbus_mmio_map(s
, 4, addr
+ 0x00300000ULL
);
580 /* NCR89C100/MACIO Internal ID register */
581 static const uint8_t idreg_data
[] = { 0xfe, 0x81, 0x01, 0x03 };
583 static void idreg_init(target_phys_addr_t addr
)
588 dev
= qdev_create(NULL
, "macio_idreg");
589 qdev_init_nofail(dev
);
590 s
= sysbus_from_qdev(dev
);
592 sysbus_mmio_map(s
, 0, addr
);
593 cpu_physical_memory_write_rom(addr
, idreg_data
, sizeof(idreg_data
));
596 typedef struct IDRegState
{
601 static int idreg_init1(SysBusDevice
*dev
)
603 IDRegState
*s
= FROM_SYSBUS(IDRegState
, dev
);
605 memory_region_init_ram(&s
->mem
, "sun4m.idreg", sizeof(idreg_data
));
606 vmstate_register_ram_global(&s
->mem
);
607 memory_region_set_readonly(&s
->mem
, true);
608 sysbus_init_mmio(dev
, &s
->mem
);
612 static void idreg_class_init(ObjectClass
*klass
, void *data
)
614 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
616 k
->init
= idreg_init1
;
619 static TypeInfo idreg_info
= {
620 .name
= "macio_idreg",
621 .parent
= TYPE_SYS_BUS_DEVICE
,
622 .instance_size
= sizeof(IDRegState
),
623 .class_init
= idreg_class_init
,
626 typedef struct AFXState
{
631 /* SS-5 TCX AFX register */
632 static void afx_init(target_phys_addr_t addr
)
637 dev
= qdev_create(NULL
, "tcx_afx");
638 qdev_init_nofail(dev
);
639 s
= sysbus_from_qdev(dev
);
641 sysbus_mmio_map(s
, 0, addr
);
644 static int afx_init1(SysBusDevice
*dev
)
646 AFXState
*s
= FROM_SYSBUS(AFXState
, dev
);
648 memory_region_init_ram(&s
->mem
, "sun4m.afx", 4);
649 vmstate_register_ram_global(&s
->mem
);
650 sysbus_init_mmio(dev
, &s
->mem
);
654 static void afx_class_init(ObjectClass
*klass
, void *data
)
656 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
661 static TypeInfo afx_info
= {
663 .parent
= TYPE_SYS_BUS_DEVICE
,
664 .instance_size
= sizeof(AFXState
),
665 .class_init
= afx_class_init
,
668 typedef struct PROMState
{
673 /* Boot PROM (OpenBIOS) */
674 static uint64_t translate_prom_address(void *opaque
, uint64_t addr
)
676 target_phys_addr_t
*base_addr
= (target_phys_addr_t
*)opaque
;
677 return addr
+ *base_addr
- PROM_VADDR
;
680 static void prom_init(target_phys_addr_t addr
, const char *bios_name
)
687 dev
= qdev_create(NULL
, "openprom");
688 qdev_init_nofail(dev
);
689 s
= sysbus_from_qdev(dev
);
691 sysbus_mmio_map(s
, 0, addr
);
694 if (bios_name
== NULL
) {
695 bios_name
= PROM_FILENAME
;
697 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
699 ret
= load_elf(filename
, translate_prom_address
, &addr
, NULL
,
700 NULL
, NULL
, 1, ELF_MACHINE
, 0);
701 if (ret
< 0 || ret
> PROM_SIZE_MAX
) {
702 ret
= load_image_targphys(filename
, addr
, PROM_SIZE_MAX
);
708 if (ret
< 0 || ret
> PROM_SIZE_MAX
) {
709 fprintf(stderr
, "qemu: could not load prom '%s'\n", bios_name
);
714 static int prom_init1(SysBusDevice
*dev
)
716 PROMState
*s
= FROM_SYSBUS(PROMState
, dev
);
718 memory_region_init_ram(&s
->prom
, "sun4m.prom", PROM_SIZE_MAX
);
719 vmstate_register_ram_global(&s
->prom
);
720 memory_region_set_readonly(&s
->prom
, true);
721 sysbus_init_mmio(dev
, &s
->prom
);
725 static Property prom_properties
[] = {
726 {/* end of property list */},
729 static void prom_class_init(ObjectClass
*klass
, void *data
)
731 DeviceClass
*dc
= DEVICE_CLASS(klass
);
732 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
734 k
->init
= prom_init1
;
735 dc
->props
= prom_properties
;
738 static TypeInfo prom_info
= {
740 .parent
= TYPE_SYS_BUS_DEVICE
,
741 .instance_size
= sizeof(PROMState
),
742 .class_init
= prom_class_init
,
745 typedef struct RamDevice
753 static int ram_init1(SysBusDevice
*dev
)
755 RamDevice
*d
= FROM_SYSBUS(RamDevice
, dev
);
757 memory_region_init_ram(&d
->ram
, "sun4m.ram", d
->size
);
758 vmstate_register_ram_global(&d
->ram
);
759 sysbus_init_mmio(dev
, &d
->ram
);
763 static void ram_init(target_phys_addr_t addr
, ram_addr_t RAM_size
,
771 if ((uint64_t)RAM_size
> max_mem
) {
773 "qemu: Too much memory for this machine: %d, maximum %d\n",
774 (unsigned int)(RAM_size
/ (1024 * 1024)),
775 (unsigned int)(max_mem
/ (1024 * 1024)));
778 dev
= qdev_create(NULL
, "memory");
779 s
= sysbus_from_qdev(dev
);
781 d
= FROM_SYSBUS(RamDevice
, s
);
783 qdev_init_nofail(dev
);
785 sysbus_mmio_map(s
, 0, addr
);
788 static Property ram_properties
[] = {
789 DEFINE_PROP_UINT64("size", RamDevice
, size
, 0),
790 DEFINE_PROP_END_OF_LIST(),
793 static void ram_class_init(ObjectClass
*klass
, void *data
)
795 DeviceClass
*dc
= DEVICE_CLASS(klass
);
796 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
799 dc
->props
= ram_properties
;
802 static TypeInfo ram_info
= {
804 .parent
= TYPE_SYS_BUS_DEVICE
,
805 .instance_size
= sizeof(RamDevice
),
806 .class_init
= ram_class_init
,
809 static void cpu_devinit(const char *cpu_model
, unsigned int id
,
810 uint64_t prom_addr
, qemu_irq
**cpu_irqs
)
814 env
= cpu_init(cpu_model
);
816 fprintf(stderr
, "qemu: Unable to find Sparc CPU definition\n");
820 cpu_sparc_set_id(env
, id
);
822 qemu_register_reset(main_cpu_reset
, env
);
824 qemu_register_reset(secondary_cpu_reset
, env
);
827 *cpu_irqs
= qemu_allocate_irqs(cpu_set_irq
, env
, MAX_PILS
);
828 env
->prom_addr
= prom_addr
;
831 static void sun4m_hw_init(const struct sun4m_hwdef
*hwdef
, ram_addr_t RAM_size
,
832 const char *boot_device
,
833 const char *kernel_filename
,
834 const char *kernel_cmdline
,
835 const char *initrd_filename
, const char *cpu_model
)
838 void *iommu
, *espdma
, *ledma
, *nvram
;
839 qemu_irq
*cpu_irqs
[MAX_CPUS
], slavio_irq
[32], slavio_cpu_irq
[MAX_CPUS
],
840 espdma_irq
, ledma_irq
;
841 qemu_irq esp_reset
, dma_enable
;
844 unsigned long kernel_size
;
845 DriveInfo
*fd
[MAX_FD
];
847 unsigned int num_vsimms
;
851 cpu_model
= hwdef
->default_cpu_model
;
853 for(i
= 0; i
< smp_cpus
; i
++) {
854 cpu_devinit(cpu_model
, i
, hwdef
->slavio_base
, &cpu_irqs
[i
]);
857 for (i
= smp_cpus
; i
< MAX_CPUS
; i
++)
858 cpu_irqs
[i
] = qemu_allocate_irqs(dummy_cpu_set_irq
, NULL
, MAX_PILS
);
862 ram_init(0, RAM_size
, hwdef
->max_mem
);
863 /* models without ECC don't trap when missing ram is accessed */
864 if (!hwdef
->ecc_base
) {
865 empty_slot_init(RAM_size
, hwdef
->max_mem
- RAM_size
);
868 prom_init(hwdef
->slavio_base
, bios_name
);
870 slavio_intctl
= slavio_intctl_init(hwdef
->intctl_base
,
871 hwdef
->intctl_base
+ 0x10000ULL
,
874 for (i
= 0; i
< 32; i
++) {
875 slavio_irq
[i
] = qdev_get_gpio_in(slavio_intctl
, i
);
877 for (i
= 0; i
< MAX_CPUS
; i
++) {
878 slavio_cpu_irq
[i
] = qdev_get_gpio_in(slavio_intctl
, 32 + i
);
881 if (hwdef
->idreg_base
) {
882 idreg_init(hwdef
->idreg_base
);
885 if (hwdef
->afx_base
) {
886 afx_init(hwdef
->afx_base
);
889 iommu
= iommu_init(hwdef
->iommu_base
, hwdef
->iommu_version
,
892 if (hwdef
->iommu_pad_base
) {
893 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
894 Software shouldn't use aliased addresses, neither should it crash
895 when does. Using empty_slot instead of aliasing can help with
896 debugging such accesses */
897 empty_slot_init(hwdef
->iommu_pad_base
,hwdef
->iommu_pad_len
);
900 espdma
= sparc32_dma_init(hwdef
->dma_base
, slavio_irq
[18],
901 iommu
, &espdma_irq
, 0);
903 ledma
= sparc32_dma_init(hwdef
->dma_base
+ 16ULL,
904 slavio_irq
[16], iommu
, &ledma_irq
, 1);
906 if (graphic_depth
!= 8 && graphic_depth
!= 24) {
907 fprintf(stderr
, "qemu: Unsupported depth: %d\n", graphic_depth
);
911 if (num_vsimms
== 0) {
912 tcx_init(hwdef
->tcx_base
, 0x00100000, graphic_width
, graphic_height
,
916 for (i
= num_vsimms
; i
< MAX_VSIMMS
; i
++) {
917 /* vsimm registers probed by OBP */
918 if (hwdef
->vsimm
[i
].reg_base
) {
919 empty_slot_init(hwdef
->vsimm
[i
].reg_base
, 0x2000);
923 if (hwdef
->sx_base
) {
924 empty_slot_init(hwdef
->sx_base
, 0x2000);
927 lance_init(&nd_table
[0], hwdef
->le_base
, ledma
, ledma_irq
);
929 nvram
= m48t59_init(slavio_irq
[0], hwdef
->nvram_base
, 0, 0x2000, 8);
931 slavio_timer_init_all(hwdef
->counter_base
, slavio_irq
[19], slavio_cpu_irq
, smp_cpus
);
933 slavio_serial_ms_kbd_init(hwdef
->ms_kb_base
, slavio_irq
[14],
934 display_type
== DT_NOGRAPHIC
, ESCC_CLOCK
, 1);
935 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
936 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
937 escc_init(hwdef
->serial_base
, slavio_irq
[15], slavio_irq
[15],
938 serial_hds
[0], serial_hds
[1], ESCC_CLOCK
, 1);
940 cpu_halt
= qemu_allocate_irqs(cpu_halt_signal
, NULL
, 1);
941 slavio_misc_init(hwdef
->slavio_base
, hwdef
->aux1_base
, hwdef
->aux2_base
,
942 slavio_irq
[30], fdc_tc
);
944 if (hwdef
->apc_base
) {
945 apc_init(hwdef
->apc_base
, cpu_halt
[0]);
948 if (hwdef
->fd_base
) {
949 /* there is zero or one floppy drive */
950 memset(fd
, 0, sizeof(fd
));
951 fd
[0] = drive_get(IF_FLOPPY
, 0, 0);
952 sun4m_fdctrl_init(slavio_irq
[22], hwdef
->fd_base
, fd
,
956 if (drive_get_max_bus(IF_SCSI
) > 0) {
957 fprintf(stderr
, "qemu: too many SCSI bus\n");
961 esp_init(hwdef
->esp_base
, 2,
962 espdma_memory_read
, espdma_memory_write
,
963 espdma
, espdma_irq
, &esp_reset
, &dma_enable
);
965 qdev_connect_gpio_out(espdma
, 0, esp_reset
);
966 qdev_connect_gpio_out(espdma
, 1, dma_enable
);
968 if (hwdef
->cs_base
) {
969 sysbus_create_simple("SUNW,CS4231", hwdef
->cs_base
,
973 if (hwdef
->dbri_base
) {
974 /* ISDN chip with attached CS4215 audio codec */
976 empty_slot_init(hwdef
->dbri_base
+0x1000, 0x30);
978 empty_slot_init(hwdef
->dbri_base
+0x10000, 0x100);
981 if (hwdef
->bpp_base
) {
983 empty_slot_init(hwdef
->bpp_base
, 0x20);
986 kernel_size
= sun4m_load_kernel(kernel_filename
, initrd_filename
,
989 nvram_init(nvram
, (uint8_t *)&nd_table
[0].macaddr
, kernel_cmdline
,
990 boot_device
, RAM_size
, kernel_size
, graphic_width
,
991 graphic_height
, graphic_depth
, hwdef
->nvram_machine_id
,
995 ecc_init(hwdef
->ecc_base
, slavio_irq
[28],
998 fw_cfg
= fw_cfg_init(0, 0, CFG_ADDR
, CFG_ADDR
+ 2);
999 fw_cfg_add_i32(fw_cfg
, FW_CFG_ID
, 1);
1000 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
1001 fw_cfg_add_i16(fw_cfg
, FW_CFG_MACHINE_ID
, hwdef
->machine_id
);
1002 fw_cfg_add_i16(fw_cfg
, FW_CFG_SUN4M_DEPTH
, graphic_depth
);
1003 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, KERNEL_LOAD_ADDR
);
1004 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
1005 if (kernel_cmdline
) {
1006 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, CMDLINE_ADDR
);
1007 pstrcpy_targphys("cmdline", CMDLINE_ADDR
, TARGET_PAGE_SIZE
, kernel_cmdline
);
1008 fw_cfg_add_bytes(fw_cfg
, FW_CFG_CMDLINE_DATA
,
1009 (uint8_t*)strdup(kernel_cmdline
),
1010 strlen(kernel_cmdline
) + 1);
1011 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
,
1012 strlen(kernel_cmdline
) + 1);
1014 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, 0);
1015 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
, 0);
1017 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, INITRD_LOAD_ADDR
);
1018 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, 0); // not used
1019 fw_cfg_add_i16(fw_cfg
, FW_CFG_BOOT_DEVICE
, boot_device
[0]);
1020 qemu_register_boot_set(fw_cfg_boot_set
, fw_cfg
);
1038 static const struct sun4m_hwdef sun4m_hwdefs
[] = {
1041 .iommu_base
= 0x10000000,
1042 .iommu_pad_base
= 0x10004000,
1043 .iommu_pad_len
= 0x0fffb000,
1044 .tcx_base
= 0x50000000,
1045 .cs_base
= 0x6c000000,
1046 .slavio_base
= 0x70000000,
1047 .ms_kb_base
= 0x71000000,
1048 .serial_base
= 0x71100000,
1049 .nvram_base
= 0x71200000,
1050 .fd_base
= 0x71400000,
1051 .counter_base
= 0x71d00000,
1052 .intctl_base
= 0x71e00000,
1053 .idreg_base
= 0x78000000,
1054 .dma_base
= 0x78400000,
1055 .esp_base
= 0x78800000,
1056 .le_base
= 0x78c00000,
1057 .apc_base
= 0x6a000000,
1058 .afx_base
= 0x6e000000,
1059 .aux1_base
= 0x71900000,
1060 .aux2_base
= 0x71910000,
1061 .nvram_machine_id
= 0x80,
1062 .machine_id
= ss5_id
,
1063 .iommu_version
= 0x05000000,
1064 .max_mem
= 0x10000000,
1065 .default_cpu_model
= "Fujitsu MB86904",
1069 .iommu_base
= 0xfe0000000ULL
,
1070 .tcx_base
= 0xe20000000ULL
,
1071 .slavio_base
= 0xff0000000ULL
,
1072 .ms_kb_base
= 0xff1000000ULL
,
1073 .serial_base
= 0xff1100000ULL
,
1074 .nvram_base
= 0xff1200000ULL
,
1075 .fd_base
= 0xff1700000ULL
,
1076 .counter_base
= 0xff1300000ULL
,
1077 .intctl_base
= 0xff1400000ULL
,
1078 .idreg_base
= 0xef0000000ULL
,
1079 .dma_base
= 0xef0400000ULL
,
1080 .esp_base
= 0xef0800000ULL
,
1081 .le_base
= 0xef0c00000ULL
,
1082 .apc_base
= 0xefa000000ULL
, // XXX should not exist
1083 .aux1_base
= 0xff1800000ULL
,
1084 .aux2_base
= 0xff1a01000ULL
,
1085 .ecc_base
= 0xf00000000ULL
,
1086 .ecc_version
= 0x10000000, // version 0, implementation 1
1087 .nvram_machine_id
= 0x72,
1088 .machine_id
= ss10_id
,
1089 .iommu_version
= 0x03000000,
1090 .max_mem
= 0xf00000000ULL
,
1091 .default_cpu_model
= "TI SuperSparc II",
1095 .iommu_base
= 0xfe0000000ULL
,
1096 .tcx_base
= 0xe20000000ULL
,
1097 .slavio_base
= 0xff0000000ULL
,
1098 .ms_kb_base
= 0xff1000000ULL
,
1099 .serial_base
= 0xff1100000ULL
,
1100 .nvram_base
= 0xff1200000ULL
,
1101 .counter_base
= 0xff1300000ULL
,
1102 .intctl_base
= 0xff1400000ULL
,
1103 .dma_base
= 0xef0081000ULL
,
1104 .esp_base
= 0xef0080000ULL
,
1105 .le_base
= 0xef0060000ULL
,
1106 .apc_base
= 0xefa000000ULL
, // XXX should not exist
1107 .aux1_base
= 0xff1800000ULL
,
1108 .aux2_base
= 0xff1a01000ULL
, // XXX should not exist
1109 .ecc_base
= 0xf00000000ULL
,
1110 .ecc_version
= 0x00000000, // version 0, implementation 0
1111 .nvram_machine_id
= 0x71,
1112 .machine_id
= ss600mp_id
,
1113 .iommu_version
= 0x01000000,
1114 .max_mem
= 0xf00000000ULL
,
1115 .default_cpu_model
= "TI SuperSparc II",
1119 .iommu_base
= 0xfe0000000ULL
,
1120 .tcx_base
= 0xe20000000ULL
,
1121 .slavio_base
= 0xff0000000ULL
,
1122 .ms_kb_base
= 0xff1000000ULL
,
1123 .serial_base
= 0xff1100000ULL
,
1124 .nvram_base
= 0xff1200000ULL
,
1125 .fd_base
= 0xff1700000ULL
,
1126 .counter_base
= 0xff1300000ULL
,
1127 .intctl_base
= 0xff1400000ULL
,
1128 .idreg_base
= 0xef0000000ULL
,
1129 .dma_base
= 0xef0400000ULL
,
1130 .esp_base
= 0xef0800000ULL
,
1131 .le_base
= 0xef0c00000ULL
,
1132 .bpp_base
= 0xef4800000ULL
,
1133 .apc_base
= 0xefa000000ULL
, // XXX should not exist
1134 .aux1_base
= 0xff1800000ULL
,
1135 .aux2_base
= 0xff1a01000ULL
,
1136 .dbri_base
= 0xee0000000ULL
,
1137 .sx_base
= 0xf80000000ULL
,
1140 .reg_base
= 0x9c000000ULL
,
1141 .vram_base
= 0xfc000000ULL
1143 .reg_base
= 0x90000000ULL
,
1144 .vram_base
= 0xf0000000ULL
1146 .reg_base
= 0x94000000ULL
1148 .reg_base
= 0x98000000ULL
1151 .ecc_base
= 0xf00000000ULL
,
1152 .ecc_version
= 0x20000000, // version 0, implementation 2
1153 .nvram_machine_id
= 0x72,
1154 .machine_id
= ss20_id
,
1155 .iommu_version
= 0x13000000,
1156 .max_mem
= 0xf00000000ULL
,
1157 .default_cpu_model
= "TI SuperSparc II",
1161 .iommu_base
= 0x10000000,
1162 .tcx_base
= 0x50000000,
1163 .slavio_base
= 0x70000000,
1164 .ms_kb_base
= 0x71000000,
1165 .serial_base
= 0x71100000,
1166 .nvram_base
= 0x71200000,
1167 .fd_base
= 0x71400000,
1168 .counter_base
= 0x71d00000,
1169 .intctl_base
= 0x71e00000,
1170 .idreg_base
= 0x78000000,
1171 .dma_base
= 0x78400000,
1172 .esp_base
= 0x78800000,
1173 .le_base
= 0x78c00000,
1174 .apc_base
= 0x71300000, // pmc
1175 .aux1_base
= 0x71900000,
1176 .aux2_base
= 0x71910000,
1177 .nvram_machine_id
= 0x80,
1178 .machine_id
= vger_id
,
1179 .iommu_version
= 0x05000000,
1180 .max_mem
= 0x10000000,
1181 .default_cpu_model
= "Fujitsu MB86904",
1185 .iommu_base
= 0x10000000,
1186 .iommu_pad_base
= 0x10004000,
1187 .iommu_pad_len
= 0x0fffb000,
1188 .tcx_base
= 0x50000000,
1189 .slavio_base
= 0x70000000,
1190 .ms_kb_base
= 0x71000000,
1191 .serial_base
= 0x71100000,
1192 .nvram_base
= 0x71200000,
1193 .fd_base
= 0x71400000,
1194 .counter_base
= 0x71d00000,
1195 .intctl_base
= 0x71e00000,
1196 .idreg_base
= 0x78000000,
1197 .dma_base
= 0x78400000,
1198 .esp_base
= 0x78800000,
1199 .le_base
= 0x78c00000,
1200 .aux1_base
= 0x71900000,
1201 .aux2_base
= 0x71910000,
1202 .nvram_machine_id
= 0x80,
1203 .machine_id
= lx_id
,
1204 .iommu_version
= 0x04000000,
1205 .max_mem
= 0x10000000,
1206 .default_cpu_model
= "TI MicroSparc I",
1210 .iommu_base
= 0x10000000,
1211 .tcx_base
= 0x50000000,
1212 .cs_base
= 0x6c000000,
1213 .slavio_base
= 0x70000000,
1214 .ms_kb_base
= 0x71000000,
1215 .serial_base
= 0x71100000,
1216 .nvram_base
= 0x71200000,
1217 .fd_base
= 0x71400000,
1218 .counter_base
= 0x71d00000,
1219 .intctl_base
= 0x71e00000,
1220 .idreg_base
= 0x78000000,
1221 .dma_base
= 0x78400000,
1222 .esp_base
= 0x78800000,
1223 .le_base
= 0x78c00000,
1224 .apc_base
= 0x6a000000,
1225 .aux1_base
= 0x71900000,
1226 .aux2_base
= 0x71910000,
1227 .nvram_machine_id
= 0x80,
1228 .machine_id
= ss4_id
,
1229 .iommu_version
= 0x05000000,
1230 .max_mem
= 0x10000000,
1231 .default_cpu_model
= "Fujitsu MB86904",
1235 .iommu_base
= 0x10000000,
1236 .tcx_base
= 0x50000000,
1237 .slavio_base
= 0x70000000,
1238 .ms_kb_base
= 0x71000000,
1239 .serial_base
= 0x71100000,
1240 .nvram_base
= 0x71200000,
1241 .fd_base
= 0x71400000,
1242 .counter_base
= 0x71d00000,
1243 .intctl_base
= 0x71e00000,
1244 .idreg_base
= 0x78000000,
1245 .dma_base
= 0x78400000,
1246 .esp_base
= 0x78800000,
1247 .le_base
= 0x78c00000,
1248 .apc_base
= 0x6a000000,
1249 .aux1_base
= 0x71900000,
1250 .aux2_base
= 0x71910000,
1251 .nvram_machine_id
= 0x80,
1252 .machine_id
= scls_id
,
1253 .iommu_version
= 0x05000000,
1254 .max_mem
= 0x10000000,
1255 .default_cpu_model
= "TI MicroSparc I",
1259 .iommu_base
= 0x10000000,
1260 .tcx_base
= 0x50000000, // XXX
1261 .slavio_base
= 0x70000000,
1262 .ms_kb_base
= 0x71000000,
1263 .serial_base
= 0x71100000,
1264 .nvram_base
= 0x71200000,
1265 .fd_base
= 0x71400000,
1266 .counter_base
= 0x71d00000,
1267 .intctl_base
= 0x71e00000,
1268 .idreg_base
= 0x78000000,
1269 .dma_base
= 0x78400000,
1270 .esp_base
= 0x78800000,
1271 .le_base
= 0x78c00000,
1272 .apc_base
= 0x6a000000,
1273 .aux1_base
= 0x71900000,
1274 .aux2_base
= 0x71910000,
1275 .nvram_machine_id
= 0x80,
1276 .machine_id
= sbook_id
,
1277 .iommu_version
= 0x05000000,
1278 .max_mem
= 0x10000000,
1279 .default_cpu_model
= "TI MicroSparc I",
1283 /* SPARCstation 5 hardware initialisation */
1284 static void ss5_init(ram_addr_t RAM_size
,
1285 const char *boot_device
,
1286 const char *kernel_filename
, const char *kernel_cmdline
,
1287 const char *initrd_filename
, const char *cpu_model
)
1289 sun4m_hw_init(&sun4m_hwdefs
[0], RAM_size
, boot_device
, kernel_filename
,
1290 kernel_cmdline
, initrd_filename
, cpu_model
);
1293 /* SPARCstation 10 hardware initialisation */
1294 static void ss10_init(ram_addr_t RAM_size
,
1295 const char *boot_device
,
1296 const char *kernel_filename
, const char *kernel_cmdline
,
1297 const char *initrd_filename
, const char *cpu_model
)
1299 sun4m_hw_init(&sun4m_hwdefs
[1], RAM_size
, boot_device
, kernel_filename
,
1300 kernel_cmdline
, initrd_filename
, cpu_model
);
1303 /* SPARCserver 600MP hardware initialisation */
1304 static void ss600mp_init(ram_addr_t RAM_size
,
1305 const char *boot_device
,
1306 const char *kernel_filename
,
1307 const char *kernel_cmdline
,
1308 const char *initrd_filename
, const char *cpu_model
)
1310 sun4m_hw_init(&sun4m_hwdefs
[2], RAM_size
, boot_device
, kernel_filename
,
1311 kernel_cmdline
, initrd_filename
, cpu_model
);
1314 /* SPARCstation 20 hardware initialisation */
1315 static void ss20_init(ram_addr_t RAM_size
,
1316 const char *boot_device
,
1317 const char *kernel_filename
, const char *kernel_cmdline
,
1318 const char *initrd_filename
, const char *cpu_model
)
1320 sun4m_hw_init(&sun4m_hwdefs
[3], RAM_size
, boot_device
, kernel_filename
,
1321 kernel_cmdline
, initrd_filename
, cpu_model
);
1324 /* SPARCstation Voyager hardware initialisation */
1325 static void vger_init(ram_addr_t RAM_size
,
1326 const char *boot_device
,
1327 const char *kernel_filename
, const char *kernel_cmdline
,
1328 const char *initrd_filename
, const char *cpu_model
)
1330 sun4m_hw_init(&sun4m_hwdefs
[4], RAM_size
, boot_device
, kernel_filename
,
1331 kernel_cmdline
, initrd_filename
, cpu_model
);
1334 /* SPARCstation LX hardware initialisation */
1335 static void ss_lx_init(ram_addr_t RAM_size
,
1336 const char *boot_device
,
1337 const char *kernel_filename
, const char *kernel_cmdline
,
1338 const char *initrd_filename
, const char *cpu_model
)
1340 sun4m_hw_init(&sun4m_hwdefs
[5], RAM_size
, boot_device
, kernel_filename
,
1341 kernel_cmdline
, initrd_filename
, cpu_model
);
1344 /* SPARCstation 4 hardware initialisation */
1345 static void ss4_init(ram_addr_t RAM_size
,
1346 const char *boot_device
,
1347 const char *kernel_filename
, const char *kernel_cmdline
,
1348 const char *initrd_filename
, const char *cpu_model
)
1350 sun4m_hw_init(&sun4m_hwdefs
[6], RAM_size
, boot_device
, kernel_filename
,
1351 kernel_cmdline
, initrd_filename
, cpu_model
);
1354 /* SPARCClassic hardware initialisation */
1355 static void scls_init(ram_addr_t RAM_size
,
1356 const char *boot_device
,
1357 const char *kernel_filename
, const char *kernel_cmdline
,
1358 const char *initrd_filename
, const char *cpu_model
)
1360 sun4m_hw_init(&sun4m_hwdefs
[7], RAM_size
, boot_device
, kernel_filename
,
1361 kernel_cmdline
, initrd_filename
, cpu_model
);
1364 /* SPARCbook hardware initialisation */
1365 static void sbook_init(ram_addr_t RAM_size
,
1366 const char *boot_device
,
1367 const char *kernel_filename
, const char *kernel_cmdline
,
1368 const char *initrd_filename
, const char *cpu_model
)
1370 sun4m_hw_init(&sun4m_hwdefs
[8], RAM_size
, boot_device
, kernel_filename
,
1371 kernel_cmdline
, initrd_filename
, cpu_model
);
1374 static QEMUMachine ss5_machine
= {
1376 .desc
= "Sun4m platform, SPARCstation 5",
1382 static QEMUMachine ss10_machine
= {
1384 .desc
= "Sun4m platform, SPARCstation 10",
1390 static QEMUMachine ss600mp_machine
= {
1392 .desc
= "Sun4m platform, SPARCserver 600MP",
1393 .init
= ss600mp_init
,
1398 static QEMUMachine ss20_machine
= {
1400 .desc
= "Sun4m platform, SPARCstation 20",
1406 static QEMUMachine voyager_machine
= {
1408 .desc
= "Sun4m platform, SPARCstation Voyager",
1413 static QEMUMachine ss_lx_machine
= {
1415 .desc
= "Sun4m platform, SPARCstation LX",
1420 static QEMUMachine ss4_machine
= {
1422 .desc
= "Sun4m platform, SPARCstation 4",
1427 static QEMUMachine scls_machine
= {
1428 .name
= "SPARCClassic",
1429 .desc
= "Sun4m platform, SPARCClassic",
1434 static QEMUMachine sbook_machine
= {
1435 .name
= "SPARCbook",
1436 .desc
= "Sun4m platform, SPARCbook",
1441 static const struct sun4d_hwdef sun4d_hwdefs
[] = {
1451 .tcx_base
= 0x820000000ULL
,
1452 .slavio_base
= 0xf00000000ULL
,
1453 .ms_kb_base
= 0xf00240000ULL
,
1454 .serial_base
= 0xf00200000ULL
,
1455 .nvram_base
= 0xf00280000ULL
,
1456 .counter_base
= 0xf00300000ULL
,
1457 .espdma_base
= 0x800081000ULL
,
1458 .esp_base
= 0x800080000ULL
,
1459 .ledma_base
= 0x800040000ULL
,
1460 .le_base
= 0x800060000ULL
,
1461 .sbi_base
= 0xf02800000ULL
,
1462 .nvram_machine_id
= 0x80,
1463 .machine_id
= ss1000_id
,
1464 .iounit_version
= 0x03000000,
1465 .max_mem
= 0xf00000000ULL
,
1466 .default_cpu_model
= "TI SuperSparc II",
1477 .tcx_base
= 0x820000000ULL
,
1478 .slavio_base
= 0xf00000000ULL
,
1479 .ms_kb_base
= 0xf00240000ULL
,
1480 .serial_base
= 0xf00200000ULL
,
1481 .nvram_base
= 0xf00280000ULL
,
1482 .counter_base
= 0xf00300000ULL
,
1483 .espdma_base
= 0x800081000ULL
,
1484 .esp_base
= 0x800080000ULL
,
1485 .ledma_base
= 0x800040000ULL
,
1486 .le_base
= 0x800060000ULL
,
1487 .sbi_base
= 0xf02800000ULL
,
1488 .nvram_machine_id
= 0x80,
1489 .machine_id
= ss2000_id
,
1490 .iounit_version
= 0x03000000,
1491 .max_mem
= 0xf00000000ULL
,
1492 .default_cpu_model
= "TI SuperSparc II",
1496 static DeviceState
*sbi_init(target_phys_addr_t addr
, qemu_irq
**parent_irq
)
1502 dev
= qdev_create(NULL
, "sbi");
1503 qdev_init_nofail(dev
);
1505 s
= sysbus_from_qdev(dev
);
1507 for (i
= 0; i
< MAX_CPUS
; i
++) {
1508 sysbus_connect_irq(s
, i
, *parent_irq
[i
]);
1511 sysbus_mmio_map(s
, 0, addr
);
1516 static void sun4d_hw_init(const struct sun4d_hwdef
*hwdef
, ram_addr_t RAM_size
,
1517 const char *boot_device
,
1518 const char *kernel_filename
,
1519 const char *kernel_cmdline
,
1520 const char *initrd_filename
, const char *cpu_model
)
1523 void *iounits
[MAX_IOUNITS
], *espdma
, *ledma
, *nvram
;
1524 qemu_irq
*cpu_irqs
[MAX_CPUS
], sbi_irq
[32], sbi_cpu_irq
[MAX_CPUS
],
1525 espdma_irq
, ledma_irq
;
1526 qemu_irq esp_reset
, dma_enable
;
1527 unsigned long kernel_size
;
1533 cpu_model
= hwdef
->default_cpu_model
;
1535 for(i
= 0; i
< smp_cpus
; i
++) {
1536 cpu_devinit(cpu_model
, i
, hwdef
->slavio_base
, &cpu_irqs
[i
]);
1539 for (i
= smp_cpus
; i
< MAX_CPUS
; i
++)
1540 cpu_irqs
[i
] = qemu_allocate_irqs(dummy_cpu_set_irq
, NULL
, MAX_PILS
);
1542 /* set up devices */
1543 ram_init(0, RAM_size
, hwdef
->max_mem
);
1545 prom_init(hwdef
->slavio_base
, bios_name
);
1547 dev
= sbi_init(hwdef
->sbi_base
, cpu_irqs
);
1549 for (i
= 0; i
< 32; i
++) {
1550 sbi_irq
[i
] = qdev_get_gpio_in(dev
, i
);
1552 for (i
= 0; i
< MAX_CPUS
; i
++) {
1553 sbi_cpu_irq
[i
] = qdev_get_gpio_in(dev
, 32 + i
);
1556 for (i
= 0; i
< MAX_IOUNITS
; i
++)
1557 if (hwdef
->iounit_bases
[i
] != (target_phys_addr_t
)-1)
1558 iounits
[i
] = iommu_init(hwdef
->iounit_bases
[i
],
1559 hwdef
->iounit_version
,
1562 espdma
= sparc32_dma_init(hwdef
->espdma_base
, sbi_irq
[3],
1563 iounits
[0], &espdma_irq
, 0);
1565 /* should be lebuffer instead */
1566 ledma
= sparc32_dma_init(hwdef
->ledma_base
, sbi_irq
[4],
1567 iounits
[0], &ledma_irq
, 0);
1569 if (graphic_depth
!= 8 && graphic_depth
!= 24) {
1570 fprintf(stderr
, "qemu: Unsupported depth: %d\n", graphic_depth
);
1573 tcx_init(hwdef
->tcx_base
, 0x00100000, graphic_width
, graphic_height
,
1576 lance_init(&nd_table
[0], hwdef
->le_base
, ledma
, ledma_irq
);
1578 nvram
= m48t59_init(sbi_irq
[0], hwdef
->nvram_base
, 0, 0x2000, 8);
1580 slavio_timer_init_all(hwdef
->counter_base
, sbi_irq
[10], sbi_cpu_irq
, smp_cpus
);
1582 slavio_serial_ms_kbd_init(hwdef
->ms_kb_base
, sbi_irq
[12],
1583 display_type
== DT_NOGRAPHIC
, ESCC_CLOCK
, 1);
1584 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
1585 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
1586 escc_init(hwdef
->serial_base
, sbi_irq
[12], sbi_irq
[12],
1587 serial_hds
[0], serial_hds
[1], ESCC_CLOCK
, 1);
1589 if (drive_get_max_bus(IF_SCSI
) > 0) {
1590 fprintf(stderr
, "qemu: too many SCSI bus\n");
1594 esp_init(hwdef
->esp_base
, 2,
1595 espdma_memory_read
, espdma_memory_write
,
1596 espdma
, espdma_irq
, &esp_reset
, &dma_enable
);
1598 qdev_connect_gpio_out(espdma
, 0, esp_reset
);
1599 qdev_connect_gpio_out(espdma
, 1, dma_enable
);
1601 kernel_size
= sun4m_load_kernel(kernel_filename
, initrd_filename
,
1604 nvram_init(nvram
, (uint8_t *)&nd_table
[0].macaddr
, kernel_cmdline
,
1605 boot_device
, RAM_size
, kernel_size
, graphic_width
,
1606 graphic_height
, graphic_depth
, hwdef
->nvram_machine_id
,
1609 fw_cfg
= fw_cfg_init(0, 0, CFG_ADDR
, CFG_ADDR
+ 2);
1610 fw_cfg_add_i32(fw_cfg
, FW_CFG_ID
, 1);
1611 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
1612 fw_cfg_add_i16(fw_cfg
, FW_CFG_MACHINE_ID
, hwdef
->machine_id
);
1613 fw_cfg_add_i16(fw_cfg
, FW_CFG_SUN4M_DEPTH
, graphic_depth
);
1614 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, KERNEL_LOAD_ADDR
);
1615 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
1616 if (kernel_cmdline
) {
1617 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, CMDLINE_ADDR
);
1618 pstrcpy_targphys("cmdline", CMDLINE_ADDR
, TARGET_PAGE_SIZE
, kernel_cmdline
);
1619 fw_cfg_add_bytes(fw_cfg
, FW_CFG_CMDLINE_DATA
,
1620 (uint8_t*)strdup(kernel_cmdline
),
1621 strlen(kernel_cmdline
) + 1);
1623 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, 0);
1625 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, INITRD_LOAD_ADDR
);
1626 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, 0); // not used
1627 fw_cfg_add_i16(fw_cfg
, FW_CFG_BOOT_DEVICE
, boot_device
[0]);
1628 qemu_register_boot_set(fw_cfg_boot_set
, fw_cfg
);
1631 /* SPARCserver 1000 hardware initialisation */
1632 static void ss1000_init(ram_addr_t RAM_size
,
1633 const char *boot_device
,
1634 const char *kernel_filename
, const char *kernel_cmdline
,
1635 const char *initrd_filename
, const char *cpu_model
)
1637 sun4d_hw_init(&sun4d_hwdefs
[0], RAM_size
, boot_device
, kernel_filename
,
1638 kernel_cmdline
, initrd_filename
, cpu_model
);
1641 /* SPARCcenter 2000 hardware initialisation */
1642 static void ss2000_init(ram_addr_t RAM_size
,
1643 const char *boot_device
,
1644 const char *kernel_filename
, const char *kernel_cmdline
,
1645 const char *initrd_filename
, const char *cpu_model
)
1647 sun4d_hw_init(&sun4d_hwdefs
[1], RAM_size
, boot_device
, kernel_filename
,
1648 kernel_cmdline
, initrd_filename
, cpu_model
);
1651 static QEMUMachine ss1000_machine
= {
1653 .desc
= "Sun4d platform, SPARCserver 1000",
1654 .init
= ss1000_init
,
1659 static QEMUMachine ss2000_machine
= {
1661 .desc
= "Sun4d platform, SPARCcenter 2000",
1662 .init
= ss2000_init
,
1667 static const struct sun4c_hwdef sun4c_hwdefs
[] = {
1670 .iommu_base
= 0xf8000000,
1671 .tcx_base
= 0xfe000000,
1672 .slavio_base
= 0xf6000000,
1673 .intctl_base
= 0xf5000000,
1674 .counter_base
= 0xf3000000,
1675 .ms_kb_base
= 0xf0000000,
1676 .serial_base
= 0xf1000000,
1677 .nvram_base
= 0xf2000000,
1678 .fd_base
= 0xf7200000,
1679 .dma_base
= 0xf8400000,
1680 .esp_base
= 0xf8800000,
1681 .le_base
= 0xf8c00000,
1682 .aux1_base
= 0xf7400003,
1683 .nvram_machine_id
= 0x55,
1684 .machine_id
= ss2_id
,
1685 .max_mem
= 0x10000000,
1686 .default_cpu_model
= "Cypress CY7C601",
1690 static DeviceState
*sun4c_intctl_init(target_phys_addr_t addr
,
1691 qemu_irq
*parent_irq
)
1697 dev
= qdev_create(NULL
, "sun4c_intctl");
1698 qdev_init_nofail(dev
);
1700 s
= sysbus_from_qdev(dev
);
1702 for (i
= 0; i
< MAX_PILS
; i
++) {
1703 sysbus_connect_irq(s
, i
, parent_irq
[i
]);
1705 sysbus_mmio_map(s
, 0, addr
);
1710 static void sun4c_hw_init(const struct sun4c_hwdef
*hwdef
, ram_addr_t RAM_size
,
1711 const char *boot_device
,
1712 const char *kernel_filename
,
1713 const char *kernel_cmdline
,
1714 const char *initrd_filename
, const char *cpu_model
)
1716 void *iommu
, *espdma
, *ledma
, *nvram
;
1717 qemu_irq
*cpu_irqs
, slavio_irq
[8], espdma_irq
, ledma_irq
;
1718 qemu_irq esp_reset
, dma_enable
;
1720 unsigned long kernel_size
;
1721 DriveInfo
*fd
[MAX_FD
];
1728 cpu_model
= hwdef
->default_cpu_model
;
1730 cpu_devinit(cpu_model
, 0, hwdef
->slavio_base
, &cpu_irqs
);
1732 /* set up devices */
1733 ram_init(0, RAM_size
, hwdef
->max_mem
);
1735 prom_init(hwdef
->slavio_base
, bios_name
);
1737 dev
= sun4c_intctl_init(hwdef
->intctl_base
, cpu_irqs
);
1739 for (i
= 0; i
< 8; i
++) {
1740 slavio_irq
[i
] = qdev_get_gpio_in(dev
, i
);
1743 iommu
= iommu_init(hwdef
->iommu_base
, hwdef
->iommu_version
,
1746 espdma
= sparc32_dma_init(hwdef
->dma_base
, slavio_irq
[2],
1747 iommu
, &espdma_irq
, 0);
1749 ledma
= sparc32_dma_init(hwdef
->dma_base
+ 16ULL,
1750 slavio_irq
[3], iommu
, &ledma_irq
, 1);
1752 if (graphic_depth
!= 8 && graphic_depth
!= 24) {
1753 fprintf(stderr
, "qemu: Unsupported depth: %d\n", graphic_depth
);
1756 tcx_init(hwdef
->tcx_base
, 0x00100000, graphic_width
, graphic_height
,
1759 lance_init(&nd_table
[0], hwdef
->le_base
, ledma
, ledma_irq
);
1761 nvram
= m48t59_init(slavio_irq
[0], hwdef
->nvram_base
, 0, 0x800, 2);
1763 slavio_serial_ms_kbd_init(hwdef
->ms_kb_base
, slavio_irq
[1],
1764 display_type
== DT_NOGRAPHIC
, ESCC_CLOCK
, 1);
1765 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
1766 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
1767 escc_init(hwdef
->serial_base
, slavio_irq
[1],
1768 slavio_irq
[1], serial_hds
[0], serial_hds
[1],
1771 slavio_misc_init(0, hwdef
->aux1_base
, 0, slavio_irq
[1], fdc_tc
);
1773 if (hwdef
->fd_base
!= (target_phys_addr_t
)-1) {
1774 /* there is zero or one floppy drive */
1775 memset(fd
, 0, sizeof(fd
));
1776 fd
[0] = drive_get(IF_FLOPPY
, 0, 0);
1777 sun4m_fdctrl_init(slavio_irq
[1], hwdef
->fd_base
, fd
,
1781 if (drive_get_max_bus(IF_SCSI
) > 0) {
1782 fprintf(stderr
, "qemu: too many SCSI bus\n");
1786 esp_init(hwdef
->esp_base
, 2,
1787 espdma_memory_read
, espdma_memory_write
,
1788 espdma
, espdma_irq
, &esp_reset
, &dma_enable
);
1790 qdev_connect_gpio_out(espdma
, 0, esp_reset
);
1791 qdev_connect_gpio_out(espdma
, 1, dma_enable
);
1793 kernel_size
= sun4m_load_kernel(kernel_filename
, initrd_filename
,
1796 nvram_init(nvram
, (uint8_t *)&nd_table
[0].macaddr
, kernel_cmdline
,
1797 boot_device
, RAM_size
, kernel_size
, graphic_width
,
1798 graphic_height
, graphic_depth
, hwdef
->nvram_machine_id
,
1801 fw_cfg
= fw_cfg_init(0, 0, CFG_ADDR
, CFG_ADDR
+ 2);
1802 fw_cfg_add_i32(fw_cfg
, FW_CFG_ID
, 1);
1803 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
1804 fw_cfg_add_i16(fw_cfg
, FW_CFG_MACHINE_ID
, hwdef
->machine_id
);
1805 fw_cfg_add_i16(fw_cfg
, FW_CFG_SUN4M_DEPTH
, graphic_depth
);
1806 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, KERNEL_LOAD_ADDR
);
1807 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
1808 if (kernel_cmdline
) {
1809 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, CMDLINE_ADDR
);
1810 pstrcpy_targphys("cmdline", CMDLINE_ADDR
, TARGET_PAGE_SIZE
, kernel_cmdline
);
1811 fw_cfg_add_bytes(fw_cfg
, FW_CFG_CMDLINE_DATA
,
1812 (uint8_t*)strdup(kernel_cmdline
),
1813 strlen(kernel_cmdline
) + 1);
1815 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, 0);
1817 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, INITRD_LOAD_ADDR
);
1818 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, 0); // not used
1819 fw_cfg_add_i16(fw_cfg
, FW_CFG_BOOT_DEVICE
, boot_device
[0]);
1820 qemu_register_boot_set(fw_cfg_boot_set
, fw_cfg
);
1823 /* SPARCstation 2 hardware initialisation */
1824 static void ss2_init(ram_addr_t RAM_size
,
1825 const char *boot_device
,
1826 const char *kernel_filename
, const char *kernel_cmdline
,
1827 const char *initrd_filename
, const char *cpu_model
)
1829 sun4c_hw_init(&sun4c_hwdefs
[0], RAM_size
, boot_device
, kernel_filename
,
1830 kernel_cmdline
, initrd_filename
, cpu_model
);
1833 static QEMUMachine ss2_machine
= {
1835 .desc
= "Sun4c platform, SPARCstation 2",
1840 static void sun4m_register_types(void)
1842 type_register_static(&idreg_info
);
1843 type_register_static(&afx_info
);
1844 type_register_static(&prom_info
);
1845 type_register_static(&ram_info
);
1848 static void ss2_machine_init(void)
1850 qemu_register_machine(&ss5_machine
);
1851 qemu_register_machine(&ss10_machine
);
1852 qemu_register_machine(&ss600mp_machine
);
1853 qemu_register_machine(&ss20_machine
);
1854 qemu_register_machine(&voyager_machine
);
1855 qemu_register_machine(&ss_lx_machine
);
1856 qemu_register_machine(&ss4_machine
);
1857 qemu_register_machine(&scls_machine
);
1858 qemu_register_machine(&sbook_machine
);
1859 qemu_register_machine(&ss1000_machine
);
1860 qemu_register_machine(&ss2000_machine
);
1861 qemu_register_machine(&ss2_machine
);
1864 type_init(sun4m_register_types
)
1865 machine_init(ss2_machine_init
);