4 * Copyright (C) 2015-2016 Broadcom Corporation
5 * Copyright (c) 2017 Red Hat, Inc.
6 * Written by Prem Mallappa, Eric Auger
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #ifndef HW_ARM_SMMU_COMMON_H
20 #define HW_ARM_SMMU_COMMON_H
22 #include "hw/sysbus.h"
23 #include "hw/pci/pci.h"
25 #define SMMU_PCI_BUS_MAX 256
26 #define SMMU_PCI_DEVFN_MAX 256
27 #define SMMU_PCI_DEVFN(sid) (sid & 0xFF)
29 #define SMMU_MAX_VA_BITS 48
32 * Page table walk error types
36 SMMU_PTW_ERR_WALK_EABT
, /* Translation walk external abort */
37 SMMU_PTW_ERR_TRANSLATION
, /* Translation fault */
38 SMMU_PTW_ERR_ADDR_SIZE
, /* Address Size fault */
39 SMMU_PTW_ERR_ACCESS
, /* Access fault */
40 SMMU_PTW_ERR_PERMISSION
, /* Permission fault */
43 typedef struct SMMUPTWEventInfo
{
44 SMMUPTWEventType type
;
45 dma_addr_t addr
; /* fetched address that induced an abort, if any */
48 typedef struct SMMUTransTableInfo
{
49 bool disabled
; /* is the translation table disabled? */
50 uint64_t ttb
; /* TT base address */
51 uint8_t tsz
; /* input range, ie. 2^(64 -tsz)*/
52 uint8_t granule_sz
; /* granule page shift */
55 typedef struct SMMUTLBEntry
{
62 * Generic structure populated by derived SMMU devices
63 * after decoding the configuration information and used as
64 * input to the page table walk
66 typedef struct SMMUTransCfg
{
67 int stage
; /* translation stage */
68 bool aa64
; /* arch64 or aarch32 translation table */
69 bool disabled
; /* smmu is disabled */
70 bool bypassed
; /* translation is bypassed */
71 bool aborted
; /* translation is aborted */
72 uint64_t ttb
; /* TT base address */
73 uint8_t oas
; /* output address width */
74 uint8_t tbi
; /* Top Byte Ignore */
76 SMMUTransTableInfo tt
[2];
77 uint32_t iotlb_hits
; /* counts IOTLB hits for this asid */
78 uint32_t iotlb_misses
; /* counts IOTLB misses for this asid */
81 typedef struct SMMUDevice
{
85 IOMMUMemoryRegion iommu
;
87 uint32_t cfg_cache_hits
;
88 uint32_t cfg_cache_misses
;
89 QLIST_ENTRY(SMMUDevice
) next
;
92 typedef struct SMMUPciBus
{
94 SMMUDevice
*pbdev
[]; /* Parent array is sparse, so dynamically alloc */
97 typedef struct SMMUIOTLBKey
{
102 typedef struct SMMUState
{
105 const char *mrtypename
;
108 GHashTable
*smmu_pcibus_by_busptr
;
109 GHashTable
*configs
; /* cache for configuration data */
111 SMMUPciBus
*smmu_pcibus_by_bus_num
[SMMU_PCI_BUS_MAX
];
113 QLIST_HEAD(, SMMUDevice
) devices_with_notifiers
;
120 SysBusDeviceClass parent_class
;
124 DeviceRealize parent_realize
;
128 #define TYPE_ARM_SMMU "arm-smmu"
129 #define ARM_SMMU(obj) OBJECT_CHECK(SMMUState, (obj), TYPE_ARM_SMMU)
130 #define ARM_SMMU_CLASS(klass) \
131 OBJECT_CLASS_CHECK(SMMUBaseClass, (klass), TYPE_ARM_SMMU)
132 #define ARM_SMMU_GET_CLASS(obj) \
133 OBJECT_GET_CLASS(SMMUBaseClass, (obj), TYPE_ARM_SMMU)
135 /* Return the SMMUPciBus handle associated to a PCI bus number */
136 SMMUPciBus
*smmu_find_smmu_pcibus(SMMUState
*s
, uint8_t bus_num
);
138 /* Return the stream ID of an SMMU device */
139 static inline uint16_t smmu_get_sid(SMMUDevice
*sdev
)
141 return PCI_BUILD_BDF(pci_bus_num(sdev
->bus
), sdev
->devfn
);
145 * smmu_ptw - Perform the page table walk for a given iova / access flags
146 * pair, according to @cfg translation config
148 int smmu_ptw(SMMUTransCfg
*cfg
, dma_addr_t iova
, IOMMUAccessFlags perm
,
149 SMMUTLBEntry
*tlbe
, SMMUPTWEventInfo
*info
);
152 * select_tt - compute which translation table shall be used according to
153 * the input iova and translation config and return the TT specific info
155 SMMUTransTableInfo
*select_tt(SMMUTransCfg
*cfg
, dma_addr_t iova
);
157 /* Return the iommu mr associated to @sid, or NULL if none */
158 IOMMUMemoryRegion
*smmu_iommu_mr(SMMUState
*s
, uint32_t sid
);
160 #define SMMU_IOTLB_MAX_SIZE 256
162 SMMUTLBEntry
*smmu_iotlb_lookup(SMMUState
*bs
, SMMUTransCfg
*cfg
, hwaddr iova
);
163 void smmu_iotlb_insert(SMMUState
*bs
, SMMUTransCfg
*cfg
, SMMUTLBEntry
*entry
);
164 SMMUIOTLBKey
smmu_get_iotlb_key(uint16_t asid
, uint64_t iova
);
165 void smmu_iotlb_inv_all(SMMUState
*s
);
166 void smmu_iotlb_inv_asid(SMMUState
*s
, uint16_t asid
);
167 void smmu_iotlb_inv_iova(SMMUState
*s
, uint16_t asid
, dma_addr_t iova
);
169 /* Unmap the range of all the notifiers registered to any IOMMU mr */
170 void smmu_inv_notifiers_all(SMMUState
*s
);
172 /* Unmap the range of all the notifiers registered to @mr */
173 void smmu_inv_notifiers_mr(IOMMUMemoryRegion
*mr
);
175 #endif /* HW_ARM_SMMU_COMMON_H */