hw/ppc/ppc440_bamboo.c

   1 /*
   2  * QEMU PowerPC 440 Bamboo board emulation
   3  *
   4  * Copyright 2007 IBM Corporation.
   5  * Authors:
   6  *  Jerone Young <jyoung5@us.ibm.com>
   7  *  Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
   8  *  Hollis Blanchard <hollisb@us.ibm.com>
   9  *
  10  * This work is licensed under the GNU GPL license version 2 or later.
  11  *
  12  */
  13
  14 #include "qemu/osdep.h"
  15 #include "qemu/units.h"
  16 #include "qemu/error-report.h"
  17 #include "qemu/datadir.h"
  18 #include "qemu/error-report.h"
  19 #include "net/net.h"
  20 #include "hw/pci/pci.h"
  21 #include "hw/boards.h"
  22 #include "sysemu/kvm.h"
  23 #include "kvm_ppc.h"
  24 #include "sysemu/device_tree.h"
  25 #include "hw/loader.h"
  26 #include "elf.h"
  27 #include "hw/char/serial.h"
  28 #include "hw/ppc/ppc.h"
  29 #include "ppc405.h"
  30 #include "sysemu/sysemu.h"
  31 #include "sysemu/reset.h"
  32 #include "hw/sysbus.h"
  33 #include "hw/intc/ppc-uic.h"
  34 #include "hw/qdev-properties.h"
  35 #include "qapi/error.h"
  36
  37 #define BINARY_DEVICE_TREE_FILE "bamboo.dtb"
  38
  39 /* from u-boot */
  40 #define KERNEL_ADDR  0x1000000
  41 #define FDT_ADDR     0x1800000
  42 #define RAMDISK_ADDR 0x1900000
  43
  44 #define PPC440EP_PCI_CONFIG     0xeec00000
  45 #define PPC440EP_PCI_INTACK     0xeed00000
  46 #define PPC440EP_PCI_SPECIAL    0xeed00000
  47 #define PPC440EP_PCI_REGS       0xef400000
  48 #define PPC440EP_PCI_IO         0xe8000000
  49 #define PPC440EP_PCI_IOLEN      0x00010000
  50
  51 #define PPC440EP_SDRAM_NR_BANKS 4
  52
  53 static const ram_addr_t ppc440ep_sdram_bank_sizes[] = {
  54     256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 0
  55 };
  56
  57 static hwaddr entry;
  58
  59 static int bamboo_load_device_tree(hwaddr addr,
  60                                      uint32_t ramsize,
  61                                      hwaddr initrd_base,
  62                                      hwaddr initrd_size,
  63                                      const char *kernel_cmdline)
  64 {
  65     int ret = -1;
  66     uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(ramsize) };
  67     char *filename;
  68     int fdt_size;
  69     void *fdt;
  70     uint32_t tb_freq = 400000000;
  71     uint32_t clock_freq = 400000000;
  72
  73     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
  74     if (!filename) {
  75         return -1;
  76     }
  77     fdt = load_device_tree(filename, &fdt_size);
  78     g_free(filename);
  79     if (fdt == NULL) {
  80         return -1;
  81     }
  82
  83     /* Manipulate device tree in memory. */
  84
  85     ret = qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property,
  86                            sizeof(mem_reg_property));
  87     if (ret < 0)
  88         fprintf(stderr, "couldn't set /memory/reg\n");
  89
  90     ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
  91                                 initrd_base);
  92     if (ret < 0)
  93         fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
  94
  95     ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
  96                                 (initrd_base + initrd_size));
  97     if (ret < 0)
  98         fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
  99
 100     ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
 101                                   kernel_cmdline);
 102     if (ret < 0)
 103         fprintf(stderr, "couldn't set /chosen/bootargs\n");
 104
 105     /* Copy data from the host device tree into the guest. Since the guest can
 106      * directly access the timebase without host involvement, we must expose
 107      * the correct frequencies. */
 108     if (kvm_enabled()) {
 109         tb_freq = kvmppc_get_tbfreq();
 110         clock_freq = kvmppc_get_clockfreq();
 111     }
 112
 113     qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "clock-frequency",
 114                           clock_freq);
 115     qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "timebase-frequency",
 116                           tb_freq);
 117
 118     rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
 119     g_free(fdt);
 120     return 0;
 121 }
 122
 123 /* Create reset TLB entries for BookE, spanning the 32bit addr space.  */
 124 static void mmubooke_create_initial_mapping(CPUPPCState *env,
 125                                      target_ulong va,
 126                                      hwaddr pa)
 127 {
 128     ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
 129
 130     tlb->attr = 0;
 131     tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
 132     tlb->size = 1U << 31; /* up to 0x80000000  */
 133     tlb->EPN = va & TARGET_PAGE_MASK;
 134     tlb->RPN = pa & TARGET_PAGE_MASK;
 135     tlb->PID = 0;
 136
 137     tlb = &env->tlb.tlbe[1];
 138     tlb->attr = 0;
 139     tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
 140     tlb->size = 1U << 31; /* up to 0xffffffff  */
 141     tlb->EPN = 0x80000000 & TARGET_PAGE_MASK;
 142     tlb->RPN = 0x80000000 & TARGET_PAGE_MASK;
 143     tlb->PID = 0;
 144 }
 145
 146 static void main_cpu_reset(void *opaque)
 147 {
 148     PowerPCCPU *cpu = opaque;
 149     CPUPPCState *env = &cpu->env;
 150
 151     cpu_reset(CPU(cpu));
 152     env->gpr[1] = (16 * MiB) - 8;
 153     env->gpr[3] = FDT_ADDR;
 154     env->nip = entry;
 155
 156     /* Create a mapping for the kernel.  */
 157     mmubooke_create_initial_mapping(env, 0, 0);
 158 }
 159
 160 static void bamboo_init(MachineState *machine)
 161 {
 162     const char *kernel_filename = machine->kernel_filename;
 163     const char *kernel_cmdline = machine->kernel_cmdline;
 164     const char *initrd_filename = machine->initrd_filename;
 165     unsigned int pci_irq_nrs[4] = { 28, 27, 26, 25 };
 166     MemoryRegion *address_space_mem = get_system_memory();
 167     MemoryRegion *isa = g_new(MemoryRegion, 1);
 168     MemoryRegion *ram_memories = g_new(MemoryRegion, PPC440EP_SDRAM_NR_BANKS);
 169     hwaddr ram_bases[PPC440EP_SDRAM_NR_BANKS];
 170     hwaddr ram_sizes[PPC440EP_SDRAM_NR_BANKS];
 171     PCIBus *pcibus;
 172     PowerPCCPU *cpu;
 173     CPUPPCState *env;
 174     target_long initrd_size = 0;
 175     DeviceState *dev;
 176     DeviceState *uicdev;
 177     SysBusDevice *uicsbd;
 178     int success;
 179     int i;
 180
 181     cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
 182     env = &cpu->env;
 183
 184     if (env->mmu_model != POWERPC_MMU_BOOKE) {
 185         error_report("MMU model %i not supported by this machine",
 186                      env->mmu_model);
 187         exit(1);
 188     }
 189
 190     qemu_register_reset(main_cpu_reset, cpu);
 191     ppc_booke_timers_init(cpu, 400000000, 0);
 192     ppc_dcr_init(env, NULL, NULL);
 193
 194     /* interrupt controller */
 195     uicdev = qdev_new(TYPE_PPC_UIC);
 196     ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(uicdev), cpu, &error_fatal);
 197     object_unref(OBJECT(uicdev));
 198     uicsbd = SYS_BUS_DEVICE(uicdev);
 199     sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT,
 200                        qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT));
 201     sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT,
 202                        qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_CINT));
 203
 204     /* SDRAM controller */
 205     memset(ram_bases, 0, sizeof(ram_bases));
 206     memset(ram_sizes, 0, sizeof(ram_sizes));
 207     ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_memories,
 208                        ram_bases, ram_sizes, ppc440ep_sdram_bank_sizes);
 209     /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
 210     ppc4xx_sdram_init(env,
 211                       qdev_get_gpio_in(uicdev, 14),
 212                       PPC440EP_SDRAM_NR_BANKS, ram_memories,
 213                       ram_bases, ram_sizes, 1);
 214
 215     /* PCI */
 216     dev = sysbus_create_varargs(TYPE_PPC4xx_PCI_HOST_BRIDGE,
 217                                 PPC440EP_PCI_CONFIG,
 218                                 qdev_get_gpio_in(uicdev, pci_irq_nrs[0]),
 219                                 qdev_get_gpio_in(uicdev, pci_irq_nrs[1]),
 220                                 qdev_get_gpio_in(uicdev, pci_irq_nrs[2]),
 221                                 qdev_get_gpio_in(uicdev, pci_irq_nrs[3]),
 222                                 NULL);
 223     pcibus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
 224     if (!pcibus) {
 225         error_report("couldn't create PCI controller");
 226         exit(1);
 227     }
 228
 229     memory_region_init_alias(isa, NULL, "isa_mmio",
 230                              get_system_io(), 0, PPC440EP_PCI_IOLEN);
 231     memory_region_add_subregion(get_system_memory(), PPC440EP_PCI_IO, isa);
 232
 233     if (serial_hd(0) != NULL) {
 234         serial_mm_init(address_space_mem, 0xef600300, 0,
 235                        qdev_get_gpio_in(uicdev, 0),
 236                        PPC_SERIAL_MM_BAUDBASE, serial_hd(0),
 237                        DEVICE_BIG_ENDIAN);
 238     }
 239     if (serial_hd(1) != NULL) {
 240         serial_mm_init(address_space_mem, 0xef600400, 0,
 241                        qdev_get_gpio_in(uicdev, 1),
 242                        PPC_SERIAL_MM_BAUDBASE, serial_hd(1),
 243                        DEVICE_BIG_ENDIAN);
 244     }
 245
 246     if (pcibus) {
 247         /* Register network interfaces. */
 248         for (i = 0; i < nb_nics; i++) {
 249             /* There are no PCI NICs on the Bamboo board, but there are
 250              * PCI slots, so we can pick whatever default model we want. */
 251             pci_nic_init_nofail(&nd_table[i], pcibus, "e1000", NULL);
 252         }
 253     }
 254
 255     /* Load kernel. */
 256     if (kernel_filename) {
 257         hwaddr loadaddr = LOAD_UIMAGE_LOADADDR_INVALID;
 258         success = load_uimage(kernel_filename, &entry, &loadaddr, NULL,
 259                               NULL, NULL);
 260         if (success < 0) {
 261             uint64_t elf_entry;
 262             success = load_elf(kernel_filename, NULL, NULL, NULL, &elf_entry,
 263                                NULL, NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0);
 264             entry = elf_entry;
 265         }
 266         /* XXX try again as binary */
 267         if (success < 0) {
 268             error_report("could not load kernel '%s'", kernel_filename);
 269             exit(1);
 270         }
 271     }
 272
 273     /* Load initrd. */
 274     if (initrd_filename) {
 275         initrd_size = load_image_targphys(initrd_filename, RAMDISK_ADDR,
 276                                           machine->ram_size - RAMDISK_ADDR);
 277
 278         if (initrd_size < 0) {
 279             error_report("could not load ram disk '%s' at %x",
 280                          initrd_filename, RAMDISK_ADDR);
 281             exit(1);
 282         }
 283     }
 284
 285     /* If we're loading a kernel directly, we must load the device tree too. */
 286     if (kernel_filename) {
 287         if (bamboo_load_device_tree(FDT_ADDR, machine->ram_size, RAMDISK_ADDR,
 288                                     initrd_size, kernel_cmdline) < 0) {
 289             error_report("couldn't load device tree");
 290             exit(1);
 291         }
 292     }
 293 }
 294
 295 static void bamboo_machine_init(MachineClass *mc)
 296 {
 297     mc->desc = "bamboo";
 298     mc->init = bamboo_init;
 299     mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("440epb");
 300     mc->default_ram_id = "ppc4xx.sdram";
 301 }
 302
 303 DEFINE_MACHINE("bamboo", bamboo_machine_init)