4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
25 #include "translate.h"
26 #include "internals.h"
27 #include "qemu/host-utils.h"
29 #include "exec/semihost.h"
30 #include "exec/gen-icount.h"
32 #include "exec/helper-proto.h"
33 #include "exec/helper-gen.h"
36 #include "trace-tcg.h"
38 static TCGv_i64 cpu_X
[32];
39 static TCGv_i64 cpu_pc
;
41 /* Load/store exclusive handling */
42 static TCGv_i64 cpu_exclusive_high
;
44 static const char *regnames
[] = {
45 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
46 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
47 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
48 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
52 A64_SHIFT_TYPE_LSL
= 0,
53 A64_SHIFT_TYPE_LSR
= 1,
54 A64_SHIFT_TYPE_ASR
= 2,
55 A64_SHIFT_TYPE_ROR
= 3
58 /* Table based decoder typedefs - used when the relevant bits for decode
59 * are too awkwardly scattered across the instruction (eg SIMD).
61 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
63 typedef struct AArch64DecodeTable
{
66 AArch64DecodeFn
*disas_fn
;
69 /* Function prototype for gen_ functions for calling Neon helpers */
70 typedef void NeonGenOneOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
);
71 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
72 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
73 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
74 typedef void NeonGenTwo64OpEnvFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
);
75 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
76 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
77 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
78 typedef void NeonGenTwoSingleOPFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
79 typedef void NeonGenTwoDoubleOPFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
80 typedef void NeonGenOneOpFn(TCGv_i64
, TCGv_i64
);
81 typedef void CryptoTwoOpEnvFn(TCGv_ptr
, TCGv_i32
, TCGv_i32
);
82 typedef void CryptoThreeOpEnvFn(TCGv_ptr
, TCGv_i32
, TCGv_i32
, TCGv_i32
);
84 /* initialize TCG globals. */
85 void a64_translate_init(void)
89 cpu_pc
= tcg_global_mem_new_i64(TCG_AREG0
,
90 offsetof(CPUARMState
, pc
),
92 for (i
= 0; i
< 32; i
++) {
93 cpu_X
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
94 offsetof(CPUARMState
, xregs
[i
]),
98 cpu_exclusive_high
= tcg_global_mem_new_i64(TCG_AREG0
,
99 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
102 static inline ARMMMUIdx
get_a64_user_mem_index(DisasContext
*s
)
104 /* Return the mmu_idx to use for A64 "unprivileged load/store" insns:
105 * if EL1, access as if EL0; otherwise access at current EL
107 switch (s
->mmu_idx
) {
108 case ARMMMUIdx_S12NSE1
:
109 return ARMMMUIdx_S12NSE0
;
110 case ARMMMUIdx_S1SE1
:
111 return ARMMMUIdx_S1SE0
;
113 g_assert_not_reached();
119 void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
,
120 fprintf_function cpu_fprintf
, int flags
)
122 ARMCPU
*cpu
= ARM_CPU(cs
);
123 CPUARMState
*env
= &cpu
->env
;
124 uint32_t psr
= pstate_read(env
);
126 int el
= arm_current_el(env
);
127 const char *ns_status
;
129 cpu_fprintf(f
, "PC=%016"PRIx64
" SP=%016"PRIx64
"\n",
130 env
->pc
, env
->xregs
[31]);
131 for (i
= 0; i
< 31; i
++) {
132 cpu_fprintf(f
, "X%02d=%016"PRIx64
, i
, env
->xregs
[i
]);
134 cpu_fprintf(f
, "\n");
140 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
141 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
146 cpu_fprintf(f
, "\nPSTATE=%08x %c%c%c%c %sEL%d%c\n",
148 psr
& PSTATE_N
? 'N' : '-',
149 psr
& PSTATE_Z
? 'Z' : '-',
150 psr
& PSTATE_C
? 'C' : '-',
151 psr
& PSTATE_V
? 'V' : '-',
154 psr
& PSTATE_SP
? 'h' : 't');
156 if (flags
& CPU_DUMP_FPU
) {
158 for (i
= 0; i
< numvfpregs
; i
+= 2) {
159 uint64_t vlo
= float64_val(env
->vfp
.regs
[i
* 2]);
160 uint64_t vhi
= float64_val(env
->vfp
.regs
[(i
* 2) + 1]);
161 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
" ",
163 vlo
= float64_val(env
->vfp
.regs
[(i
+ 1) * 2]);
164 vhi
= float64_val(env
->vfp
.regs
[((i
+ 1) * 2) + 1]);
165 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
"\n",
168 cpu_fprintf(f
, "FPCR: %08x FPSR: %08x\n",
169 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
173 void gen_a64_set_pc_im(uint64_t val
)
175 tcg_gen_movi_i64(cpu_pc
, val
);
178 typedef struct DisasCompare64
{
183 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
187 arm_test_cc(&c32
, cc
);
189 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
190 * properly. The NE/EQ comparisons are also fine with this choice. */
191 c64
->cond
= c32
.cond
;
192 c64
->value
= tcg_temp_new_i64();
193 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
198 static void a64_free_cc(DisasCompare64
*c64
)
200 tcg_temp_free_i64(c64
->value
);
203 static void gen_exception_internal(int excp
)
205 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
207 assert(excp_is_internal(excp
));
208 gen_helper_exception_internal(cpu_env
, tcg_excp
);
209 tcg_temp_free_i32(tcg_excp
);
212 static void gen_exception(int excp
, uint32_t syndrome
, uint32_t target_el
)
214 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
215 TCGv_i32 tcg_syn
= tcg_const_i32(syndrome
);
216 TCGv_i32 tcg_el
= tcg_const_i32(target_el
);
218 gen_helper_exception_with_syndrome(cpu_env
, tcg_excp
,
220 tcg_temp_free_i32(tcg_el
);
221 tcg_temp_free_i32(tcg_syn
);
222 tcg_temp_free_i32(tcg_excp
);
225 static void gen_exception_internal_insn(DisasContext
*s
, int offset
, int excp
)
227 gen_a64_set_pc_im(s
->pc
- offset
);
228 gen_exception_internal(excp
);
229 s
->is_jmp
= DISAS_EXC
;
232 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
,
233 uint32_t syndrome
, uint32_t target_el
)
235 gen_a64_set_pc_im(s
->pc
- offset
);
236 gen_exception(excp
, syndrome
, target_el
);
237 s
->is_jmp
= DISAS_EXC
;
240 static void gen_ss_advance(DisasContext
*s
)
242 /* If the singlestep state is Active-not-pending, advance to
247 gen_helper_clear_pstate_ss(cpu_env
);
251 static void gen_step_complete_exception(DisasContext
*s
)
253 /* We just completed step of an insn. Move from Active-not-pending
254 * to Active-pending, and then also take the swstep exception.
255 * This corresponds to making the (IMPDEF) choice to prioritize
256 * swstep exceptions over asynchronous exceptions taken to an exception
257 * level where debug is disabled. This choice has the advantage that
258 * we do not need to maintain internal state corresponding to the
259 * ISV/EX syndrome bits between completion of the step and generation
260 * of the exception, and our syndrome information is always correct.
263 gen_exception(EXCP_UDEF
, syn_swstep(s
->ss_same_el
, 1, s
->is_ldex
),
264 default_exception_el(s
));
265 s
->is_jmp
= DISAS_EXC
;
268 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
270 /* No direct tb linking with singlestep (either QEMU's or the ARM
271 * debug architecture kind) or deterministic io
273 if (s
->singlestep_enabled
|| s
->ss_active
|| (s
->tb
->cflags
& CF_LAST_IO
)) {
277 /* Only link tbs from inside the same guest page */
278 if ((s
->tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
285 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
287 TranslationBlock
*tb
;
290 if (use_goto_tb(s
, n
, dest
)) {
292 gen_a64_set_pc_im(dest
);
293 tcg_gen_exit_tb((intptr_t)tb
+ n
);
294 s
->is_jmp
= DISAS_TB_JUMP
;
296 gen_a64_set_pc_im(dest
);
298 gen_step_complete_exception(s
);
299 } else if (s
->singlestep_enabled
) {
300 gen_exception_internal(EXCP_DEBUG
);
303 s
->is_jmp
= DISAS_TB_JUMP
;
308 static void unallocated_encoding(DisasContext
*s
)
310 /* Unallocated and reserved encodings are uncategorized */
311 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized(),
312 default_exception_el(s
));
315 #define unsupported_encoding(s, insn) \
317 qemu_log_mask(LOG_UNIMP, \
318 "%s:%d: unsupported instruction encoding 0x%08x " \
319 "at pc=%016" PRIx64 "\n", \
320 __FILE__, __LINE__, insn, s->pc - 4); \
321 unallocated_encoding(s); \
324 static void init_tmp_a64_array(DisasContext
*s
)
326 #ifdef CONFIG_DEBUG_TCG
328 for (i
= 0; i
< ARRAY_SIZE(s
->tmp_a64
); i
++) {
329 TCGV_UNUSED_I64(s
->tmp_a64
[i
]);
332 s
->tmp_a64_count
= 0;
335 static void free_tmp_a64(DisasContext
*s
)
338 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
339 tcg_temp_free_i64(s
->tmp_a64
[i
]);
341 init_tmp_a64_array(s
);
344 static TCGv_i64
new_tmp_a64(DisasContext
*s
)
346 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
347 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
350 static TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
352 TCGv_i64 t
= new_tmp_a64(s
);
353 tcg_gen_movi_i64(t
, 0);
358 * Register access functions
360 * These functions are used for directly accessing a register in where
361 * changes to the final register value are likely to be made. If you
362 * need to use a register for temporary calculation (e.g. index type
363 * operations) use the read_* form.
365 * B1.2.1 Register mappings
367 * In instruction register encoding 31 can refer to ZR (zero register) or
368 * the SP (stack pointer) depending on context. In QEMU's case we map SP
369 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
370 * This is the point of the _sp forms.
372 static TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
375 return new_tmp_a64_zero(s
);
381 /* register access for when 31 == SP */
382 static TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
387 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
388 * representing the register contents. This TCGv is an auto-freed
389 * temporary so it need not be explicitly freed, and may be modified.
391 static TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
393 TCGv_i64 v
= new_tmp_a64(s
);
396 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
398 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
401 tcg_gen_movi_i64(v
, 0);
406 static TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
408 TCGv_i64 v
= new_tmp_a64(s
);
410 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
412 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
417 /* We should have at some point before trying to access an FP register
418 * done the necessary access check, so assert that
419 * (a) we did the check and
420 * (b) we didn't then just plough ahead anyway if it failed.
421 * Print the instruction pattern in the abort message so we can figure
422 * out what we need to fix if a user encounters this problem in the wild.
424 static inline void assert_fp_access_checked(DisasContext
*s
)
426 #ifdef CONFIG_DEBUG_TCG
427 if (unlikely(!s
->fp_access_checked
|| s
->fp_excp_el
)) {
428 fprintf(stderr
, "target-arm: FP access check missing for "
429 "instruction 0x%08x\n", s
->insn
);
435 /* Return the offset into CPUARMState of an element of specified
436 * size, 'element' places in from the least significant end of
437 * the FP/vector register Qn.
439 static inline int vec_reg_offset(DisasContext
*s
, int regno
,
440 int element
, TCGMemOp size
)
442 int offs
= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
443 #ifdef HOST_WORDS_BIGENDIAN
444 /* This is complicated slightly because vfp.regs[2n] is
445 * still the low half and vfp.regs[2n+1] the high half
446 * of the 128 bit vector, even on big endian systems.
447 * Calculate the offset assuming a fully bigendian 128 bits,
448 * then XOR to account for the order of the two 64 bit halves.
450 offs
+= (16 - ((element
+ 1) * (1 << size
)));
453 offs
+= element
* (1 << size
);
455 assert_fp_access_checked(s
);
459 /* Return the offset into CPUARMState of a slice (from
460 * the least significant end) of FP register Qn (ie
462 * (Note that this is not the same mapping as for A32; see cpu.h)
464 static inline int fp_reg_offset(DisasContext
*s
, int regno
, TCGMemOp size
)
466 int offs
= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
467 #ifdef HOST_WORDS_BIGENDIAN
468 offs
+= (8 - (1 << size
));
470 assert_fp_access_checked(s
);
474 /* Offset of the high half of the 128 bit vector Qn */
475 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
477 assert_fp_access_checked(s
);
478 return offsetof(CPUARMState
, vfp
.regs
[regno
* 2 + 1]);
481 /* Convenience accessors for reading and writing single and double
482 * FP registers. Writing clears the upper parts of the associated
483 * 128 bit vector register, as required by the architecture.
484 * Note that unlike the GP register accessors, the values returned
485 * by the read functions must be manually freed.
487 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
489 TCGv_i64 v
= tcg_temp_new_i64();
491 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
495 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
497 TCGv_i32 v
= tcg_temp_new_i32();
499 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
503 static void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
505 TCGv_i64 tcg_zero
= tcg_const_i64(0);
507 tcg_gen_st_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
508 tcg_gen_st_i64(tcg_zero
, cpu_env
, fp_reg_hi_offset(s
, reg
));
509 tcg_temp_free_i64(tcg_zero
);
512 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
514 TCGv_i64 tmp
= tcg_temp_new_i64();
516 tcg_gen_extu_i32_i64(tmp
, v
);
517 write_fp_dreg(s
, reg
, tmp
);
518 tcg_temp_free_i64(tmp
);
521 static TCGv_ptr
get_fpstatus_ptr(void)
523 TCGv_ptr statusptr
= tcg_temp_new_ptr();
526 /* In A64 all instructions (both FP and Neon) use the FPCR;
527 * there is no equivalent of the A32 Neon "standard FPSCR value"
528 * and all operations use vfp.fp_status.
530 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
531 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
535 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
536 * than the 32 bit equivalent.
538 static inline void gen_set_NZ64(TCGv_i64 result
)
540 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
541 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
544 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
545 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
548 gen_set_NZ64(result
);
550 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
551 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
553 tcg_gen_movi_i32(cpu_CF
, 0);
554 tcg_gen_movi_i32(cpu_VF
, 0);
557 /* dest = T0 + T1; compute C, N, V and Z flags */
558 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
561 TCGv_i64 result
, flag
, tmp
;
562 result
= tcg_temp_new_i64();
563 flag
= tcg_temp_new_i64();
564 tmp
= tcg_temp_new_i64();
566 tcg_gen_movi_i64(tmp
, 0);
567 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
569 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
571 gen_set_NZ64(result
);
573 tcg_gen_xor_i64(flag
, result
, t0
);
574 tcg_gen_xor_i64(tmp
, t0
, t1
);
575 tcg_gen_andc_i64(flag
, flag
, tmp
);
576 tcg_temp_free_i64(tmp
);
577 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
579 tcg_gen_mov_i64(dest
, result
);
580 tcg_temp_free_i64(result
);
581 tcg_temp_free_i64(flag
);
583 /* 32 bit arithmetic */
584 TCGv_i32 t0_32
= tcg_temp_new_i32();
585 TCGv_i32 t1_32
= tcg_temp_new_i32();
586 TCGv_i32 tmp
= tcg_temp_new_i32();
588 tcg_gen_movi_i32(tmp
, 0);
589 tcg_gen_extrl_i64_i32(t0_32
, t0
);
590 tcg_gen_extrl_i64_i32(t1_32
, t1
);
591 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
592 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
593 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
594 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
595 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
596 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
598 tcg_temp_free_i32(tmp
);
599 tcg_temp_free_i32(t0_32
);
600 tcg_temp_free_i32(t1_32
);
604 /* dest = T0 - T1; compute C, N, V and Z flags */
605 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
608 /* 64 bit arithmetic */
609 TCGv_i64 result
, flag
, tmp
;
611 result
= tcg_temp_new_i64();
612 flag
= tcg_temp_new_i64();
613 tcg_gen_sub_i64(result
, t0
, t1
);
615 gen_set_NZ64(result
);
617 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
618 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
620 tcg_gen_xor_i64(flag
, result
, t0
);
621 tmp
= tcg_temp_new_i64();
622 tcg_gen_xor_i64(tmp
, t0
, t1
);
623 tcg_gen_and_i64(flag
, flag
, tmp
);
624 tcg_temp_free_i64(tmp
);
625 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
626 tcg_gen_mov_i64(dest
, result
);
627 tcg_temp_free_i64(flag
);
628 tcg_temp_free_i64(result
);
630 /* 32 bit arithmetic */
631 TCGv_i32 t0_32
= tcg_temp_new_i32();
632 TCGv_i32 t1_32
= tcg_temp_new_i32();
635 tcg_gen_extrl_i64_i32(t0_32
, t0
);
636 tcg_gen_extrl_i64_i32(t1_32
, t1
);
637 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
638 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
639 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
640 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
641 tmp
= tcg_temp_new_i32();
642 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
643 tcg_temp_free_i32(t0_32
);
644 tcg_temp_free_i32(t1_32
);
645 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
646 tcg_temp_free_i32(tmp
);
647 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
651 /* dest = T0 + T1 + CF; do not compute flags. */
652 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
654 TCGv_i64 flag
= tcg_temp_new_i64();
655 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
656 tcg_gen_add_i64(dest
, t0
, t1
);
657 tcg_gen_add_i64(dest
, dest
, flag
);
658 tcg_temp_free_i64(flag
);
661 tcg_gen_ext32u_i64(dest
, dest
);
665 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
666 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
669 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
670 result
= tcg_temp_new_i64();
671 cf_64
= tcg_temp_new_i64();
672 vf_64
= tcg_temp_new_i64();
673 tmp
= tcg_const_i64(0);
675 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
676 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
677 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
678 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
679 gen_set_NZ64(result
);
681 tcg_gen_xor_i64(vf_64
, result
, t0
);
682 tcg_gen_xor_i64(tmp
, t0
, t1
);
683 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
684 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
686 tcg_gen_mov_i64(dest
, result
);
688 tcg_temp_free_i64(tmp
);
689 tcg_temp_free_i64(vf_64
);
690 tcg_temp_free_i64(cf_64
);
691 tcg_temp_free_i64(result
);
693 TCGv_i32 t0_32
, t1_32
, tmp
;
694 t0_32
= tcg_temp_new_i32();
695 t1_32
= tcg_temp_new_i32();
696 tmp
= tcg_const_i32(0);
698 tcg_gen_extrl_i64_i32(t0_32
, t0
);
699 tcg_gen_extrl_i64_i32(t1_32
, t1
);
700 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
701 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
703 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
704 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
705 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
706 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
707 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
709 tcg_temp_free_i32(tmp
);
710 tcg_temp_free_i32(t1_32
);
711 tcg_temp_free_i32(t0_32
);
716 * Load/Store generators
720 * Store from GPR register to memory.
722 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
723 TCGv_i64 tcg_addr
, int size
, int memidx
)
726 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, MO_TE
+ size
);
729 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
730 TCGv_i64 tcg_addr
, int size
)
732 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
));
736 * Load from memory to GPR register
738 static void do_gpr_ld_memidx(DisasContext
*s
, TCGv_i64 dest
, TCGv_i64 tcg_addr
,
739 int size
, bool is_signed
, bool extend
, int memidx
)
741 TCGMemOp memop
= MO_TE
+ size
;
749 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
751 if (extend
&& is_signed
) {
753 tcg_gen_ext32u_i64(dest
, dest
);
757 static void do_gpr_ld(DisasContext
*s
, TCGv_i64 dest
, TCGv_i64 tcg_addr
,
758 int size
, bool is_signed
, bool extend
)
760 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
765 * Store from FP register to memory
767 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
769 /* This writes the bottom N bits of a 128 bit wide vector to memory */
770 TCGv_i64 tmp
= tcg_temp_new_i64();
771 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
773 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
), MO_TE
+ size
);
775 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
776 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
), MO_TEQ
);
777 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
778 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
779 tcg_gen_qemu_st_i64(tmp
, tcg_hiaddr
, get_mem_index(s
), MO_TEQ
);
780 tcg_temp_free_i64(tcg_hiaddr
);
783 tcg_temp_free_i64(tmp
);
787 * Load from memory to FP register
789 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
791 /* This always zero-extends and writes to a full 128 bit wide vector */
792 TCGv_i64 tmplo
= tcg_temp_new_i64();
796 TCGMemOp memop
= MO_TE
+ size
;
797 tmphi
= tcg_const_i64(0);
798 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
801 tmphi
= tcg_temp_new_i64();
802 tcg_hiaddr
= tcg_temp_new_i64();
804 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), MO_TEQ
);
805 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
806 tcg_gen_qemu_ld_i64(tmphi
, tcg_hiaddr
, get_mem_index(s
), MO_TEQ
);
807 tcg_temp_free_i64(tcg_hiaddr
);
810 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
811 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
813 tcg_temp_free_i64(tmplo
);
814 tcg_temp_free_i64(tmphi
);
818 * Vector load/store helpers.
820 * The principal difference between this and a FP load is that we don't
821 * zero extend as we are filling a partial chunk of the vector register.
822 * These functions don't support 128 bit loads/stores, which would be
823 * normal load/store operations.
825 * The _i32 versions are useful when operating on 32 bit quantities
826 * (eg for floating point single or using Neon helper functions).
829 /* Get value of an element within a vector register */
830 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
831 int element
, TCGMemOp memop
)
833 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
836 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
839 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
842 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
845 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
848 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
851 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
855 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
858 g_assert_not_reached();
862 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
863 int element
, TCGMemOp memop
)
865 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
868 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
871 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
874 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
877 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
881 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
884 g_assert_not_reached();
888 /* Set value of an element within a vector register */
889 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
890 int element
, TCGMemOp memop
)
892 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
895 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
898 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
901 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
904 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
907 g_assert_not_reached();
911 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
912 int destidx
, int element
, TCGMemOp memop
)
914 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
917 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
920 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
923 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
926 g_assert_not_reached();
930 /* Clear the high 64 bits of a 128 bit vector (in general non-quad
931 * vector ops all need to do this).
933 static void clear_vec_high(DisasContext
*s
, int rd
)
935 TCGv_i64 tcg_zero
= tcg_const_i64(0);
937 write_vec_element(s
, tcg_zero
, rd
, 1, MO_64
);
938 tcg_temp_free_i64(tcg_zero
);
941 /* Store from vector register to memory */
942 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
943 TCGv_i64 tcg_addr
, int size
)
945 TCGMemOp memop
= MO_TE
+ size
;
946 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
948 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
949 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
951 tcg_temp_free_i64(tcg_tmp
);
954 /* Load from memory to vector register */
955 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
956 TCGv_i64 tcg_addr
, int size
)
958 TCGMemOp memop
= MO_TE
+ size
;
959 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
961 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
962 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
964 tcg_temp_free_i64(tcg_tmp
);
967 /* Check that FP/Neon access is enabled. If it is, return
968 * true. If not, emit code to generate an appropriate exception,
969 * and return false; the caller should not emit any code for
970 * the instruction. Note that this check must happen after all
971 * unallocated-encoding checks (otherwise the syndrome information
972 * for the resulting exception will be incorrect).
974 static inline bool fp_access_check(DisasContext
*s
)
976 assert(!s
->fp_access_checked
);
977 s
->fp_access_checked
= true;
979 if (!s
->fp_excp_el
) {
983 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_fp_access_trap(1, 0xe, false),
989 * This utility function is for doing register extension with an
990 * optional shift. You will likely want to pass a temporary for the
991 * destination register. See DecodeRegExtend() in the ARM ARM.
993 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
994 int option
, unsigned int shift
)
996 int extsize
= extract32(option
, 0, 2);
997 bool is_signed
= extract32(option
, 2, 1);
1002 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1005 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1008 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1011 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1017 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1020 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1023 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1026 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1032 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1036 static inline void gen_check_sp_alignment(DisasContext
*s
)
1038 /* The AArch64 architecture mandates that (if enabled via PSTATE
1039 * or SCTLR bits) there is a check that SP is 16-aligned on every
1040 * SP-relative load or store (with an exception generated if it is not).
1041 * In line with general QEMU practice regarding misaligned accesses,
1042 * we omit these checks for the sake of guest program performance.
1043 * This function is provided as a hook so we can more easily add these
1044 * checks in future (possibly as a "favour catching guest program bugs
1045 * over speed" user selectable option).
1050 * This provides a simple table based table lookup decoder. It is
1051 * intended to be used when the relevant bits for decode are too
1052 * awkwardly placed and switch/if based logic would be confusing and
1053 * deeply nested. Since it's a linear search through the table, tables
1054 * should be kept small.
1056 * It returns the first handler where insn & mask == pattern, or
1057 * NULL if there is no match.
1058 * The table is terminated by an empty mask (i.e. 0)
1060 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1063 const AArch64DecodeTable
*tptr
= table
;
1065 while (tptr
->mask
) {
1066 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1067 return tptr
->disas_fn
;
1075 * the instruction disassembly implemented here matches
1076 * the instruction encoding classifications in chapter 3 (C3)
1077 * of the ARM Architecture Reference Manual (DDI0487A_a)
1080 /* C3.2.7 Unconditional branch (immediate)
1082 * +----+-----------+-------------------------------------+
1083 * | op | 0 0 1 0 1 | imm26 |
1084 * +----+-----------+-------------------------------------+
1086 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1088 uint64_t addr
= s
->pc
+ sextract32(insn
, 0, 26) * 4 - 4;
1090 if (insn
& (1U << 31)) {
1091 /* C5.6.26 BL Branch with link */
1092 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1095 /* C5.6.20 B Branch / C5.6.26 BL Branch with link */
1096 gen_goto_tb(s
, 0, addr
);
1099 /* C3.2.1 Compare & branch (immediate)
1100 * 31 30 25 24 23 5 4 0
1101 * +----+-------------+----+---------------------+--------+
1102 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1103 * +----+-------------+----+---------------------+--------+
1105 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1107 unsigned int sf
, op
, rt
;
1109 TCGLabel
*label_match
;
1112 sf
= extract32(insn
, 31, 1);
1113 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1114 rt
= extract32(insn
, 0, 5);
1115 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1117 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1118 label_match
= gen_new_label();
1120 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1121 tcg_cmp
, 0, label_match
);
1123 gen_goto_tb(s
, 0, s
->pc
);
1124 gen_set_label(label_match
);
1125 gen_goto_tb(s
, 1, addr
);
1128 /* C3.2.5 Test & branch (immediate)
1129 * 31 30 25 24 23 19 18 5 4 0
1130 * +----+-------------+----+-------+-------------+------+
1131 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1132 * +----+-------------+----+-------+-------------+------+
1134 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1136 unsigned int bit_pos
, op
, rt
;
1138 TCGLabel
*label_match
;
1141 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1142 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1143 addr
= s
->pc
+ sextract32(insn
, 5, 14) * 4 - 4;
1144 rt
= extract32(insn
, 0, 5);
1146 tcg_cmp
= tcg_temp_new_i64();
1147 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1148 label_match
= gen_new_label();
1149 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1150 tcg_cmp
, 0, label_match
);
1151 tcg_temp_free_i64(tcg_cmp
);
1152 gen_goto_tb(s
, 0, s
->pc
);
1153 gen_set_label(label_match
);
1154 gen_goto_tb(s
, 1, addr
);
1157 /* C3.2.2 / C5.6.19 Conditional branch (immediate)
1158 * 31 25 24 23 5 4 3 0
1159 * +---------------+----+---------------------+----+------+
1160 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1161 * +---------------+----+---------------------+----+------+
1163 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1168 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1169 unallocated_encoding(s
);
1172 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1173 cond
= extract32(insn
, 0, 4);
1176 /* genuinely conditional branches */
1177 TCGLabel
*label_match
= gen_new_label();
1178 arm_gen_test_cc(cond
, label_match
);
1179 gen_goto_tb(s
, 0, s
->pc
);
1180 gen_set_label(label_match
);
1181 gen_goto_tb(s
, 1, addr
);
1183 /* 0xe and 0xf are both "always" conditions */
1184 gen_goto_tb(s
, 0, addr
);
1189 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1190 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1192 unsigned int selector
= crm
<< 3 | op2
;
1195 unallocated_encoding(s
);
1203 s
->is_jmp
= DISAS_WFI
;
1206 s
->is_jmp
= DISAS_YIELD
;
1209 s
->is_jmp
= DISAS_WFE
;
1213 /* we treat all as NOP at least for now */
1216 /* default specified as NOP equivalent */
1221 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1223 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1226 /* CLREX, DSB, DMB, ISB */
1227 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1228 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1231 unallocated_encoding(s
);
1241 /* We don't emulate caches so barriers are no-ops */
1244 /* We need to break the TB after this insn to execute
1245 * a self-modified code correctly and also to take
1246 * any pending interrupts immediately.
1248 s
->is_jmp
= DISAS_UPDATE
;
1251 unallocated_encoding(s
);
1256 /* C5.6.130 MSR (immediate) - move immediate to processor state field */
1257 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1258 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1260 int op
= op1
<< 3 | op2
;
1262 case 0x05: /* SPSel */
1263 if (s
->current_el
== 0) {
1264 unallocated_encoding(s
);
1268 case 0x1e: /* DAIFSet */
1269 case 0x1f: /* DAIFClear */
1271 TCGv_i32 tcg_imm
= tcg_const_i32(crm
);
1272 TCGv_i32 tcg_op
= tcg_const_i32(op
);
1273 gen_a64_set_pc_im(s
->pc
- 4);
1274 gen_helper_msr_i_pstate(cpu_env
, tcg_op
, tcg_imm
);
1275 tcg_temp_free_i32(tcg_imm
);
1276 tcg_temp_free_i32(tcg_op
);
1277 s
->is_jmp
= DISAS_UPDATE
;
1281 unallocated_encoding(s
);
1286 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1288 TCGv_i32 tmp
= tcg_temp_new_i32();
1289 TCGv_i32 nzcv
= tcg_temp_new_i32();
1291 /* build bit 31, N */
1292 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1293 /* build bit 30, Z */
1294 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1295 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1296 /* build bit 29, C */
1297 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1298 /* build bit 28, V */
1299 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1300 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1301 /* generate result */
1302 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1304 tcg_temp_free_i32(nzcv
);
1305 tcg_temp_free_i32(tmp
);
1308 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1311 TCGv_i32 nzcv
= tcg_temp_new_i32();
1313 /* take NZCV from R[t] */
1314 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1317 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1319 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1320 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1322 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1323 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1325 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1326 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1327 tcg_temp_free_i32(nzcv
);
1330 /* C5.6.129 MRS - move from system register
1331 * C5.6.131 MSR (register) - move to system register
1334 * These are all essentially the same insn in 'read' and 'write'
1335 * versions, with varying op0 fields.
1337 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1338 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1339 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1341 const ARMCPRegInfo
*ri
;
1344 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1345 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1346 crn
, crm
, op0
, op1
, op2
));
1349 /* Unknown register; this might be a guest error or a QEMU
1350 * unimplemented feature.
1352 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1353 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1354 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1355 unallocated_encoding(s
);
1359 /* Check access permissions */
1360 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1361 unallocated_encoding(s
);
1366 /* Emit code to perform further access permissions checks at
1367 * runtime; this may result in an exception.
1373 gen_a64_set_pc_im(s
->pc
- 4);
1374 tmpptr
= tcg_const_ptr(ri
);
1375 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1376 tcg_syn
= tcg_const_i32(syndrome
);
1377 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
);
1378 tcg_temp_free_ptr(tmpptr
);
1379 tcg_temp_free_i32(tcg_syn
);
1382 /* Handle special cases first */
1383 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1387 tcg_rt
= cpu_reg(s
, rt
);
1389 gen_get_nzcv(tcg_rt
);
1391 gen_set_nzcv(tcg_rt
);
1394 case ARM_CP_CURRENTEL
:
1395 /* Reads as current EL value from pstate, which is
1396 * guaranteed to be constant by the tb flags.
1398 tcg_rt
= cpu_reg(s
, rt
);
1399 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1402 /* Writes clear the aligned block of memory which rt points into. */
1403 tcg_rt
= cpu_reg(s
, rt
);
1404 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1410 if ((s
->tb
->cflags
& CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1414 tcg_rt
= cpu_reg(s
, rt
);
1417 if (ri
->type
& ARM_CP_CONST
) {
1418 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1419 } else if (ri
->readfn
) {
1421 tmpptr
= tcg_const_ptr(ri
);
1422 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1423 tcg_temp_free_ptr(tmpptr
);
1425 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1428 if (ri
->type
& ARM_CP_CONST
) {
1429 /* If not forbidden by access permissions, treat as WI */
1431 } else if (ri
->writefn
) {
1433 tmpptr
= tcg_const_ptr(ri
);
1434 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1435 tcg_temp_free_ptr(tmpptr
);
1437 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1441 if ((s
->tb
->cflags
& CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1442 /* I/O operations must end the TB here (whether read or write) */
1444 s
->is_jmp
= DISAS_UPDATE
;
1445 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1446 /* We default to ending the TB on a coprocessor register write,
1447 * but allow this to be suppressed by the register definition
1448 * (usually only necessary to work around guest bugs).
1450 s
->is_jmp
= DISAS_UPDATE
;
1455 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1456 * +---------------------+---+-----+-----+-------+-------+-----+------+
1457 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1458 * +---------------------+---+-----+-----+-------+-------+-----+------+
1460 static void disas_system(DisasContext
*s
, uint32_t insn
)
1462 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1463 l
= extract32(insn
, 21, 1);
1464 op0
= extract32(insn
, 19, 2);
1465 op1
= extract32(insn
, 16, 3);
1466 crn
= extract32(insn
, 12, 4);
1467 crm
= extract32(insn
, 8, 4);
1468 op2
= extract32(insn
, 5, 3);
1469 rt
= extract32(insn
, 0, 5);
1472 if (l
|| rt
!= 31) {
1473 unallocated_encoding(s
);
1477 case 2: /* C5.6.68 HINT */
1478 handle_hint(s
, insn
, op1
, op2
, crm
);
1480 case 3: /* CLREX, DSB, DMB, ISB */
1481 handle_sync(s
, insn
, op1
, op2
, crm
);
1483 case 4: /* C5.6.130 MSR (immediate) */
1484 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1487 unallocated_encoding(s
);
1492 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1495 /* C3.2.3 Exception generation
1497 * 31 24 23 21 20 5 4 2 1 0
1498 * +-----------------+-----+------------------------+-----+----+
1499 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1500 * +-----------------------+------------------------+----------+
1502 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1504 int opc
= extract32(insn
, 21, 3);
1505 int op2_ll
= extract32(insn
, 0, 5);
1506 int imm16
= extract32(insn
, 5, 16);
1511 /* For SVC, HVC and SMC we advance the single-step state
1512 * machine before taking the exception. This is architecturally
1513 * mandated, to ensure that single-stepping a system call
1514 * instruction works properly.
1519 gen_exception_insn(s
, 0, EXCP_SWI
, syn_aa64_svc(imm16
),
1520 default_exception_el(s
));
1523 if (s
->current_el
== 0) {
1524 unallocated_encoding(s
);
1527 /* The pre HVC helper handles cases when HVC gets trapped
1528 * as an undefined insn by runtime configuration.
1530 gen_a64_set_pc_im(s
->pc
- 4);
1531 gen_helper_pre_hvc(cpu_env
);
1533 gen_exception_insn(s
, 0, EXCP_HVC
, syn_aa64_hvc(imm16
), 2);
1536 if (s
->current_el
== 0) {
1537 unallocated_encoding(s
);
1540 gen_a64_set_pc_im(s
->pc
- 4);
1541 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
1542 gen_helper_pre_smc(cpu_env
, tmp
);
1543 tcg_temp_free_i32(tmp
);
1545 gen_exception_insn(s
, 0, EXCP_SMC
, syn_aa64_smc(imm16
), 3);
1548 unallocated_encoding(s
);
1554 unallocated_encoding(s
);
1558 gen_exception_insn(s
, 4, EXCP_BKPT
, syn_aa64_bkpt(imm16
),
1559 default_exception_el(s
));
1563 unallocated_encoding(s
);
1566 /* HLT. This has two purposes.
1567 * Architecturally, it is an external halting debug instruction.
1568 * Since QEMU doesn't implement external debug, we treat this as
1569 * it is required for halting debug disabled: it will UNDEF.
1570 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
1572 if (semihosting_enabled() && imm16
== 0xf000) {
1573 #ifndef CONFIG_USER_ONLY
1574 /* In system mode, don't allow userspace access to semihosting,
1575 * to provide some semblance of security (and for consistency
1576 * with our 32-bit semihosting).
1578 if (s
->current_el
== 0) {
1579 unsupported_encoding(s
, insn
);
1583 gen_exception_internal_insn(s
, 0, EXCP_SEMIHOST
);
1585 unsupported_encoding(s
, insn
);
1589 if (op2_ll
< 1 || op2_ll
> 3) {
1590 unallocated_encoding(s
);
1593 /* DCPS1, DCPS2, DCPS3 */
1594 unsupported_encoding(s
, insn
);
1597 unallocated_encoding(s
);
1602 /* C3.2.7 Unconditional branch (register)
1603 * 31 25 24 21 20 16 15 10 9 5 4 0
1604 * +---------------+-------+-------+-------+------+-------+
1605 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1606 * +---------------+-------+-------+-------+------+-------+
1608 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
1610 unsigned int opc
, op2
, op3
, rn
, op4
;
1612 opc
= extract32(insn
, 21, 4);
1613 op2
= extract32(insn
, 16, 5);
1614 op3
= extract32(insn
, 10, 6);
1615 rn
= extract32(insn
, 5, 5);
1616 op4
= extract32(insn
, 0, 5);
1618 if (op4
!= 0x0 || op3
!= 0x0 || op2
!= 0x1f) {
1619 unallocated_encoding(s
);
1626 tcg_gen_mov_i64(cpu_pc
, cpu_reg(s
, rn
));
1629 tcg_gen_mov_i64(cpu_pc
, cpu_reg(s
, rn
));
1630 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1633 if (s
->current_el
== 0) {
1634 unallocated_encoding(s
);
1637 gen_helper_exception_return(cpu_env
);
1638 s
->is_jmp
= DISAS_JUMP
;
1642 unallocated_encoding(s
);
1644 unsupported_encoding(s
, insn
);
1648 unallocated_encoding(s
);
1652 s
->is_jmp
= DISAS_JUMP
;
1655 /* C3.2 Branches, exception generating and system instructions */
1656 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
1658 switch (extract32(insn
, 25, 7)) {
1659 case 0x0a: case 0x0b:
1660 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
1661 disas_uncond_b_imm(s
, insn
);
1663 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
1664 disas_comp_b_imm(s
, insn
);
1666 case 0x1b: case 0x5b: /* Test & branch (immediate) */
1667 disas_test_b_imm(s
, insn
);
1669 case 0x2a: /* Conditional branch (immediate) */
1670 disas_cond_b_imm(s
, insn
);
1672 case 0x6a: /* Exception generation / System */
1673 if (insn
& (1 << 24)) {
1674 disas_system(s
, insn
);
1679 case 0x6b: /* Unconditional branch (register) */
1680 disas_uncond_b_reg(s
, insn
);
1683 unallocated_encoding(s
);
1689 * Load/Store exclusive instructions are implemented by remembering
1690 * the value/address loaded, and seeing if these are the same
1691 * when the store is performed. This is not actually the architecturally
1692 * mandated semantics, but it works for typical guest code sequences
1693 * and avoids having to monitor regular stores.
1695 * In system emulation mode only one CPU will be running at once, so
1696 * this sequence is effectively atomic. In user emulation mode we
1697 * throw an exception and handle the atomic operation elsewhere.
1699 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
1700 TCGv_i64 addr
, int size
, bool is_pair
)
1702 TCGv_i64 tmp
= tcg_temp_new_i64();
1703 TCGMemOp memop
= MO_TE
+ size
;
1705 g_assert(size
<= 3);
1706 tcg_gen_qemu_ld_i64(tmp
, addr
, get_mem_index(s
), memop
);
1709 TCGv_i64 addr2
= tcg_temp_new_i64();
1710 TCGv_i64 hitmp
= tcg_temp_new_i64();
1712 g_assert(size
>= 2);
1713 tcg_gen_addi_i64(addr2
, addr
, 1 << size
);
1714 tcg_gen_qemu_ld_i64(hitmp
, addr2
, get_mem_index(s
), memop
);
1715 tcg_temp_free_i64(addr2
);
1716 tcg_gen_mov_i64(cpu_exclusive_high
, hitmp
);
1717 tcg_gen_mov_i64(cpu_reg(s
, rt2
), hitmp
);
1718 tcg_temp_free_i64(hitmp
);
1721 tcg_gen_mov_i64(cpu_exclusive_val
, tmp
);
1722 tcg_gen_mov_i64(cpu_reg(s
, rt
), tmp
);
1724 tcg_temp_free_i64(tmp
);
1725 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
1728 #ifdef CONFIG_USER_ONLY
1729 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
1730 TCGv_i64 addr
, int size
, int is_pair
)
1732 tcg_gen_mov_i64(cpu_exclusive_test
, addr
);
1733 tcg_gen_movi_i32(cpu_exclusive_info
,
1734 size
| is_pair
<< 2 | (rd
<< 4) | (rt
<< 9) | (rt2
<< 14));
1735 gen_exception_internal_insn(s
, 4, EXCP_STREX
);
1738 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
1739 TCGv_i64 inaddr
, int size
, int is_pair
)
1741 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
1742 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
1745 * [addr + datasize] = {Rt2};
1751 * env->exclusive_addr = -1;
1753 TCGLabel
*fail_label
= gen_new_label();
1754 TCGLabel
*done_label
= gen_new_label();
1755 TCGv_i64 addr
= tcg_temp_local_new_i64();
1758 /* Copy input into a local temp so it is not trashed when the
1759 * basic block ends at the branch insn.
1761 tcg_gen_mov_i64(addr
, inaddr
);
1762 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
1764 tmp
= tcg_temp_new_i64();
1765 tcg_gen_qemu_ld_i64(tmp
, addr
, get_mem_index(s
), MO_TE
+ size
);
1766 tcg_gen_brcond_i64(TCG_COND_NE
, tmp
, cpu_exclusive_val
, fail_label
);
1767 tcg_temp_free_i64(tmp
);
1770 TCGv_i64 addrhi
= tcg_temp_new_i64();
1771 TCGv_i64 tmphi
= tcg_temp_new_i64();
1773 tcg_gen_addi_i64(addrhi
, addr
, 1 << size
);
1774 tcg_gen_qemu_ld_i64(tmphi
, addrhi
, get_mem_index(s
), MO_TE
+ size
);
1775 tcg_gen_brcond_i64(TCG_COND_NE
, tmphi
, cpu_exclusive_high
, fail_label
);
1777 tcg_temp_free_i64(tmphi
);
1778 tcg_temp_free_i64(addrhi
);
1781 /* We seem to still have the exclusive monitor, so do the store */
1782 tcg_gen_qemu_st_i64(cpu_reg(s
, rt
), addr
, get_mem_index(s
), MO_TE
+ size
);
1784 TCGv_i64 addrhi
= tcg_temp_new_i64();
1786 tcg_gen_addi_i64(addrhi
, addr
, 1 << size
);
1787 tcg_gen_qemu_st_i64(cpu_reg(s
, rt2
), addrhi
,
1788 get_mem_index(s
), MO_TE
+ size
);
1789 tcg_temp_free_i64(addrhi
);
1792 tcg_temp_free_i64(addr
);
1794 tcg_gen_movi_i64(cpu_reg(s
, rd
), 0);
1795 tcg_gen_br(done_label
);
1796 gen_set_label(fail_label
);
1797 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
1798 gen_set_label(done_label
);
1799 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1804 /* C3.3.6 Load/store exclusive
1806 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
1807 * +-----+-------------+----+---+----+------+----+-------+------+------+
1808 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
1809 * +-----+-------------+----+---+----+------+----+-------+------+------+
1811 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
1812 * L: 0 -> store, 1 -> load
1813 * o2: 0 -> exclusive, 1 -> not
1814 * o1: 0 -> single register, 1 -> register pair
1815 * o0: 1 -> load-acquire/store-release, 0 -> not
1817 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
1819 int rt
= extract32(insn
, 0, 5);
1820 int rn
= extract32(insn
, 5, 5);
1821 int rt2
= extract32(insn
, 10, 5);
1822 int is_lasr
= extract32(insn
, 15, 1);
1823 int rs
= extract32(insn
, 16, 5);
1824 int is_pair
= extract32(insn
, 21, 1);
1825 int is_store
= !extract32(insn
, 22, 1);
1826 int is_excl
= !extract32(insn
, 23, 1);
1827 int size
= extract32(insn
, 30, 2);
1830 if ((!is_excl
&& !is_pair
&& !is_lasr
) ||
1831 (!is_excl
&& is_pair
) ||
1832 (is_pair
&& size
< 2)) {
1833 unallocated_encoding(s
);
1838 gen_check_sp_alignment(s
);
1840 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
1842 /* Note that since TCG is single threaded load-acquire/store-release
1843 * semantics require no extra if (is_lasr) { ... } handling.
1849 gen_load_exclusive(s
, rt
, rt2
, tcg_addr
, size
, is_pair
);
1851 gen_store_exclusive(s
, rs
, rt
, rt2
, tcg_addr
, size
, is_pair
);
1854 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
1856 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
1858 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, false, false);
1864 * C3.3.5 Load register (literal)
1866 * 31 30 29 27 26 25 24 23 5 4 0
1867 * +-----+-------+---+-----+-------------------+-------+
1868 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
1869 * +-----+-------+---+-----+-------------------+-------+
1871 * V: 1 -> vector (simd/fp)
1872 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
1873 * 10-> 32 bit signed, 11 -> prefetch
1874 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
1876 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
1878 int rt
= extract32(insn
, 0, 5);
1879 int64_t imm
= sextract32(insn
, 5, 19) << 2;
1880 bool is_vector
= extract32(insn
, 26, 1);
1881 int opc
= extract32(insn
, 30, 2);
1882 bool is_signed
= false;
1884 TCGv_i64 tcg_rt
, tcg_addr
;
1888 unallocated_encoding(s
);
1892 if (!fp_access_check(s
)) {
1897 /* PRFM (literal) : prefetch */
1900 size
= 2 + extract32(opc
, 0, 1);
1901 is_signed
= extract32(opc
, 1, 1);
1904 tcg_rt
= cpu_reg(s
, rt
);
1906 tcg_addr
= tcg_const_i64((s
->pc
- 4) + imm
);
1908 do_fp_ld(s
, rt
, tcg_addr
, size
);
1910 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false);
1912 tcg_temp_free_i64(tcg_addr
);
1916 * C5.6.80 LDNP (Load Pair - non-temporal hint)
1917 * C5.6.81 LDP (Load Pair - non vector)
1918 * C5.6.82 LDPSW (Load Pair Signed Word - non vector)
1919 * C5.6.176 STNP (Store Pair - non-temporal hint)
1920 * C5.6.177 STP (Store Pair - non vector)
1921 * C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint)
1922 * C6.3.165 LDP (Load Pair of SIMD&FP)
1923 * C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint)
1924 * C6.3.284 STP (Store Pair of SIMD&FP)
1926 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
1927 * +-----+-------+---+---+-------+---+-----------------------------+
1928 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
1929 * +-----+-------+---+---+-------+---+-------+-------+------+------+
1931 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
1933 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
1934 * V: 0 -> GPR, 1 -> Vector
1935 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
1936 * 10 -> signed offset, 11 -> pre-index
1937 * L: 0 -> Store 1 -> Load
1939 * Rt, Rt2 = GPR or SIMD registers to be stored
1940 * Rn = general purpose register containing address
1941 * imm7 = signed offset (multiple of 4 or 8 depending on size)
1943 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
1945 int rt
= extract32(insn
, 0, 5);
1946 int rn
= extract32(insn
, 5, 5);
1947 int rt2
= extract32(insn
, 10, 5);
1948 uint64_t offset
= sextract64(insn
, 15, 7);
1949 int index
= extract32(insn
, 23, 2);
1950 bool is_vector
= extract32(insn
, 26, 1);
1951 bool is_load
= extract32(insn
, 22, 1);
1952 int opc
= extract32(insn
, 30, 2);
1954 bool is_signed
= false;
1955 bool postindex
= false;
1958 TCGv_i64 tcg_addr
; /* calculated address */
1962 unallocated_encoding(s
);
1969 size
= 2 + extract32(opc
, 1, 1);
1970 is_signed
= extract32(opc
, 0, 1);
1971 if (!is_load
&& is_signed
) {
1972 unallocated_encoding(s
);
1978 case 1: /* post-index */
1983 /* signed offset with "non-temporal" hint. Since we don't emulate
1984 * caches we don't care about hints to the cache system about
1985 * data access patterns, and handle this identically to plain
1989 /* There is no non-temporal-hint version of LDPSW */
1990 unallocated_encoding(s
);
1995 case 2: /* signed offset, rn not updated */
1998 case 3: /* pre-index */
2004 if (is_vector
&& !fp_access_check(s
)) {
2011 gen_check_sp_alignment(s
);
2014 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2017 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2022 do_fp_ld(s
, rt
, tcg_addr
, size
);
2024 do_fp_st(s
, rt
, tcg_addr
, size
);
2027 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2029 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false);
2031 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
2034 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2037 do_fp_ld(s
, rt2
, tcg_addr
, size
);
2039 do_fp_st(s
, rt2
, tcg_addr
, size
);
2042 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2044 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, is_signed
, false);
2046 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
);
2052 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
- (1 << size
));
2054 tcg_gen_subi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2056 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), tcg_addr
);
2061 * C3.3.8 Load/store (immediate post-indexed)
2062 * C3.3.9 Load/store (immediate pre-indexed)
2063 * C3.3.12 Load/store (unscaled immediate)
2065 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2066 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2067 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2068 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2070 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2072 * V = 0 -> non-vector
2073 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2074 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2076 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
)
2078 int rt
= extract32(insn
, 0, 5);
2079 int rn
= extract32(insn
, 5, 5);
2080 int imm9
= sextract32(insn
, 12, 9);
2081 int opc
= extract32(insn
, 22, 2);
2082 int size
= extract32(insn
, 30, 2);
2083 int idx
= extract32(insn
, 10, 2);
2084 bool is_signed
= false;
2085 bool is_store
= false;
2086 bool is_extended
= false;
2087 bool is_unpriv
= (idx
== 2);
2088 bool is_vector
= extract32(insn
, 26, 1);
2095 size
|= (opc
& 2) << 1;
2096 if (size
> 4 || is_unpriv
) {
2097 unallocated_encoding(s
);
2100 is_store
= ((opc
& 1) == 0);
2101 if (!fp_access_check(s
)) {
2105 if (size
== 3 && opc
== 2) {
2106 /* PRFM - prefetch */
2108 unallocated_encoding(s
);
2113 if (opc
== 3 && size
> 1) {
2114 unallocated_encoding(s
);
2117 is_store
= (opc
== 0);
2118 is_signed
= opc
& (1<<1);
2119 is_extended
= (size
< 3) && (opc
& 1);
2139 gen_check_sp_alignment(s
);
2141 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2144 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2149 do_fp_st(s
, rt
, tcg_addr
, size
);
2151 do_fp_ld(s
, rt
, tcg_addr
, size
);
2154 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2155 int memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
2158 do_gpr_st_memidx(s
, tcg_rt
, tcg_addr
, size
, memidx
);
2160 do_gpr_ld_memidx(s
, tcg_rt
, tcg_addr
, size
,
2161 is_signed
, is_extended
, memidx
);
2166 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2168 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2170 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2175 * C3.3.10 Load/store (register offset)
2177 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2178 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2179 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2180 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2183 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2184 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2186 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2187 * opc<0>: 0 -> store, 1 -> load
2188 * V: 1 -> vector/simd
2189 * opt: extend encoding (see DecodeRegExtend)
2190 * S: if S=1 then scale (essentially index by sizeof(size))
2191 * Rt: register to transfer into/out of
2192 * Rn: address register or SP for base
2193 * Rm: offset register or ZR for offset
2195 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
)
2197 int rt
= extract32(insn
, 0, 5);
2198 int rn
= extract32(insn
, 5, 5);
2199 int shift
= extract32(insn
, 12, 1);
2200 int rm
= extract32(insn
, 16, 5);
2201 int opc
= extract32(insn
, 22, 2);
2202 int opt
= extract32(insn
, 13, 3);
2203 int size
= extract32(insn
, 30, 2);
2204 bool is_signed
= false;
2205 bool is_store
= false;
2206 bool is_extended
= false;
2207 bool is_vector
= extract32(insn
, 26, 1);
2212 if (extract32(opt
, 1, 1) == 0) {
2213 unallocated_encoding(s
);
2218 size
|= (opc
& 2) << 1;
2220 unallocated_encoding(s
);
2223 is_store
= !extract32(opc
, 0, 1);
2224 if (!fp_access_check(s
)) {
2228 if (size
== 3 && opc
== 2) {
2229 /* PRFM - prefetch */
2232 if (opc
== 3 && size
> 1) {
2233 unallocated_encoding(s
);
2236 is_store
= (opc
== 0);
2237 is_signed
= extract32(opc
, 1, 1);
2238 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2242 gen_check_sp_alignment(s
);
2244 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2246 tcg_rm
= read_cpu_reg(s
, rm
, 1);
2247 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
2249 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_rm
);
2253 do_fp_st(s
, rt
, tcg_addr
, size
);
2255 do_fp_ld(s
, rt
, tcg_addr
, size
);
2258 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2260 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
2262 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
);
2268 * C3.3.13 Load/store (unsigned immediate)
2270 * 31 30 29 27 26 25 24 23 22 21 10 9 5
2271 * +----+-------+---+-----+-----+------------+-------+------+
2272 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
2273 * +----+-------+---+-----+-----+------------+-------+------+
2276 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2277 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2279 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2280 * opc<0>: 0 -> store, 1 -> load
2281 * Rn: base address register (inc SP)
2282 * Rt: target register
2284 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
)
2286 int rt
= extract32(insn
, 0, 5);
2287 int rn
= extract32(insn
, 5, 5);
2288 unsigned int imm12
= extract32(insn
, 10, 12);
2289 bool is_vector
= extract32(insn
, 26, 1);
2290 int size
= extract32(insn
, 30, 2);
2291 int opc
= extract32(insn
, 22, 2);
2292 unsigned int offset
;
2297 bool is_signed
= false;
2298 bool is_extended
= false;
2301 size
|= (opc
& 2) << 1;
2303 unallocated_encoding(s
);
2306 is_store
= !extract32(opc
, 0, 1);
2307 if (!fp_access_check(s
)) {
2311 if (size
== 3 && opc
== 2) {
2312 /* PRFM - prefetch */
2315 if (opc
== 3 && size
> 1) {
2316 unallocated_encoding(s
);
2319 is_store
= (opc
== 0);
2320 is_signed
= extract32(opc
, 1, 1);
2321 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2325 gen_check_sp_alignment(s
);
2327 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2328 offset
= imm12
<< size
;
2329 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2333 do_fp_st(s
, rt
, tcg_addr
, size
);
2335 do_fp_ld(s
, rt
, tcg_addr
, size
);
2338 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2340 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
2342 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
);
2347 /* Load/store register (all forms) */
2348 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
2350 switch (extract32(insn
, 24, 2)) {
2352 if (extract32(insn
, 21, 1) == 1 && extract32(insn
, 10, 2) == 2) {
2353 disas_ldst_reg_roffset(s
, insn
);
2355 /* Load/store register (unscaled immediate)
2356 * Load/store immediate pre/post-indexed
2357 * Load/store register unprivileged
2359 disas_ldst_reg_imm9(s
, insn
);
2363 disas_ldst_reg_unsigned_imm(s
, insn
);
2366 unallocated_encoding(s
);
2371 /* C3.3.1 AdvSIMD load/store multiple structures
2373 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
2374 * +---+---+---------------+---+-------------+--------+------+------+------+
2375 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
2376 * +---+---+---------------+---+-------------+--------+------+------+------+
2378 * C3.3.2 AdvSIMD load/store multiple structures (post-indexed)
2380 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
2381 * +---+---+---------------+---+---+---------+--------+------+------+------+
2382 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
2383 * +---+---+---------------+---+---+---------+--------+------+------+------+
2385 * Rt: first (or only) SIMD&FP register to be transferred
2386 * Rn: base address or SP
2387 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2389 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
2391 int rt
= extract32(insn
, 0, 5);
2392 int rn
= extract32(insn
, 5, 5);
2393 int size
= extract32(insn
, 10, 2);
2394 int opcode
= extract32(insn
, 12, 4);
2395 bool is_store
= !extract32(insn
, 22, 1);
2396 bool is_postidx
= extract32(insn
, 23, 1);
2397 bool is_q
= extract32(insn
, 30, 1);
2398 TCGv_i64 tcg_addr
, tcg_rn
;
2400 int ebytes
= 1 << size
;
2401 int elements
= (is_q
? 128 : 64) / (8 << size
);
2402 int rpt
; /* num iterations */
2403 int selem
; /* structure elements */
2406 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
2407 unallocated_encoding(s
);
2411 /* From the shared decode logic */
2442 unallocated_encoding(s
);
2446 if (size
== 3 && !is_q
&& selem
!= 1) {
2448 unallocated_encoding(s
);
2452 if (!fp_access_check(s
)) {
2457 gen_check_sp_alignment(s
);
2460 tcg_rn
= cpu_reg_sp(s
, rn
);
2461 tcg_addr
= tcg_temp_new_i64();
2462 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2464 for (r
= 0; r
< rpt
; r
++) {
2466 for (e
= 0; e
< elements
; e
++) {
2467 int tt
= (rt
+ r
) % 32;
2469 for (xs
= 0; xs
< selem
; xs
++) {
2471 do_vec_st(s
, tt
, e
, tcg_addr
, size
);
2473 do_vec_ld(s
, tt
, e
, tcg_addr
, size
);
2475 /* For non-quad operations, setting a slice of the low
2476 * 64 bits of the register clears the high 64 bits (in
2477 * the ARM ARM pseudocode this is implicit in the fact
2478 * that 'rval' is a 64 bit wide variable). We optimize
2479 * by noticing that we only need to do this the first
2480 * time we touch a register.
2482 if (!is_q
&& e
== 0 && (r
== 0 || xs
== selem
- 1)) {
2483 clear_vec_high(s
, tt
);
2486 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2493 int rm
= extract32(insn
, 16, 5);
2495 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2497 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2500 tcg_temp_free_i64(tcg_addr
);
2503 /* C3.3.3 AdvSIMD load/store single structure
2505 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2506 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2507 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
2508 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2510 * C3.3.4 AdvSIMD load/store single structure (post-indexed)
2512 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2513 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2514 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
2515 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2517 * Rt: first (or only) SIMD&FP register to be transferred
2518 * Rn: base address or SP
2519 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2520 * index = encoded in Q:S:size dependent on size
2522 * lane_size = encoded in R, opc
2523 * transfer width = encoded in opc, S, size
2525 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
2527 int rt
= extract32(insn
, 0, 5);
2528 int rn
= extract32(insn
, 5, 5);
2529 int size
= extract32(insn
, 10, 2);
2530 int S
= extract32(insn
, 12, 1);
2531 int opc
= extract32(insn
, 13, 3);
2532 int R
= extract32(insn
, 21, 1);
2533 int is_load
= extract32(insn
, 22, 1);
2534 int is_postidx
= extract32(insn
, 23, 1);
2535 int is_q
= extract32(insn
, 30, 1);
2537 int scale
= extract32(opc
, 1, 2);
2538 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
2539 bool replicate
= false;
2540 int index
= is_q
<< 3 | S
<< 2 | size
;
2542 TCGv_i64 tcg_addr
, tcg_rn
;
2546 if (!is_load
|| S
) {
2547 unallocated_encoding(s
);
2556 if (extract32(size
, 0, 1)) {
2557 unallocated_encoding(s
);
2563 if (extract32(size
, 1, 1)) {
2564 unallocated_encoding(s
);
2567 if (!extract32(size
, 0, 1)) {
2571 unallocated_encoding(s
);
2579 g_assert_not_reached();
2582 if (!fp_access_check(s
)) {
2586 ebytes
= 1 << scale
;
2589 gen_check_sp_alignment(s
);
2592 tcg_rn
= cpu_reg_sp(s
, rn
);
2593 tcg_addr
= tcg_temp_new_i64();
2594 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2596 for (xs
= 0; xs
< selem
; xs
++) {
2598 /* Load and replicate to all elements */
2600 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
2602 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
,
2603 get_mem_index(s
), MO_TE
+ scale
);
2606 mulconst
= 0x0101010101010101ULL
;
2609 mulconst
= 0x0001000100010001ULL
;
2612 mulconst
= 0x0000000100000001ULL
;
2618 g_assert_not_reached();
2621 tcg_gen_muli_i64(tcg_tmp
, tcg_tmp
, mulconst
);
2623 write_vec_element(s
, tcg_tmp
, rt
, 0, MO_64
);
2625 write_vec_element(s
, tcg_tmp
, rt
, 1, MO_64
);
2627 clear_vec_high(s
, rt
);
2629 tcg_temp_free_i64(tcg_tmp
);
2631 /* Load/store one element per register */
2633 do_vec_ld(s
, rt
, index
, tcg_addr
, MO_TE
+ scale
);
2635 do_vec_st(s
, rt
, index
, tcg_addr
, MO_TE
+ scale
);
2638 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2643 int rm
= extract32(insn
, 16, 5);
2645 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2647 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2650 tcg_temp_free_i64(tcg_addr
);
2653 /* C3.3 Loads and stores */
2654 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
2656 switch (extract32(insn
, 24, 6)) {
2657 case 0x08: /* Load/store exclusive */
2658 disas_ldst_excl(s
, insn
);
2660 case 0x18: case 0x1c: /* Load register (literal) */
2661 disas_ld_lit(s
, insn
);
2663 case 0x28: case 0x29:
2664 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
2665 disas_ldst_pair(s
, insn
);
2667 case 0x38: case 0x39:
2668 case 0x3c: case 0x3d: /* Load/store register (all forms) */
2669 disas_ldst_reg(s
, insn
);
2671 case 0x0c: /* AdvSIMD load/store multiple structures */
2672 disas_ldst_multiple_struct(s
, insn
);
2674 case 0x0d: /* AdvSIMD load/store single structure */
2675 disas_ldst_single_struct(s
, insn
);
2678 unallocated_encoding(s
);
2683 /* C3.4.6 PC-rel. addressing
2684 * 31 30 29 28 24 23 5 4 0
2685 * +----+-------+-----------+-------------------+------+
2686 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
2687 * +----+-------+-----------+-------------------+------+
2689 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
2691 unsigned int page
, rd
;
2695 page
= extract32(insn
, 31, 1);
2696 /* SignExtend(immhi:immlo) -> offset */
2697 offset
= sextract64(insn
, 5, 19);
2698 offset
= offset
<< 2 | extract32(insn
, 29, 2);
2699 rd
= extract32(insn
, 0, 5);
2703 /* ADRP (page based) */
2708 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
2712 * C3.4.1 Add/subtract (immediate)
2714 * 31 30 29 28 24 23 22 21 10 9 5 4 0
2715 * +--+--+--+-----------+-----+-------------+-----+-----+
2716 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
2717 * +--+--+--+-----------+-----+-------------+-----+-----+
2719 * sf: 0 -> 32bit, 1 -> 64bit
2720 * op: 0 -> add , 1 -> sub
2722 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
2724 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
2726 int rd
= extract32(insn
, 0, 5);
2727 int rn
= extract32(insn
, 5, 5);
2728 uint64_t imm
= extract32(insn
, 10, 12);
2729 int shift
= extract32(insn
, 22, 2);
2730 bool setflags
= extract32(insn
, 29, 1);
2731 bool sub_op
= extract32(insn
, 30, 1);
2732 bool is_64bit
= extract32(insn
, 31, 1);
2734 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2735 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
2736 TCGv_i64 tcg_result
;
2745 unallocated_encoding(s
);
2749 tcg_result
= tcg_temp_new_i64();
2752 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
2754 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
2757 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
2759 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2761 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2763 tcg_temp_free_i64(tcg_imm
);
2767 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
2769 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
2772 tcg_temp_free_i64(tcg_result
);
2775 /* The input should be a value in the bottom e bits (with higher
2776 * bits zero); returns that value replicated into every element
2777 * of size e in a 64 bit integer.
2779 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
2789 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
2790 static inline uint64_t bitmask64(unsigned int length
)
2792 assert(length
> 0 && length
<= 64);
2793 return ~0ULL >> (64 - length
);
2796 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
2797 * only require the wmask. Returns false if the imms/immr/immn are a reserved
2798 * value (ie should cause a guest UNDEF exception), and true if they are
2799 * valid, in which case the decoded bit pattern is written to result.
2801 static bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
2802 unsigned int imms
, unsigned int immr
)
2805 unsigned e
, levels
, s
, r
;
2808 assert(immn
< 2 && imms
< 64 && immr
< 64);
2810 /* The bit patterns we create here are 64 bit patterns which
2811 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
2812 * 64 bits each. Each element contains the same value: a run
2813 * of between 1 and e-1 non-zero bits, rotated within the
2814 * element by between 0 and e-1 bits.
2816 * The element size and run length are encoded into immn (1 bit)
2817 * and imms (6 bits) as follows:
2818 * 64 bit elements: immn = 1, imms = <length of run - 1>
2819 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
2820 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
2821 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
2822 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
2823 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
2824 * Notice that immn = 0, imms = 11111x is the only combination
2825 * not covered by one of the above options; this is reserved.
2826 * Further, <length of run - 1> all-ones is a reserved pattern.
2828 * In all cases the rotation is by immr % e (and immr is 6 bits).
2831 /* First determine the element size */
2832 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
2834 /* This is the immn == 0, imms == 0x11111x case */
2844 /* <length of run - 1> mustn't be all-ones. */
2848 /* Create the value of one element: s+1 set bits rotated
2849 * by r within the element (which is e bits wide)...
2851 mask
= bitmask64(s
+ 1);
2853 mask
= (mask
>> r
) | (mask
<< (e
- r
));
2854 mask
&= bitmask64(e
);
2856 /* ...then replicate the element over the whole 64 bit value */
2857 mask
= bitfield_replicate(mask
, e
);
2862 /* C3.4.4 Logical (immediate)
2863 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
2864 * +----+-----+-------------+---+------+------+------+------+
2865 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
2866 * +----+-----+-------------+---+------+------+------+------+
2868 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
2870 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
2871 TCGv_i64 tcg_rd
, tcg_rn
;
2873 bool is_and
= false;
2875 sf
= extract32(insn
, 31, 1);
2876 opc
= extract32(insn
, 29, 2);
2877 is_n
= extract32(insn
, 22, 1);
2878 immr
= extract32(insn
, 16, 6);
2879 imms
= extract32(insn
, 10, 6);
2880 rn
= extract32(insn
, 5, 5);
2881 rd
= extract32(insn
, 0, 5);
2884 unallocated_encoding(s
);
2888 if (opc
== 0x3) { /* ANDS */
2889 tcg_rd
= cpu_reg(s
, rd
);
2891 tcg_rd
= cpu_reg_sp(s
, rd
);
2893 tcg_rn
= cpu_reg(s
, rn
);
2895 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
2896 /* some immediate field values are reserved */
2897 unallocated_encoding(s
);
2902 wmask
&= 0xffffffff;
2906 case 0x3: /* ANDS */
2908 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
2912 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
2915 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
2918 assert(FALSE
); /* must handle all above */
2922 if (!sf
&& !is_and
) {
2923 /* zero extend final result; we know we can skip this for AND
2924 * since the immediate had the high 32 bits clear.
2926 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2929 if (opc
== 3) { /* ANDS */
2930 gen_logic_CC(sf
, tcg_rd
);
2935 * C3.4.5 Move wide (immediate)
2937 * 31 30 29 28 23 22 21 20 5 4 0
2938 * +--+-----+-------------+-----+----------------+------+
2939 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
2940 * +--+-----+-------------+-----+----------------+------+
2942 * sf: 0 -> 32 bit, 1 -> 64 bit
2943 * opc: 00 -> N, 10 -> Z, 11 -> K
2944 * hw: shift/16 (0,16, and sf only 32, 48)
2946 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
2948 int rd
= extract32(insn
, 0, 5);
2949 uint64_t imm
= extract32(insn
, 5, 16);
2950 int sf
= extract32(insn
, 31, 1);
2951 int opc
= extract32(insn
, 29, 2);
2952 int pos
= extract32(insn
, 21, 2) << 4;
2953 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
2956 if (!sf
&& (pos
>= 32)) {
2957 unallocated_encoding(s
);
2971 tcg_gen_movi_i64(tcg_rd
, imm
);
2974 tcg_imm
= tcg_const_i64(imm
);
2975 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
2976 tcg_temp_free_i64(tcg_imm
);
2978 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2982 unallocated_encoding(s
);
2988 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
2989 * +----+-----+-------------+---+------+------+------+------+
2990 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
2991 * +----+-----+-------------+---+------+------+------+------+
2993 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
2995 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
2996 TCGv_i64 tcg_rd
, tcg_tmp
;
2998 sf
= extract32(insn
, 31, 1);
2999 opc
= extract32(insn
, 29, 2);
3000 n
= extract32(insn
, 22, 1);
3001 ri
= extract32(insn
, 16, 6);
3002 si
= extract32(insn
, 10, 6);
3003 rn
= extract32(insn
, 5, 5);
3004 rd
= extract32(insn
, 0, 5);
3005 bitsize
= sf
? 64 : 32;
3007 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
3008 unallocated_encoding(s
);
3012 tcg_rd
= cpu_reg(s
, rd
);
3014 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
3015 to be smaller than bitsize, we'll never reference data outside the
3016 low 32-bits anyway. */
3017 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
3019 /* Recognize the common aliases. */
3020 if (opc
== 0) { /* SBFM */
3022 if (si
== 7) { /* SXTB */
3023 tcg_gen_ext8s_i64(tcg_rd
, tcg_tmp
);
3025 } else if (si
== 15) { /* SXTH */
3026 tcg_gen_ext16s_i64(tcg_rd
, tcg_tmp
);
3028 } else if (si
== 31) { /* SXTW */
3029 tcg_gen_ext32s_i64(tcg_rd
, tcg_tmp
);
3033 if (si
== 63 || (si
== 31 && ri
<= si
)) { /* ASR */
3035 tcg_gen_ext32s_i64(tcg_tmp
, tcg_tmp
);
3037 tcg_gen_sari_i64(tcg_rd
, tcg_tmp
, ri
);
3040 } else if (opc
== 2) { /* UBFM */
3041 if (ri
== 0) { /* UXTB, UXTH, plus non-canonical AND */
3042 tcg_gen_andi_i64(tcg_rd
, tcg_tmp
, bitmask64(si
+ 1));
3045 if (si
== 63 || (si
== 31 && ri
<= si
)) { /* LSR */
3047 tcg_gen_ext32u_i64(tcg_tmp
, tcg_tmp
);
3049 tcg_gen_shri_i64(tcg_rd
, tcg_tmp
, ri
);
3052 if (si
+ 1 == ri
&& si
!= bitsize
- 1) { /* LSL */
3053 int shift
= bitsize
- 1 - si
;
3054 tcg_gen_shli_i64(tcg_rd
, tcg_tmp
, shift
);
3059 if (opc
!= 1) { /* SBFM or UBFM */
3060 tcg_gen_movi_i64(tcg_rd
, 0);
3063 /* do the bit move operation */
3065 /* Wd<s-r:0> = Wn<s:r> */
3066 tcg_gen_shri_i64(tcg_tmp
, tcg_tmp
, ri
);
3068 len
= (si
- ri
) + 1;
3070 /* Wd<32+s-r,32-r> = Wn<s:0> */
3075 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
3077 if (opc
== 0) { /* SBFM - sign extend the destination field */
3078 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 64 - (pos
+ len
));
3079 tcg_gen_sari_i64(tcg_rd
, tcg_rd
, 64 - (pos
+ len
));
3083 if (!sf
) { /* zero extend final result */
3084 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3089 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
3090 * +----+------+-------------+---+----+------+--------+------+------+
3091 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
3092 * +----+------+-------------+---+----+------+--------+------+------+
3094 static void disas_extract(DisasContext
*s
, uint32_t insn
)
3096 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
3098 sf
= extract32(insn
, 31, 1);
3099 n
= extract32(insn
, 22, 1);
3100 rm
= extract32(insn
, 16, 5);
3101 imm
= extract32(insn
, 10, 6);
3102 rn
= extract32(insn
, 5, 5);
3103 rd
= extract32(insn
, 0, 5);
3104 op21
= extract32(insn
, 29, 2);
3105 op0
= extract32(insn
, 21, 1);
3106 bitsize
= sf
? 64 : 32;
3108 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
3109 unallocated_encoding(s
);
3111 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
3113 tcg_rd
= cpu_reg(s
, rd
);
3115 if (unlikely(imm
== 0)) {
3116 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
3117 * so an extract from bit 0 is a special case.
3120 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
3122 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
3124 } else if (rm
== rn
) { /* ROR */
3125 tcg_rm
= cpu_reg(s
, rm
);
3127 tcg_gen_rotri_i64(tcg_rd
, tcg_rm
, imm
);
3129 TCGv_i32 tmp
= tcg_temp_new_i32();
3130 tcg_gen_extrl_i64_i32(tmp
, tcg_rm
);
3131 tcg_gen_rotri_i32(tmp
, tmp
, imm
);
3132 tcg_gen_extu_i32_i64(tcg_rd
, tmp
);
3133 tcg_temp_free_i32(tmp
);
3136 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3137 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3138 tcg_gen_shri_i64(tcg_rm
, tcg_rm
, imm
);
3139 tcg_gen_shli_i64(tcg_rn
, tcg_rn
, bitsize
- imm
);
3140 tcg_gen_or_i64(tcg_rd
, tcg_rm
, tcg_rn
);
3142 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3148 /* C3.4 Data processing - immediate */
3149 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
3151 switch (extract32(insn
, 23, 6)) {
3152 case 0x20: case 0x21: /* PC-rel. addressing */
3153 disas_pc_rel_adr(s
, insn
);
3155 case 0x22: case 0x23: /* Add/subtract (immediate) */
3156 disas_add_sub_imm(s
, insn
);
3158 case 0x24: /* Logical (immediate) */
3159 disas_logic_imm(s
, insn
);
3161 case 0x25: /* Move wide (immediate) */
3162 disas_movw_imm(s
, insn
);
3164 case 0x26: /* Bitfield */
3165 disas_bitfield(s
, insn
);
3167 case 0x27: /* Extract */
3168 disas_extract(s
, insn
);
3171 unallocated_encoding(s
);
3176 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
3177 * Note that it is the caller's responsibility to ensure that the
3178 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
3179 * mandated semantics for out of range shifts.
3181 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3182 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
3184 switch (shift_type
) {
3185 case A64_SHIFT_TYPE_LSL
:
3186 tcg_gen_shl_i64(dst
, src
, shift_amount
);
3188 case A64_SHIFT_TYPE_LSR
:
3189 tcg_gen_shr_i64(dst
, src
, shift_amount
);
3191 case A64_SHIFT_TYPE_ASR
:
3193 tcg_gen_ext32s_i64(dst
, src
);
3195 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
3197 case A64_SHIFT_TYPE_ROR
:
3199 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
3202 t0
= tcg_temp_new_i32();
3203 t1
= tcg_temp_new_i32();
3204 tcg_gen_extrl_i64_i32(t0
, src
);
3205 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
3206 tcg_gen_rotr_i32(t0
, t0
, t1
);
3207 tcg_gen_extu_i32_i64(dst
, t0
);
3208 tcg_temp_free_i32(t0
);
3209 tcg_temp_free_i32(t1
);
3213 assert(FALSE
); /* all shift types should be handled */
3217 if (!sf
) { /* zero extend final result */
3218 tcg_gen_ext32u_i64(dst
, dst
);
3222 /* Shift a TCGv src by immediate, put result in dst.
3223 * The shift amount must be in range (this should always be true as the
3224 * relevant instructions will UNDEF on bad shift immediates).
3226 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3227 enum a64_shift_type shift_type
, unsigned int shift_i
)
3229 assert(shift_i
< (sf
? 64 : 32));
3232 tcg_gen_mov_i64(dst
, src
);
3234 TCGv_i64 shift_const
;
3236 shift_const
= tcg_const_i64(shift_i
);
3237 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
3238 tcg_temp_free_i64(shift_const
);
3242 /* C3.5.10 Logical (shifted register)
3243 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3244 * +----+-----+-----------+-------+---+------+--------+------+------+
3245 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
3246 * +----+-----+-----------+-------+---+------+--------+------+------+
3248 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
3250 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
3251 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
3253 sf
= extract32(insn
, 31, 1);
3254 opc
= extract32(insn
, 29, 2);
3255 shift_type
= extract32(insn
, 22, 2);
3256 invert
= extract32(insn
, 21, 1);
3257 rm
= extract32(insn
, 16, 5);
3258 shift_amount
= extract32(insn
, 10, 6);
3259 rn
= extract32(insn
, 5, 5);
3260 rd
= extract32(insn
, 0, 5);
3262 if (!sf
&& (shift_amount
& (1 << 5))) {
3263 unallocated_encoding(s
);
3267 tcg_rd
= cpu_reg(s
, rd
);
3269 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
3270 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
3271 * register-register MOV and MVN, so it is worth special casing.
3273 tcg_rm
= cpu_reg(s
, rm
);
3275 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
3277 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3281 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
3283 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
3289 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3292 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
3295 tcg_rn
= cpu_reg(s
, rn
);
3297 switch (opc
| (invert
<< 2)) {
3300 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3303 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3306 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3310 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3313 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3316 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3324 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3328 gen_logic_CC(sf
, tcg_rd
);
3333 * C3.5.1 Add/subtract (extended register)
3335 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
3336 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3337 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
3338 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3340 * sf: 0 -> 32bit, 1 -> 64bit
3341 * op: 0 -> add , 1 -> sub
3344 * option: extension type (see DecodeRegExtend)
3345 * imm3: optional shift to Rm
3347 * Rd = Rn + LSL(extend(Rm), amount)
3349 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
3351 int rd
= extract32(insn
, 0, 5);
3352 int rn
= extract32(insn
, 5, 5);
3353 int imm3
= extract32(insn
, 10, 3);
3354 int option
= extract32(insn
, 13, 3);
3355 int rm
= extract32(insn
, 16, 5);
3356 bool setflags
= extract32(insn
, 29, 1);
3357 bool sub_op
= extract32(insn
, 30, 1);
3358 bool sf
= extract32(insn
, 31, 1);
3360 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
3362 TCGv_i64 tcg_result
;
3365 unallocated_encoding(s
);
3369 /* non-flag setting ops may use SP */
3371 tcg_rd
= cpu_reg_sp(s
, rd
);
3373 tcg_rd
= cpu_reg(s
, rd
);
3375 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
3377 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3378 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
3380 tcg_result
= tcg_temp_new_i64();
3384 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3386 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3390 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3392 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3397 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3399 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3402 tcg_temp_free_i64(tcg_result
);
3406 * C3.5.2 Add/subtract (shifted register)
3408 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3409 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3410 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
3411 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3413 * sf: 0 -> 32bit, 1 -> 64bit
3414 * op: 0 -> add , 1 -> sub
3416 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
3417 * imm6: Shift amount to apply to Rm before the add/sub
3419 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
3421 int rd
= extract32(insn
, 0, 5);
3422 int rn
= extract32(insn
, 5, 5);
3423 int imm6
= extract32(insn
, 10, 6);
3424 int rm
= extract32(insn
, 16, 5);
3425 int shift_type
= extract32(insn
, 22, 2);
3426 bool setflags
= extract32(insn
, 29, 1);
3427 bool sub_op
= extract32(insn
, 30, 1);
3428 bool sf
= extract32(insn
, 31, 1);
3430 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3431 TCGv_i64 tcg_rn
, tcg_rm
;
3432 TCGv_i64 tcg_result
;
3434 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
3435 unallocated_encoding(s
);
3439 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3440 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3442 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
3444 tcg_result
= tcg_temp_new_i64();
3448 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3450 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3454 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3456 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3461 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3463 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3466 tcg_temp_free_i64(tcg_result
);
3469 /* C3.5.9 Data-processing (3 source)
3471 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
3472 +--+------+-----------+------+------+----+------+------+------+
3473 |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
3474 +--+------+-----------+------+------+----+------+------+------+
3477 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
3479 int rd
= extract32(insn
, 0, 5);
3480 int rn
= extract32(insn
, 5, 5);
3481 int ra
= extract32(insn
, 10, 5);
3482 int rm
= extract32(insn
, 16, 5);
3483 int op_id
= (extract32(insn
, 29, 3) << 4) |
3484 (extract32(insn
, 21, 3) << 1) |
3485 extract32(insn
, 15, 1);
3486 bool sf
= extract32(insn
, 31, 1);
3487 bool is_sub
= extract32(op_id
, 0, 1);
3488 bool is_high
= extract32(op_id
, 2, 1);
3489 bool is_signed
= false;
3494 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
3496 case 0x42: /* SMADDL */
3497 case 0x43: /* SMSUBL */
3498 case 0x44: /* SMULH */
3501 case 0x0: /* MADD (32bit) */
3502 case 0x1: /* MSUB (32bit) */
3503 case 0x40: /* MADD (64bit) */
3504 case 0x41: /* MSUB (64bit) */
3505 case 0x4a: /* UMADDL */
3506 case 0x4b: /* UMSUBL */
3507 case 0x4c: /* UMULH */
3510 unallocated_encoding(s
);
3515 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
3516 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3517 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
3518 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
3521 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3523 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3526 tcg_temp_free_i64(low_bits
);
3530 tcg_op1
= tcg_temp_new_i64();
3531 tcg_op2
= tcg_temp_new_i64();
3532 tcg_tmp
= tcg_temp_new_i64();
3535 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
3536 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
3539 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
3540 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
3542 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
3543 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
3547 if (ra
== 31 && !is_sub
) {
3548 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
3549 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
3551 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
3553 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3555 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3560 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
3563 tcg_temp_free_i64(tcg_op1
);
3564 tcg_temp_free_i64(tcg_op2
);
3565 tcg_temp_free_i64(tcg_tmp
);
3568 /* C3.5.3 - Add/subtract (with carry)
3569 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
3570 * +--+--+--+------------------------+------+---------+------+-----+
3571 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
3572 * +--+--+--+------------------------+------+---------+------+-----+
3576 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
3578 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
3579 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
3581 if (extract32(insn
, 10, 6) != 0) {
3582 unallocated_encoding(s
);
3586 sf
= extract32(insn
, 31, 1);
3587 op
= extract32(insn
, 30, 1);
3588 setflags
= extract32(insn
, 29, 1);
3589 rm
= extract32(insn
, 16, 5);
3590 rn
= extract32(insn
, 5, 5);
3591 rd
= extract32(insn
, 0, 5);
3593 tcg_rd
= cpu_reg(s
, rd
);
3594 tcg_rn
= cpu_reg(s
, rn
);
3597 tcg_y
= new_tmp_a64(s
);
3598 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
3600 tcg_y
= cpu_reg(s
, rm
);
3604 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3606 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3610 /* C3.5.4 - C3.5.5 Conditional compare (immediate / register)
3611 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
3612 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3613 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
3614 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3617 static void disas_cc(DisasContext
*s
, uint32_t insn
)
3619 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
3620 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
3621 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
3624 if (!extract32(insn
, 29, 1)) {
3625 unallocated_encoding(s
);
3628 if (insn
& (1 << 10 | 1 << 4)) {
3629 unallocated_encoding(s
);
3632 sf
= extract32(insn
, 31, 1);
3633 op
= extract32(insn
, 30, 1);
3634 is_imm
= extract32(insn
, 11, 1);
3635 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
3636 cond
= extract32(insn
, 12, 4);
3637 rn
= extract32(insn
, 5, 5);
3638 nzcv
= extract32(insn
, 0, 4);
3640 /* Set T0 = !COND. */
3641 tcg_t0
= tcg_temp_new_i32();
3642 arm_test_cc(&c
, cond
);
3643 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
3646 /* Load the arguments for the new comparison. */
3648 tcg_y
= new_tmp_a64(s
);
3649 tcg_gen_movi_i64(tcg_y
, y
);
3651 tcg_y
= cpu_reg(s
, y
);
3653 tcg_rn
= cpu_reg(s
, rn
);
3655 /* Set the flags for the new comparison. */
3656 tcg_tmp
= tcg_temp_new_i64();
3658 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3660 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3662 tcg_temp_free_i64(tcg_tmp
);
3664 /* If COND was false, force the flags to #nzcv. Compute two masks
3665 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
3666 * For tcg hosts that support ANDC, we can make do with just T1.
3667 * In either case, allow the tcg optimizer to delete any unused mask.
3669 tcg_t1
= tcg_temp_new_i32();
3670 tcg_t2
= tcg_temp_new_i32();
3671 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
3672 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
3674 if (nzcv
& 8) { /* N */
3675 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
3677 if (TCG_TARGET_HAS_andc_i32
) {
3678 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
3680 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
3683 if (nzcv
& 4) { /* Z */
3684 if (TCG_TARGET_HAS_andc_i32
) {
3685 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
3687 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
3690 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
3692 if (nzcv
& 2) { /* C */
3693 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
3695 if (TCG_TARGET_HAS_andc_i32
) {
3696 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
3698 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
3701 if (nzcv
& 1) { /* V */
3702 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
3704 if (TCG_TARGET_HAS_andc_i32
) {
3705 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
3707 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
3710 tcg_temp_free_i32(tcg_t0
);
3711 tcg_temp_free_i32(tcg_t1
);
3712 tcg_temp_free_i32(tcg_t2
);
3715 /* C3.5.6 Conditional select
3716 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
3717 * +----+----+---+-----------------+------+------+-----+------+------+
3718 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
3719 * +----+----+---+-----------------+------+------+-----+------+------+
3721 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
3723 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
3724 TCGv_i64 tcg_rd
, zero
;
3727 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
3728 /* S == 1 or op2<1> == 1 */
3729 unallocated_encoding(s
);
3732 sf
= extract32(insn
, 31, 1);
3733 else_inv
= extract32(insn
, 30, 1);
3734 rm
= extract32(insn
, 16, 5);
3735 cond
= extract32(insn
, 12, 4);
3736 else_inc
= extract32(insn
, 10, 1);
3737 rn
= extract32(insn
, 5, 5);
3738 rd
= extract32(insn
, 0, 5);
3740 tcg_rd
= cpu_reg(s
, rd
);
3742 a64_test_cc(&c
, cond
);
3743 zero
= tcg_const_i64(0);
3745 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
3747 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
3749 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
3752 TCGv_i64 t_true
= cpu_reg(s
, rn
);
3753 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
3754 if (else_inv
&& else_inc
) {
3755 tcg_gen_neg_i64(t_false
, t_false
);
3756 } else if (else_inv
) {
3757 tcg_gen_not_i64(t_false
, t_false
);
3758 } else if (else_inc
) {
3759 tcg_gen_addi_i64(t_false
, t_false
, 1);
3761 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
3764 tcg_temp_free_i64(zero
);
3768 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3772 static void handle_clz(DisasContext
*s
, unsigned int sf
,
3773 unsigned int rn
, unsigned int rd
)
3775 TCGv_i64 tcg_rd
, tcg_rn
;
3776 tcg_rd
= cpu_reg(s
, rd
);
3777 tcg_rn
= cpu_reg(s
, rn
);
3780 gen_helper_clz64(tcg_rd
, tcg_rn
);
3782 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3783 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
3784 gen_helper_clz(tcg_tmp32
, tcg_tmp32
);
3785 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3786 tcg_temp_free_i32(tcg_tmp32
);
3790 static void handle_cls(DisasContext
*s
, unsigned int sf
,
3791 unsigned int rn
, unsigned int rd
)
3793 TCGv_i64 tcg_rd
, tcg_rn
;
3794 tcg_rd
= cpu_reg(s
, rd
);
3795 tcg_rn
= cpu_reg(s
, rn
);
3798 gen_helper_cls64(tcg_rd
, tcg_rn
);
3800 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3801 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
3802 gen_helper_cls32(tcg_tmp32
, tcg_tmp32
);
3803 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3804 tcg_temp_free_i32(tcg_tmp32
);
3808 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
3809 unsigned int rn
, unsigned int rd
)
3811 TCGv_i64 tcg_rd
, tcg_rn
;
3812 tcg_rd
= cpu_reg(s
, rd
);
3813 tcg_rn
= cpu_reg(s
, rn
);
3816 gen_helper_rbit64(tcg_rd
, tcg_rn
);
3818 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3819 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
3820 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
3821 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3822 tcg_temp_free_i32(tcg_tmp32
);
3826 /* C5.6.149 REV with sf==1, opcode==3 ("REV64") */
3827 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
3828 unsigned int rn
, unsigned int rd
)
3831 unallocated_encoding(s
);
3834 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
3837 /* C5.6.149 REV with sf==0, opcode==2
3838 * C5.6.151 REV32 (sf==1, opcode==2)
3840 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
3841 unsigned int rn
, unsigned int rd
)
3843 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3846 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3847 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3849 /* bswap32_i64 requires zero high word */
3850 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
3851 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
3852 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
3853 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
3854 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
3856 tcg_temp_free_i64(tcg_tmp
);
3858 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
3859 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
3863 /* C5.6.150 REV16 (opcode==1) */
3864 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
3865 unsigned int rn
, unsigned int rd
)
3867 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3868 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3869 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3871 tcg_gen_andi_i64(tcg_tmp
, tcg_rn
, 0xffff);
3872 tcg_gen_bswap16_i64(tcg_rd
, tcg_tmp
);
3874 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 16);
3875 tcg_gen_andi_i64(tcg_tmp
, tcg_tmp
, 0xffff);
3876 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
3877 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 16, 16);
3880 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
3881 tcg_gen_andi_i64(tcg_tmp
, tcg_tmp
, 0xffff);
3882 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
3883 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 32, 16);
3885 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 48);
3886 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
3887 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 48, 16);
3890 tcg_temp_free_i64(tcg_tmp
);
3893 /* C3.5.7 Data-processing (1 source)
3894 * 31 30 29 28 21 20 16 15 10 9 5 4 0
3895 * +----+---+---+-----------------+---------+--------+------+------+
3896 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
3897 * +----+---+---+-----------------+---------+--------+------+------+
3899 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
3901 unsigned int sf
, opcode
, rn
, rd
;
3903 if (extract32(insn
, 29, 1) || extract32(insn
, 16, 5)) {
3904 unallocated_encoding(s
);
3908 sf
= extract32(insn
, 31, 1);
3909 opcode
= extract32(insn
, 10, 6);
3910 rn
= extract32(insn
, 5, 5);
3911 rd
= extract32(insn
, 0, 5);
3915 handle_rbit(s
, sf
, rn
, rd
);
3918 handle_rev16(s
, sf
, rn
, rd
);
3921 handle_rev32(s
, sf
, rn
, rd
);
3924 handle_rev64(s
, sf
, rn
, rd
);
3927 handle_clz(s
, sf
, rn
, rd
);
3930 handle_cls(s
, sf
, rn
, rd
);
3935 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
3936 unsigned int rm
, unsigned int rn
, unsigned int rd
)
3938 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
3939 tcg_rd
= cpu_reg(s
, rd
);
3941 if (!sf
&& is_signed
) {
3942 tcg_n
= new_tmp_a64(s
);
3943 tcg_m
= new_tmp_a64(s
);
3944 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
3945 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
3947 tcg_n
= read_cpu_reg(s
, rn
, sf
);
3948 tcg_m
= read_cpu_reg(s
, rm
, sf
);
3952 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
3954 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
3957 if (!sf
) { /* zero extend final result */
3958 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3962 /* C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV */
3963 static void handle_shift_reg(DisasContext
*s
,
3964 enum a64_shift_type shift_type
, unsigned int sf
,
3965 unsigned int rm
, unsigned int rn
, unsigned int rd
)
3967 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
3968 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3969 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3971 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
3972 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
3973 tcg_temp_free_i64(tcg_shift
);
3976 /* CRC32[BHWX], CRC32C[BHWX] */
3977 static void handle_crc32(DisasContext
*s
,
3978 unsigned int sf
, unsigned int sz
, bool crc32c
,
3979 unsigned int rm
, unsigned int rn
, unsigned int rd
)
3981 TCGv_i64 tcg_acc
, tcg_val
;
3984 if (!arm_dc_feature(s
, ARM_FEATURE_CRC
)
3985 || (sf
== 1 && sz
!= 3)
3986 || (sf
== 0 && sz
== 3)) {
3987 unallocated_encoding(s
);
3992 tcg_val
= cpu_reg(s
, rm
);
4006 g_assert_not_reached();
4008 tcg_val
= new_tmp_a64(s
);
4009 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
4012 tcg_acc
= cpu_reg(s
, rn
);
4013 tcg_bytes
= tcg_const_i32(1 << sz
);
4016 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
4018 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
4021 tcg_temp_free_i32(tcg_bytes
);
4024 /* C3.5.8 Data-processing (2 source)
4025 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4026 * +----+---+---+-----------------+------+--------+------+------+
4027 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
4028 * +----+---+---+-----------------+------+--------+------+------+
4030 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
4032 unsigned int sf
, rm
, opcode
, rn
, rd
;
4033 sf
= extract32(insn
, 31, 1);
4034 rm
= extract32(insn
, 16, 5);
4035 opcode
= extract32(insn
, 10, 6);
4036 rn
= extract32(insn
, 5, 5);
4037 rd
= extract32(insn
, 0, 5);
4039 if (extract32(insn
, 29, 1)) {
4040 unallocated_encoding(s
);
4046 handle_div(s
, false, sf
, rm
, rn
, rd
);
4049 handle_div(s
, true, sf
, rm
, rn
, rd
);
4052 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
4055 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
4058 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
4061 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
4070 case 23: /* CRC32 */
4072 int sz
= extract32(opcode
, 0, 2);
4073 bool crc32c
= extract32(opcode
, 2, 1);
4074 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
4078 unallocated_encoding(s
);
4083 /* C3.5 Data processing - register */
4084 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
4086 switch (extract32(insn
, 24, 5)) {
4087 case 0x0a: /* Logical (shifted register) */
4088 disas_logic_reg(s
, insn
);
4090 case 0x0b: /* Add/subtract */
4091 if (insn
& (1 << 21)) { /* (extended register) */
4092 disas_add_sub_ext_reg(s
, insn
);
4094 disas_add_sub_reg(s
, insn
);
4097 case 0x1b: /* Data-processing (3 source) */
4098 disas_data_proc_3src(s
, insn
);
4101 switch (extract32(insn
, 21, 3)) {
4102 case 0x0: /* Add/subtract (with carry) */
4103 disas_adc_sbc(s
, insn
);
4105 case 0x2: /* Conditional compare */
4106 disas_cc(s
, insn
); /* both imm and reg forms */
4108 case 0x4: /* Conditional select */
4109 disas_cond_select(s
, insn
);
4111 case 0x6: /* Data-processing */
4112 if (insn
& (1 << 30)) { /* (1 source) */
4113 disas_data_proc_1src(s
, insn
);
4114 } else { /* (2 source) */
4115 disas_data_proc_2src(s
, insn
);
4119 unallocated_encoding(s
);
4124 unallocated_encoding(s
);
4129 static void handle_fp_compare(DisasContext
*s
, bool is_double
,
4130 unsigned int rn
, unsigned int rm
,
4131 bool cmp_with_zero
, bool signal_all_nans
)
4133 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
4134 TCGv_ptr fpst
= get_fpstatus_ptr();
4137 TCGv_i64 tcg_vn
, tcg_vm
;
4139 tcg_vn
= read_fp_dreg(s
, rn
);
4140 if (cmp_with_zero
) {
4141 tcg_vm
= tcg_const_i64(0);
4143 tcg_vm
= read_fp_dreg(s
, rm
);
4145 if (signal_all_nans
) {
4146 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4148 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4150 tcg_temp_free_i64(tcg_vn
);
4151 tcg_temp_free_i64(tcg_vm
);
4153 TCGv_i32 tcg_vn
, tcg_vm
;
4155 tcg_vn
= read_fp_sreg(s
, rn
);
4156 if (cmp_with_zero
) {
4157 tcg_vm
= tcg_const_i32(0);
4159 tcg_vm
= read_fp_sreg(s
, rm
);
4161 if (signal_all_nans
) {
4162 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4164 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4166 tcg_temp_free_i32(tcg_vn
);
4167 tcg_temp_free_i32(tcg_vm
);
4170 tcg_temp_free_ptr(fpst
);
4172 gen_set_nzcv(tcg_flags
);
4174 tcg_temp_free_i64(tcg_flags
);
4177 /* C3.6.22 Floating point compare
4178 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
4179 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4180 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
4181 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4183 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
4185 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
4187 mos
= extract32(insn
, 29, 3);
4188 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4189 rm
= extract32(insn
, 16, 5);
4190 op
= extract32(insn
, 14, 2);
4191 rn
= extract32(insn
, 5, 5);
4192 opc
= extract32(insn
, 3, 2);
4193 op2r
= extract32(insn
, 0, 3);
4195 if (mos
|| op
|| op2r
|| type
> 1) {
4196 unallocated_encoding(s
);
4200 if (!fp_access_check(s
)) {
4204 handle_fp_compare(s
, type
, rn
, rm
, opc
& 1, opc
& 2);
4207 /* C3.6.23 Floating point conditional compare
4208 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4209 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4210 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
4211 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4213 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
4215 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
4217 TCGLabel
*label_continue
= NULL
;
4219 mos
= extract32(insn
, 29, 3);
4220 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4221 rm
= extract32(insn
, 16, 5);
4222 cond
= extract32(insn
, 12, 4);
4223 rn
= extract32(insn
, 5, 5);
4224 op
= extract32(insn
, 4, 1);
4225 nzcv
= extract32(insn
, 0, 4);
4227 if (mos
|| type
> 1) {
4228 unallocated_encoding(s
);
4232 if (!fp_access_check(s
)) {
4236 if (cond
< 0x0e) { /* not always */
4237 TCGLabel
*label_match
= gen_new_label();
4238 label_continue
= gen_new_label();
4239 arm_gen_test_cc(cond
, label_match
);
4241 tcg_flags
= tcg_const_i64(nzcv
<< 28);
4242 gen_set_nzcv(tcg_flags
);
4243 tcg_temp_free_i64(tcg_flags
);
4244 tcg_gen_br(label_continue
);
4245 gen_set_label(label_match
);
4248 handle_fp_compare(s
, type
, rn
, rm
, false, op
);
4251 gen_set_label(label_continue
);
4255 /* C3.6.24 Floating point conditional select
4256 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4257 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4258 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
4259 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4261 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
4263 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
4264 TCGv_i64 t_true
, t_false
, t_zero
;
4267 mos
= extract32(insn
, 29, 3);
4268 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4269 rm
= extract32(insn
, 16, 5);
4270 cond
= extract32(insn
, 12, 4);
4271 rn
= extract32(insn
, 5, 5);
4272 rd
= extract32(insn
, 0, 5);
4274 if (mos
|| type
> 1) {
4275 unallocated_encoding(s
);
4279 if (!fp_access_check(s
)) {
4283 /* Zero extend sreg inputs to 64 bits now. */
4284 t_true
= tcg_temp_new_i64();
4285 t_false
= tcg_temp_new_i64();
4286 read_vec_element(s
, t_true
, rn
, 0, type
? MO_64
: MO_32
);
4287 read_vec_element(s
, t_false
, rm
, 0, type
? MO_64
: MO_32
);
4289 a64_test_cc(&c
, cond
);
4290 t_zero
= tcg_const_i64(0);
4291 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
4292 tcg_temp_free_i64(t_zero
);
4293 tcg_temp_free_i64(t_false
);
4296 /* Note that sregs write back zeros to the high bits,
4297 and we've already done the zero-extension. */
4298 write_fp_dreg(s
, rd
, t_true
);
4299 tcg_temp_free_i64(t_true
);
4302 /* C3.6.25 Floating-point data-processing (1 source) - single precision */
4303 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
4309 fpst
= get_fpstatus_ptr();
4310 tcg_op
= read_fp_sreg(s
, rn
);
4311 tcg_res
= tcg_temp_new_i32();
4314 case 0x0: /* FMOV */
4315 tcg_gen_mov_i32(tcg_res
, tcg_op
);
4317 case 0x1: /* FABS */
4318 gen_helper_vfp_abss(tcg_res
, tcg_op
);
4320 case 0x2: /* FNEG */
4321 gen_helper_vfp_negs(tcg_res
, tcg_op
);
4323 case 0x3: /* FSQRT */
4324 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
4326 case 0x8: /* FRINTN */
4327 case 0x9: /* FRINTP */
4328 case 0xa: /* FRINTM */
4329 case 0xb: /* FRINTZ */
4330 case 0xc: /* FRINTA */
4332 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4334 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4335 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
4337 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4338 tcg_temp_free_i32(tcg_rmode
);
4341 case 0xe: /* FRINTX */
4342 gen_helper_rints_exact(tcg_res
, tcg_op
, fpst
);
4344 case 0xf: /* FRINTI */
4345 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
4351 write_fp_sreg(s
, rd
, tcg_res
);
4353 tcg_temp_free_ptr(fpst
);
4354 tcg_temp_free_i32(tcg_op
);
4355 tcg_temp_free_i32(tcg_res
);
4358 /* C3.6.25 Floating-point data-processing (1 source) - double precision */
4359 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
4365 fpst
= get_fpstatus_ptr();
4366 tcg_op
= read_fp_dreg(s
, rn
);
4367 tcg_res
= tcg_temp_new_i64();
4370 case 0x0: /* FMOV */
4371 tcg_gen_mov_i64(tcg_res
, tcg_op
);
4373 case 0x1: /* FABS */
4374 gen_helper_vfp_absd(tcg_res
, tcg_op
);
4376 case 0x2: /* FNEG */
4377 gen_helper_vfp_negd(tcg_res
, tcg_op
);
4379 case 0x3: /* FSQRT */
4380 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
4382 case 0x8: /* FRINTN */
4383 case 0x9: /* FRINTP */
4384 case 0xa: /* FRINTM */
4385 case 0xb: /* FRINTZ */
4386 case 0xc: /* FRINTA */
4388 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4390 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4391 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4393 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4394 tcg_temp_free_i32(tcg_rmode
);
4397 case 0xe: /* FRINTX */
4398 gen_helper_rintd_exact(tcg_res
, tcg_op
, fpst
);
4400 case 0xf: /* FRINTI */
4401 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4407 write_fp_dreg(s
, rd
, tcg_res
);
4409 tcg_temp_free_ptr(fpst
);
4410 tcg_temp_free_i64(tcg_op
);
4411 tcg_temp_free_i64(tcg_res
);
4414 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
4415 int rd
, int rn
, int dtype
, int ntype
)
4420 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4422 /* Single to double */
4423 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4424 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
4425 write_fp_dreg(s
, rd
, tcg_rd
);
4426 tcg_temp_free_i64(tcg_rd
);
4428 /* Single to half */
4429 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4430 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4431 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4432 write_fp_sreg(s
, rd
, tcg_rd
);
4433 tcg_temp_free_i32(tcg_rd
);
4435 tcg_temp_free_i32(tcg_rn
);
4440 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
4441 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4443 /* Double to single */
4444 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
4446 /* Double to half */
4447 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4448 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4450 write_fp_sreg(s
, rd
, tcg_rd
);
4451 tcg_temp_free_i32(tcg_rd
);
4452 tcg_temp_free_i64(tcg_rn
);
4457 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4458 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
4460 /* Half to single */
4461 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4462 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, cpu_env
);
4463 write_fp_sreg(s
, rd
, tcg_rd
);
4464 tcg_temp_free_i32(tcg_rd
);
4466 /* Half to double */
4467 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4468 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, cpu_env
);
4469 write_fp_dreg(s
, rd
, tcg_rd
);
4470 tcg_temp_free_i64(tcg_rd
);
4472 tcg_temp_free_i32(tcg_rn
);
4480 /* C3.6.25 Floating point data-processing (1 source)
4481 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
4482 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4483 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
4484 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4486 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
4488 int type
= extract32(insn
, 22, 2);
4489 int opcode
= extract32(insn
, 15, 6);
4490 int rn
= extract32(insn
, 5, 5);
4491 int rd
= extract32(insn
, 0, 5);
4494 case 0x4: case 0x5: case 0x7:
4496 /* FCVT between half, single and double precision */
4497 int dtype
= extract32(opcode
, 0, 2);
4498 if (type
== 2 || dtype
== type
) {
4499 unallocated_encoding(s
);
4502 if (!fp_access_check(s
)) {
4506 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
4512 /* 32-to-32 and 64-to-64 ops */
4515 if (!fp_access_check(s
)) {
4519 handle_fp_1src_single(s
, opcode
, rd
, rn
);
4522 if (!fp_access_check(s
)) {
4526 handle_fp_1src_double(s
, opcode
, rd
, rn
);
4529 unallocated_encoding(s
);
4533 unallocated_encoding(s
);
4538 /* C3.6.26 Floating-point data-processing (2 source) - single precision */
4539 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
4540 int rd
, int rn
, int rm
)
4547 tcg_res
= tcg_temp_new_i32();
4548 fpst
= get_fpstatus_ptr();
4549 tcg_op1
= read_fp_sreg(s
, rn
);
4550 tcg_op2
= read_fp_sreg(s
, rm
);
4553 case 0x0: /* FMUL */
4554 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4556 case 0x1: /* FDIV */
4557 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4559 case 0x2: /* FADD */
4560 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4562 case 0x3: /* FSUB */
4563 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4565 case 0x4: /* FMAX */
4566 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4568 case 0x5: /* FMIN */
4569 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4571 case 0x6: /* FMAXNM */
4572 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4574 case 0x7: /* FMINNM */
4575 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4577 case 0x8: /* FNMUL */
4578 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4579 gen_helper_vfp_negs(tcg_res
, tcg_res
);
4583 write_fp_sreg(s
, rd
, tcg_res
);
4585 tcg_temp_free_ptr(fpst
);
4586 tcg_temp_free_i32(tcg_op1
);
4587 tcg_temp_free_i32(tcg_op2
);
4588 tcg_temp_free_i32(tcg_res
);
4591 /* C3.6.26 Floating-point data-processing (2 source) - double precision */
4592 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
4593 int rd
, int rn
, int rm
)
4600 tcg_res
= tcg_temp_new_i64();
4601 fpst
= get_fpstatus_ptr();
4602 tcg_op1
= read_fp_dreg(s
, rn
);
4603 tcg_op2
= read_fp_dreg(s
, rm
);
4606 case 0x0: /* FMUL */
4607 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4609 case 0x1: /* FDIV */
4610 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4612 case 0x2: /* FADD */
4613 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4615 case 0x3: /* FSUB */
4616 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4618 case 0x4: /* FMAX */
4619 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4621 case 0x5: /* FMIN */
4622 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4624 case 0x6: /* FMAXNM */
4625 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4627 case 0x7: /* FMINNM */
4628 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4630 case 0x8: /* FNMUL */
4631 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4632 gen_helper_vfp_negd(tcg_res
, tcg_res
);
4636 write_fp_dreg(s
, rd
, tcg_res
);
4638 tcg_temp_free_ptr(fpst
);
4639 tcg_temp_free_i64(tcg_op1
);
4640 tcg_temp_free_i64(tcg_op2
);
4641 tcg_temp_free_i64(tcg_res
);
4644 /* C3.6.26 Floating point data-processing (2 source)
4645 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4646 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4647 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
4648 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4650 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
4652 int type
= extract32(insn
, 22, 2);
4653 int rd
= extract32(insn
, 0, 5);
4654 int rn
= extract32(insn
, 5, 5);
4655 int rm
= extract32(insn
, 16, 5);
4656 int opcode
= extract32(insn
, 12, 4);
4659 unallocated_encoding(s
);
4665 if (!fp_access_check(s
)) {
4668 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
4671 if (!fp_access_check(s
)) {
4674 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
4677 unallocated_encoding(s
);
4681 /* C3.6.27 Floating-point data-processing (3 source) - single precision */
4682 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
4683 int rd
, int rn
, int rm
, int ra
)
4685 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
4686 TCGv_i32 tcg_res
= tcg_temp_new_i32();
4687 TCGv_ptr fpst
= get_fpstatus_ptr();
4689 tcg_op1
= read_fp_sreg(s
, rn
);
4690 tcg_op2
= read_fp_sreg(s
, rm
);
4691 tcg_op3
= read_fp_sreg(s
, ra
);
4693 /* These are fused multiply-add, and must be done as one
4694 * floating point operation with no rounding between the
4695 * multiplication and addition steps.
4696 * NB that doing the negations here as separate steps is
4697 * correct : an input NaN should come out with its sign bit
4698 * flipped if it is a negated-input.
4701 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
4705 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
4708 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4710 write_fp_sreg(s
, rd
, tcg_res
);
4712 tcg_temp_free_ptr(fpst
);
4713 tcg_temp_free_i32(tcg_op1
);
4714 tcg_temp_free_i32(tcg_op2
);
4715 tcg_temp_free_i32(tcg_op3
);
4716 tcg_temp_free_i32(tcg_res
);
4719 /* C3.6.27 Floating-point data-processing (3 source) - double precision */
4720 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
4721 int rd
, int rn
, int rm
, int ra
)
4723 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
4724 TCGv_i64 tcg_res
= tcg_temp_new_i64();
4725 TCGv_ptr fpst
= get_fpstatus_ptr();
4727 tcg_op1
= read_fp_dreg(s
, rn
);
4728 tcg_op2
= read_fp_dreg(s
, rm
);
4729 tcg_op3
= read_fp_dreg(s
, ra
);
4731 /* These are fused multiply-add, and must be done as one
4732 * floating point operation with no rounding between the
4733 * multiplication and addition steps.
4734 * NB that doing the negations here as separate steps is
4735 * correct : an input NaN should come out with its sign bit
4736 * flipped if it is a negated-input.
4739 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
4743 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
4746 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4748 write_fp_dreg(s
, rd
, tcg_res
);
4750 tcg_temp_free_ptr(fpst
);
4751 tcg_temp_free_i64(tcg_op1
);
4752 tcg_temp_free_i64(tcg_op2
);
4753 tcg_temp_free_i64(tcg_op3
);
4754 tcg_temp_free_i64(tcg_res
);
4757 /* C3.6.27 Floating point data-processing (3 source)
4758 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
4759 * +---+---+---+-----------+------+----+------+----+------+------+------+
4760 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
4761 * +---+---+---+-----------+------+----+------+----+------+------+------+
4763 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
4765 int type
= extract32(insn
, 22, 2);
4766 int rd
= extract32(insn
, 0, 5);
4767 int rn
= extract32(insn
, 5, 5);
4768 int ra
= extract32(insn
, 10, 5);
4769 int rm
= extract32(insn
, 16, 5);
4770 bool o0
= extract32(insn
, 15, 1);
4771 bool o1
= extract32(insn
, 21, 1);
4775 if (!fp_access_check(s
)) {
4778 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4781 if (!fp_access_check(s
)) {
4784 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4787 unallocated_encoding(s
);
4791 /* C3.6.28 Floating point immediate
4792 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
4793 * +---+---+---+-----------+------+---+------------+-------+------+------+
4794 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
4795 * +---+---+---+-----------+------+---+------------+-------+------+------+
4797 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
4799 int rd
= extract32(insn
, 0, 5);
4800 int imm8
= extract32(insn
, 13, 8);
4801 int is_double
= extract32(insn
, 22, 2);
4805 if (is_double
> 1) {
4806 unallocated_encoding(s
);
4810 if (!fp_access_check(s
)) {
4814 /* The imm8 encodes the sign bit, enough bits to represent
4815 * an exponent in the range 01....1xx to 10....0xx,
4816 * and the most significant 4 bits of the mantissa; see
4817 * VFPExpandImm() in the v8 ARM ARM.
4820 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
4821 (extract32(imm8
, 6, 1) ? 0x3fc0 : 0x4000) |
4822 extract32(imm8
, 0, 6);
4825 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
4826 (extract32(imm8
, 6, 1) ? 0x3e00 : 0x4000) |
4827 (extract32(imm8
, 0, 6) << 3);
4831 tcg_res
= tcg_const_i64(imm
);
4832 write_fp_dreg(s
, rd
, tcg_res
);
4833 tcg_temp_free_i64(tcg_res
);
4836 /* Handle floating point <=> fixed point conversions. Note that we can
4837 * also deal with fp <=> integer conversions as a special case (scale == 64)
4838 * OPTME: consider handling that special case specially or at least skipping
4839 * the call to scalbn in the helpers for zero shifts.
4841 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
4842 bool itof
, int rmode
, int scale
, int sf
, int type
)
4844 bool is_signed
= !(opcode
& 1);
4845 bool is_double
= type
;
4846 TCGv_ptr tcg_fpstatus
;
4849 tcg_fpstatus
= get_fpstatus_ptr();
4851 tcg_shift
= tcg_const_i32(64 - scale
);
4854 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
4856 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
4859 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
4861 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
4864 tcg_int
= tcg_extend
;
4868 TCGv_i64 tcg_double
= tcg_temp_new_i64();
4870 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
4871 tcg_shift
, tcg_fpstatus
);
4873 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
4874 tcg_shift
, tcg_fpstatus
);
4876 write_fp_dreg(s
, rd
, tcg_double
);
4877 tcg_temp_free_i64(tcg_double
);
4879 TCGv_i32 tcg_single
= tcg_temp_new_i32();
4881 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
4882 tcg_shift
, tcg_fpstatus
);
4884 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
4885 tcg_shift
, tcg_fpstatus
);
4887 write_fp_sreg(s
, rd
, tcg_single
);
4888 tcg_temp_free_i32(tcg_single
);
4891 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
4894 if (extract32(opcode
, 2, 1)) {
4895 /* There are too many rounding modes to all fit into rmode,
4896 * so FCVTA[US] is a special case.
4898 rmode
= FPROUNDING_TIEAWAY
;
4901 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
4903 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4906 TCGv_i64 tcg_double
= read_fp_dreg(s
, rn
);
4909 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
4910 tcg_shift
, tcg_fpstatus
);
4912 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
4913 tcg_shift
, tcg_fpstatus
);
4917 gen_helper_vfp_tould(tcg_int
, tcg_double
,
4918 tcg_shift
, tcg_fpstatus
);
4920 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
4921 tcg_shift
, tcg_fpstatus
);
4924 tcg_temp_free_i64(tcg_double
);
4926 TCGv_i32 tcg_single
= read_fp_sreg(s
, rn
);
4929 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
4930 tcg_shift
, tcg_fpstatus
);
4932 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
4933 tcg_shift
, tcg_fpstatus
);
4936 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
4938 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
4939 tcg_shift
, tcg_fpstatus
);
4941 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
4942 tcg_shift
, tcg_fpstatus
);
4944 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
4945 tcg_temp_free_i32(tcg_dest
);
4947 tcg_temp_free_i32(tcg_single
);
4950 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4951 tcg_temp_free_i32(tcg_rmode
);
4954 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
4958 tcg_temp_free_ptr(tcg_fpstatus
);
4959 tcg_temp_free_i32(tcg_shift
);
4962 /* C3.6.29 Floating point <-> fixed point conversions
4963 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
4964 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
4965 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
4966 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
4968 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
4970 int rd
= extract32(insn
, 0, 5);
4971 int rn
= extract32(insn
, 5, 5);
4972 int scale
= extract32(insn
, 10, 6);
4973 int opcode
= extract32(insn
, 16, 3);
4974 int rmode
= extract32(insn
, 19, 2);
4975 int type
= extract32(insn
, 22, 2);
4976 bool sbit
= extract32(insn
, 29, 1);
4977 bool sf
= extract32(insn
, 31, 1);
4980 if (sbit
|| (type
> 1)
4981 || (!sf
&& scale
< 32)) {
4982 unallocated_encoding(s
);
4986 switch ((rmode
<< 3) | opcode
) {
4987 case 0x2: /* SCVTF */
4988 case 0x3: /* UCVTF */
4991 case 0x18: /* FCVTZS */
4992 case 0x19: /* FCVTZU */
4996 unallocated_encoding(s
);
5000 if (!fp_access_check(s
)) {
5004 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
5007 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
5009 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
5010 * without conversion.
5014 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
5020 TCGv_i64 tmp
= tcg_temp_new_i64();
5021 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
5022 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_offset(s
, rd
, MO_64
));
5023 tcg_gen_movi_i64(tmp
, 0);
5024 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5025 tcg_temp_free_i64(tmp
);
5031 TCGv_i64 tmp
= tcg_const_i64(0);
5032 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_offset(s
, rd
, MO_64
));
5033 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5034 tcg_temp_free_i64(tmp
);
5038 /* 64 bit to top half. */
5039 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5043 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5048 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
5052 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
5055 /* 64 bits from top half */
5056 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
5062 /* C3.6.30 Floating point <-> integer conversions
5063 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
5064 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
5065 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
5066 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
5068 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
5070 int rd
= extract32(insn
, 0, 5);
5071 int rn
= extract32(insn
, 5, 5);
5072 int opcode
= extract32(insn
, 16, 3);
5073 int rmode
= extract32(insn
, 19, 2);
5074 int type
= extract32(insn
, 22, 2);
5075 bool sbit
= extract32(insn
, 29, 1);
5076 bool sf
= extract32(insn
, 31, 1);
5079 unallocated_encoding(s
);
5085 bool itof
= opcode
& 1;
5088 unallocated_encoding(s
);
5092 switch (sf
<< 3 | type
<< 1 | rmode
) {
5093 case 0x0: /* 32 bit */
5094 case 0xa: /* 64 bit */
5095 case 0xd: /* 64 bit to top half of quad */
5098 /* all other sf/type/rmode combinations are invalid */
5099 unallocated_encoding(s
);
5103 if (!fp_access_check(s
)) {
5106 handle_fmov(s
, rd
, rn
, type
, itof
);
5108 /* actual FP conversions */
5109 bool itof
= extract32(opcode
, 1, 1);
5111 if (type
> 1 || (rmode
!= 0 && opcode
> 1)) {
5112 unallocated_encoding(s
);
5116 if (!fp_access_check(s
)) {
5119 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
5123 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
5124 * 31 30 29 28 25 24 0
5125 * +---+---+---+---------+-----------------------------+
5126 * | | 0 | | 1 1 1 1 | |
5127 * +---+---+---+---------+-----------------------------+
5129 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
5131 if (extract32(insn
, 24, 1)) {
5132 /* Floating point data-processing (3 source) */
5133 disas_fp_3src(s
, insn
);
5134 } else if (extract32(insn
, 21, 1) == 0) {
5135 /* Floating point to fixed point conversions */
5136 disas_fp_fixed_conv(s
, insn
);
5138 switch (extract32(insn
, 10, 2)) {
5140 /* Floating point conditional compare */
5141 disas_fp_ccomp(s
, insn
);
5144 /* Floating point data-processing (2 source) */
5145 disas_fp_2src(s
, insn
);
5148 /* Floating point conditional select */
5149 disas_fp_csel(s
, insn
);
5152 switch (ctz32(extract32(insn
, 12, 4))) {
5153 case 0: /* [15:12] == xxx1 */
5154 /* Floating point immediate */
5155 disas_fp_imm(s
, insn
);
5157 case 1: /* [15:12] == xx10 */
5158 /* Floating point compare */
5159 disas_fp_compare(s
, insn
);
5161 case 2: /* [15:12] == x100 */
5162 /* Floating point data-processing (1 source) */
5163 disas_fp_1src(s
, insn
);
5165 case 3: /* [15:12] == 1000 */
5166 unallocated_encoding(s
);
5168 default: /* [15:12] == 0000 */
5169 /* Floating point <-> integer conversions */
5170 disas_fp_int_conv(s
, insn
);
5178 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
5181 /* Extract 64 bits from the middle of two concatenated 64 bit
5182 * vector register slices left:right. The extracted bits start
5183 * at 'pos' bits into the right (least significant) side.
5184 * We return the result in tcg_right, and guarantee not to
5187 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
5188 assert(pos
> 0 && pos
< 64);
5190 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
5191 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
5192 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
5194 tcg_temp_free_i64(tcg_tmp
);
5198 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
5199 * +---+---+-------------+-----+---+------+---+------+---+------+------+
5200 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
5201 * +---+---+-------------+-----+---+------+---+------+---+------+------+
5203 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
5205 int is_q
= extract32(insn
, 30, 1);
5206 int op2
= extract32(insn
, 22, 2);
5207 int imm4
= extract32(insn
, 11, 4);
5208 int rm
= extract32(insn
, 16, 5);
5209 int rn
= extract32(insn
, 5, 5);
5210 int rd
= extract32(insn
, 0, 5);
5211 int pos
= imm4
<< 3;
5212 TCGv_i64 tcg_resl
, tcg_resh
;
5214 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
5215 unallocated_encoding(s
);
5219 if (!fp_access_check(s
)) {
5223 tcg_resh
= tcg_temp_new_i64();
5224 tcg_resl
= tcg_temp_new_i64();
5226 /* Vd gets bits starting at pos bits into Vm:Vn. This is
5227 * either extracting 128 bits from a 128:128 concatenation, or
5228 * extracting 64 bits from a 64:64 concatenation.
5231 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
5233 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
5234 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
5236 tcg_gen_movi_i64(tcg_resh
, 0);
5243 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
5244 EltPosns
*elt
= eltposns
;
5251 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
5253 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
5256 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
5257 tcg_hh
= tcg_temp_new_i64();
5258 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
5259 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
5260 tcg_temp_free_i64(tcg_hh
);
5264 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5265 tcg_temp_free_i64(tcg_resl
);
5266 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5267 tcg_temp_free_i64(tcg_resh
);
5271 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
5272 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5273 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
5274 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5276 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
5278 int op2
= extract32(insn
, 22, 2);
5279 int is_q
= extract32(insn
, 30, 1);
5280 int rm
= extract32(insn
, 16, 5);
5281 int rn
= extract32(insn
, 5, 5);
5282 int rd
= extract32(insn
, 0, 5);
5283 int is_tblx
= extract32(insn
, 12, 1);
5284 int len
= extract32(insn
, 13, 2);
5285 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
5286 TCGv_i32 tcg_regno
, tcg_numregs
;
5289 unallocated_encoding(s
);
5293 if (!fp_access_check(s
)) {
5297 /* This does a table lookup: for every byte element in the input
5298 * we index into a table formed from up to four vector registers,
5299 * and then the output is the result of the lookups. Our helper
5300 * function does the lookup operation for a single 64 bit part of
5303 tcg_resl
= tcg_temp_new_i64();
5304 tcg_resh
= tcg_temp_new_i64();
5307 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5309 tcg_gen_movi_i64(tcg_resl
, 0);
5311 if (is_tblx
&& is_q
) {
5312 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5314 tcg_gen_movi_i64(tcg_resh
, 0);
5317 tcg_idx
= tcg_temp_new_i64();
5318 tcg_regno
= tcg_const_i32(rn
);
5319 tcg_numregs
= tcg_const_i32(len
+ 1);
5320 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
5321 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
5322 tcg_regno
, tcg_numregs
);
5324 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
5325 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
5326 tcg_regno
, tcg_numregs
);
5328 tcg_temp_free_i64(tcg_idx
);
5329 tcg_temp_free_i32(tcg_regno
);
5330 tcg_temp_free_i32(tcg_numregs
);
5332 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5333 tcg_temp_free_i64(tcg_resl
);
5334 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5335 tcg_temp_free_i64(tcg_resh
);
5338 /* C3.6.3 ZIP/UZP/TRN
5339 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
5340 * +---+---+-------------+------+---+------+---+------------------+------+
5341 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
5342 * +---+---+-------------+------+---+------+---+------------------+------+
5344 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
5346 int rd
= extract32(insn
, 0, 5);
5347 int rn
= extract32(insn
, 5, 5);
5348 int rm
= extract32(insn
, 16, 5);
5349 int size
= extract32(insn
, 22, 2);
5350 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
5351 * bit 2 indicates 1 vs 2 variant of the insn.
5353 int opcode
= extract32(insn
, 12, 2);
5354 bool part
= extract32(insn
, 14, 1);
5355 bool is_q
= extract32(insn
, 30, 1);
5356 int esize
= 8 << size
;
5358 int datasize
= is_q
? 128 : 64;
5359 int elements
= datasize
/ esize
;
5360 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
5362 if (opcode
== 0 || (size
== 3 && !is_q
)) {
5363 unallocated_encoding(s
);
5367 if (!fp_access_check(s
)) {
5371 tcg_resl
= tcg_const_i64(0);
5372 tcg_resh
= tcg_const_i64(0);
5373 tcg_res
= tcg_temp_new_i64();
5375 for (i
= 0; i
< elements
; i
++) {
5377 case 1: /* UZP1/2 */
5379 int midpoint
= elements
/ 2;
5381 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
5383 read_vec_element(s
, tcg_res
, rm
,
5384 2 * (i
- midpoint
) + part
, size
);
5388 case 2: /* TRN1/2 */
5390 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
5392 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
5395 case 3: /* ZIP1/2 */
5397 int base
= part
* elements
/ 2;
5399 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
5401 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
5406 g_assert_not_reached();
5411 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
5412 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
5414 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
5415 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
5419 tcg_temp_free_i64(tcg_res
);
5421 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5422 tcg_temp_free_i64(tcg_resl
);
5423 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5424 tcg_temp_free_i64(tcg_resh
);
5427 static void do_minmaxop(DisasContext
*s
, TCGv_i32 tcg_elt1
, TCGv_i32 tcg_elt2
,
5428 int opc
, bool is_min
, TCGv_ptr fpst
)
5430 /* Helper function for disas_simd_across_lanes: do a single precision
5431 * min/max operation on the specified two inputs,
5432 * and return the result in tcg_elt1.
5436 gen_helper_vfp_minnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5438 gen_helper_vfp_maxnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5443 gen_helper_vfp_mins(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5445 gen_helper_vfp_maxs(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5450 /* C3.6.4 AdvSIMD across lanes
5451 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
5452 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5453 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
5454 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5456 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
5458 int rd
= extract32(insn
, 0, 5);
5459 int rn
= extract32(insn
, 5, 5);
5460 int size
= extract32(insn
, 22, 2);
5461 int opcode
= extract32(insn
, 12, 5);
5462 bool is_q
= extract32(insn
, 30, 1);
5463 bool is_u
= extract32(insn
, 29, 1);
5465 bool is_min
= false;
5469 TCGv_i64 tcg_res
, tcg_elt
;
5472 case 0x1b: /* ADDV */
5474 unallocated_encoding(s
);
5478 case 0x3: /* SADDLV, UADDLV */
5479 case 0xa: /* SMAXV, UMAXV */
5480 case 0x1a: /* SMINV, UMINV */
5481 if (size
== 3 || (size
== 2 && !is_q
)) {
5482 unallocated_encoding(s
);
5486 case 0xc: /* FMAXNMV, FMINNMV */
5487 case 0xf: /* FMAXV, FMINV */
5488 if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
5489 unallocated_encoding(s
);
5492 /* Bit 1 of size field encodes min vs max, and actual size is always
5493 * 32 bits: adjust the size variable so following code can rely on it
5495 is_min
= extract32(size
, 1, 1);
5500 unallocated_encoding(s
);
5504 if (!fp_access_check(s
)) {
5509 elements
= (is_q
? 128 : 64) / esize
;
5511 tcg_res
= tcg_temp_new_i64();
5512 tcg_elt
= tcg_temp_new_i64();
5514 /* These instructions operate across all lanes of a vector
5515 * to produce a single result. We can guarantee that a 64
5516 * bit intermediate is sufficient:
5517 * + for [US]ADDLV the maximum element size is 32 bits, and
5518 * the result type is 64 bits
5519 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
5520 * same as the element size, which is 32 bits at most
5521 * For the integer operations we can choose to work at 64
5522 * or 32 bits and truncate at the end; for simplicity
5523 * we use 64 bits always. The floating point
5524 * ops do require 32 bit intermediates, though.
5527 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
5529 for (i
= 1; i
< elements
; i
++) {
5530 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
5533 case 0x03: /* SADDLV / UADDLV */
5534 case 0x1b: /* ADDV */
5535 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
5537 case 0x0a: /* SMAXV / UMAXV */
5538 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
5540 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5542 case 0x1a: /* SMINV / UMINV */
5543 tcg_gen_movcond_i64(is_u
? TCG_COND_LEU
: TCG_COND_LE
,
5545 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5549 g_assert_not_reached();
5554 /* Floating point ops which work on 32 bit (single) intermediates.
5555 * Note that correct NaN propagation requires that we do these
5556 * operations in exactly the order specified by the pseudocode.
5558 TCGv_i32 tcg_elt1
= tcg_temp_new_i32();
5559 TCGv_i32 tcg_elt2
= tcg_temp_new_i32();
5560 TCGv_i32 tcg_elt3
= tcg_temp_new_i32();
5561 TCGv_ptr fpst
= get_fpstatus_ptr();
5563 assert(esize
== 32);
5564 assert(elements
== 4);
5566 read_vec_element(s
, tcg_elt
, rn
, 0, MO_32
);
5567 tcg_gen_extrl_i64_i32(tcg_elt1
, tcg_elt
);
5568 read_vec_element(s
, tcg_elt
, rn
, 1, MO_32
);
5569 tcg_gen_extrl_i64_i32(tcg_elt2
, tcg_elt
);
5571 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5573 read_vec_element(s
, tcg_elt
, rn
, 2, MO_32
);
5574 tcg_gen_extrl_i64_i32(tcg_elt2
, tcg_elt
);
5575 read_vec_element(s
, tcg_elt
, rn
, 3, MO_32
);
5576 tcg_gen_extrl_i64_i32(tcg_elt3
, tcg_elt
);
5578 do_minmaxop(s
, tcg_elt2
, tcg_elt3
, opcode
, is_min
, fpst
);
5580 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5582 tcg_gen_extu_i32_i64(tcg_res
, tcg_elt1
);
5583 tcg_temp_free_i32(tcg_elt1
);
5584 tcg_temp_free_i32(tcg_elt2
);
5585 tcg_temp_free_i32(tcg_elt3
);
5586 tcg_temp_free_ptr(fpst
);
5589 tcg_temp_free_i64(tcg_elt
);
5591 /* Now truncate the result to the width required for the final output */
5592 if (opcode
== 0x03) {
5593 /* SADDLV, UADDLV: result is 2*esize */
5599 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
5602 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
5605 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
5610 g_assert_not_reached();
5613 write_fp_dreg(s
, rd
, tcg_res
);
5614 tcg_temp_free_i64(tcg_res
);
5617 /* C6.3.31 DUP (Element, Vector)
5619 * 31 30 29 21 20 16 15 10 9 5 4 0
5620 * +---+---+-------------------+--------+-------------+------+------+
5621 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5622 * +---+---+-------------------+--------+-------------+------+------+
5624 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5626 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
5629 int size
= ctz32(imm5
);
5630 int esize
= 8 << size
;
5631 int elements
= (is_q
? 128 : 64) / esize
;
5635 if (size
> 3 || (size
== 3 && !is_q
)) {
5636 unallocated_encoding(s
);
5640 if (!fp_access_check(s
)) {
5644 index
= imm5
>> (size
+ 1);
5646 tmp
= tcg_temp_new_i64();
5647 read_vec_element(s
, tmp
, rn
, index
, size
);
5649 for (i
= 0; i
< elements
; i
++) {
5650 write_vec_element(s
, tmp
, rd
, i
, size
);
5654 clear_vec_high(s
, rd
);
5657 tcg_temp_free_i64(tmp
);
5660 /* C6.3.31 DUP (element, scalar)
5661 * 31 21 20 16 15 10 9 5 4 0
5662 * +-----------------------+--------+-------------+------+------+
5663 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5664 * +-----------------------+--------+-------------+------+------+
5666 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
5669 int size
= ctz32(imm5
);
5674 unallocated_encoding(s
);
5678 if (!fp_access_check(s
)) {
5682 index
= imm5
>> (size
+ 1);
5684 /* This instruction just extracts the specified element and
5685 * zero-extends it into the bottom of the destination register.
5687 tmp
= tcg_temp_new_i64();
5688 read_vec_element(s
, tmp
, rn
, index
, size
);
5689 write_fp_dreg(s
, rd
, tmp
);
5690 tcg_temp_free_i64(tmp
);
5693 /* C6.3.32 DUP (General)
5695 * 31 30 29 21 20 16 15 10 9 5 4 0
5696 * +---+---+-------------------+--------+-------------+------+------+
5697 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
5698 * +---+---+-------------------+--------+-------------+------+------+
5700 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5702 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
5705 int size
= ctz32(imm5
);
5706 int esize
= 8 << size
;
5707 int elements
= (is_q
? 128 : 64)/esize
;
5710 if (size
> 3 || ((size
== 3) && !is_q
)) {
5711 unallocated_encoding(s
);
5715 if (!fp_access_check(s
)) {
5719 for (i
= 0; i
< elements
; i
++) {
5720 write_vec_element(s
, cpu_reg(s
, rn
), rd
, i
, size
);
5723 clear_vec_high(s
, rd
);
5727 /* C6.3.150 INS (Element)
5729 * 31 21 20 16 15 14 11 10 9 5 4 0
5730 * +-----------------------+--------+------------+---+------+------+
5731 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5732 * +-----------------------+--------+------------+---+------+------+
5734 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5735 * index: encoded in imm5<4:size+1>
5737 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
5740 int size
= ctz32(imm5
);
5741 int src_index
, dst_index
;
5745 unallocated_encoding(s
);
5749 if (!fp_access_check(s
)) {
5753 dst_index
= extract32(imm5
, 1+size
, 5);
5754 src_index
= extract32(imm4
, size
, 4);
5756 tmp
= tcg_temp_new_i64();
5758 read_vec_element(s
, tmp
, rn
, src_index
, size
);
5759 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
5761 tcg_temp_free_i64(tmp
);
5765 /* C6.3.151 INS (General)
5767 * 31 21 20 16 15 10 9 5 4 0
5768 * +-----------------------+--------+-------------+------+------+
5769 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
5770 * +-----------------------+--------+-------------+------+------+
5772 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5773 * index: encoded in imm5<4:size+1>
5775 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
5777 int size
= ctz32(imm5
);
5781 unallocated_encoding(s
);
5785 if (!fp_access_check(s
)) {
5789 idx
= extract32(imm5
, 1 + size
, 4 - size
);
5790 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
5794 * C6.3.321 UMOV (General)
5795 * C6.3.237 SMOV (General)
5797 * 31 30 29 21 20 16 15 12 10 9 5 4 0
5798 * +---+---+-------------------+--------+-------------+------+------+
5799 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
5800 * +---+---+-------------------+--------+-------------+------+------+
5802 * U: unsigned when set
5803 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5805 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
5806 int rn
, int rd
, int imm5
)
5808 int size
= ctz32(imm5
);
5812 /* Check for UnallocatedEncodings */
5814 if (size
> 2 || (size
== 2 && !is_q
)) {
5815 unallocated_encoding(s
);
5820 || (size
< 3 && is_q
)
5821 || (size
== 3 && !is_q
)) {
5822 unallocated_encoding(s
);
5827 if (!fp_access_check(s
)) {
5831 element
= extract32(imm5
, 1+size
, 4);
5833 tcg_rd
= cpu_reg(s
, rd
);
5834 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
5835 if (is_signed
&& !is_q
) {
5836 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5840 /* C3.6.5 AdvSIMD copy
5841 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
5842 * +---+---+----+-----------------+------+---+------+---+------+------+
5843 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5844 * +---+---+----+-----------------+------+---+------+---+------+------+
5846 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
5848 int rd
= extract32(insn
, 0, 5);
5849 int rn
= extract32(insn
, 5, 5);
5850 int imm4
= extract32(insn
, 11, 4);
5851 int op
= extract32(insn
, 29, 1);
5852 int is_q
= extract32(insn
, 30, 1);
5853 int imm5
= extract32(insn
, 16, 5);
5858 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
5860 unallocated_encoding(s
);
5865 /* DUP (element - vector) */
5866 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
5870 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
5875 handle_simd_insg(s
, rd
, rn
, imm5
);
5877 unallocated_encoding(s
);
5882 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
5883 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
5886 unallocated_encoding(s
);
5892 /* C3.6.6 AdvSIMD modified immediate
5893 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
5894 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
5895 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
5896 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
5898 * There are a number of operations that can be carried out here:
5899 * MOVI - move (shifted) imm into register
5900 * MVNI - move inverted (shifted) imm into register
5901 * ORR - bitwise OR of (shifted) imm with register
5902 * BIC - bitwise clear of (shifted) imm with register
5904 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
5906 int rd
= extract32(insn
, 0, 5);
5907 int cmode
= extract32(insn
, 12, 4);
5908 int cmode_3_1
= extract32(cmode
, 1, 3);
5909 int cmode_0
= extract32(cmode
, 0, 1);
5910 int o2
= extract32(insn
, 11, 1);
5911 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
5912 bool is_neg
= extract32(insn
, 29, 1);
5913 bool is_q
= extract32(insn
, 30, 1);
5915 TCGv_i64 tcg_rd
, tcg_imm
;
5918 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
5919 unallocated_encoding(s
);
5923 if (!fp_access_check(s
)) {
5927 /* See AdvSIMDExpandImm() in ARM ARM */
5928 switch (cmode_3_1
) {
5929 case 0: /* Replicate(Zeros(24):imm8, 2) */
5930 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
5931 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
5932 case 3: /* Replicate(imm8:Zeros(24), 2) */
5934 int shift
= cmode_3_1
* 8;
5935 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
5938 case 4: /* Replicate(Zeros(8):imm8, 4) */
5939 case 5: /* Replicate(imm8:Zeros(8), 4) */
5941 int shift
= (cmode_3_1
& 0x1) * 8;
5942 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
5947 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
5948 imm
= (abcdefgh
<< 16) | 0xffff;
5950 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
5951 imm
= (abcdefgh
<< 8) | 0xff;
5953 imm
= bitfield_replicate(imm
, 32);
5956 if (!cmode_0
&& !is_neg
) {
5957 imm
= bitfield_replicate(abcdefgh
, 8);
5958 } else if (!cmode_0
&& is_neg
) {
5961 for (i
= 0; i
< 8; i
++) {
5962 if ((abcdefgh
) & (1 << i
)) {
5963 imm
|= 0xffULL
<< (i
* 8);
5966 } else if (cmode_0
) {
5968 imm
= (abcdefgh
& 0x3f) << 48;
5969 if (abcdefgh
& 0x80) {
5970 imm
|= 0x8000000000000000ULL
;
5972 if (abcdefgh
& 0x40) {
5973 imm
|= 0x3fc0000000000000ULL
;
5975 imm
|= 0x4000000000000000ULL
;
5978 imm
= (abcdefgh
& 0x3f) << 19;
5979 if (abcdefgh
& 0x80) {
5982 if (abcdefgh
& 0x40) {
5993 if (cmode_3_1
!= 7 && is_neg
) {
5997 tcg_imm
= tcg_const_i64(imm
);
5998 tcg_rd
= new_tmp_a64(s
);
6000 for (i
= 0; i
< 2; i
++) {
6001 int foffs
= i
? fp_reg_hi_offset(s
, rd
) : fp_reg_offset(s
, rd
, MO_64
);
6003 if (i
== 1 && !is_q
) {
6004 /* non-quad ops clear high half of vector */
6005 tcg_gen_movi_i64(tcg_rd
, 0);
6006 } else if ((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9) {
6007 tcg_gen_ld_i64(tcg_rd
, cpu_env
, foffs
);
6010 tcg_gen_and_i64(tcg_rd
, tcg_rd
, tcg_imm
);
6013 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_imm
);
6017 tcg_gen_mov_i64(tcg_rd
, tcg_imm
);
6019 tcg_gen_st_i64(tcg_rd
, cpu_env
, foffs
);
6022 tcg_temp_free_i64(tcg_imm
);
6025 /* C3.6.7 AdvSIMD scalar copy
6026 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
6027 * +-----+----+-----------------+------+---+------+---+------+------+
6028 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
6029 * +-----+----+-----------------+------+---+------+---+------+------+
6031 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
6033 int rd
= extract32(insn
, 0, 5);
6034 int rn
= extract32(insn
, 5, 5);
6035 int imm4
= extract32(insn
, 11, 4);
6036 int imm5
= extract32(insn
, 16, 5);
6037 int op
= extract32(insn
, 29, 1);
6039 if (op
!= 0 || imm4
!= 0) {
6040 unallocated_encoding(s
);
6044 /* DUP (element, scalar) */
6045 handle_simd_dupes(s
, rd
, rn
, imm5
);
6048 /* C3.6.8 AdvSIMD scalar pairwise
6049 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
6050 * +-----+---+-----------+------+-----------+--------+-----+------+------+
6051 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
6052 * +-----+---+-----------+------+-----------+--------+-----+------+------+
6054 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
6056 int u
= extract32(insn
, 29, 1);
6057 int size
= extract32(insn
, 22, 2);
6058 int opcode
= extract32(insn
, 12, 5);
6059 int rn
= extract32(insn
, 5, 5);
6060 int rd
= extract32(insn
, 0, 5);
6063 /* For some ops (the FP ones), size[1] is part of the encoding.
6064 * For ADDP strictly it is not but size[1] is always 1 for valid
6067 opcode
|= (extract32(size
, 1, 1) << 5);
6070 case 0x3b: /* ADDP */
6071 if (u
|| size
!= 3) {
6072 unallocated_encoding(s
);
6075 if (!fp_access_check(s
)) {
6079 TCGV_UNUSED_PTR(fpst
);
6081 case 0xc: /* FMAXNMP */
6082 case 0xd: /* FADDP */
6083 case 0xf: /* FMAXP */
6084 case 0x2c: /* FMINNMP */
6085 case 0x2f: /* FMINP */
6086 /* FP op, size[0] is 32 or 64 bit */
6088 unallocated_encoding(s
);
6091 if (!fp_access_check(s
)) {
6095 size
= extract32(size
, 0, 1) ? 3 : 2;
6096 fpst
= get_fpstatus_ptr();
6099 unallocated_encoding(s
);
6104 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
6105 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
6106 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6108 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
6109 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
6112 case 0x3b: /* ADDP */
6113 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
6115 case 0xc: /* FMAXNMP */
6116 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6118 case 0xd: /* FADDP */
6119 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6121 case 0xf: /* FMAXP */
6122 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6124 case 0x2c: /* FMINNMP */
6125 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6127 case 0x2f: /* FMINP */
6128 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6131 g_assert_not_reached();
6134 write_fp_dreg(s
, rd
, tcg_res
);
6136 tcg_temp_free_i64(tcg_op1
);
6137 tcg_temp_free_i64(tcg_op2
);
6138 tcg_temp_free_i64(tcg_res
);
6140 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
6141 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
6142 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6144 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_32
);
6145 read_vec_element_i32(s
, tcg_op2
, rn
, 1, MO_32
);
6148 case 0xc: /* FMAXNMP */
6149 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6151 case 0xd: /* FADDP */
6152 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6154 case 0xf: /* FMAXP */
6155 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6157 case 0x2c: /* FMINNMP */
6158 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6160 case 0x2f: /* FMINP */
6161 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6164 g_assert_not_reached();
6167 write_fp_sreg(s
, rd
, tcg_res
);
6169 tcg_temp_free_i32(tcg_op1
);
6170 tcg_temp_free_i32(tcg_op2
);
6171 tcg_temp_free_i32(tcg_res
);
6174 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
6175 tcg_temp_free_ptr(fpst
);
6180 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
6182 * This code is handles the common shifting code and is used by both
6183 * the vector and scalar code.
6185 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6186 TCGv_i64 tcg_rnd
, bool accumulate
,
6187 bool is_u
, int size
, int shift
)
6189 bool extended_result
= false;
6190 bool round
= !TCGV_IS_UNUSED_I64(tcg_rnd
);
6192 TCGv_i64 tcg_src_hi
;
6194 if (round
&& size
== 3) {
6195 extended_result
= true;
6196 ext_lshift
= 64 - shift
;
6197 tcg_src_hi
= tcg_temp_new_i64();
6198 } else if (shift
== 64) {
6199 if (!accumulate
&& is_u
) {
6200 /* result is zero */
6201 tcg_gen_movi_i64(tcg_res
, 0);
6206 /* Deal with the rounding step */
6208 if (extended_result
) {
6209 TCGv_i64 tcg_zero
= tcg_const_i64(0);
6211 /* take care of sign extending tcg_res */
6212 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
6213 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
6214 tcg_src
, tcg_src_hi
,
6217 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
6221 tcg_temp_free_i64(tcg_zero
);
6223 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
6227 /* Now do the shift right */
6228 if (round
&& extended_result
) {
6229 /* extended case, >64 bit precision required */
6230 if (ext_lshift
== 0) {
6231 /* special case, only high bits matter */
6232 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
6234 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6235 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
6236 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
6241 /* essentially shifting in 64 zeros */
6242 tcg_gen_movi_i64(tcg_src
, 0);
6244 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6248 /* effectively extending the sign-bit */
6249 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
6251 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
6257 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
6259 tcg_gen_mov_i64(tcg_res
, tcg_src
);
6262 if (extended_result
) {
6263 tcg_temp_free_i64(tcg_src_hi
);
6267 /* Common SHL/SLI - Shift left with an optional insert */
6268 static void handle_shli_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6269 bool insert
, int shift
)
6271 if (insert
) { /* SLI */
6272 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, shift
, 64 - shift
);
6274 tcg_gen_shli_i64(tcg_res
, tcg_src
, shift
);
6278 /* SRI: shift right with insert */
6279 static void handle_shri_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6280 int size
, int shift
)
6282 int esize
= 8 << size
;
6284 /* shift count same as element size is valid but does nothing;
6285 * special case to avoid potential shift by 64.
6287 if (shift
!= esize
) {
6288 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6289 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, 0, esize
- shift
);
6293 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
6294 static void handle_scalar_simd_shri(DisasContext
*s
,
6295 bool is_u
, int immh
, int immb
,
6296 int opcode
, int rn
, int rd
)
6299 int immhb
= immh
<< 3 | immb
;
6300 int shift
= 2 * (8 << size
) - immhb
;
6301 bool accumulate
= false;
6303 bool insert
= false;
6308 if (!extract32(immh
, 3, 1)) {
6309 unallocated_encoding(s
);
6313 if (!fp_access_check(s
)) {
6318 case 0x02: /* SSRA / USRA (accumulate) */
6321 case 0x04: /* SRSHR / URSHR (rounding) */
6324 case 0x06: /* SRSRA / URSRA (accum + rounding) */
6325 accumulate
= round
= true;
6327 case 0x08: /* SRI */
6333 uint64_t round_const
= 1ULL << (shift
- 1);
6334 tcg_round
= tcg_const_i64(round_const
);
6336 TCGV_UNUSED_I64(tcg_round
);
6339 tcg_rn
= read_fp_dreg(s
, rn
);
6340 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
6343 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
6345 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
6346 accumulate
, is_u
, size
, shift
);
6349 write_fp_dreg(s
, rd
, tcg_rd
);
6351 tcg_temp_free_i64(tcg_rn
);
6352 tcg_temp_free_i64(tcg_rd
);
6354 tcg_temp_free_i64(tcg_round
);
6358 /* SHL/SLI - Scalar shift left */
6359 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
6360 int immh
, int immb
, int opcode
,
6363 int size
= 32 - clz32(immh
) - 1;
6364 int immhb
= immh
<< 3 | immb
;
6365 int shift
= immhb
- (8 << size
);
6366 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
6367 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
6369 if (!extract32(immh
, 3, 1)) {
6370 unallocated_encoding(s
);
6374 if (!fp_access_check(s
)) {
6378 tcg_rn
= read_fp_dreg(s
, rn
);
6379 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
6381 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
6383 write_fp_dreg(s
, rd
, tcg_rd
);
6385 tcg_temp_free_i64(tcg_rn
);
6386 tcg_temp_free_i64(tcg_rd
);
6389 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
6390 * (signed/unsigned) narrowing */
6391 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
6392 bool is_u_shift
, bool is_u_narrow
,
6393 int immh
, int immb
, int opcode
,
6396 int immhb
= immh
<< 3 | immb
;
6397 int size
= 32 - clz32(immh
) - 1;
6398 int esize
= 8 << size
;
6399 int shift
= (2 * esize
) - immhb
;
6400 int elements
= is_scalar
? 1 : (64 / esize
);
6401 bool round
= extract32(opcode
, 0, 1);
6402 TCGMemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
6403 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
6404 TCGv_i32 tcg_rd_narrowed
;
6407 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
6408 { gen_helper_neon_narrow_sat_s8
,
6409 gen_helper_neon_unarrow_sat8
},
6410 { gen_helper_neon_narrow_sat_s16
,
6411 gen_helper_neon_unarrow_sat16
},
6412 { gen_helper_neon_narrow_sat_s32
,
6413 gen_helper_neon_unarrow_sat32
},
6416 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
6417 gen_helper_neon_narrow_sat_u8
,
6418 gen_helper_neon_narrow_sat_u16
,
6419 gen_helper_neon_narrow_sat_u32
,
6422 NeonGenNarrowEnvFn
*narrowfn
;
6428 if (extract32(immh
, 3, 1)) {
6429 unallocated_encoding(s
);
6433 if (!fp_access_check(s
)) {
6438 narrowfn
= unsigned_narrow_fns
[size
];
6440 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
6443 tcg_rn
= tcg_temp_new_i64();
6444 tcg_rd
= tcg_temp_new_i64();
6445 tcg_rd_narrowed
= tcg_temp_new_i32();
6446 tcg_final
= tcg_const_i64(0);
6449 uint64_t round_const
= 1ULL << (shift
- 1);
6450 tcg_round
= tcg_const_i64(round_const
);
6452 TCGV_UNUSED_I64(tcg_round
);
6455 for (i
= 0; i
< elements
; i
++) {
6456 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
6457 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
6458 false, is_u_shift
, size
+1, shift
);
6459 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
6460 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
6461 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
6465 clear_vec_high(s
, rd
);
6466 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
6468 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
6472 tcg_temp_free_i64(tcg_round
);
6474 tcg_temp_free_i64(tcg_rn
);
6475 tcg_temp_free_i64(tcg_rd
);
6476 tcg_temp_free_i32(tcg_rd_narrowed
);
6477 tcg_temp_free_i64(tcg_final
);
6481 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
6482 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
6483 bool src_unsigned
, bool dst_unsigned
,
6484 int immh
, int immb
, int rn
, int rd
)
6486 int immhb
= immh
<< 3 | immb
;
6487 int size
= 32 - clz32(immh
) - 1;
6488 int shift
= immhb
- (8 << size
);
6492 assert(!(scalar
&& is_q
));
6495 if (!is_q
&& extract32(immh
, 3, 1)) {
6496 unallocated_encoding(s
);
6500 /* Since we use the variable-shift helpers we must
6501 * replicate the shift count into each element of
6502 * the tcg_shift value.
6506 shift
|= shift
<< 8;
6509 shift
|= shift
<< 16;
6515 g_assert_not_reached();
6519 if (!fp_access_check(s
)) {
6524 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
6525 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
6526 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
6527 { NULL
, gen_helper_neon_qshl_u64
},
6529 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
6530 int maxpass
= is_q
? 2 : 1;
6532 for (pass
= 0; pass
< maxpass
; pass
++) {
6533 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6535 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6536 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
6537 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
6539 tcg_temp_free_i64(tcg_op
);
6541 tcg_temp_free_i64(tcg_shift
);
6544 clear_vec_high(s
, rd
);
6547 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
6548 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
6550 { gen_helper_neon_qshl_s8
,
6551 gen_helper_neon_qshl_s16
,
6552 gen_helper_neon_qshl_s32
},
6553 { gen_helper_neon_qshlu_s8
,
6554 gen_helper_neon_qshlu_s16
,
6555 gen_helper_neon_qshlu_s32
}
6557 { NULL
, NULL
, NULL
},
6558 { gen_helper_neon_qshl_u8
,
6559 gen_helper_neon_qshl_u16
,
6560 gen_helper_neon_qshl_u32
}
6563 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
6564 TCGMemOp memop
= scalar
? size
: MO_32
;
6565 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
6567 for (pass
= 0; pass
< maxpass
; pass
++) {
6568 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6570 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
6571 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
6575 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
6578 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
6583 g_assert_not_reached();
6585 write_fp_sreg(s
, rd
, tcg_op
);
6587 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
6590 tcg_temp_free_i32(tcg_op
);
6592 tcg_temp_free_i32(tcg_shift
);
6594 if (!is_q
&& !scalar
) {
6595 clear_vec_high(s
, rd
);
6600 /* Common vector code for handling integer to FP conversion */
6601 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
6602 int elements
, int is_signed
,
6603 int fracbits
, int size
)
6605 bool is_double
= size
== 3 ? true : false;
6606 TCGv_ptr tcg_fpst
= get_fpstatus_ptr();
6607 TCGv_i32 tcg_shift
= tcg_const_i32(fracbits
);
6608 TCGv_i64 tcg_int
= tcg_temp_new_i64();
6609 TCGMemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
6612 for (pass
= 0; pass
< elements
; pass
++) {
6613 read_vec_element(s
, tcg_int
, rn
, pass
, mop
);
6616 TCGv_i64 tcg_double
= tcg_temp_new_i64();
6618 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6619 tcg_shift
, tcg_fpst
);
6621 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6622 tcg_shift
, tcg_fpst
);
6624 if (elements
== 1) {
6625 write_fp_dreg(s
, rd
, tcg_double
);
6627 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
6629 tcg_temp_free_i64(tcg_double
);
6631 TCGv_i32 tcg_single
= tcg_temp_new_i32();
6633 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6634 tcg_shift
, tcg_fpst
);
6636 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6637 tcg_shift
, tcg_fpst
);
6639 if (elements
== 1) {
6640 write_fp_sreg(s
, rd
, tcg_single
);
6642 write_vec_element_i32(s
, tcg_single
, rd
, pass
, MO_32
);
6644 tcg_temp_free_i32(tcg_single
);
6648 if (!is_double
&& elements
== 2) {
6649 clear_vec_high(s
, rd
);
6652 tcg_temp_free_i64(tcg_int
);
6653 tcg_temp_free_ptr(tcg_fpst
);
6654 tcg_temp_free_i32(tcg_shift
);
6657 /* UCVTF/SCVTF - Integer to FP conversion */
6658 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
6659 bool is_q
, bool is_u
,
6660 int immh
, int immb
, int opcode
,
6663 bool is_double
= extract32(immh
, 3, 1);
6664 int size
= is_double
? MO_64
: MO_32
;
6666 int immhb
= immh
<< 3 | immb
;
6667 int fracbits
= (is_double
? 128 : 64) - immhb
;
6669 if (!extract32(immh
, 2, 2)) {
6670 unallocated_encoding(s
);
6677 elements
= is_double
? 2 : is_q
? 4 : 2;
6678 if (is_double
&& !is_q
) {
6679 unallocated_encoding(s
);
6684 if (!fp_access_check(s
)) {
6688 /* immh == 0 would be a failure of the decode logic */
6691 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
6694 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
6695 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
6696 bool is_q
, bool is_u
,
6697 int immh
, int immb
, int rn
, int rd
)
6699 bool is_double
= extract32(immh
, 3, 1);
6700 int immhb
= immh
<< 3 | immb
;
6701 int fracbits
= (is_double
? 128 : 64) - immhb
;
6703 TCGv_ptr tcg_fpstatus
;
6704 TCGv_i32 tcg_rmode
, tcg_shift
;
6706 if (!extract32(immh
, 2, 2)) {
6707 unallocated_encoding(s
);
6711 if (!is_scalar
&& !is_q
&& is_double
) {
6712 unallocated_encoding(s
);
6716 if (!fp_access_check(s
)) {
6720 assert(!(is_scalar
&& is_q
));
6722 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
6723 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
6724 tcg_fpstatus
= get_fpstatus_ptr();
6725 tcg_shift
= tcg_const_i32(fracbits
);
6728 int maxpass
= is_scalar
? 1 : 2;
6730 for (pass
= 0; pass
< maxpass
; pass
++) {
6731 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6733 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6735 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6737 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6739 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
6740 tcg_temp_free_i64(tcg_op
);
6743 clear_vec_high(s
, rd
);
6746 int maxpass
= is_scalar
? 1 : is_q
? 4 : 2;
6747 for (pass
= 0; pass
< maxpass
; pass
++) {
6748 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6750 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
6752 gen_helper_vfp_touls(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6754 gen_helper_vfp_tosls(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6757 write_fp_sreg(s
, rd
, tcg_op
);
6759 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
6761 tcg_temp_free_i32(tcg_op
);
6763 if (!is_q
&& !is_scalar
) {
6764 clear_vec_high(s
, rd
);
6768 tcg_temp_free_ptr(tcg_fpstatus
);
6769 tcg_temp_free_i32(tcg_shift
);
6770 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
6771 tcg_temp_free_i32(tcg_rmode
);
6774 /* C3.6.9 AdvSIMD scalar shift by immediate
6775 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
6776 * +-----+---+-------------+------+------+--------+---+------+------+
6777 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
6778 * +-----+---+-------------+------+------+--------+---+------+------+
6780 * This is the scalar version so it works on a fixed sized registers
6782 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
6784 int rd
= extract32(insn
, 0, 5);
6785 int rn
= extract32(insn
, 5, 5);
6786 int opcode
= extract32(insn
, 11, 5);
6787 int immb
= extract32(insn
, 16, 3);
6788 int immh
= extract32(insn
, 19, 4);
6789 bool is_u
= extract32(insn
, 29, 1);
6792 unallocated_encoding(s
);
6797 case 0x08: /* SRI */
6799 unallocated_encoding(s
);
6803 case 0x00: /* SSHR / USHR */
6804 case 0x02: /* SSRA / USRA */
6805 case 0x04: /* SRSHR / URSHR */
6806 case 0x06: /* SRSRA / URSRA */
6807 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
6809 case 0x0a: /* SHL / SLI */
6810 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
6812 case 0x1c: /* SCVTF, UCVTF */
6813 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
6816 case 0x10: /* SQSHRUN, SQSHRUN2 */
6817 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
6819 unallocated_encoding(s
);
6822 handle_vec_simd_sqshrn(s
, true, false, false, true,
6823 immh
, immb
, opcode
, rn
, rd
);
6825 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
6826 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
6827 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
6828 immh
, immb
, opcode
, rn
, rd
);
6830 case 0xc: /* SQSHLU */
6832 unallocated_encoding(s
);
6835 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
6837 case 0xe: /* SQSHL, UQSHL */
6838 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
6840 case 0x1f: /* FCVTZS, FCVTZU */
6841 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
6844 unallocated_encoding(s
);
6849 /* C3.6.10 AdvSIMD scalar three different
6850 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6851 * +-----+---+-----------+------+---+------+--------+-----+------+------+
6852 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
6853 * +-----+---+-----------+------+---+------+--------+-----+------+------+
6855 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
6857 bool is_u
= extract32(insn
, 29, 1);
6858 int size
= extract32(insn
, 22, 2);
6859 int opcode
= extract32(insn
, 12, 4);
6860 int rm
= extract32(insn
, 16, 5);
6861 int rn
= extract32(insn
, 5, 5);
6862 int rd
= extract32(insn
, 0, 5);
6865 unallocated_encoding(s
);
6870 case 0x9: /* SQDMLAL, SQDMLAL2 */
6871 case 0xb: /* SQDMLSL, SQDMLSL2 */
6872 case 0xd: /* SQDMULL, SQDMULL2 */
6873 if (size
== 0 || size
== 3) {
6874 unallocated_encoding(s
);
6879 unallocated_encoding(s
);
6883 if (!fp_access_check(s
)) {
6888 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
6889 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
6890 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6892 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
6893 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
6895 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
6896 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
6899 case 0xd: /* SQDMULL, SQDMULL2 */
6901 case 0xb: /* SQDMLSL, SQDMLSL2 */
6902 tcg_gen_neg_i64(tcg_res
, tcg_res
);
6904 case 0x9: /* SQDMLAL, SQDMLAL2 */
6905 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
6906 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
6910 g_assert_not_reached();
6913 write_fp_dreg(s
, rd
, tcg_res
);
6915 tcg_temp_free_i64(tcg_op1
);
6916 tcg_temp_free_i64(tcg_op2
);
6917 tcg_temp_free_i64(tcg_res
);
6919 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
6920 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
6921 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6923 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_16
);
6924 read_vec_element_i32(s
, tcg_op2
, rm
, 0, MO_16
);
6926 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
6927 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
6930 case 0xd: /* SQDMULL, SQDMULL2 */
6932 case 0xb: /* SQDMLSL, SQDMLSL2 */
6933 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
6935 case 0x9: /* SQDMLAL, SQDMLAL2 */
6937 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
6938 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
6939 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
6941 tcg_temp_free_i64(tcg_op3
);
6945 g_assert_not_reached();
6948 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
6949 write_fp_dreg(s
, rd
, tcg_res
);
6951 tcg_temp_free_i32(tcg_op1
);
6952 tcg_temp_free_i32(tcg_op2
);
6953 tcg_temp_free_i64(tcg_res
);
6957 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
6958 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
6960 /* Handle 64x64->64 opcodes which are shared between the scalar
6961 * and vector 3-same groups. We cover every opcode where size == 3
6962 * is valid in either the three-reg-same (integer, not pairwise)
6963 * or scalar-three-reg-same groups. (Some opcodes are not yet
6969 case 0x1: /* SQADD */
6971 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6973 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6976 case 0x5: /* SQSUB */
6978 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6980 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6983 case 0x6: /* CMGT, CMHI */
6984 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
6985 * We implement this using setcond (test) and then negating.
6987 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
6989 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
6990 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
6992 case 0x7: /* CMGE, CMHS */
6993 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
6995 case 0x11: /* CMTST, CMEQ */
7000 /* CMTST : test is "if (X & Y != 0)". */
7001 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
7002 tcg_gen_setcondi_i64(TCG_COND_NE
, tcg_rd
, tcg_rd
, 0);
7003 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7005 case 0x8: /* SSHL, USHL */
7007 gen_helper_neon_shl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
7009 gen_helper_neon_shl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
7012 case 0x9: /* SQSHL, UQSHL */
7014 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7016 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7019 case 0xa: /* SRSHL, URSHL */
7021 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
7023 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
7026 case 0xb: /* SQRSHL, UQRSHL */
7028 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7030 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7033 case 0x10: /* ADD, SUB */
7035 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
7037 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
7041 g_assert_not_reached();
7045 /* Handle the 3-same-operands float operations; shared by the scalar
7046 * and vector encodings. The caller must filter out any encodings
7047 * not allocated for the encoding it is dealing with.
7049 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
7050 int fpopcode
, int rd
, int rn
, int rm
)
7053 TCGv_ptr fpst
= get_fpstatus_ptr();
7055 for (pass
= 0; pass
< elements
; pass
++) {
7058 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7059 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7060 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7062 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
7063 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
7066 case 0x39: /* FMLS */
7067 /* As usual for ARM, separate negation for fused multiply-add */
7068 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
7070 case 0x19: /* FMLA */
7071 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7072 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
7075 case 0x18: /* FMAXNM */
7076 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7078 case 0x1a: /* FADD */
7079 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7081 case 0x1b: /* FMULX */
7082 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7084 case 0x1c: /* FCMEQ */
7085 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7087 case 0x1e: /* FMAX */
7088 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7090 case 0x1f: /* FRECPS */
7091 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7093 case 0x38: /* FMINNM */
7094 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7096 case 0x3a: /* FSUB */
7097 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7099 case 0x3e: /* FMIN */
7100 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7102 case 0x3f: /* FRSQRTS */
7103 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7105 case 0x5b: /* FMUL */
7106 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7108 case 0x5c: /* FCMGE */
7109 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7111 case 0x5d: /* FACGE */
7112 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7114 case 0x5f: /* FDIV */
7115 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7117 case 0x7a: /* FABD */
7118 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7119 gen_helper_vfp_absd(tcg_res
, tcg_res
);
7121 case 0x7c: /* FCMGT */
7122 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7124 case 0x7d: /* FACGT */
7125 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7128 g_assert_not_reached();
7131 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7133 tcg_temp_free_i64(tcg_res
);
7134 tcg_temp_free_i64(tcg_op1
);
7135 tcg_temp_free_i64(tcg_op2
);
7138 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7139 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7140 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7142 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
7143 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
7146 case 0x39: /* FMLS */
7147 /* As usual for ARM, separate negation for fused multiply-add */
7148 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
7150 case 0x19: /* FMLA */
7151 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7152 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
7155 case 0x1a: /* FADD */
7156 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7158 case 0x1b: /* FMULX */
7159 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7161 case 0x1c: /* FCMEQ */
7162 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7164 case 0x1e: /* FMAX */
7165 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7167 case 0x1f: /* FRECPS */
7168 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7170 case 0x18: /* FMAXNM */
7171 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7173 case 0x38: /* FMINNM */
7174 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7176 case 0x3a: /* FSUB */
7177 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7179 case 0x3e: /* FMIN */
7180 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7182 case 0x3f: /* FRSQRTS */
7183 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7185 case 0x5b: /* FMUL */
7186 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7188 case 0x5c: /* FCMGE */
7189 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7191 case 0x5d: /* FACGE */
7192 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7194 case 0x5f: /* FDIV */
7195 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7197 case 0x7a: /* FABD */
7198 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7199 gen_helper_vfp_abss(tcg_res
, tcg_res
);
7201 case 0x7c: /* FCMGT */
7202 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7204 case 0x7d: /* FACGT */
7205 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7208 g_assert_not_reached();
7211 if (elements
== 1) {
7212 /* scalar single so clear high part */
7213 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
7215 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
7216 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
7217 tcg_temp_free_i64(tcg_tmp
);
7219 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7222 tcg_temp_free_i32(tcg_res
);
7223 tcg_temp_free_i32(tcg_op1
);
7224 tcg_temp_free_i32(tcg_op2
);
7228 tcg_temp_free_ptr(fpst
);
7230 if ((elements
<< size
) < 4) {
7231 /* scalar, or non-quad vector op */
7232 clear_vec_high(s
, rd
);
7236 /* C3.6.11 AdvSIMD scalar three same
7237 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
7238 * +-----+---+-----------+------+---+------+--------+---+------+------+
7239 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
7240 * +-----+---+-----------+------+---+------+--------+---+------+------+
7242 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
7244 int rd
= extract32(insn
, 0, 5);
7245 int rn
= extract32(insn
, 5, 5);
7246 int opcode
= extract32(insn
, 11, 5);
7247 int rm
= extract32(insn
, 16, 5);
7248 int size
= extract32(insn
, 22, 2);
7249 bool u
= extract32(insn
, 29, 1);
7252 if (opcode
>= 0x18) {
7253 /* Floating point: U, size[1] and opcode indicate operation */
7254 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
7256 case 0x1b: /* FMULX */
7257 case 0x1f: /* FRECPS */
7258 case 0x3f: /* FRSQRTS */
7259 case 0x5d: /* FACGE */
7260 case 0x7d: /* FACGT */
7261 case 0x1c: /* FCMEQ */
7262 case 0x5c: /* FCMGE */
7263 case 0x7c: /* FCMGT */
7264 case 0x7a: /* FABD */
7267 unallocated_encoding(s
);
7271 if (!fp_access_check(s
)) {
7275 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
7280 case 0x1: /* SQADD, UQADD */
7281 case 0x5: /* SQSUB, UQSUB */
7282 case 0x9: /* SQSHL, UQSHL */
7283 case 0xb: /* SQRSHL, UQRSHL */
7285 case 0x8: /* SSHL, USHL */
7286 case 0xa: /* SRSHL, URSHL */
7287 case 0x6: /* CMGT, CMHI */
7288 case 0x7: /* CMGE, CMHS */
7289 case 0x11: /* CMTST, CMEQ */
7290 case 0x10: /* ADD, SUB (vector) */
7292 unallocated_encoding(s
);
7296 case 0x16: /* SQDMULH, SQRDMULH (vector) */
7297 if (size
!= 1 && size
!= 2) {
7298 unallocated_encoding(s
);
7303 unallocated_encoding(s
);
7307 if (!fp_access_check(s
)) {
7311 tcg_rd
= tcg_temp_new_i64();
7314 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
7315 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
7317 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
7318 tcg_temp_free_i64(tcg_rn
);
7319 tcg_temp_free_i64(tcg_rm
);
7321 /* Do a single operation on the lowest element in the vector.
7322 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
7323 * no side effects for all these operations.
7324 * OPTME: special-purpose helpers would avoid doing some
7325 * unnecessary work in the helper for the 8 and 16 bit cases.
7327 NeonGenTwoOpEnvFn
*genenvfn
;
7328 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
7329 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
7330 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
7332 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
7333 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
7336 case 0x1: /* SQADD, UQADD */
7338 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7339 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
7340 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
7341 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
7343 genenvfn
= fns
[size
][u
];
7346 case 0x5: /* SQSUB, UQSUB */
7348 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7349 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
7350 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
7351 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
7353 genenvfn
= fns
[size
][u
];
7356 case 0x9: /* SQSHL, UQSHL */
7358 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7359 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
7360 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
7361 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
7363 genenvfn
= fns
[size
][u
];
7366 case 0xb: /* SQRSHL, UQRSHL */
7368 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7369 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
7370 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
7371 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
7373 genenvfn
= fns
[size
][u
];
7376 case 0x16: /* SQDMULH, SQRDMULH */
7378 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
7379 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
7380 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
7382 assert(size
== 1 || size
== 2);
7383 genenvfn
= fns
[size
- 1][u
];
7387 g_assert_not_reached();
7390 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
7391 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
7392 tcg_temp_free_i32(tcg_rd32
);
7393 tcg_temp_free_i32(tcg_rn
);
7394 tcg_temp_free_i32(tcg_rm
);
7397 write_fp_dreg(s
, rd
, tcg_rd
);
7399 tcg_temp_free_i64(tcg_rd
);
7402 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
7403 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
7404 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
7406 /* Handle 64->64 opcodes which are shared between the scalar and
7407 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
7408 * is valid in either group and also the double-precision fp ops.
7409 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
7415 case 0x4: /* CLS, CLZ */
7417 gen_helper_clz64(tcg_rd
, tcg_rn
);
7419 gen_helper_cls64(tcg_rd
, tcg_rn
);
7423 /* This opcode is shared with CNT and RBIT but we have earlier
7424 * enforced that size == 3 if and only if this is the NOT insn.
7426 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
7428 case 0x7: /* SQABS, SQNEG */
7430 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
7432 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
7435 case 0xa: /* CMLT */
7436 /* 64 bit integer comparison against zero, result is
7437 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
7442 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
7443 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7445 case 0x8: /* CMGT, CMGE */
7446 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
7448 case 0x9: /* CMEQ, CMLE */
7449 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
7451 case 0xb: /* ABS, NEG */
7453 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
7455 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7456 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
7457 tcg_gen_movcond_i64(TCG_COND_GT
, tcg_rd
, tcg_rn
, tcg_zero
,
7459 tcg_temp_free_i64(tcg_zero
);
7462 case 0x2f: /* FABS */
7463 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
7465 case 0x6f: /* FNEG */
7466 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
7468 case 0x7f: /* FSQRT */
7469 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
7471 case 0x1a: /* FCVTNS */
7472 case 0x1b: /* FCVTMS */
7473 case 0x1c: /* FCVTAS */
7474 case 0x3a: /* FCVTPS */
7475 case 0x3b: /* FCVTZS */
7477 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7478 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7479 tcg_temp_free_i32(tcg_shift
);
7482 case 0x5a: /* FCVTNU */
7483 case 0x5b: /* FCVTMU */
7484 case 0x5c: /* FCVTAU */
7485 case 0x7a: /* FCVTPU */
7486 case 0x7b: /* FCVTZU */
7488 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7489 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7490 tcg_temp_free_i32(tcg_shift
);
7493 case 0x18: /* FRINTN */
7494 case 0x19: /* FRINTM */
7495 case 0x38: /* FRINTP */
7496 case 0x39: /* FRINTZ */
7497 case 0x58: /* FRINTA */
7498 case 0x79: /* FRINTI */
7499 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
7501 case 0x59: /* FRINTX */
7502 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
7505 g_assert_not_reached();
7509 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
7510 bool is_scalar
, bool is_u
, bool is_q
,
7511 int size
, int rn
, int rd
)
7513 bool is_double
= (size
== 3);
7516 if (!fp_access_check(s
)) {
7520 fpst
= get_fpstatus_ptr();
7523 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7524 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7525 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7526 NeonGenTwoDoubleOPFn
*genfn
;
7531 case 0x2e: /* FCMLT (zero) */
7534 case 0x2c: /* FCMGT (zero) */
7535 genfn
= gen_helper_neon_cgt_f64
;
7537 case 0x2d: /* FCMEQ (zero) */
7538 genfn
= gen_helper_neon_ceq_f64
;
7540 case 0x6d: /* FCMLE (zero) */
7543 case 0x6c: /* FCMGE (zero) */
7544 genfn
= gen_helper_neon_cge_f64
;
7547 g_assert_not_reached();
7550 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7551 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7553 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
7555 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
7557 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7560 clear_vec_high(s
, rd
);
7563 tcg_temp_free_i64(tcg_res
);
7564 tcg_temp_free_i64(tcg_zero
);
7565 tcg_temp_free_i64(tcg_op
);
7567 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7568 TCGv_i32 tcg_zero
= tcg_const_i32(0);
7569 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7570 NeonGenTwoSingleOPFn
*genfn
;
7572 int pass
, maxpasses
;
7575 case 0x2e: /* FCMLT (zero) */
7578 case 0x2c: /* FCMGT (zero) */
7579 genfn
= gen_helper_neon_cgt_f32
;
7581 case 0x2d: /* FCMEQ (zero) */
7582 genfn
= gen_helper_neon_ceq_f32
;
7584 case 0x6d: /* FCMLE (zero) */
7587 case 0x6c: /* FCMGE (zero) */
7588 genfn
= gen_helper_neon_cge_f32
;
7591 g_assert_not_reached();
7597 maxpasses
= is_q
? 4 : 2;
7600 for (pass
= 0; pass
< maxpasses
; pass
++) {
7601 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7603 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
7605 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
7608 write_fp_sreg(s
, rd
, tcg_res
);
7610 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7613 tcg_temp_free_i32(tcg_res
);
7614 tcg_temp_free_i32(tcg_zero
);
7615 tcg_temp_free_i32(tcg_op
);
7616 if (!is_q
&& !is_scalar
) {
7617 clear_vec_high(s
, rd
);
7621 tcg_temp_free_ptr(fpst
);
7624 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
7625 bool is_scalar
, bool is_u
, bool is_q
,
7626 int size
, int rn
, int rd
)
7628 bool is_double
= (size
== 3);
7629 TCGv_ptr fpst
= get_fpstatus_ptr();
7632 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7633 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7636 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7637 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7639 case 0x3d: /* FRECPE */
7640 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
7642 case 0x3f: /* FRECPX */
7643 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
7645 case 0x7d: /* FRSQRTE */
7646 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
7649 g_assert_not_reached();
7651 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7654 clear_vec_high(s
, rd
);
7657 tcg_temp_free_i64(tcg_res
);
7658 tcg_temp_free_i64(tcg_op
);
7660 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7661 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7662 int pass
, maxpasses
;
7667 maxpasses
= is_q
? 4 : 2;
7670 for (pass
= 0; pass
< maxpasses
; pass
++) {
7671 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7674 case 0x3c: /* URECPE */
7675 gen_helper_recpe_u32(tcg_res
, tcg_op
, fpst
);
7677 case 0x3d: /* FRECPE */
7678 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
7680 case 0x3f: /* FRECPX */
7681 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
7683 case 0x7d: /* FRSQRTE */
7684 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
7687 g_assert_not_reached();
7691 write_fp_sreg(s
, rd
, tcg_res
);
7693 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7696 tcg_temp_free_i32(tcg_res
);
7697 tcg_temp_free_i32(tcg_op
);
7698 if (!is_q
&& !is_scalar
) {
7699 clear_vec_high(s
, rd
);
7702 tcg_temp_free_ptr(fpst
);
7705 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
7706 int opcode
, bool u
, bool is_q
,
7707 int size
, int rn
, int rd
)
7709 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
7710 * in the source becomes a size element in the destination).
7713 TCGv_i32 tcg_res
[2];
7714 int destelt
= is_q
? 2 : 0;
7715 int passes
= scalar
? 1 : 2;
7718 tcg_res
[1] = tcg_const_i32(0);
7721 for (pass
= 0; pass
< passes
; pass
++) {
7722 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7723 NeonGenNarrowFn
*genfn
= NULL
;
7724 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
7727 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
7729 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7731 tcg_res
[pass
] = tcg_temp_new_i32();
7734 case 0x12: /* XTN, SQXTUN */
7736 static NeonGenNarrowFn
* const xtnfns
[3] = {
7737 gen_helper_neon_narrow_u8
,
7738 gen_helper_neon_narrow_u16
,
7739 tcg_gen_extrl_i64_i32
,
7741 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
7742 gen_helper_neon_unarrow_sat8
,
7743 gen_helper_neon_unarrow_sat16
,
7744 gen_helper_neon_unarrow_sat32
,
7747 genenvfn
= sqxtunfns
[size
];
7749 genfn
= xtnfns
[size
];
7753 case 0x14: /* SQXTN, UQXTN */
7755 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
7756 { gen_helper_neon_narrow_sat_s8
,
7757 gen_helper_neon_narrow_sat_u8
},
7758 { gen_helper_neon_narrow_sat_s16
,
7759 gen_helper_neon_narrow_sat_u16
},
7760 { gen_helper_neon_narrow_sat_s32
,
7761 gen_helper_neon_narrow_sat_u32
},
7763 genenvfn
= fns
[size
][u
];
7766 case 0x16: /* FCVTN, FCVTN2 */
7767 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
7769 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
7771 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
7772 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
7773 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
7774 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, cpu_env
);
7775 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, cpu_env
);
7776 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
7777 tcg_temp_free_i32(tcg_lo
);
7778 tcg_temp_free_i32(tcg_hi
);
7781 case 0x56: /* FCVTXN, FCVTXN2 */
7782 /* 64 bit to 32 bit float conversion
7783 * with von Neumann rounding (round to odd)
7786 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
7789 g_assert_not_reached();
7793 genfn(tcg_res
[pass
], tcg_op
);
7794 } else if (genenvfn
) {
7795 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
7798 tcg_temp_free_i64(tcg_op
);
7801 for (pass
= 0; pass
< 2; pass
++) {
7802 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
7803 tcg_temp_free_i32(tcg_res
[pass
]);
7806 clear_vec_high(s
, rd
);
7810 /* Remaining saturating accumulating ops */
7811 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
7812 bool is_q
, int size
, int rn
, int rd
)
7814 bool is_double
= (size
== 3);
7817 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
7818 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
7821 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7822 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
7823 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
7825 if (is_u
) { /* USQADD */
7826 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7827 } else { /* SUQADD */
7828 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7830 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
7833 clear_vec_high(s
, rd
);
7836 tcg_temp_free_i64(tcg_rd
);
7837 tcg_temp_free_i64(tcg_rn
);
7839 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
7840 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
7841 int pass
, maxpasses
;
7846 maxpasses
= is_q
? 4 : 2;
7849 for (pass
= 0; pass
< maxpasses
; pass
++) {
7851 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
7852 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
7854 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
7855 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
7858 if (is_u
) { /* USQADD */
7861 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7864 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7867 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7870 g_assert_not_reached();
7872 } else { /* SUQADD */
7875 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7878 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7881 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7884 g_assert_not_reached();
7889 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7890 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
7891 tcg_temp_free_i64(tcg_zero
);
7893 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
7897 clear_vec_high(s
, rd
);
7900 tcg_temp_free_i32(tcg_rd
);
7901 tcg_temp_free_i32(tcg_rn
);
7905 /* C3.6.12 AdvSIMD scalar two reg misc
7906 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7907 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7908 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
7909 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7911 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
7913 int rd
= extract32(insn
, 0, 5);
7914 int rn
= extract32(insn
, 5, 5);
7915 int opcode
= extract32(insn
, 12, 5);
7916 int size
= extract32(insn
, 22, 2);
7917 bool u
= extract32(insn
, 29, 1);
7918 bool is_fcvt
= false;
7921 TCGv_ptr tcg_fpstatus
;
7924 case 0x3: /* USQADD / SUQADD*/
7925 if (!fp_access_check(s
)) {
7928 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
7930 case 0x7: /* SQABS / SQNEG */
7932 case 0xa: /* CMLT */
7934 unallocated_encoding(s
);
7938 case 0x8: /* CMGT, CMGE */
7939 case 0x9: /* CMEQ, CMLE */
7940 case 0xb: /* ABS, NEG */
7942 unallocated_encoding(s
);
7946 case 0x12: /* SQXTUN */
7948 unallocated_encoding(s
);
7952 case 0x14: /* SQXTN, UQXTN */
7954 unallocated_encoding(s
);
7957 if (!fp_access_check(s
)) {
7960 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
7965 /* Floating point: U, size[1] and opcode indicate operation;
7966 * size[0] indicates single or double precision.
7968 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
7969 size
= extract32(size
, 0, 1) ? 3 : 2;
7971 case 0x2c: /* FCMGT (zero) */
7972 case 0x2d: /* FCMEQ (zero) */
7973 case 0x2e: /* FCMLT (zero) */
7974 case 0x6c: /* FCMGE (zero) */
7975 case 0x6d: /* FCMLE (zero) */
7976 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
7978 case 0x1d: /* SCVTF */
7979 case 0x5d: /* UCVTF */
7981 bool is_signed
= (opcode
== 0x1d);
7982 if (!fp_access_check(s
)) {
7985 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
7988 case 0x3d: /* FRECPE */
7989 case 0x3f: /* FRECPX */
7990 case 0x7d: /* FRSQRTE */
7991 if (!fp_access_check(s
)) {
7994 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
7996 case 0x1a: /* FCVTNS */
7997 case 0x1b: /* FCVTMS */
7998 case 0x3a: /* FCVTPS */
7999 case 0x3b: /* FCVTZS */
8000 case 0x5a: /* FCVTNU */
8001 case 0x5b: /* FCVTMU */
8002 case 0x7a: /* FCVTPU */
8003 case 0x7b: /* FCVTZU */
8005 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
8007 case 0x1c: /* FCVTAS */
8008 case 0x5c: /* FCVTAU */
8009 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
8011 rmode
= FPROUNDING_TIEAWAY
;
8013 case 0x56: /* FCVTXN, FCVTXN2 */
8015 unallocated_encoding(s
);
8018 if (!fp_access_check(s
)) {
8021 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
8024 unallocated_encoding(s
);
8029 unallocated_encoding(s
);
8033 if (!fp_access_check(s
)) {
8038 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
8039 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
8040 tcg_fpstatus
= get_fpstatus_ptr();
8042 TCGV_UNUSED_I32(tcg_rmode
);
8043 TCGV_UNUSED_PTR(tcg_fpstatus
);
8047 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
8048 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
8050 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
8051 write_fp_dreg(s
, rd
, tcg_rd
);
8052 tcg_temp_free_i64(tcg_rd
);
8053 tcg_temp_free_i64(tcg_rn
);
8055 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
8056 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
8058 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
8061 case 0x7: /* SQABS, SQNEG */
8063 NeonGenOneOpEnvFn
*genfn
;
8064 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
8065 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
8066 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
8067 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
8069 genfn
= fns
[size
][u
];
8070 genfn(tcg_rd
, cpu_env
, tcg_rn
);
8073 case 0x1a: /* FCVTNS */
8074 case 0x1b: /* FCVTMS */
8075 case 0x1c: /* FCVTAS */
8076 case 0x3a: /* FCVTPS */
8077 case 0x3b: /* FCVTZS */
8079 TCGv_i32 tcg_shift
= tcg_const_i32(0);
8080 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
8081 tcg_temp_free_i32(tcg_shift
);
8084 case 0x5a: /* FCVTNU */
8085 case 0x5b: /* FCVTMU */
8086 case 0x5c: /* FCVTAU */
8087 case 0x7a: /* FCVTPU */
8088 case 0x7b: /* FCVTZU */
8090 TCGv_i32 tcg_shift
= tcg_const_i32(0);
8091 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
8092 tcg_temp_free_i32(tcg_shift
);
8096 g_assert_not_reached();
8099 write_fp_sreg(s
, rd
, tcg_rd
);
8100 tcg_temp_free_i32(tcg_rd
);
8101 tcg_temp_free_i32(tcg_rn
);
8105 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
8106 tcg_temp_free_i32(tcg_rmode
);
8107 tcg_temp_free_ptr(tcg_fpstatus
);
8111 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
8112 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
8113 int immh
, int immb
, int opcode
, int rn
, int rd
)
8115 int size
= 32 - clz32(immh
) - 1;
8116 int immhb
= immh
<< 3 | immb
;
8117 int shift
= 2 * (8 << size
) - immhb
;
8118 bool accumulate
= false;
8120 bool insert
= false;
8121 int dsize
= is_q
? 128 : 64;
8122 int esize
= 8 << size
;
8123 int elements
= dsize
/esize
;
8124 TCGMemOp memop
= size
| (is_u
? 0 : MO_SIGN
);
8125 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8126 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8130 if (extract32(immh
, 3, 1) && !is_q
) {
8131 unallocated_encoding(s
);
8135 if (size
> 3 && !is_q
) {
8136 unallocated_encoding(s
);
8140 if (!fp_access_check(s
)) {
8145 case 0x02: /* SSRA / USRA (accumulate) */
8148 case 0x04: /* SRSHR / URSHR (rounding) */
8151 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8152 accumulate
= round
= true;
8154 case 0x08: /* SRI */
8160 uint64_t round_const
= 1ULL << (shift
- 1);
8161 tcg_round
= tcg_const_i64(round_const
);
8163 TCGV_UNUSED_I64(tcg_round
);
8166 for (i
= 0; i
< elements
; i
++) {
8167 read_vec_element(s
, tcg_rn
, rn
, i
, memop
);
8168 if (accumulate
|| insert
) {
8169 read_vec_element(s
, tcg_rd
, rd
, i
, memop
);
8173 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
8175 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8176 accumulate
, is_u
, size
, shift
);
8179 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
8183 clear_vec_high(s
, rd
);
8187 tcg_temp_free_i64(tcg_round
);
8191 /* SHL/SLI - Vector shift left */
8192 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
8193 int immh
, int immb
, int opcode
, int rn
, int rd
)
8195 int size
= 32 - clz32(immh
) - 1;
8196 int immhb
= immh
<< 3 | immb
;
8197 int shift
= immhb
- (8 << size
);
8198 int dsize
= is_q
? 128 : 64;
8199 int esize
= 8 << size
;
8200 int elements
= dsize
/esize
;
8201 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8202 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8205 if (extract32(immh
, 3, 1) && !is_q
) {
8206 unallocated_encoding(s
);
8210 if (size
> 3 && !is_q
) {
8211 unallocated_encoding(s
);
8215 if (!fp_access_check(s
)) {
8219 for (i
= 0; i
< elements
; i
++) {
8220 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
8222 read_vec_element(s
, tcg_rd
, rd
, i
, size
);
8225 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
8227 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
8231 clear_vec_high(s
, rd
);
8235 /* USHLL/SHLL - Vector shift left with widening */
8236 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
8237 int immh
, int immb
, int opcode
, int rn
, int rd
)
8239 int size
= 32 - clz32(immh
) - 1;
8240 int immhb
= immh
<< 3 | immb
;
8241 int shift
= immhb
- (8 << size
);
8243 int esize
= 8 << size
;
8244 int elements
= dsize
/esize
;
8245 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8246 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8250 unallocated_encoding(s
);
8254 if (!fp_access_check(s
)) {
8258 /* For the LL variants the store is larger than the load,
8259 * so if rd == rn we would overwrite parts of our input.
8260 * So load everything right now and use shifts in the main loop.
8262 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
8264 for (i
= 0; i
< elements
; i
++) {
8265 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
8266 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
8267 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
8268 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
8272 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
8273 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
8274 int immh
, int immb
, int opcode
, int rn
, int rd
)
8276 int immhb
= immh
<< 3 | immb
;
8277 int size
= 32 - clz32(immh
) - 1;
8279 int esize
= 8 << size
;
8280 int elements
= dsize
/esize
;
8281 int shift
= (2 * esize
) - immhb
;
8282 bool round
= extract32(opcode
, 0, 1);
8283 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
8287 if (extract32(immh
, 3, 1)) {
8288 unallocated_encoding(s
);
8292 if (!fp_access_check(s
)) {
8296 tcg_rn
= tcg_temp_new_i64();
8297 tcg_rd
= tcg_temp_new_i64();
8298 tcg_final
= tcg_temp_new_i64();
8299 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
8302 uint64_t round_const
= 1ULL << (shift
- 1);
8303 tcg_round
= tcg_const_i64(round_const
);
8305 TCGV_UNUSED_I64(tcg_round
);
8308 for (i
= 0; i
< elements
; i
++) {
8309 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
8310 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8311 false, true, size
+1, shift
);
8313 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8317 clear_vec_high(s
, rd
);
8318 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8320 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8324 tcg_temp_free_i64(tcg_round
);
8326 tcg_temp_free_i64(tcg_rn
);
8327 tcg_temp_free_i64(tcg_rd
);
8328 tcg_temp_free_i64(tcg_final
);
8333 /* C3.6.14 AdvSIMD shift by immediate
8334 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
8335 * +---+---+---+-------------+------+------+--------+---+------+------+
8336 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
8337 * +---+---+---+-------------+------+------+--------+---+------+------+
8339 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
8341 int rd
= extract32(insn
, 0, 5);
8342 int rn
= extract32(insn
, 5, 5);
8343 int opcode
= extract32(insn
, 11, 5);
8344 int immb
= extract32(insn
, 16, 3);
8345 int immh
= extract32(insn
, 19, 4);
8346 bool is_u
= extract32(insn
, 29, 1);
8347 bool is_q
= extract32(insn
, 30, 1);
8350 case 0x08: /* SRI */
8352 unallocated_encoding(s
);
8356 case 0x00: /* SSHR / USHR */
8357 case 0x02: /* SSRA / USRA (accumulate) */
8358 case 0x04: /* SRSHR / URSHR (rounding) */
8359 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8360 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8362 case 0x0a: /* SHL / SLI */
8363 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8365 case 0x10: /* SHRN */
8366 case 0x11: /* RSHRN / SQRSHRUN */
8368 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
8371 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
8374 case 0x12: /* SQSHRN / UQSHRN */
8375 case 0x13: /* SQRSHRN / UQRSHRN */
8376 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
8379 case 0x14: /* SSHLL / USHLL */
8380 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8382 case 0x1c: /* SCVTF / UCVTF */
8383 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
8386 case 0xc: /* SQSHLU */
8388 unallocated_encoding(s
);
8391 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
8393 case 0xe: /* SQSHL, UQSHL */
8394 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
8396 case 0x1f: /* FCVTZS/ FCVTZU */
8397 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
8400 unallocated_encoding(s
);
8405 /* Generate code to do a "long" addition or subtraction, ie one done in
8406 * TCGv_i64 on vector lanes twice the width specified by size.
8408 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
8409 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
8411 static NeonGenTwo64OpFn
* const fns
[3][2] = {
8412 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
8413 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
8414 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
8416 NeonGenTwo64OpFn
*genfn
;
8419 genfn
= fns
[size
][is_sub
];
8420 genfn(tcg_res
, tcg_op1
, tcg_op2
);
8423 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
8424 int opcode
, int rd
, int rn
, int rm
)
8426 /* 3-reg-different widening insns: 64 x 64 -> 128 */
8427 TCGv_i64 tcg_res
[2];
8430 tcg_res
[0] = tcg_temp_new_i64();
8431 tcg_res
[1] = tcg_temp_new_i64();
8433 /* Does this op do an adding accumulate, a subtracting accumulate,
8434 * or no accumulate at all?
8452 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8453 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8456 /* size == 2 means two 32x32->64 operations; this is worth special
8457 * casing because we can generally handle it inline.
8460 for (pass
= 0; pass
< 2; pass
++) {
8461 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8462 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8463 TCGv_i64 tcg_passres
;
8464 TCGMemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
8466 int elt
= pass
+ is_q
* 2;
8468 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
8469 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
8472 tcg_passres
= tcg_res
[pass
];
8474 tcg_passres
= tcg_temp_new_i64();
8478 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8479 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8481 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8482 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8484 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8485 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8487 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
8488 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
8490 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
8491 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
8492 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
8494 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
8495 tcg_temp_free_i64(tcg_tmp1
);
8496 tcg_temp_free_i64(tcg_tmp2
);
8499 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8500 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8501 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8502 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8504 case 9: /* SQDMLAL, SQDMLAL2 */
8505 case 11: /* SQDMLSL, SQDMLSL2 */
8506 case 13: /* SQDMULL, SQDMULL2 */
8507 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8508 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
8509 tcg_passres
, tcg_passres
);
8512 g_assert_not_reached();
8515 if (opcode
== 9 || opcode
== 11) {
8516 /* saturating accumulate ops */
8518 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
8520 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
8521 tcg_res
[pass
], tcg_passres
);
8522 } else if (accop
> 0) {
8523 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
8524 } else if (accop
< 0) {
8525 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
8529 tcg_temp_free_i64(tcg_passres
);
8532 tcg_temp_free_i64(tcg_op1
);
8533 tcg_temp_free_i64(tcg_op2
);
8536 /* size 0 or 1, generally helper functions */
8537 for (pass
= 0; pass
< 2; pass
++) {
8538 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8539 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8540 TCGv_i64 tcg_passres
;
8541 int elt
= pass
+ is_q
* 2;
8543 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
8544 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
8547 tcg_passres
= tcg_res
[pass
];
8549 tcg_passres
= tcg_temp_new_i64();
8553 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8554 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8556 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
8557 static NeonGenWidenFn
* const widenfns
[2][2] = {
8558 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
8559 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
8561 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
8563 widenfn(tcg_op2_64
, tcg_op2
);
8564 widenfn(tcg_passres
, tcg_op1
);
8565 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
8566 tcg_passres
, tcg_op2_64
);
8567 tcg_temp_free_i64(tcg_op2_64
);
8570 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8571 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8574 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
8576 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8580 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
8582 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
8586 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8587 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8588 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8591 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
8593 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
8597 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
8599 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8603 case 9: /* SQDMLAL, SQDMLAL2 */
8604 case 11: /* SQDMLSL, SQDMLSL2 */
8605 case 13: /* SQDMULL, SQDMULL2 */
8607 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8608 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
8609 tcg_passres
, tcg_passres
);
8611 case 14: /* PMULL */
8613 gen_helper_neon_mull_p8(tcg_passres
, tcg_op1
, tcg_op2
);
8616 g_assert_not_reached();
8618 tcg_temp_free_i32(tcg_op1
);
8619 tcg_temp_free_i32(tcg_op2
);
8622 if (opcode
== 9 || opcode
== 11) {
8623 /* saturating accumulate ops */
8625 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
8627 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
8631 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
8632 tcg_res
[pass
], tcg_passres
);
8634 tcg_temp_free_i64(tcg_passres
);
8639 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8640 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8641 tcg_temp_free_i64(tcg_res
[0]);
8642 tcg_temp_free_i64(tcg_res
[1]);
8645 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
8646 int opcode
, int rd
, int rn
, int rm
)
8648 TCGv_i64 tcg_res
[2];
8649 int part
= is_q
? 2 : 0;
8652 for (pass
= 0; pass
< 2; pass
++) {
8653 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8654 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8655 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
8656 static NeonGenWidenFn
* const widenfns
[3][2] = {
8657 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
8658 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
8659 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
8661 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
8663 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8664 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
8665 widenfn(tcg_op2_wide
, tcg_op2
);
8666 tcg_temp_free_i32(tcg_op2
);
8667 tcg_res
[pass
] = tcg_temp_new_i64();
8668 gen_neon_addl(size
, (opcode
== 3),
8669 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
8670 tcg_temp_free_i64(tcg_op1
);
8671 tcg_temp_free_i64(tcg_op2_wide
);
8674 for (pass
= 0; pass
< 2; pass
++) {
8675 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8676 tcg_temp_free_i64(tcg_res
[pass
]);
8680 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
8682 tcg_gen_addi_i64(in
, in
, 1U << 31);
8683 tcg_gen_extrh_i64_i32(res
, in
);
8686 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
8687 int opcode
, int rd
, int rn
, int rm
)
8689 TCGv_i32 tcg_res
[2];
8690 int part
= is_q
? 2 : 0;
8693 for (pass
= 0; pass
< 2; pass
++) {
8694 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8695 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8696 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
8697 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
8698 { gen_helper_neon_narrow_high_u8
,
8699 gen_helper_neon_narrow_round_high_u8
},
8700 { gen_helper_neon_narrow_high_u16
,
8701 gen_helper_neon_narrow_round_high_u16
},
8702 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
8704 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
8706 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8707 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8709 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
8711 tcg_temp_free_i64(tcg_op1
);
8712 tcg_temp_free_i64(tcg_op2
);
8714 tcg_res
[pass
] = tcg_temp_new_i32();
8715 gennarrow(tcg_res
[pass
], tcg_wideres
);
8716 tcg_temp_free_i64(tcg_wideres
);
8719 for (pass
= 0; pass
< 2; pass
++) {
8720 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
8721 tcg_temp_free_i32(tcg_res
[pass
]);
8724 clear_vec_high(s
, rd
);
8728 static void handle_pmull_64(DisasContext
*s
, int is_q
, int rd
, int rn
, int rm
)
8730 /* PMULL of 64 x 64 -> 128 is an odd special case because it
8731 * is the only three-reg-diff instruction which produces a
8732 * 128-bit wide result from a single operation. However since
8733 * it's possible to calculate the two halves more or less
8734 * separately we just use two helper calls.
8736 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8737 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8738 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8740 read_vec_element(s
, tcg_op1
, rn
, is_q
, MO_64
);
8741 read_vec_element(s
, tcg_op2
, rm
, is_q
, MO_64
);
8742 gen_helper_neon_pmull_64_lo(tcg_res
, tcg_op1
, tcg_op2
);
8743 write_vec_element(s
, tcg_res
, rd
, 0, MO_64
);
8744 gen_helper_neon_pmull_64_hi(tcg_res
, tcg_op1
, tcg_op2
);
8745 write_vec_element(s
, tcg_res
, rd
, 1, MO_64
);
8747 tcg_temp_free_i64(tcg_op1
);
8748 tcg_temp_free_i64(tcg_op2
);
8749 tcg_temp_free_i64(tcg_res
);
8752 /* C3.6.15 AdvSIMD three different
8753 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
8754 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8755 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
8756 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8758 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
8760 /* Instructions in this group fall into three basic classes
8761 * (in each case with the operation working on each element in
8762 * the input vectors):
8763 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
8765 * (2) wide 64 x 128 -> 128
8766 * (3) narrowing 128 x 128 -> 64
8767 * Here we do initial decode, catch unallocated cases and
8768 * dispatch to separate functions for each class.
8770 int is_q
= extract32(insn
, 30, 1);
8771 int is_u
= extract32(insn
, 29, 1);
8772 int size
= extract32(insn
, 22, 2);
8773 int opcode
= extract32(insn
, 12, 4);
8774 int rm
= extract32(insn
, 16, 5);
8775 int rn
= extract32(insn
, 5, 5);
8776 int rd
= extract32(insn
, 0, 5);
8779 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
8780 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
8781 /* 64 x 128 -> 128 */
8783 unallocated_encoding(s
);
8786 if (!fp_access_check(s
)) {
8789 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8791 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
8792 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
8793 /* 128 x 128 -> 64 */
8795 unallocated_encoding(s
);
8798 if (!fp_access_check(s
)) {
8801 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8803 case 14: /* PMULL, PMULL2 */
8804 if (is_u
|| size
== 1 || size
== 2) {
8805 unallocated_encoding(s
);
8809 if (!arm_dc_feature(s
, ARM_FEATURE_V8_PMULL
)) {
8810 unallocated_encoding(s
);
8813 if (!fp_access_check(s
)) {
8816 handle_pmull_64(s
, is_q
, rd
, rn
, rm
);
8820 case 9: /* SQDMLAL, SQDMLAL2 */
8821 case 11: /* SQDMLSL, SQDMLSL2 */
8822 case 13: /* SQDMULL, SQDMULL2 */
8823 if (is_u
|| size
== 0) {
8824 unallocated_encoding(s
);
8828 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8829 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8830 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8831 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8832 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8833 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8834 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
8835 /* 64 x 64 -> 128 */
8837 unallocated_encoding(s
);
8841 if (!fp_access_check(s
)) {
8845 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8848 /* opcode 15 not allocated */
8849 unallocated_encoding(s
);
8854 /* Logic op (opcode == 3) subgroup of C3.6.16. */
8855 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
8857 int rd
= extract32(insn
, 0, 5);
8858 int rn
= extract32(insn
, 5, 5);
8859 int rm
= extract32(insn
, 16, 5);
8860 int size
= extract32(insn
, 22, 2);
8861 bool is_u
= extract32(insn
, 29, 1);
8862 bool is_q
= extract32(insn
, 30, 1);
8863 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
8866 if (!fp_access_check(s
)) {
8870 tcg_op1
= tcg_temp_new_i64();
8871 tcg_op2
= tcg_temp_new_i64();
8872 tcg_res
[0] = tcg_temp_new_i64();
8873 tcg_res
[1] = tcg_temp_new_i64();
8875 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
8876 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8877 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8882 tcg_gen_and_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8885 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8888 tcg_gen_or_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8891 tcg_gen_orc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8896 /* B* ops need res loaded to operate on */
8897 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8902 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8904 case 1: /* BSL bitwise select */
8905 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_op2
);
8906 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
8907 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op1
);
8909 case 2: /* BIT, bitwise insert if true */
8910 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
8911 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_op2
);
8912 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
8914 case 3: /* BIF, bitwise insert if false */
8915 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
8916 tcg_gen_andc_i64(tcg_op1
, tcg_op1
, tcg_op2
);
8917 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
8923 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8925 tcg_gen_movi_i64(tcg_res
[1], 0);
8927 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8929 tcg_temp_free_i64(tcg_op1
);
8930 tcg_temp_free_i64(tcg_op2
);
8931 tcg_temp_free_i64(tcg_res
[0]);
8932 tcg_temp_free_i64(tcg_res
[1]);
8935 /* Helper functions for 32 bit comparisons */
8936 static void gen_max_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
8938 tcg_gen_movcond_i32(TCG_COND_GE
, res
, op1
, op2
, op1
, op2
);
8941 static void gen_max_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
8943 tcg_gen_movcond_i32(TCG_COND_GEU
, res
, op1
, op2
, op1
, op2
);
8946 static void gen_min_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
8948 tcg_gen_movcond_i32(TCG_COND_LE
, res
, op1
, op2
, op1
, op2
);
8951 static void gen_min_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
8953 tcg_gen_movcond_i32(TCG_COND_LEU
, res
, op1
, op2
, op1
, op2
);
8956 /* Pairwise op subgroup of C3.6.16.
8958 * This is called directly or via the handle_3same_float for float pairwise
8959 * operations where the opcode and size are calculated differently.
8961 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
8962 int size
, int rn
, int rm
, int rd
)
8967 /* Floating point operations need fpst */
8968 if (opcode
>= 0x58) {
8969 fpst
= get_fpstatus_ptr();
8971 TCGV_UNUSED_PTR(fpst
);
8974 if (!fp_access_check(s
)) {
8978 /* These operations work on the concatenated rm:rn, with each pair of
8979 * adjacent elements being operated on to produce an element in the result.
8982 TCGv_i64 tcg_res
[2];
8984 for (pass
= 0; pass
< 2; pass
++) {
8985 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8986 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8987 int passreg
= (pass
== 0) ? rn
: rm
;
8989 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
8990 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
8991 tcg_res
[pass
] = tcg_temp_new_i64();
8994 case 0x17: /* ADDP */
8995 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8997 case 0x58: /* FMAXNMP */
8998 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9000 case 0x5a: /* FADDP */
9001 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9003 case 0x5e: /* FMAXP */
9004 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9006 case 0x78: /* FMINNMP */
9007 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9009 case 0x7e: /* FMINP */
9010 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9013 g_assert_not_reached();
9016 tcg_temp_free_i64(tcg_op1
);
9017 tcg_temp_free_i64(tcg_op2
);
9020 for (pass
= 0; pass
< 2; pass
++) {
9021 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9022 tcg_temp_free_i64(tcg_res
[pass
]);
9025 int maxpass
= is_q
? 4 : 2;
9026 TCGv_i32 tcg_res
[4];
9028 for (pass
= 0; pass
< maxpass
; pass
++) {
9029 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9030 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9031 NeonGenTwoOpFn
*genfn
= NULL
;
9032 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
9033 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
9035 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
9036 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
9037 tcg_res
[pass
] = tcg_temp_new_i32();
9040 case 0x17: /* ADDP */
9042 static NeonGenTwoOpFn
* const fns
[3] = {
9043 gen_helper_neon_padd_u8
,
9044 gen_helper_neon_padd_u16
,
9050 case 0x14: /* SMAXP, UMAXP */
9052 static NeonGenTwoOpFn
* const fns
[3][2] = {
9053 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
9054 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
9055 { gen_max_s32
, gen_max_u32
},
9057 genfn
= fns
[size
][u
];
9060 case 0x15: /* SMINP, UMINP */
9062 static NeonGenTwoOpFn
* const fns
[3][2] = {
9063 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
9064 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
9065 { gen_min_s32
, gen_min_u32
},
9067 genfn
= fns
[size
][u
];
9070 /* The FP operations are all on single floats (32 bit) */
9071 case 0x58: /* FMAXNMP */
9072 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9074 case 0x5a: /* FADDP */
9075 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9077 case 0x5e: /* FMAXP */
9078 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9080 case 0x78: /* FMINNMP */
9081 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9083 case 0x7e: /* FMINP */
9084 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9087 g_assert_not_reached();
9090 /* FP ops called directly, otherwise call now */
9092 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9095 tcg_temp_free_i32(tcg_op1
);
9096 tcg_temp_free_i32(tcg_op2
);
9099 for (pass
= 0; pass
< maxpass
; pass
++) {
9100 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
9101 tcg_temp_free_i32(tcg_res
[pass
]);
9104 clear_vec_high(s
, rd
);
9108 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
9109 tcg_temp_free_ptr(fpst
);
9113 /* Floating point op subgroup of C3.6.16. */
9114 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
9116 /* For floating point ops, the U, size[1] and opcode bits
9117 * together indicate the operation. size[0] indicates single
9120 int fpopcode
= extract32(insn
, 11, 5)
9121 | (extract32(insn
, 23, 1) << 5)
9122 | (extract32(insn
, 29, 1) << 6);
9123 int is_q
= extract32(insn
, 30, 1);
9124 int size
= extract32(insn
, 22, 1);
9125 int rm
= extract32(insn
, 16, 5);
9126 int rn
= extract32(insn
, 5, 5);
9127 int rd
= extract32(insn
, 0, 5);
9129 int datasize
= is_q
? 128 : 64;
9130 int esize
= 32 << size
;
9131 int elements
= datasize
/ esize
;
9133 if (size
== 1 && !is_q
) {
9134 unallocated_encoding(s
);
9139 case 0x58: /* FMAXNMP */
9140 case 0x5a: /* FADDP */
9141 case 0x5e: /* FMAXP */
9142 case 0x78: /* FMINNMP */
9143 case 0x7e: /* FMINP */
9144 if (size
&& !is_q
) {
9145 unallocated_encoding(s
);
9148 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
9151 case 0x1b: /* FMULX */
9152 case 0x1f: /* FRECPS */
9153 case 0x3f: /* FRSQRTS */
9154 case 0x5d: /* FACGE */
9155 case 0x7d: /* FACGT */
9156 case 0x19: /* FMLA */
9157 case 0x39: /* FMLS */
9158 case 0x18: /* FMAXNM */
9159 case 0x1a: /* FADD */
9160 case 0x1c: /* FCMEQ */
9161 case 0x1e: /* FMAX */
9162 case 0x38: /* FMINNM */
9163 case 0x3a: /* FSUB */
9164 case 0x3e: /* FMIN */
9165 case 0x5b: /* FMUL */
9166 case 0x5c: /* FCMGE */
9167 case 0x5f: /* FDIV */
9168 case 0x7a: /* FABD */
9169 case 0x7c: /* FCMGT */
9170 if (!fp_access_check(s
)) {
9174 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
9177 unallocated_encoding(s
);
9182 /* Integer op subgroup of C3.6.16. */
9183 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
9185 int is_q
= extract32(insn
, 30, 1);
9186 int u
= extract32(insn
, 29, 1);
9187 int size
= extract32(insn
, 22, 2);
9188 int opcode
= extract32(insn
, 11, 5);
9189 int rm
= extract32(insn
, 16, 5);
9190 int rn
= extract32(insn
, 5, 5);
9191 int rd
= extract32(insn
, 0, 5);
9195 case 0x13: /* MUL, PMUL */
9196 if (u
&& size
!= 0) {
9197 unallocated_encoding(s
);
9201 case 0x0: /* SHADD, UHADD */
9202 case 0x2: /* SRHADD, URHADD */
9203 case 0x4: /* SHSUB, UHSUB */
9204 case 0xc: /* SMAX, UMAX */
9205 case 0xd: /* SMIN, UMIN */
9206 case 0xe: /* SABD, UABD */
9207 case 0xf: /* SABA, UABA */
9208 case 0x12: /* MLA, MLS */
9210 unallocated_encoding(s
);
9214 case 0x16: /* SQDMULH, SQRDMULH */
9215 if (size
== 0 || size
== 3) {
9216 unallocated_encoding(s
);
9221 if (size
== 3 && !is_q
) {
9222 unallocated_encoding(s
);
9228 if (!fp_access_check(s
)) {
9234 for (pass
= 0; pass
< 2; pass
++) {
9235 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9236 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9237 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9239 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9240 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
9242 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
9244 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9246 tcg_temp_free_i64(tcg_res
);
9247 tcg_temp_free_i64(tcg_op1
);
9248 tcg_temp_free_i64(tcg_op2
);
9251 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
9252 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9253 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9254 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9255 NeonGenTwoOpFn
*genfn
= NULL
;
9256 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
9258 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
9259 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
9262 case 0x0: /* SHADD, UHADD */
9264 static NeonGenTwoOpFn
* const fns
[3][2] = {
9265 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
9266 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
9267 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
9269 genfn
= fns
[size
][u
];
9272 case 0x1: /* SQADD, UQADD */
9274 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9275 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9276 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9277 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9279 genenvfn
= fns
[size
][u
];
9282 case 0x2: /* SRHADD, URHADD */
9284 static NeonGenTwoOpFn
* const fns
[3][2] = {
9285 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
9286 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
9287 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
9289 genfn
= fns
[size
][u
];
9292 case 0x4: /* SHSUB, UHSUB */
9294 static NeonGenTwoOpFn
* const fns
[3][2] = {
9295 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
9296 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
9297 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
9299 genfn
= fns
[size
][u
];
9302 case 0x5: /* SQSUB, UQSUB */
9304 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9305 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9306 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9307 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9309 genenvfn
= fns
[size
][u
];
9312 case 0x6: /* CMGT, CMHI */
9314 static NeonGenTwoOpFn
* const fns
[3][2] = {
9315 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_u8
},
9316 { gen_helper_neon_cgt_s16
, gen_helper_neon_cgt_u16
},
9317 { gen_helper_neon_cgt_s32
, gen_helper_neon_cgt_u32
},
9319 genfn
= fns
[size
][u
];
9322 case 0x7: /* CMGE, CMHS */
9324 static NeonGenTwoOpFn
* const fns
[3][2] = {
9325 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_u8
},
9326 { gen_helper_neon_cge_s16
, gen_helper_neon_cge_u16
},
9327 { gen_helper_neon_cge_s32
, gen_helper_neon_cge_u32
},
9329 genfn
= fns
[size
][u
];
9332 case 0x8: /* SSHL, USHL */
9334 static NeonGenTwoOpFn
* const fns
[3][2] = {
9335 { gen_helper_neon_shl_s8
, gen_helper_neon_shl_u8
},
9336 { gen_helper_neon_shl_s16
, gen_helper_neon_shl_u16
},
9337 { gen_helper_neon_shl_s32
, gen_helper_neon_shl_u32
},
9339 genfn
= fns
[size
][u
];
9342 case 0x9: /* SQSHL, UQSHL */
9344 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9345 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9346 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9347 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9349 genenvfn
= fns
[size
][u
];
9352 case 0xa: /* SRSHL, URSHL */
9354 static NeonGenTwoOpFn
* const fns
[3][2] = {
9355 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
9356 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
9357 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
9359 genfn
= fns
[size
][u
];
9362 case 0xb: /* SQRSHL, UQRSHL */
9364 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9365 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9366 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9367 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9369 genenvfn
= fns
[size
][u
];
9372 case 0xc: /* SMAX, UMAX */
9374 static NeonGenTwoOpFn
* const fns
[3][2] = {
9375 { gen_helper_neon_max_s8
, gen_helper_neon_max_u8
},
9376 { gen_helper_neon_max_s16
, gen_helper_neon_max_u16
},
9377 { gen_max_s32
, gen_max_u32
},
9379 genfn
= fns
[size
][u
];
9383 case 0xd: /* SMIN, UMIN */
9385 static NeonGenTwoOpFn
* const fns
[3][2] = {
9386 { gen_helper_neon_min_s8
, gen_helper_neon_min_u8
},
9387 { gen_helper_neon_min_s16
, gen_helper_neon_min_u16
},
9388 { gen_min_s32
, gen_min_u32
},
9390 genfn
= fns
[size
][u
];
9393 case 0xe: /* SABD, UABD */
9394 case 0xf: /* SABA, UABA */
9396 static NeonGenTwoOpFn
* const fns
[3][2] = {
9397 { gen_helper_neon_abd_s8
, gen_helper_neon_abd_u8
},
9398 { gen_helper_neon_abd_s16
, gen_helper_neon_abd_u16
},
9399 { gen_helper_neon_abd_s32
, gen_helper_neon_abd_u32
},
9401 genfn
= fns
[size
][u
];
9404 case 0x10: /* ADD, SUB */
9406 static NeonGenTwoOpFn
* const fns
[3][2] = {
9407 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
9408 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
9409 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
9411 genfn
= fns
[size
][u
];
9414 case 0x11: /* CMTST, CMEQ */
9416 static NeonGenTwoOpFn
* const fns
[3][2] = {
9417 { gen_helper_neon_tst_u8
, gen_helper_neon_ceq_u8
},
9418 { gen_helper_neon_tst_u16
, gen_helper_neon_ceq_u16
},
9419 { gen_helper_neon_tst_u32
, gen_helper_neon_ceq_u32
},
9421 genfn
= fns
[size
][u
];
9424 case 0x13: /* MUL, PMUL */
9428 genfn
= gen_helper_neon_mul_p8
;
9431 /* fall through : MUL */
9432 case 0x12: /* MLA, MLS */
9434 static NeonGenTwoOpFn
* const fns
[3] = {
9435 gen_helper_neon_mul_u8
,
9436 gen_helper_neon_mul_u16
,
9442 case 0x16: /* SQDMULH, SQRDMULH */
9444 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9445 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9446 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9448 assert(size
== 1 || size
== 2);
9449 genenvfn
= fns
[size
- 1][u
];
9453 g_assert_not_reached();
9457 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
9459 genfn(tcg_res
, tcg_op1
, tcg_op2
);
9462 if (opcode
== 0xf || opcode
== 0x12) {
9463 /* SABA, UABA, MLA, MLS: accumulating ops */
9464 static NeonGenTwoOpFn
* const fns
[3][2] = {
9465 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
9466 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
9467 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
9469 bool is_sub
= (opcode
== 0x12 && u
); /* MLS */
9471 genfn
= fns
[size
][is_sub
];
9472 read_vec_element_i32(s
, tcg_op1
, rd
, pass
, MO_32
);
9473 genfn(tcg_res
, tcg_op1
, tcg_res
);
9476 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9478 tcg_temp_free_i32(tcg_res
);
9479 tcg_temp_free_i32(tcg_op1
);
9480 tcg_temp_free_i32(tcg_op2
);
9485 clear_vec_high(s
, rd
);
9489 /* C3.6.16 AdvSIMD three same
9490 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9491 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9492 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9493 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9495 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
9497 int opcode
= extract32(insn
, 11, 5);
9500 case 0x3: /* logic ops */
9501 disas_simd_3same_logic(s
, insn
);
9503 case 0x17: /* ADDP */
9504 case 0x14: /* SMAXP, UMAXP */
9505 case 0x15: /* SMINP, UMINP */
9507 /* Pairwise operations */
9508 int is_q
= extract32(insn
, 30, 1);
9509 int u
= extract32(insn
, 29, 1);
9510 int size
= extract32(insn
, 22, 2);
9511 int rm
= extract32(insn
, 16, 5);
9512 int rn
= extract32(insn
, 5, 5);
9513 int rd
= extract32(insn
, 0, 5);
9514 if (opcode
== 0x17) {
9515 if (u
|| (size
== 3 && !is_q
)) {
9516 unallocated_encoding(s
);
9521 unallocated_encoding(s
);
9525 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
9529 /* floating point ops, sz[1] and U are part of opcode */
9530 disas_simd_3same_float(s
, insn
);
9533 disas_simd_3same_int(s
, insn
);
9538 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
9539 int size
, int rn
, int rd
)
9541 /* Handle 2-reg-misc ops which are widening (so each size element
9542 * in the source becomes a 2*size element in the destination.
9543 * The only instruction like this is FCVTL.
9548 /* 32 -> 64 bit fp conversion */
9549 TCGv_i64 tcg_res
[2];
9550 int srcelt
= is_q
? 2 : 0;
9552 for (pass
= 0; pass
< 2; pass
++) {
9553 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9554 tcg_res
[pass
] = tcg_temp_new_i64();
9556 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
9557 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
9558 tcg_temp_free_i32(tcg_op
);
9560 for (pass
= 0; pass
< 2; pass
++) {
9561 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9562 tcg_temp_free_i64(tcg_res
[pass
]);
9565 /* 16 -> 32 bit fp conversion */
9566 int srcelt
= is_q
? 4 : 0;
9567 TCGv_i32 tcg_res
[4];
9569 for (pass
= 0; pass
< 4; pass
++) {
9570 tcg_res
[pass
] = tcg_temp_new_i32();
9572 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
9573 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
9576 for (pass
= 0; pass
< 4; pass
++) {
9577 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
9578 tcg_temp_free_i32(tcg_res
[pass
]);
9583 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
9584 bool is_q
, int size
, int rn
, int rd
)
9586 int op
= (opcode
<< 1) | u
;
9587 int opsz
= op
+ size
;
9588 int grp_size
= 3 - opsz
;
9589 int dsize
= is_q
? 128 : 64;
9593 unallocated_encoding(s
);
9597 if (!fp_access_check(s
)) {
9602 /* Special case bytes, use bswap op on each group of elements */
9603 int groups
= dsize
/ (8 << grp_size
);
9605 for (i
= 0; i
< groups
; i
++) {
9606 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
9608 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
9611 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
9614 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
9617 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
9620 g_assert_not_reached();
9622 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
9623 tcg_temp_free_i64(tcg_tmp
);
9626 clear_vec_high(s
, rd
);
9629 int revmask
= (1 << grp_size
) - 1;
9630 int esize
= 8 << size
;
9631 int elements
= dsize
/ esize
;
9632 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9633 TCGv_i64 tcg_rd
= tcg_const_i64(0);
9634 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
9636 for (i
= 0; i
< elements
; i
++) {
9637 int e_rev
= (i
& 0xf) ^ revmask
;
9638 int off
= e_rev
* esize
;
9639 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
9641 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
9642 tcg_rn
, off
- 64, esize
);
9644 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
9647 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
9648 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
9650 tcg_temp_free_i64(tcg_rd_hi
);
9651 tcg_temp_free_i64(tcg_rd
);
9652 tcg_temp_free_i64(tcg_rn
);
9656 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
9657 bool is_q
, int size
, int rn
, int rd
)
9659 /* Implement the pairwise operations from 2-misc:
9660 * SADDLP, UADDLP, SADALP, UADALP.
9661 * These all add pairs of elements in the input to produce a
9662 * double-width result element in the output (possibly accumulating).
9664 bool accum
= (opcode
== 0x6);
9665 int maxpass
= is_q
? 2 : 1;
9667 TCGv_i64 tcg_res
[2];
9670 /* 32 + 32 -> 64 op */
9671 TCGMemOp memop
= size
+ (u
? 0 : MO_SIGN
);
9673 for (pass
= 0; pass
< maxpass
; pass
++) {
9674 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9675 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9677 tcg_res
[pass
] = tcg_temp_new_i64();
9679 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
9680 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
9681 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9683 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
9684 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
9687 tcg_temp_free_i64(tcg_op1
);
9688 tcg_temp_free_i64(tcg_op2
);
9691 for (pass
= 0; pass
< maxpass
; pass
++) {
9692 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9693 NeonGenOneOpFn
*genfn
;
9694 static NeonGenOneOpFn
* const fns
[2][2] = {
9695 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
9696 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
9699 genfn
= fns
[size
][u
];
9701 tcg_res
[pass
] = tcg_temp_new_i64();
9703 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9704 genfn(tcg_res
[pass
], tcg_op
);
9707 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
9709 gen_helper_neon_addl_u16(tcg_res
[pass
],
9710 tcg_res
[pass
], tcg_op
);
9712 gen_helper_neon_addl_u32(tcg_res
[pass
],
9713 tcg_res
[pass
], tcg_op
);
9716 tcg_temp_free_i64(tcg_op
);
9720 tcg_res
[1] = tcg_const_i64(0);
9722 for (pass
= 0; pass
< 2; pass
++) {
9723 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9724 tcg_temp_free_i64(tcg_res
[pass
]);
9728 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
9730 /* Implement SHLL and SHLL2 */
9732 int part
= is_q
? 2 : 0;
9733 TCGv_i64 tcg_res
[2];
9735 for (pass
= 0; pass
< 2; pass
++) {
9736 static NeonGenWidenFn
* const widenfns
[3] = {
9737 gen_helper_neon_widen_u8
,
9738 gen_helper_neon_widen_u16
,
9739 tcg_gen_extu_i32_i64
,
9741 NeonGenWidenFn
*widenfn
= widenfns
[size
];
9742 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9744 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
9745 tcg_res
[pass
] = tcg_temp_new_i64();
9746 widenfn(tcg_res
[pass
], tcg_op
);
9747 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
9749 tcg_temp_free_i32(tcg_op
);
9752 for (pass
= 0; pass
< 2; pass
++) {
9753 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9754 tcg_temp_free_i64(tcg_res
[pass
]);
9758 /* C3.6.17 AdvSIMD two reg misc
9759 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9760 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9761 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9762 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9764 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
9766 int size
= extract32(insn
, 22, 2);
9767 int opcode
= extract32(insn
, 12, 5);
9768 bool u
= extract32(insn
, 29, 1);
9769 bool is_q
= extract32(insn
, 30, 1);
9770 int rn
= extract32(insn
, 5, 5);
9771 int rd
= extract32(insn
, 0, 5);
9772 bool need_fpstatus
= false;
9773 bool need_rmode
= false;
9776 TCGv_ptr tcg_fpstatus
;
9779 case 0x0: /* REV64, REV32 */
9780 case 0x1: /* REV16 */
9781 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
9783 case 0x5: /* CNT, NOT, RBIT */
9784 if (u
&& size
== 0) {
9785 /* NOT: adjust size so we can use the 64-bits-at-a-time loop. */
9788 } else if (u
&& size
== 1) {
9791 } else if (!u
&& size
== 0) {
9795 unallocated_encoding(s
);
9797 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
9798 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
9800 unallocated_encoding(s
);
9803 if (!fp_access_check(s
)) {
9807 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
9809 case 0x4: /* CLS, CLZ */
9811 unallocated_encoding(s
);
9815 case 0x2: /* SADDLP, UADDLP */
9816 case 0x6: /* SADALP, UADALP */
9818 unallocated_encoding(s
);
9821 if (!fp_access_check(s
)) {
9824 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
9826 case 0x13: /* SHLL, SHLL2 */
9827 if (u
== 0 || size
== 3) {
9828 unallocated_encoding(s
);
9831 if (!fp_access_check(s
)) {
9834 handle_shll(s
, is_q
, size
, rn
, rd
);
9836 case 0xa: /* CMLT */
9838 unallocated_encoding(s
);
9842 case 0x8: /* CMGT, CMGE */
9843 case 0x9: /* CMEQ, CMLE */
9844 case 0xb: /* ABS, NEG */
9845 if (size
== 3 && !is_q
) {
9846 unallocated_encoding(s
);
9850 case 0x3: /* SUQADD, USQADD */
9851 if (size
== 3 && !is_q
) {
9852 unallocated_encoding(s
);
9855 if (!fp_access_check(s
)) {
9858 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
9860 case 0x7: /* SQABS, SQNEG */
9861 if (size
== 3 && !is_q
) {
9862 unallocated_encoding(s
);
9870 /* Floating point: U, size[1] and opcode indicate operation;
9871 * size[0] indicates single or double precision.
9873 int is_double
= extract32(size
, 0, 1);
9874 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
9875 size
= is_double
? 3 : 2;
9877 case 0x2f: /* FABS */
9878 case 0x6f: /* FNEG */
9879 if (size
== 3 && !is_q
) {
9880 unallocated_encoding(s
);
9884 case 0x1d: /* SCVTF */
9885 case 0x5d: /* UCVTF */
9887 bool is_signed
= (opcode
== 0x1d) ? true : false;
9888 int elements
= is_double
? 2 : is_q
? 4 : 2;
9889 if (is_double
&& !is_q
) {
9890 unallocated_encoding(s
);
9893 if (!fp_access_check(s
)) {
9896 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
9899 case 0x2c: /* FCMGT (zero) */
9900 case 0x2d: /* FCMEQ (zero) */
9901 case 0x2e: /* FCMLT (zero) */
9902 case 0x6c: /* FCMGE (zero) */
9903 case 0x6d: /* FCMLE (zero) */
9904 if (size
== 3 && !is_q
) {
9905 unallocated_encoding(s
);
9908 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
9910 case 0x7f: /* FSQRT */
9911 if (size
== 3 && !is_q
) {
9912 unallocated_encoding(s
);
9916 case 0x1a: /* FCVTNS */
9917 case 0x1b: /* FCVTMS */
9918 case 0x3a: /* FCVTPS */
9919 case 0x3b: /* FCVTZS */
9920 case 0x5a: /* FCVTNU */
9921 case 0x5b: /* FCVTMU */
9922 case 0x7a: /* FCVTPU */
9923 case 0x7b: /* FCVTZU */
9924 need_fpstatus
= true;
9926 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
9927 if (size
== 3 && !is_q
) {
9928 unallocated_encoding(s
);
9932 case 0x5c: /* FCVTAU */
9933 case 0x1c: /* FCVTAS */
9934 need_fpstatus
= true;
9936 rmode
= FPROUNDING_TIEAWAY
;
9937 if (size
== 3 && !is_q
) {
9938 unallocated_encoding(s
);
9942 case 0x3c: /* URECPE */
9944 unallocated_encoding(s
);
9948 case 0x3d: /* FRECPE */
9949 case 0x7d: /* FRSQRTE */
9950 if (size
== 3 && !is_q
) {
9951 unallocated_encoding(s
);
9954 if (!fp_access_check(s
)) {
9957 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
9959 case 0x56: /* FCVTXN, FCVTXN2 */
9961 unallocated_encoding(s
);
9965 case 0x16: /* FCVTN, FCVTN2 */
9966 /* handle_2misc_narrow does a 2*size -> size operation, but these
9967 * instructions encode the source size rather than dest size.
9969 if (!fp_access_check(s
)) {
9972 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
9974 case 0x17: /* FCVTL, FCVTL2 */
9975 if (!fp_access_check(s
)) {
9978 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
9980 case 0x18: /* FRINTN */
9981 case 0x19: /* FRINTM */
9982 case 0x38: /* FRINTP */
9983 case 0x39: /* FRINTZ */
9985 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
9987 case 0x59: /* FRINTX */
9988 case 0x79: /* FRINTI */
9989 need_fpstatus
= true;
9990 if (size
== 3 && !is_q
) {
9991 unallocated_encoding(s
);
9995 case 0x58: /* FRINTA */
9997 rmode
= FPROUNDING_TIEAWAY
;
9998 need_fpstatus
= true;
9999 if (size
== 3 && !is_q
) {
10000 unallocated_encoding(s
);
10004 case 0x7c: /* URSQRTE */
10006 unallocated_encoding(s
);
10009 need_fpstatus
= true;
10012 unallocated_encoding(s
);
10018 unallocated_encoding(s
);
10022 if (!fp_access_check(s
)) {
10026 if (need_fpstatus
) {
10027 tcg_fpstatus
= get_fpstatus_ptr();
10029 TCGV_UNUSED_PTR(tcg_fpstatus
);
10032 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
10033 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
10035 TCGV_UNUSED_I32(tcg_rmode
);
10039 /* All 64-bit element operations can be shared with scalar 2misc */
10042 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
10043 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10044 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10046 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10048 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
10049 tcg_rmode
, tcg_fpstatus
);
10051 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10053 tcg_temp_free_i64(tcg_res
);
10054 tcg_temp_free_i64(tcg_op
);
10059 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
10060 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10061 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10064 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
10067 /* Special cases for 32 bit elements */
10069 case 0xa: /* CMLT */
10070 /* 32 bit integer comparison against zero, result is
10071 * test ? (2^32 - 1) : 0. We implement via setcond(test)
10074 cond
= TCG_COND_LT
;
10076 tcg_gen_setcondi_i32(cond
, tcg_res
, tcg_op
, 0);
10077 tcg_gen_neg_i32(tcg_res
, tcg_res
);
10079 case 0x8: /* CMGT, CMGE */
10080 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
10082 case 0x9: /* CMEQ, CMLE */
10083 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
10085 case 0x4: /* CLS */
10087 gen_helper_clz32(tcg_res
, tcg_op
);
10089 gen_helper_cls32(tcg_res
, tcg_op
);
10092 case 0x7: /* SQABS, SQNEG */
10094 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
10096 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
10099 case 0xb: /* ABS, NEG */
10101 tcg_gen_neg_i32(tcg_res
, tcg_op
);
10103 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10104 tcg_gen_neg_i32(tcg_res
, tcg_op
);
10105 tcg_gen_movcond_i32(TCG_COND_GT
, tcg_res
, tcg_op
,
10106 tcg_zero
, tcg_op
, tcg_res
);
10107 tcg_temp_free_i32(tcg_zero
);
10110 case 0x2f: /* FABS */
10111 gen_helper_vfp_abss(tcg_res
, tcg_op
);
10113 case 0x6f: /* FNEG */
10114 gen_helper_vfp_negs(tcg_res
, tcg_op
);
10116 case 0x7f: /* FSQRT */
10117 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
10119 case 0x1a: /* FCVTNS */
10120 case 0x1b: /* FCVTMS */
10121 case 0x1c: /* FCVTAS */
10122 case 0x3a: /* FCVTPS */
10123 case 0x3b: /* FCVTZS */
10125 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10126 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
10127 tcg_shift
, tcg_fpstatus
);
10128 tcg_temp_free_i32(tcg_shift
);
10131 case 0x5a: /* FCVTNU */
10132 case 0x5b: /* FCVTMU */
10133 case 0x5c: /* FCVTAU */
10134 case 0x7a: /* FCVTPU */
10135 case 0x7b: /* FCVTZU */
10137 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10138 gen_helper_vfp_touls(tcg_res
, tcg_op
,
10139 tcg_shift
, tcg_fpstatus
);
10140 tcg_temp_free_i32(tcg_shift
);
10143 case 0x18: /* FRINTN */
10144 case 0x19: /* FRINTM */
10145 case 0x38: /* FRINTP */
10146 case 0x39: /* FRINTZ */
10147 case 0x58: /* FRINTA */
10148 case 0x79: /* FRINTI */
10149 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
10151 case 0x59: /* FRINTX */
10152 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
10154 case 0x7c: /* URSQRTE */
10155 gen_helper_rsqrte_u32(tcg_res
, tcg_op
, tcg_fpstatus
);
10158 g_assert_not_reached();
10161 /* Use helpers for 8 and 16 bit elements */
10163 case 0x5: /* CNT, RBIT */
10164 /* For these two insns size is part of the opcode specifier
10165 * (handled earlier); they always operate on byte elements.
10168 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
10170 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
10173 case 0x7: /* SQABS, SQNEG */
10175 NeonGenOneOpEnvFn
*genfn
;
10176 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
10177 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
10178 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
10180 genfn
= fns
[size
][u
];
10181 genfn(tcg_res
, cpu_env
, tcg_op
);
10184 case 0x8: /* CMGT, CMGE */
10185 case 0x9: /* CMEQ, CMLE */
10186 case 0xa: /* CMLT */
10188 static NeonGenTwoOpFn
* const fns
[3][2] = {
10189 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_s16
},
10190 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_s16
},
10191 { gen_helper_neon_ceq_u8
, gen_helper_neon_ceq_u16
},
10193 NeonGenTwoOpFn
*genfn
;
10196 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10198 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
10199 comp
= (opcode
- 0x8) * 2 + u
;
10200 /* ...but LE, LT are implemented as reverse GE, GT */
10201 reverse
= (comp
> 2);
10205 genfn
= fns
[comp
][size
];
10207 genfn(tcg_res
, tcg_zero
, tcg_op
);
10209 genfn(tcg_res
, tcg_op
, tcg_zero
);
10211 tcg_temp_free_i32(tcg_zero
);
10214 case 0xb: /* ABS, NEG */
10216 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10218 gen_helper_neon_sub_u16(tcg_res
, tcg_zero
, tcg_op
);
10220 gen_helper_neon_sub_u8(tcg_res
, tcg_zero
, tcg_op
);
10222 tcg_temp_free_i32(tcg_zero
);
10225 gen_helper_neon_abs_s16(tcg_res
, tcg_op
);
10227 gen_helper_neon_abs_s8(tcg_res
, tcg_op
);
10231 case 0x4: /* CLS, CLZ */
10234 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
10236 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
10240 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
10242 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
10247 g_assert_not_reached();
10251 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10253 tcg_temp_free_i32(tcg_res
);
10254 tcg_temp_free_i32(tcg_op
);
10258 clear_vec_high(s
, rd
);
10262 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
10263 tcg_temp_free_i32(tcg_rmode
);
10265 if (need_fpstatus
) {
10266 tcg_temp_free_ptr(tcg_fpstatus
);
10270 /* C3.6.13 AdvSIMD scalar x indexed element
10271 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10272 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10273 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10274 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10275 * C3.6.18 AdvSIMD vector x indexed element
10276 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10277 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10278 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10279 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10281 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
10283 /* This encoding has two kinds of instruction:
10284 * normal, where we perform elt x idxelt => elt for each
10285 * element in the vector
10286 * long, where we perform elt x idxelt and generate a result of
10287 * double the width of the input element
10288 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
10290 bool is_scalar
= extract32(insn
, 28, 1);
10291 bool is_q
= extract32(insn
, 30, 1);
10292 bool u
= extract32(insn
, 29, 1);
10293 int size
= extract32(insn
, 22, 2);
10294 int l
= extract32(insn
, 21, 1);
10295 int m
= extract32(insn
, 20, 1);
10296 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
10297 int rm
= extract32(insn
, 16, 4);
10298 int opcode
= extract32(insn
, 12, 4);
10299 int h
= extract32(insn
, 11, 1);
10300 int rn
= extract32(insn
, 5, 5);
10301 int rd
= extract32(insn
, 0, 5);
10302 bool is_long
= false;
10303 bool is_fp
= false;
10308 case 0x0: /* MLA */
10309 case 0x4: /* MLS */
10310 if (!u
|| is_scalar
) {
10311 unallocated_encoding(s
);
10315 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10316 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10317 case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */
10319 unallocated_encoding(s
);
10324 case 0x3: /* SQDMLAL, SQDMLAL2 */
10325 case 0x7: /* SQDMLSL, SQDMLSL2 */
10326 case 0xb: /* SQDMULL, SQDMULL2 */
10329 case 0xc: /* SQDMULH */
10330 case 0xd: /* SQRDMULH */
10332 unallocated_encoding(s
);
10336 case 0x8: /* MUL */
10337 if (u
|| is_scalar
) {
10338 unallocated_encoding(s
);
10342 case 0x1: /* FMLA */
10343 case 0x5: /* FMLS */
10345 unallocated_encoding(s
);
10349 case 0x9: /* FMUL, FMULX */
10350 if (!extract32(size
, 1, 1)) {
10351 unallocated_encoding(s
);
10357 unallocated_encoding(s
);
10362 /* low bit of size indicates single/double */
10363 size
= extract32(size
, 0, 1) ? 3 : 2;
10365 index
= h
<< 1 | l
;
10368 unallocated_encoding(s
);
10377 index
= h
<< 2 | l
<< 1 | m
;
10380 index
= h
<< 1 | l
;
10384 unallocated_encoding(s
);
10389 if (!fp_access_check(s
)) {
10394 fpst
= get_fpstatus_ptr();
10396 TCGV_UNUSED_PTR(fpst
);
10400 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
10403 assert(is_fp
&& is_q
&& !is_long
);
10405 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
10407 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10408 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10409 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10411 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10414 case 0x5: /* FMLS */
10415 /* As usual for ARM, separate negation for fused multiply-add */
10416 gen_helper_vfp_negd(tcg_op
, tcg_op
);
10418 case 0x1: /* FMLA */
10419 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10420 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
10422 case 0x9: /* FMUL, FMULX */
10424 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10426 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10430 g_assert_not_reached();
10433 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10434 tcg_temp_free_i64(tcg_op
);
10435 tcg_temp_free_i64(tcg_res
);
10439 clear_vec_high(s
, rd
);
10442 tcg_temp_free_i64(tcg_idx
);
10443 } else if (!is_long
) {
10444 /* 32 bit floating point, or 16 or 32 bit integer.
10445 * For the 16 bit scalar case we use the usual Neon helpers and
10446 * rely on the fact that 0 op 0 == 0 with no side effects.
10448 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
10449 int pass
, maxpasses
;
10454 maxpasses
= is_q
? 4 : 2;
10457 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
10459 if (size
== 1 && !is_scalar
) {
10460 /* The simplest way to handle the 16x16 indexed ops is to duplicate
10461 * the index into both halves of the 32 bit tcg_idx and then use
10462 * the usual Neon helpers.
10464 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
10467 for (pass
= 0; pass
< maxpasses
; pass
++) {
10468 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10469 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10471 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
10474 case 0x0: /* MLA */
10475 case 0x4: /* MLS */
10476 case 0x8: /* MUL */
10478 static NeonGenTwoOpFn
* const fns
[2][2] = {
10479 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
10480 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
10482 NeonGenTwoOpFn
*genfn
;
10483 bool is_sub
= opcode
== 0x4;
10486 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
10488 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
10490 if (opcode
== 0x8) {
10493 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
10494 genfn
= fns
[size
- 1][is_sub
];
10495 genfn(tcg_res
, tcg_op
, tcg_res
);
10498 case 0x5: /* FMLS */
10499 /* As usual for ARM, separate negation for fused multiply-add */
10500 gen_helper_vfp_negs(tcg_op
, tcg_op
);
10502 case 0x1: /* FMLA */
10503 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10504 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
10506 case 0x9: /* FMUL, FMULX */
10508 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10510 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10513 case 0xc: /* SQDMULH */
10515 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
10518 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
10522 case 0xd: /* SQRDMULH */
10524 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
10527 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
10532 g_assert_not_reached();
10536 write_fp_sreg(s
, rd
, tcg_res
);
10538 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10541 tcg_temp_free_i32(tcg_op
);
10542 tcg_temp_free_i32(tcg_res
);
10545 tcg_temp_free_i32(tcg_idx
);
10548 clear_vec_high(s
, rd
);
10551 /* long ops: 16x16->32 or 32x32->64 */
10552 TCGv_i64 tcg_res
[2];
10554 bool satop
= extract32(opcode
, 0, 1);
10555 TCGMemOp memop
= MO_32
;
10562 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
10564 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
10566 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10567 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10568 TCGv_i64 tcg_passres
;
10574 passelt
= pass
+ (is_q
* 2);
10577 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
10579 tcg_res
[pass
] = tcg_temp_new_i64();
10581 if (opcode
== 0xa || opcode
== 0xb) {
10582 /* Non-accumulating ops */
10583 tcg_passres
= tcg_res
[pass
];
10585 tcg_passres
= tcg_temp_new_i64();
10588 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
10589 tcg_temp_free_i64(tcg_op
);
10592 /* saturating, doubling */
10593 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10594 tcg_passres
, tcg_passres
);
10597 if (opcode
== 0xa || opcode
== 0xb) {
10601 /* Accumulating op: handle accumulate step */
10602 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10605 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10606 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10608 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10609 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10611 case 0x7: /* SQDMLSL, SQDMLSL2 */
10612 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10614 case 0x3: /* SQDMLAL, SQDMLAL2 */
10615 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10620 g_assert_not_reached();
10622 tcg_temp_free_i64(tcg_passres
);
10624 tcg_temp_free_i64(tcg_idx
);
10627 clear_vec_high(s
, rd
);
10630 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
10633 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
10636 /* The simplest way to handle the 16x16 indexed ops is to
10637 * duplicate the index into both halves of the 32 bit tcg_idx
10638 * and then use the usual Neon helpers.
10640 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
10643 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10644 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10645 TCGv_i64 tcg_passres
;
10648 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
10650 read_vec_element_i32(s
, tcg_op
, rn
,
10651 pass
+ (is_q
* 2), MO_32
);
10654 tcg_res
[pass
] = tcg_temp_new_i64();
10656 if (opcode
== 0xa || opcode
== 0xb) {
10657 /* Non-accumulating ops */
10658 tcg_passres
= tcg_res
[pass
];
10660 tcg_passres
= tcg_temp_new_i64();
10663 if (memop
& MO_SIGN
) {
10664 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
10666 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
10669 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
10670 tcg_passres
, tcg_passres
);
10672 tcg_temp_free_i32(tcg_op
);
10674 if (opcode
== 0xa || opcode
== 0xb) {
10678 /* Accumulating op: handle accumulate step */
10679 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10682 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10683 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
10686 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10687 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
10690 case 0x7: /* SQDMLSL, SQDMLSL2 */
10691 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
10693 case 0x3: /* SQDMLAL, SQDMLAL2 */
10694 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
10699 g_assert_not_reached();
10701 tcg_temp_free_i64(tcg_passres
);
10703 tcg_temp_free_i32(tcg_idx
);
10706 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
10711 tcg_res
[1] = tcg_const_i64(0);
10714 for (pass
= 0; pass
< 2; pass
++) {
10715 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10716 tcg_temp_free_i64(tcg_res
[pass
]);
10720 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
10721 tcg_temp_free_ptr(fpst
);
10725 /* C3.6.19 Crypto AES
10726 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
10727 * +-----------------+------+-----------+--------+-----+------+------+
10728 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
10729 * +-----------------+------+-----------+--------+-----+------+------+
10731 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
10733 int size
= extract32(insn
, 22, 2);
10734 int opcode
= extract32(insn
, 12, 5);
10735 int rn
= extract32(insn
, 5, 5);
10736 int rd
= extract32(insn
, 0, 5);
10738 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
, tcg_decrypt
;
10739 CryptoThreeOpEnvFn
*genfn
;
10741 if (!arm_dc_feature(s
, ARM_FEATURE_V8_AES
)
10743 unallocated_encoding(s
);
10748 case 0x4: /* AESE */
10750 genfn
= gen_helper_crypto_aese
;
10752 case 0x6: /* AESMC */
10754 genfn
= gen_helper_crypto_aesmc
;
10756 case 0x5: /* AESD */
10758 genfn
= gen_helper_crypto_aese
;
10760 case 0x7: /* AESIMC */
10762 genfn
= gen_helper_crypto_aesmc
;
10765 unallocated_encoding(s
);
10769 /* Note that we convert the Vx register indexes into the
10770 * index within the vfp.regs[] array, so we can share the
10771 * helper with the AArch32 instructions.
10773 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
10774 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
10775 tcg_decrypt
= tcg_const_i32(decrypt
);
10777 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
, tcg_decrypt
);
10779 tcg_temp_free_i32(tcg_rd_regno
);
10780 tcg_temp_free_i32(tcg_rn_regno
);
10781 tcg_temp_free_i32(tcg_decrypt
);
10784 /* C3.6.20 Crypto three-reg SHA
10785 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
10786 * +-----------------+------+---+------+---+--------+-----+------+------+
10787 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
10788 * +-----------------+------+---+------+---+--------+-----+------+------+
10790 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
10792 int size
= extract32(insn
, 22, 2);
10793 int opcode
= extract32(insn
, 12, 3);
10794 int rm
= extract32(insn
, 16, 5);
10795 int rn
= extract32(insn
, 5, 5);
10796 int rd
= extract32(insn
, 0, 5);
10797 CryptoThreeOpEnvFn
*genfn
;
10798 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
, tcg_rm_regno
;
10799 int feature
= ARM_FEATURE_V8_SHA256
;
10802 unallocated_encoding(s
);
10807 case 0: /* SHA1C */
10808 case 1: /* SHA1P */
10809 case 2: /* SHA1M */
10810 case 3: /* SHA1SU0 */
10812 feature
= ARM_FEATURE_V8_SHA1
;
10814 case 4: /* SHA256H */
10815 genfn
= gen_helper_crypto_sha256h
;
10817 case 5: /* SHA256H2 */
10818 genfn
= gen_helper_crypto_sha256h2
;
10820 case 6: /* SHA256SU1 */
10821 genfn
= gen_helper_crypto_sha256su1
;
10824 unallocated_encoding(s
);
10828 if (!arm_dc_feature(s
, feature
)) {
10829 unallocated_encoding(s
);
10833 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
10834 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
10835 tcg_rm_regno
= tcg_const_i32(rm
<< 1);
10838 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
, tcg_rm_regno
);
10840 TCGv_i32 tcg_opcode
= tcg_const_i32(opcode
);
10842 gen_helper_crypto_sha1_3reg(cpu_env
, tcg_rd_regno
,
10843 tcg_rn_regno
, tcg_rm_regno
, tcg_opcode
);
10844 tcg_temp_free_i32(tcg_opcode
);
10847 tcg_temp_free_i32(tcg_rd_regno
);
10848 tcg_temp_free_i32(tcg_rn_regno
);
10849 tcg_temp_free_i32(tcg_rm_regno
);
10852 /* C3.6.21 Crypto two-reg SHA
10853 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
10854 * +-----------------+------+-----------+--------+-----+------+------+
10855 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
10856 * +-----------------+------+-----------+--------+-----+------+------+
10858 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
10860 int size
= extract32(insn
, 22, 2);
10861 int opcode
= extract32(insn
, 12, 5);
10862 int rn
= extract32(insn
, 5, 5);
10863 int rd
= extract32(insn
, 0, 5);
10864 CryptoTwoOpEnvFn
*genfn
;
10866 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
;
10869 unallocated_encoding(s
);
10874 case 0: /* SHA1H */
10875 feature
= ARM_FEATURE_V8_SHA1
;
10876 genfn
= gen_helper_crypto_sha1h
;
10878 case 1: /* SHA1SU1 */
10879 feature
= ARM_FEATURE_V8_SHA1
;
10880 genfn
= gen_helper_crypto_sha1su1
;
10882 case 2: /* SHA256SU0 */
10883 feature
= ARM_FEATURE_V8_SHA256
;
10884 genfn
= gen_helper_crypto_sha256su0
;
10887 unallocated_encoding(s
);
10891 if (!arm_dc_feature(s
, feature
)) {
10892 unallocated_encoding(s
);
10896 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
10897 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
10899 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
);
10901 tcg_temp_free_i32(tcg_rd_regno
);
10902 tcg_temp_free_i32(tcg_rn_regno
);
10905 /* C3.6 Data processing - SIMD, inc Crypto
10907 * As the decode gets a little complex we are using a table based
10908 * approach for this part of the decode.
10910 static const AArch64DecodeTable data_proc_simd
[] = {
10911 /* pattern , mask , fn */
10912 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
10913 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
10914 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
10915 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
10916 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
10917 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
10918 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
10919 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
10920 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
10921 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
10922 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
10923 { 0x2e000000, 0xbf208400, disas_simd_ext
},
10924 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
10925 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
10926 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
10927 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
10928 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
10929 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
10930 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
10931 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
10932 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
10933 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
10934 { 0x00000000, 0x00000000, NULL
}
10937 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
10939 /* Note that this is called with all non-FP cases from
10940 * table C3-6 so it must UNDEF for entries not specifically
10941 * allocated to instructions in that table.
10943 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
10947 unallocated_encoding(s
);
10951 /* C3.6 Data processing - SIMD and floating point */
10952 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
10954 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
10955 disas_data_proc_fp(s
, insn
);
10957 /* SIMD, including crypto */
10958 disas_data_proc_simd(s
, insn
);
10962 /* C3.1 A64 instruction index by encoding */
10963 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
10967 insn
= arm_ldl_code(env
, s
->pc
, s
->bswap_code
);
10971 s
->fp_access_checked
= false;
10973 switch (extract32(insn
, 25, 4)) {
10974 case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */
10975 unallocated_encoding(s
);
10977 case 0x8: case 0x9: /* Data processing - immediate */
10978 disas_data_proc_imm(s
, insn
);
10980 case 0xa: case 0xb: /* Branch, exception generation and system insns */
10981 disas_b_exc_sys(s
, insn
);
10986 case 0xe: /* Loads and stores */
10987 disas_ldst(s
, insn
);
10990 case 0xd: /* Data processing - register */
10991 disas_data_proc_reg(s
, insn
);
10994 case 0xf: /* Data processing - SIMD and floating point */
10995 disas_data_proc_simd_fp(s
, insn
);
10998 assert(FALSE
); /* all 15 cases should be handled above */
11002 /* if we allocated any temporaries, free them here */
11006 void gen_intermediate_code_a64(ARMCPU
*cpu
, TranslationBlock
*tb
)
11008 CPUState
*cs
= CPU(cpu
);
11009 CPUARMState
*env
= &cpu
->env
;
11010 DisasContext dc1
, *dc
= &dc1
;
11011 target_ulong pc_start
;
11012 target_ulong next_page_start
;
11020 dc
->is_jmp
= DISAS_NEXT
;
11022 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
11026 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
11027 * there is no secure EL1, so we route exceptions to EL3.
11029 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
11030 !arm_el_is_aa64(env
, 3);
11032 dc
->bswap_code
= 0;
11033 dc
->condexec_mask
= 0;
11034 dc
->condexec_cond
= 0;
11035 dc
->mmu_idx
= ARM_TBFLAG_MMUIDX(tb
->flags
);
11036 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
11037 #if !defined(CONFIG_USER_ONLY)
11038 dc
->user
= (dc
->current_el
== 0);
11040 dc
->fp_excp_el
= ARM_TBFLAG_FPEXC_EL(tb
->flags
);
11042 dc
->vec_stride
= 0;
11043 dc
->cp_regs
= cpu
->cp_regs
;
11044 dc
->features
= env
->features
;
11046 /* Single step state. The code-generation logic here is:
11048 * generate code with no special handling for single-stepping (except
11049 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
11050 * this happens anyway because those changes are all system register or
11052 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
11053 * emit code for one insn
11054 * emit code to clear PSTATE.SS
11055 * emit code to generate software step exception for completed step
11056 * end TB (as usual for having generated an exception)
11057 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
11058 * emit code to generate a software step exception
11061 dc
->ss_active
= ARM_TBFLAG_SS_ACTIVE(tb
->flags
);
11062 dc
->pstate_ss
= ARM_TBFLAG_PSTATE_SS(tb
->flags
);
11063 dc
->is_ldex
= false;
11064 dc
->ss_same_el
= (arm_debug_target_el(env
) == dc
->current_el
);
11066 init_tmp_a64_array(dc
);
11068 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
11070 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
11071 if (max_insns
== 0) {
11072 max_insns
= CF_COUNT_MASK
;
11074 if (max_insns
> TCG_MAX_INSNS
) {
11075 max_insns
= TCG_MAX_INSNS
;
11080 tcg_clear_temp_count();
11083 tcg_gen_insn_start(dc
->pc
, 0);
11086 if (unlikely(!QTAILQ_EMPTY(&cs
->breakpoints
))) {
11088 QTAILQ_FOREACH(bp
, &cs
->breakpoints
, entry
) {
11089 if (bp
->pc
== dc
->pc
) {
11090 if (bp
->flags
& BP_CPU
) {
11091 gen_a64_set_pc_im(dc
->pc
);
11092 gen_helper_check_breakpoints(cpu_env
);
11093 /* End the TB early; it likely won't be executed */
11094 dc
->is_jmp
= DISAS_UPDATE
;
11096 gen_exception_internal_insn(dc
, 0, EXCP_DEBUG
);
11097 /* The address covered by the breakpoint must be
11098 included in [tb->pc, tb->pc + tb->size) in order
11099 to for it to be properly cleared -- thus we
11100 increment the PC here so that the logic setting
11101 tb->size below does the right thing. */
11103 goto done_generating
;
11110 if (num_insns
== max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
11114 if (dc
->ss_active
&& !dc
->pstate_ss
) {
11115 /* Singlestep state is Active-pending.
11116 * If we're in this state at the start of a TB then either
11117 * a) we just took an exception to an EL which is being debugged
11118 * and this is the first insn in the exception handler
11119 * b) debug exceptions were masked and we just unmasked them
11120 * without changing EL (eg by clearing PSTATE.D)
11121 * In either case we're going to take a swstep exception in the
11122 * "did not step an insn" case, and so the syndrome ISV and EX
11123 * bits should be zero.
11125 assert(num_insns
== 1);
11126 gen_exception(EXCP_UDEF
, syn_swstep(dc
->ss_same_el
, 0, 0),
11127 default_exception_el(dc
));
11128 dc
->is_jmp
= DISAS_EXC
;
11132 disas_a64_insn(env
, dc
);
11134 if (tcg_check_temp_count()) {
11135 fprintf(stderr
, "TCG temporary leak before "TARGET_FMT_lx
"\n",
11139 /* Translation stops when a conditional branch is encountered.
11140 * Otherwise the subsequent code could get translated several times.
11141 * Also stop translation when a page boundary is reached. This
11142 * ensures prefetch aborts occur at the right place.
11144 } while (!dc
->is_jmp
&& !tcg_op_buf_full() &&
11145 !cs
->singlestep_enabled
&&
11148 dc
->pc
< next_page_start
&&
11149 num_insns
< max_insns
);
11151 if (tb
->cflags
& CF_LAST_IO
) {
11155 if (unlikely(cs
->singlestep_enabled
|| dc
->ss_active
)
11156 && dc
->is_jmp
!= DISAS_EXC
) {
11157 /* Note that this means single stepping WFI doesn't halt the CPU.
11158 * For conditional branch insns this is harmless unreachable code as
11159 * gen_goto_tb() has already handled emitting the debug exception
11160 * (and thus a tb-jump is not possible when singlestepping).
11162 assert(dc
->is_jmp
!= DISAS_TB_JUMP
);
11163 if (dc
->is_jmp
!= DISAS_JUMP
) {
11164 gen_a64_set_pc_im(dc
->pc
);
11166 if (cs
->singlestep_enabled
) {
11167 gen_exception_internal(EXCP_DEBUG
);
11169 gen_step_complete_exception(dc
);
11172 switch (dc
->is_jmp
) {
11174 gen_goto_tb(dc
, 1, dc
->pc
);
11178 gen_a64_set_pc_im(dc
->pc
);
11181 /* indicate that the hash table must be used to find the next TB */
11182 tcg_gen_exit_tb(0);
11184 case DISAS_TB_JUMP
:
11189 gen_a64_set_pc_im(dc
->pc
);
11190 gen_helper_wfe(cpu_env
);
11193 gen_a64_set_pc_im(dc
->pc
);
11194 gen_helper_yield(cpu_env
);
11197 /* This is a special case because we don't want to just halt the CPU
11198 * if trying to debug across a WFI.
11200 gen_a64_set_pc_im(dc
->pc
);
11201 gen_helper_wfi(cpu_env
);
11202 /* The helper doesn't necessarily throw an exception, but we
11203 * must go back to the main loop to check for interrupts anyway.
11205 tcg_gen_exit_tb(0);
11211 gen_tb_end(tb
, num_insns
);
11214 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
11215 qemu_log("----------------\n");
11216 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
11217 log_target_disas(cs
, pc_start
, dc
->pc
- pc_start
,
11218 4 | (dc
->bswap_code
<< 1));
11222 tb
->size
= dc
->pc
- pc_start
;
11223 tb
->icount
= num_insns
;