hw/cpu/a9mpcore.c

   1 /*
   2  * Cortex-A9MPCore internal peripheral emulation.
   3  *
   4  * Copyright (c) 2009 CodeSourcery.
   5  * Copyright (c) 2011 Linaro Limited.
   6  * Written by Paul Brook, Peter Maydell.
   7  *
   8  * This code is licensed under the GPL.
   9  */
  10
  11 #include "qemu/osdep.h"
  12 #include "qapi/error.h"
  13 #include "hw/cpu/a9mpcore.h"
  14 #include "qom/cpu.h"
  15
  16 static void a9mp_priv_set_irq(void *opaque, int irq, int level)
  17 {
  18     A9MPPrivState *s = (A9MPPrivState *)opaque;
  19
  20     qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level);
  21 }
  22
  23 static void a9mp_priv_initfn(Object *obj)
  24 {
  25     A9MPPrivState *s = A9MPCORE_PRIV(obj);
  26
  27     memory_region_init(&s->container, obj, "a9mp-priv-container", 0x2000);
  28     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container);
  29
  30     sysbus_init_child_obj(obj, "scu", &s->scu, sizeof(s->scu), TYPE_A9_SCU);
  31
  32     sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic), TYPE_ARM_GIC);
  33
  34     sysbus_init_child_obj(obj, "gtimer", &s->gtimer, sizeof(s->gtimer),
  35                           TYPE_A9_GTIMER);
  36
  37     sysbus_init_child_obj(obj, "mptimer", &s->mptimer, sizeof(s->mptimer),
  38                           TYPE_ARM_MPTIMER);
  39
  40     sysbus_init_child_obj(obj, "wdt", &s->wdt, sizeof(s->wdt),
  41                           TYPE_ARM_MPTIMER);
  42 }
  43
  44 static void a9mp_priv_realize(DeviceState *dev, Error **errp)
  45 {
  46     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
  47     A9MPPrivState *s = A9MPCORE_PRIV(dev);
  48     DeviceState *scudev, *gicdev, *gtimerdev, *mptimerdev, *wdtdev;
  49     SysBusDevice *scubusdev, *gicbusdev, *gtimerbusdev, *mptimerbusdev,
  50                  *wdtbusdev;
  51     Error *err = NULL;
  52     int i;
  53     bool has_el3;
  54     Object *cpuobj;
  55
  56     scudev = DEVICE(&s->scu);
  57     qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu);
  58     object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
  59     if (err != NULL) {
  60         error_propagate(errp, err);
  61         return;
  62     }
  63     scubusdev = SYS_BUS_DEVICE(&s->scu);
  64
  65     gicdev = DEVICE(&s->gic);
  66     qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
  67     qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
  68
  69     /* Make the GIC's TZ support match the CPUs. We assume that
  70      * either all the CPUs have TZ, or none do.
  71      */
  72     cpuobj = OBJECT(qemu_get_cpu(0));
  73     has_el3 = object_property_find(cpuobj, "has_el3", NULL) &&
  74         object_property_get_bool(cpuobj, "has_el3", &error_abort);
  75     qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3);
  76
  77     object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
  78     if (err != NULL) {
  79         error_propagate(errp, err);
  80         return;
  81     }
  82     gicbusdev = SYS_BUS_DEVICE(&s->gic);
  83
  84     /* Pass through outbound IRQ lines from the GIC */
  85     sysbus_pass_irq(sbd, gicbusdev);
  86
  87     /* Pass through inbound GPIO lines to the GIC */
  88     qdev_init_gpio_in(dev, a9mp_priv_set_irq, s->num_irq - 32);
  89
  90     gtimerdev = DEVICE(&s->gtimer);
  91     qdev_prop_set_uint32(gtimerdev, "num-cpu", s->num_cpu);
  92     object_property_set_bool(OBJECT(&s->gtimer), true, "realized", &err);
  93     if (err != NULL) {
  94         error_propagate(errp, err);
  95         return;
  96     }
  97     gtimerbusdev = SYS_BUS_DEVICE(&s->gtimer);
  98
  99     mptimerdev = DEVICE(&s->mptimer);
 100     qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu);
 101     object_property_set_bool(OBJECT(&s->mptimer), true, "realized", &err);
 102     if (err != NULL) {
 103         error_propagate(errp, err);
 104         return;
 105     }
 106     mptimerbusdev = SYS_BUS_DEVICE(&s->mptimer);
 107
 108     wdtdev = DEVICE(&s->wdt);
 109     qdev_prop_set_uint32(wdtdev, "num-cpu", s->num_cpu);
 110     object_property_set_bool(OBJECT(&s->wdt), true, "realized", &err);
 111     if (err != NULL) {
 112         error_propagate(errp, err);
 113         return;
 114     }
 115     wdtbusdev = SYS_BUS_DEVICE(&s->wdt);
 116
 117     /* Memory map (addresses are offsets from PERIPHBASE):
 118      *  0x0000-0x00ff -- Snoop Control Unit
 119      *  0x0100-0x01ff -- GIC CPU interface
 120      *  0x0200-0x02ff -- Global Timer
 121      *  0x0300-0x05ff -- nothing
 122      *  0x0600-0x06ff -- private timers and watchdogs
 123      *  0x0700-0x0fff -- nothing
 124      *  0x1000-0x1fff -- GIC Distributor
 125      */
 126     memory_region_add_subregion(&s->container, 0,
 127                                 sysbus_mmio_get_region(scubusdev, 0));
 128     /* GIC CPU interface */
 129     memory_region_add_subregion(&s->container, 0x100,
 130                                 sysbus_mmio_get_region(gicbusdev, 1));
 131     memory_region_add_subregion(&s->container, 0x200,
 132                                 sysbus_mmio_get_region(gtimerbusdev, 0));
 133     /* Note that the A9 exposes only the "timer/watchdog for this core"
 134      * memory region, not the "timer/watchdog for core X" ones 11MPcore has.
 135      */
 136     memory_region_add_subregion(&s->container, 0x600,
 137                                 sysbus_mmio_get_region(mptimerbusdev, 0));
 138     memory_region_add_subregion(&s->container, 0x620,
 139                                 sysbus_mmio_get_region(wdtbusdev, 0));
 140     memory_region_add_subregion(&s->container, 0x1000,
 141                                 sysbus_mmio_get_region(gicbusdev, 0));
 142
 143     /* Wire up the interrupt from each watchdog and timer.
 144      * For each core the global timer is PPI 27, the private
 145      * timer is PPI 29 and the watchdog PPI 30.
 146      */
 147     for (i = 0; i < s->num_cpu; i++) {
 148         int ppibase = (s->num_irq - 32) + i * 32;
 149         sysbus_connect_irq(gtimerbusdev, i,
 150                            qdev_get_gpio_in(gicdev, ppibase + 27));
 151         sysbus_connect_irq(mptimerbusdev, i,
 152                            qdev_get_gpio_in(gicdev, ppibase + 29));
 153         sysbus_connect_irq(wdtbusdev, i,
 154                            qdev_get_gpio_in(gicdev, ppibase + 30));
 155     }
 156 }
 157
 158 static Property a9mp_priv_properties[] = {
 159     DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1),
 160     /* The Cortex-A9MP may have anything from 0 to 224 external interrupt
 161      * IRQ lines (with another 32 internal). We default to 64+32, which
 162      * is the number provided by the Cortex-A9MP test chip in the
 163      * Realview PBX-A9 and Versatile Express A9 development boards.
 164      * Other boards may differ and should set this property appropriately.
 165      */
 166     DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 96),
 167     DEFINE_PROP_END_OF_LIST(),
 168 };
 169
 170 static void a9mp_priv_class_init(ObjectClass *klass, void *data)
 171 {
 172     DeviceClass *dc = DEVICE_CLASS(klass);
 173
 174     dc->realize = a9mp_priv_realize;
 175     dc->props = a9mp_priv_properties;
 176 }
 177
 178 static const TypeInfo a9mp_priv_info = {
 179     .name          = TYPE_A9MPCORE_PRIV,
 180     .parent        = TYPE_SYS_BUS_DEVICE,
 181     .instance_size = sizeof(A9MPPrivState),
 182     .instance_init = a9mp_priv_initfn,
 183     .class_init    = a9mp_priv_class_init,
 184 };
 185
 186 static void a9mp_register_types(void)
 187 {
 188     type_register_static(&a9mp_priv_info);
 189 }
 190
 191 type_init(a9mp_register_types)