hw/spapr.c

   1 /*
   2  * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
   3  *
   4  * Copyright (c) 2004-2007 Fabrice Bellard
   5  * Copyright (c) 2007 Jocelyn Mayer
   6  * Copyright (c) 2010 David Gibson, IBM Corporation.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  *
  26  */
  27 #include "sysemu.h"
  28 #include "hw.h"
  29 #include "elf.h"
  30 #include "net.h"
  31 #include "blockdev.h"
  32 #include "cpus.h"
  33 #include "kvm.h"
  34 #include "kvm_ppc.h"
  35
  36 #include "hw/boards.h"
  37 #include "hw/ppc.h"
  38 #include "hw/loader.h"
  39
  40 #include "hw/spapr.h"
  41 #include "hw/spapr_vio.h"
  42 #include "hw/spapr_pci.h"
  43 #include "hw/xics.h"
  44
  45 #include "kvm.h"
  46 #include "kvm_ppc.h"
  47 #include "pci.h"
  48 #include "vga-pci.h"
  49
  50 #include "exec-memory.h"
  51
  52 #include <libfdt.h>
  53
  54 /* SLOF memory layout:
  55  *
  56  * SLOF raw image loaded at 0, copies its romfs right below the flat
  57  * device-tree, then position SLOF itself 31M below that
  58  *
  59  * So we set FW_OVERHEAD to 40MB which should account for all of that
  60  * and more
  61  *
  62  * We load our kernel at 4M, leaving space for SLOF initial image
  63  */
  64 #define FDT_MAX_SIZE            0x10000
  65 #define RTAS_MAX_SIZE           0x10000
  66 #define FW_MAX_SIZE             0x400000
  67 #define FW_FILE_NAME            "slof.bin"
  68 #define FW_OVERHEAD             0x2800000
  69 #define KERNEL_LOAD_ADDR        FW_MAX_SIZE
  70
  71 #define MIN_RMA_SLOF            128UL
  72
  73 #define TIMEBASE_FREQ           512000000ULL
  74
  75 #define MAX_CPUS                256
  76 #define XICS_IRQS               1024
  77
  78 #define SPAPR_PCI_BUID          0x800000020000001ULL
  79 #define SPAPR_PCI_MEM_WIN_ADDR  (0x10000000000ULL + 0xA0000000)
  80 #define SPAPR_PCI_MEM_WIN_SIZE  0x20000000
  81 #define SPAPR_PCI_IO_WIN_ADDR   (0x10000000000ULL + 0x80000000)
  82
  83 #define PHANDLE_XICP            0x00001111
  84
  85 sPAPREnvironment *spapr;
  86
  87 int spapr_allocate_irq(int hint, enum xics_irq_type type)
  88 {
  89     int irq;
  90
  91     if (hint) {
  92         irq = hint;
  93         /* FIXME: we should probably check for collisions somehow */
  94     } else {
  95         irq = spapr->next_irq++;
  96     }
  97
  98     /* Configure irq type */
  99     if (!xics_get_qirq(spapr->icp, irq)) {
 100         return 0;
 101     }
 102
 103     xics_set_irq_type(spapr->icp, irq, type);
 104
 105     return irq;
 106 }
 107
 108 static int spapr_set_associativity(void *fdt, sPAPREnvironment *spapr)
 109 {
 110     int ret = 0, offset;
 111     CPUPPCState *env;
 112     char cpu_model[32];
 113     int smt = kvmppc_smt_threads();
 114
 115     assert(spapr->cpu_model);
 116
 117     for (env = first_cpu; env != NULL; env = env->next_cpu) {
 118         uint32_t associativity[] = {cpu_to_be32(0x5),
 119                                     cpu_to_be32(0x0),
 120                                     cpu_to_be32(0x0),
 121                                     cpu_to_be32(0x0),
 122                                     cpu_to_be32(env->numa_node),
 123                                     cpu_to_be32(env->cpu_index)};
 124
 125         if ((env->cpu_index % smt) != 0) {
 126             continue;
 127         }
 128
 129         snprintf(cpu_model, 32, "/cpus/%s@%x", spapr->cpu_model,
 130                  env->cpu_index);
 131
 132         offset = fdt_path_offset(fdt, cpu_model);
 133         if (offset < 0) {
 134             return offset;
 135         }
 136
 137         ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity,
 138                           sizeof(associativity));
 139         if (ret < 0) {
 140             return ret;
 141         }
 142     }
 143     return ret;
 144 }
 145
 146
 147 static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop,
 148                                      size_t maxsize)
 149 {
 150     size_t maxcells = maxsize / sizeof(uint32_t);
 151     int i, j, count;
 152     uint32_t *p = prop;
 153
 154     for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
 155         struct ppc_one_seg_page_size *sps = &env->sps.sps[i];
 156
 157         if (!sps->page_shift) {
 158             break;
 159         }
 160         for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) {
 161             if (sps->enc[count].page_shift == 0) {
 162                 break;
 163             }
 164         }
 165         if ((p - prop) >= (maxcells - 3 - count * 2)) {
 166             break;
 167         }
 168         *(p++) = cpu_to_be32(sps->page_shift);
 169         *(p++) = cpu_to_be32(sps->slb_enc);
 170         *(p++) = cpu_to_be32(count);
 171         for (j = 0; j < count; j++) {
 172             *(p++) = cpu_to_be32(sps->enc[j].page_shift);
 173             *(p++) = cpu_to_be32(sps->enc[j].pte_enc);
 174         }
 175     }
 176
 177     return (p - prop) * sizeof(uint32_t);
 178 }
 179
 180 static void *spapr_create_fdt_skel(const char *cpu_model,
 181                                    target_phys_addr_t rma_size,
 182                                    target_phys_addr_t initrd_base,
 183                                    target_phys_addr_t initrd_size,
 184                                    target_phys_addr_t kernel_size,
 185                                    const char *boot_device,
 186                                    const char *kernel_cmdline,
 187                                    long hash_shift)
 188 {
 189     void *fdt;
 190     CPUPPCState *env;
 191     uint64_t mem_reg_property[2];
 192     uint32_t start_prop = cpu_to_be32(initrd_base);
 193     uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size);
 194     uint32_t pft_size_prop[] = {0, cpu_to_be32(hash_shift)};
 195     char hypertas_prop[] = "hcall-pft\0hcall-term\0hcall-dabr\0hcall-interrupt"
 196         "\0hcall-tce\0hcall-vio\0hcall-splpar\0hcall-bulk";
 197     char qemu_hypertas_prop[] = "hcall-memop1";
 198     uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)};
 199     int i;
 200     char *modelname;
 201     int smt = kvmppc_smt_threads();
 202     unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80};
 203     uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)};
 204     uint32_t associativity[] = {cpu_to_be32(0x4), cpu_to_be32(0x0),
 205                                 cpu_to_be32(0x0), cpu_to_be32(0x0),
 206                                 cpu_to_be32(0x0)};
 207     char mem_name[32];
 208     target_phys_addr_t node0_size, mem_start;
 209
 210 #define _FDT(exp) \
 211     do { \
 212         int ret = (exp);                                           \
 213         if (ret < 0) {                                             \
 214             fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
 215                     #exp, fdt_strerror(ret));                      \
 216             exit(1);                                               \
 217         }                                                          \
 218     } while (0)
 219
 220     fdt = g_malloc0(FDT_MAX_SIZE);
 221     _FDT((fdt_create(fdt, FDT_MAX_SIZE)));
 222
 223     if (kernel_size) {
 224         _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size)));
 225     }
 226     if (initrd_size) {
 227         _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size)));
 228     }
 229     _FDT((fdt_finish_reservemap(fdt)));
 230
 231     /* Root node */
 232     _FDT((fdt_begin_node(fdt, "")));
 233     _FDT((fdt_property_string(fdt, "device_type", "chrp")));
 234     _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)")));
 235
 236     _FDT((fdt_property_cell(fdt, "#address-cells", 0x2)));
 237     _FDT((fdt_property_cell(fdt, "#size-cells", 0x2)));
 238
 239     /* /chosen */
 240     _FDT((fdt_begin_node(fdt, "chosen")));
 241
 242     /* Set Form1_affinity */
 243     _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5))));
 244
 245     _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline)));
 246     _FDT((fdt_property(fdt, "linux,initrd-start",
 247                        &start_prop, sizeof(start_prop))));
 248     _FDT((fdt_property(fdt, "linux,initrd-end",
 249                        &end_prop, sizeof(end_prop))));
 250     if (kernel_size) {
 251         uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
 252                               cpu_to_be64(kernel_size) };
 253
 254         _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop))));
 255     }
 256     _FDT((fdt_property_string(fdt, "qemu,boot-device", boot_device)));
 257     _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width)));
 258     _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height)));
 259     _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth)));
 260
 261     _FDT((fdt_end_node(fdt)));
 262
 263     /* memory node(s) */
 264     node0_size = (nb_numa_nodes > 1) ? node_mem[0] : ram_size;
 265     if (rma_size > node0_size) {
 266         rma_size = node0_size;
 267     }
 268
 269     /* RMA */
 270     mem_reg_property[0] = 0;
 271     mem_reg_property[1] = cpu_to_be64(rma_size);
 272     _FDT((fdt_begin_node(fdt, "memory@0")));
 273     _FDT((fdt_property_string(fdt, "device_type", "memory")));
 274     _FDT((fdt_property(fdt, "reg", mem_reg_property,
 275         sizeof(mem_reg_property))));
 276     _FDT((fdt_property(fdt, "ibm,associativity", associativity,
 277         sizeof(associativity))));
 278     _FDT((fdt_end_node(fdt)));
 279
 280     /* RAM: Node 0 */
 281     if (node0_size > rma_size) {
 282         mem_reg_property[0] = cpu_to_be64(rma_size);
 283         mem_reg_property[1] = cpu_to_be64(node0_size - rma_size);
 284
 285         sprintf(mem_name, "memory@" TARGET_FMT_lx, rma_size);
 286         _FDT((fdt_begin_node(fdt, mem_name)));
 287         _FDT((fdt_property_string(fdt, "device_type", "memory")));
 288         _FDT((fdt_property(fdt, "reg", mem_reg_property,
 289                            sizeof(mem_reg_property))));
 290         _FDT((fdt_property(fdt, "ibm,associativity", associativity,
 291                            sizeof(associativity))));
 292         _FDT((fdt_end_node(fdt)));
 293     }
 294
 295     /* RAM: Node 1 and beyond */
 296     mem_start = node0_size;
 297     for (i = 1; i < nb_numa_nodes; i++) {
 298         mem_reg_property[0] = cpu_to_be64(mem_start);
 299         mem_reg_property[1] = cpu_to_be64(node_mem[i]);
 300         associativity[3] = associativity[4] = cpu_to_be32(i);
 301         sprintf(mem_name, "memory@" TARGET_FMT_lx, mem_start);
 302         _FDT((fdt_begin_node(fdt, mem_name)));
 303         _FDT((fdt_property_string(fdt, "device_type", "memory")));
 304         _FDT((fdt_property(fdt, "reg", mem_reg_property,
 305             sizeof(mem_reg_property))));
 306         _FDT((fdt_property(fdt, "ibm,associativity", associativity,
 307             sizeof(associativity))));
 308         _FDT((fdt_end_node(fdt)));
 309         mem_start += node_mem[i];
 310     }
 311
 312     /* cpus */
 313     _FDT((fdt_begin_node(fdt, "cpus")));
 314
 315     _FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
 316     _FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
 317
 318     modelname = g_strdup(cpu_model);
 319
 320     for (i = 0; i < strlen(modelname); i++) {
 321         modelname[i] = toupper(modelname[i]);
 322     }
 323
 324     /* This is needed during FDT finalization */
 325     spapr->cpu_model = g_strdup(modelname);
 326
 327     for (env = first_cpu; env != NULL; env = env->next_cpu) {
 328         int index = env->cpu_index;
 329         uint32_t servers_prop[smp_threads];
 330         uint32_t gservers_prop[smp_threads * 2];
 331         char *nodename;
 332         uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
 333                            0xffffffff, 0xffffffff};
 334         uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ;
 335         uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
 336         uint32_t page_sizes_prop[64];
 337         size_t page_sizes_prop_size;
 338
 339         if ((index % smt) != 0) {
 340             continue;
 341         }
 342
 343         if (asprintf(&nodename, "%s@%x", modelname, index) < 0) {
 344             fprintf(stderr, "Allocation failure\n");
 345             exit(1);
 346         }
 347
 348         _FDT((fdt_begin_node(fdt, nodename)));
 349
 350         free(nodename);
 351
 352         _FDT((fdt_property_cell(fdt, "reg", index)));
 353         _FDT((fdt_property_string(fdt, "device_type", "cpu")));
 354
 355         _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR])));
 356         _FDT((fdt_property_cell(fdt, "dcache-block-size",
 357                                 env->dcache_line_size)));
 358         _FDT((fdt_property_cell(fdt, "icache-block-size",
 359                                 env->icache_line_size)));
 360         _FDT((fdt_property_cell(fdt, "timebase-frequency", tbfreq)));
 361         _FDT((fdt_property_cell(fdt, "clock-frequency", cpufreq)));
 362         _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr)));
 363         _FDT((fdt_property(fdt, "ibm,pft-size",
 364                            pft_size_prop, sizeof(pft_size_prop))));
 365         _FDT((fdt_property_string(fdt, "status", "okay")));
 366         _FDT((fdt_property(fdt, "64-bit", NULL, 0)));
 367
 368         /* Build interrupt servers and gservers properties */
 369         for (i = 0; i < smp_threads; i++) {
 370             servers_prop[i] = cpu_to_be32(index + i);
 371             /* Hack, direct the group queues back to cpu 0 */
 372             gservers_prop[i*2] = cpu_to_be32(index + i);
 373             gservers_prop[i*2 + 1] = 0;
 374         }
 375         _FDT((fdt_property(fdt, "ibm,ppc-interrupt-server#s",
 376                            servers_prop, sizeof(servers_prop))));
 377         _FDT((fdt_property(fdt, "ibm,ppc-interrupt-gserver#s",
 378                            gservers_prop, sizeof(gservers_prop))));
 379
 380         if (env->mmu_model & POWERPC_MMU_1TSEG) {
 381             _FDT((fdt_property(fdt, "ibm,processor-segment-sizes",
 382                                segs, sizeof(segs))));
 383         }
 384
 385         /* Advertise VMX/VSX (vector extensions) if available
 386          *   0 / no property == no vector extensions
 387          *   1               == VMX / Altivec available
 388          *   2               == VSX available */
 389         if (env->insns_flags & PPC_ALTIVEC) {
 390             uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
 391
 392             _FDT((fdt_property_cell(fdt, "ibm,vmx", vmx)));
 393         }
 394
 395         /* Advertise DFP (Decimal Floating Point) if available
 396          *   0 / no property == no DFP
 397          *   1               == DFP available */
 398         if (env->insns_flags2 & PPC2_DFP) {
 399             _FDT((fdt_property_cell(fdt, "ibm,dfp", 1)));
 400         }
 401
 402         page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop,
 403                                                       sizeof(page_sizes_prop));
 404         if (page_sizes_prop_size) {
 405             _FDT((fdt_property(fdt, "ibm,segment-page-sizes",
 406                                page_sizes_prop, page_sizes_prop_size)));
 407         }
 408
 409         _FDT((fdt_end_node(fdt)));
 410     }
 411
 412     g_free(modelname);
 413
 414     _FDT((fdt_end_node(fdt)));
 415
 416     /* RTAS */
 417     _FDT((fdt_begin_node(fdt, "rtas")));
 418
 419     _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas_prop,
 420                        sizeof(hypertas_prop))));
 421     _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas_prop,
 422                        sizeof(qemu_hypertas_prop))));
 423
 424     _FDT((fdt_property(fdt, "ibm,associativity-reference-points",
 425         refpoints, sizeof(refpoints))));
 426
 427     _FDT((fdt_end_node(fdt)));
 428
 429     /* interrupt controller */
 430     _FDT((fdt_begin_node(fdt, "interrupt-controller")));
 431
 432     _FDT((fdt_property_string(fdt, "device_type",
 433                               "PowerPC-External-Interrupt-Presentation")));
 434     _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp")));
 435     _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
 436     _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges",
 437                        interrupt_server_ranges_prop,
 438                        sizeof(interrupt_server_ranges_prop))));
 439     _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2)));
 440     _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP)));
 441     _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP)));
 442
 443     _FDT((fdt_end_node(fdt)));
 444
 445     /* vdevice */
 446     _FDT((fdt_begin_node(fdt, "vdevice")));
 447
 448     _FDT((fdt_property_string(fdt, "device_type", "vdevice")));
 449     _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice")));
 450     _FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
 451     _FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
 452     _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2)));
 453     _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
 454
 455     _FDT((fdt_end_node(fdt)));
 456
 457     _FDT((fdt_end_node(fdt))); /* close root node */
 458     _FDT((fdt_finish(fdt)));
 459
 460     return fdt;
 461 }
 462
 463 static void spapr_finalize_fdt(sPAPREnvironment *spapr,
 464                                target_phys_addr_t fdt_addr,
 465                                target_phys_addr_t rtas_addr,
 466                                target_phys_addr_t rtas_size)
 467 {
 468     int ret;
 469     void *fdt;
 470     sPAPRPHBState *phb;
 471
 472     fdt = g_malloc(FDT_MAX_SIZE);
 473
 474     /* open out the base tree into a temp buffer for the final tweaks */
 475     _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE)));
 476
 477     ret = spapr_populate_vdevice(spapr->vio_bus, fdt);
 478     if (ret < 0) {
 479         fprintf(stderr, "couldn't setup vio devices in fdt\n");
 480         exit(1);
 481     }
 482
 483     QLIST_FOREACH(phb, &spapr->phbs, list) {
 484         ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
 485     }
 486
 487     if (ret < 0) {
 488         fprintf(stderr, "couldn't setup PCI devices in fdt\n");
 489         exit(1);
 490     }
 491
 492     /* RTAS */
 493     ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size);
 494     if (ret < 0) {
 495         fprintf(stderr, "Couldn't set up RTAS device tree properties\n");
 496     }
 497
 498     /* Advertise NUMA via ibm,associativity */
 499     if (nb_numa_nodes > 1) {
 500         ret = spapr_set_associativity(fdt, spapr);
 501         if (ret < 0) {
 502             fprintf(stderr, "Couldn't set up NUMA device tree properties\n");
 503         }
 504     }
 505
 506     if (!spapr->has_graphics) {
 507         spapr_populate_chosen_stdout(fdt, spapr->vio_bus);
 508     }
 509
 510     _FDT((fdt_pack(fdt)));
 511
 512     if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
 513         hw_error("FDT too big ! 0x%x bytes (max is 0x%x)\n",
 514                  fdt_totalsize(fdt), FDT_MAX_SIZE);
 515         exit(1);
 516     }
 517
 518     cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
 519
 520     g_free(fdt);
 521 }
 522
 523 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
 524 {
 525     return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
 526 }
 527
 528 static void emulate_spapr_hypercall(CPUPPCState *env)
 529 {
 530     env->gpr[3] = spapr_hypercall(env, env->gpr[3], &env->gpr[4]);
 531 }
 532
 533 static void spapr_reset(void *opaque)
 534 {
 535     sPAPREnvironment *spapr = (sPAPREnvironment *)opaque;
 536
 537     /* flush out the hash table */
 538     memset(spapr->htab, 0, spapr->htab_size);
 539
 540     /* Load the fdt */
 541     spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr,
 542                        spapr->rtas_size);
 543
 544     /* Set up the entry state */
 545     first_cpu->gpr[3] = spapr->fdt_addr;
 546     first_cpu->gpr[5] = 0;
 547     first_cpu->halted = 0;
 548     first_cpu->nip = spapr->entry_point;
 549
 550 }
 551
 552 static void spapr_cpu_reset(void *opaque)
 553 {
 554     PowerPCCPU *cpu = opaque;
 555
 556     cpu_reset(CPU(cpu));
 557 }
 558
 559 /* Returns whether we want to use VGA or not */
 560 static int spapr_vga_init(PCIBus *pci_bus)
 561 {
 562     switch (vga_interface_type) {
 563     case VGA_STD:
 564         pci_vga_init(pci_bus);
 565         return 1;
 566     case VGA_NONE:
 567         return 0;
 568     default:
 569         fprintf(stderr, "This vga model is not supported,"
 570                 "currently it only supports -vga std\n");
 571         exit(0);
 572         break;
 573     }
 574 }
 575
 576 /* pSeries LPAR / sPAPR hardware init */
 577 static void ppc_spapr_init(ram_addr_t ram_size,
 578                            const char *boot_device,
 579                            const char *kernel_filename,
 580                            const char *kernel_cmdline,
 581                            const char *initrd_filename,
 582                            const char *cpu_model)
 583 {
 584     PowerPCCPU *cpu;
 585     CPUPPCState *env;
 586     int i;
 587     MemoryRegion *sysmem = get_system_memory();
 588     MemoryRegion *ram = g_new(MemoryRegion, 1);
 589     target_phys_addr_t rma_alloc_size, rma_size;
 590     uint32_t initrd_base = 0;
 591     long kernel_size = 0, initrd_size = 0;
 592     long load_limit, rtas_limit, fw_size;
 593     long pteg_shift = 17;
 594     char *filename;
 595
 596     spapr = g_malloc0(sizeof(*spapr));
 597     QLIST_INIT(&spapr->phbs);
 598
 599     cpu_ppc_hypercall = emulate_spapr_hypercall;
 600
 601     /* Allocate RMA if necessary */
 602     rma_alloc_size = kvmppc_alloc_rma("ppc_spapr.rma", sysmem);
 603
 604     if (rma_alloc_size == -1) {
 605         hw_error("qemu: Unable to create RMA\n");
 606         exit(1);
 607     }
 608     if (rma_alloc_size && (rma_alloc_size < ram_size)) {
 609         rma_size = rma_alloc_size;
 610     } else {
 611         rma_size = ram_size;
 612     }
 613
 614     /* We place the device tree and RTAS just below either the top of the RMA,
 615      * or just below 2GB, whichever is lowere, so that it can be
 616      * processed with 32-bit real mode code if necessary */
 617     rtas_limit = MIN(rma_size, 0x80000000);
 618     spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE;
 619     spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE;
 620     load_limit = spapr->fdt_addr - FW_OVERHEAD;
 621
 622     /* init CPUs */
 623     if (cpu_model == NULL) {
 624         cpu_model = kvm_enabled() ? "host" : "POWER7";
 625     }
 626     for (i = 0; i < smp_cpus; i++) {
 627         cpu = cpu_ppc_init(cpu_model);
 628         if (cpu == NULL) {
 629             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
 630             exit(1);
 631         }
 632         env = &cpu->env;
 633
 634         /* Set time-base frequency to 512 MHz */
 635         cpu_ppc_tb_init(env, TIMEBASE_FREQ);
 636         qemu_register_reset(spapr_cpu_reset, cpu);
 637
 638         env->hreset_vector = 0x60;
 639         env->hreset_excp_prefix = 0;
 640         env->gpr[3] = env->cpu_index;
 641     }
 642
 643     /* allocate RAM */
 644     spapr->ram_limit = ram_size;
 645     if (spapr->ram_limit > rma_alloc_size) {
 646         ram_addr_t nonrma_base = rma_alloc_size;
 647         ram_addr_t nonrma_size = spapr->ram_limit - rma_alloc_size;
 648
 649         memory_region_init_ram(ram, "ppc_spapr.ram", nonrma_size);
 650         vmstate_register_ram_global(ram);
 651         memory_region_add_subregion(sysmem, nonrma_base, ram);
 652     }
 653
 654     /* allocate hash page table.  For now we always make this 16mb,
 655      * later we should probably make it scale to the size of guest
 656      * RAM */
 657     spapr->htab_size = 1ULL << (pteg_shift + 7);
 658     spapr->htab = qemu_memalign(spapr->htab_size, spapr->htab_size);
 659
 660     for (env = first_cpu; env != NULL; env = env->next_cpu) {
 661         env->external_htab = spapr->htab;
 662         env->htab_base = -1;
 663         env->htab_mask = spapr->htab_size - 1;
 664
 665         /* Tell KVM that we're in PAPR mode */
 666         env->spr[SPR_SDR1] = (unsigned long)spapr->htab |
 667                              ((pteg_shift + 7) - 18);
 668         env->spr[SPR_HIOR] = 0;
 669
 670         if (kvm_enabled()) {
 671             kvmppc_set_papr(env);
 672         }
 673     }
 674
 675     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
 676     spapr->rtas_size = load_image_targphys(filename, spapr->rtas_addr,
 677                                            rtas_limit - spapr->rtas_addr);
 678     if (spapr->rtas_size < 0) {
 679         hw_error("qemu: could not load LPAR rtas '%s'\n", filename);
 680         exit(1);
 681     }
 682     if (spapr->rtas_size > RTAS_MAX_SIZE) {
 683         hw_error("RTAS too big ! 0x%lx bytes (max is 0x%x)\n",
 684                  spapr->rtas_size, RTAS_MAX_SIZE);
 685         exit(1);
 686     }
 687     g_free(filename);
 688
 689
 690     /* Set up Interrupt Controller */
 691     spapr->icp = xics_system_init(XICS_IRQS);
 692     spapr->next_irq = 16;
 693
 694     /* Set up IOMMU */
 695     spapr_iommu_init();
 696
 697     /* Set up VIO bus */
 698     spapr->vio_bus = spapr_vio_bus_init();
 699
 700     for (i = 0; i < MAX_SERIAL_PORTS; i++) {
 701         if (serial_hds[i]) {
 702             spapr_vty_create(spapr->vio_bus, serial_hds[i]);
 703         }
 704     }
 705
 706     /* Set up PCI */
 707     spapr_create_phb(spapr, "pci", SPAPR_PCI_BUID,
 708                      SPAPR_PCI_MEM_WIN_ADDR,
 709                      SPAPR_PCI_MEM_WIN_SIZE,
 710                      SPAPR_PCI_IO_WIN_ADDR);
 711
 712     for (i = 0; i < nb_nics; i++) {
 713         NICInfo *nd = &nd_table[i];
 714
 715         if (!nd->model) {
 716             nd->model = g_strdup("ibmveth");
 717         }
 718
 719         if (strcmp(nd->model, "ibmveth") == 0) {
 720             spapr_vlan_create(spapr->vio_bus, nd);
 721         } else {
 722             pci_nic_init_nofail(&nd_table[i], nd->model, NULL);
 723         }
 724     }
 725
 726     for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
 727         spapr_vscsi_create(spapr->vio_bus);
 728     }
 729
 730     /* Graphics */
 731     if (spapr_vga_init(QLIST_FIRST(&spapr->phbs)->host_state.bus)) {
 732         spapr->has_graphics = true;
 733     }
 734
 735     if (rma_size < (MIN_RMA_SLOF << 20)) {
 736         fprintf(stderr, "qemu: pSeries SLOF firmware requires >= "
 737                 "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF);
 738         exit(1);
 739     }
 740
 741     if (kernel_filename) {
 742         uint64_t lowaddr = 0;
 743
 744         kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
 745                                NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0);
 746         if (kernel_size < 0) {
 747             kernel_size = load_image_targphys(kernel_filename,
 748                                               KERNEL_LOAD_ADDR,
 749                                               load_limit - KERNEL_LOAD_ADDR);
 750         }
 751         if (kernel_size < 0) {
 752             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 753                     kernel_filename);
 754             exit(1);
 755         }
 756
 757         /* load initrd */
 758         if (initrd_filename) {
 759             /* Try to locate the initrd in the gap between the kernel
 760              * and the firmware. Add a bit of space just in case
 761              */
 762             initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff;
 763             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 764                                               load_limit - initrd_base);
 765             if (initrd_size < 0) {
 766                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 767                         initrd_filename);
 768                 exit(1);
 769             }
 770         } else {
 771             initrd_base = 0;
 772             initrd_size = 0;
 773         }
 774     }
 775
 776     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, FW_FILE_NAME);
 777     fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
 778     if (fw_size < 0) {
 779         hw_error("qemu: could not load LPAR rtas '%s'\n", filename);
 780         exit(1);
 781     }
 782     g_free(filename);
 783
 784     spapr->entry_point = 0x100;
 785
 786     /* SLOF will startup the secondary CPUs using RTAS */
 787     for (env = first_cpu; env != NULL; env = env->next_cpu) {
 788         env->halted = 1;
 789     }
 790
 791     /* Prepare the device tree */
 792     spapr->fdt_skel = spapr_create_fdt_skel(cpu_model, rma_size,
 793                                             initrd_base, initrd_size,
 794                                             kernel_size,
 795                                             boot_device, kernel_cmdline,
 796                                             pteg_shift + 7);
 797     assert(spapr->fdt_skel != NULL);
 798
 799     qemu_register_reset(spapr_reset, spapr);
 800 }
 801
 802 static QEMUMachine spapr_machine = {
 803     .name = "pseries",
 804     .desc = "pSeries Logical Partition (PAPR compliant)",
 805     .init = ppc_spapr_init,
 806     .max_cpus = MAX_CPUS,
 807     .no_parallel = 1,
 808     .use_scsi = 1,
 809 };
 810
 811 static void spapr_machine_init(void)
 812 {
 813     qemu_register_machine(&spapr_machine);
 814 }
 815
 816 machine_init(spapr_machine_init);