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tcg: Remove temp_buf
[qemu/kevin.git] / tcg / tcg-op.h
blob364964d8d4d2e0fd90e478fda90b65e3d3618d91
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "tcg.h"
25
26 int gen_new_label(void);
27
28 static inline void tcg_gen_op0(TCGOpcode opc)
29 {
30 *tcg_ctx.gen_opc_ptr++ = opc;
31 }
32
33 static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 arg1)
34 {
35 *tcg_ctx.gen_opc_ptr++ = opc;
36 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
37 }
38
39 static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 arg1)
40 {
41 *tcg_ctx.gen_opc_ptr++ = opc;
42 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
43 }
44
45 static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg arg1)
46 {
47 *tcg_ctx.gen_opc_ptr++ = opc;
48 *tcg_ctx.gen_opparam_ptr++ = arg1;
49 }
50
51 static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2)
52 {
53 *tcg_ctx.gen_opc_ptr++ = opc;
54 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
55 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg2);
56 }
57
58 static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2)
59 {
60 *tcg_ctx.gen_opc_ptr++ = opc;
61 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
62 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg2);
63 }
64
65 static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGArg arg2)
66 {
67 *tcg_ctx.gen_opc_ptr++ = opc;
68 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
69 *tcg_ctx.gen_opparam_ptr++ = arg2;
70 }
71
72 static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGArg arg2)
73 {
74 *tcg_ctx.gen_opc_ptr++ = opc;
75 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
76 *tcg_ctx.gen_opparam_ptr++ = arg2;
77 }
78
79 static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg arg1, TCGArg arg2)
80 {
81 *tcg_ctx.gen_opc_ptr++ = opc;
82 *tcg_ctx.gen_opparam_ptr++ = arg1;
83 *tcg_ctx.gen_opparam_ptr++ = arg2;
84 }
85
86 static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
87 TCGv_i32 arg3)
88 {
89 *tcg_ctx.gen_opc_ptr++ = opc;
90 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
91 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg2);
92 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg3);
93 }
94
95 static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
96 TCGv_i64 arg3)
97 {
98 *tcg_ctx.gen_opc_ptr++ = opc;
99 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
100 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg2);
101 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg3);
102 }
103
104 static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 arg1,
105 TCGv_i32 arg2, TCGArg arg3)
106 {
107 *tcg_ctx.gen_opc_ptr++ = opc;
108 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
109 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg2);
110 *tcg_ctx.gen_opparam_ptr++ = arg3;
111 }
112
113 static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 arg1,
114 TCGv_i64 arg2, TCGArg arg3)
115 {
116 *tcg_ctx.gen_opc_ptr++ = opc;
117 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
118 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg2);
119 *tcg_ctx.gen_opparam_ptr++ = arg3;
120 }
121
122 static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val,
123 TCGv_ptr base, TCGArg offset)
124 {
125 *tcg_ctx.gen_opc_ptr++ = opc;
126 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(val);
127 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_PTR(base);
128 *tcg_ctx.gen_opparam_ptr++ = offset;
129 }
130
131 static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val,
132 TCGv_ptr base, TCGArg offset)
133 {
134 *tcg_ctx.gen_opc_ptr++ = opc;
135 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(val);
136 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_PTR(base);
137 *tcg_ctx.gen_opparam_ptr++ = offset;
138 }
139
140 static inline void tcg_gen_qemu_ldst_op_i64_i32(TCGOpcode opc, TCGv_i64 val,
141 TCGv_i32 addr, TCGArg mem_index)
142 {
143 *tcg_ctx.gen_opc_ptr++ = opc;
144 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(val);
145 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(addr);
146 *tcg_ctx.gen_opparam_ptr++ = mem_index;
147 }
148
149 static inline void tcg_gen_qemu_ldst_op_i64_i64(TCGOpcode opc, TCGv_i64 val,
150 TCGv_i64 addr, TCGArg mem_index)
151 {
152 *tcg_ctx.gen_opc_ptr++ = opc;
153 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(val);
154 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(addr);
155 *tcg_ctx.gen_opparam_ptr++ = mem_index;
156 }
157
158 static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
159 TCGv_i32 arg3, TCGv_i32 arg4)
160 {
161 *tcg_ctx.gen_opc_ptr++ = opc;
162 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
163 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg2);
164 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg3);
165 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg4);
166 }
167
168 static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
169 TCGv_i64 arg3, TCGv_i64 arg4)
170 {
171 *tcg_ctx.gen_opc_ptr++ = opc;
172 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
173 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg2);
174 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg3);
175 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg4);
176 }
177
178 static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
179 TCGv_i32 arg3, TCGArg arg4)
180 {
181 *tcg_ctx.gen_opc_ptr++ = opc;
182 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
183 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg2);
184 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg3);
185 *tcg_ctx.gen_opparam_ptr++ = arg4;
186 }
187
188 static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
189 TCGv_i64 arg3, TCGArg arg4)
190 {
191 *tcg_ctx.gen_opc_ptr++ = opc;
192 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
193 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg2);
194 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg3);
195 *tcg_ctx.gen_opparam_ptr++ = arg4;
196 }
197
198 static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
199 TCGArg arg3, TCGArg arg4)
200 {
201 *tcg_ctx.gen_opc_ptr++ = opc;
202 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
203 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg2);
204 *tcg_ctx.gen_opparam_ptr++ = arg3;
205 *tcg_ctx.gen_opparam_ptr++ = arg4;
206 }
207
208 static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
209 TCGArg arg3, TCGArg arg4)
210 {
211 *tcg_ctx.gen_opc_ptr++ = opc;
212 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
213 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg2);
214 *tcg_ctx.gen_opparam_ptr++ = arg3;
215 *tcg_ctx.gen_opparam_ptr++ = arg4;
216 }
217
218 static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
219 TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5)
220 {
221 *tcg_ctx.gen_opc_ptr++ = opc;
222 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
223 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg2);
224 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg3);
225 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg4);
226 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg5);
227 }
228
229 static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
230 TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5)
231 {
232 *tcg_ctx.gen_opc_ptr++ = opc;
233 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
234 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg2);
235 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg3);
236 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg4);
237 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg5);
238 }
239
240 static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
241 TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5)
242 {
243 *tcg_ctx.gen_opc_ptr++ = opc;
244 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
245 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg2);
246 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg3);
247 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg4);
248 *tcg_ctx.gen_opparam_ptr++ = arg5;
249 }
250
251 static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
252 TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5)
253 {
254 *tcg_ctx.gen_opc_ptr++ = opc;
255 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
256 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg2);
257 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg3);
258 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg4);
259 *tcg_ctx.gen_opparam_ptr++ = arg5;
260 }
261
262 static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 arg1,
263 TCGv_i32 arg2, TCGv_i32 arg3,
264 TCGArg arg4, TCGArg arg5)
265 {
266 *tcg_ctx.gen_opc_ptr++ = opc;
267 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
268 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg2);
269 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg3);
270 *tcg_ctx.gen_opparam_ptr++ = arg4;
271 *tcg_ctx.gen_opparam_ptr++ = arg5;
272 }
273
274 static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 arg1,
275 TCGv_i64 arg2, TCGv_i64 arg3,
276 TCGArg arg4, TCGArg arg5)
277 {
278 *tcg_ctx.gen_opc_ptr++ = opc;
279 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
280 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg2);
281 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg3);
282 *tcg_ctx.gen_opparam_ptr++ = arg4;
283 *tcg_ctx.gen_opparam_ptr++ = arg5;
284 }
285
286 static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
287 TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5,
288 TCGv_i32 arg6)
289 {
290 *tcg_ctx.gen_opc_ptr++ = opc;
291 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
292 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg2);
293 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg3);
294 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg4);
295 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg5);
296 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg6);
297 }
298
299 static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
300 TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5,
301 TCGv_i64 arg6)
302 {
303 *tcg_ctx.gen_opc_ptr++ = opc;
304 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
305 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg2);
306 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg3);
307 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg4);
308 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg5);
309 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg6);
310 }
311
312 static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 arg1, TCGv_i32 arg2,
313 TCGv_i32 arg3, TCGv_i32 arg4,
314 TCGv_i32 arg5, TCGArg arg6)
315 {
316 *tcg_ctx.gen_opc_ptr++ = opc;
317 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
318 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg2);
319 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg3);
320 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg4);
321 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg5);
322 *tcg_ctx.gen_opparam_ptr++ = arg6;
323 }
324
325 static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 arg1, TCGv_i64 arg2,
326 TCGv_i64 arg3, TCGv_i64 arg4,
327 TCGv_i64 arg5, TCGArg arg6)
328 {
329 *tcg_ctx.gen_opc_ptr++ = opc;
330 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
331 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg2);
332 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg3);
333 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg4);
334 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg5);
335 *tcg_ctx.gen_opparam_ptr++ = arg6;
336 }
337
338 static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 arg1,
339 TCGv_i32 arg2, TCGv_i32 arg3,
340 TCGv_i32 arg4, TCGArg arg5, TCGArg arg6)
341 {
342 *tcg_ctx.gen_opc_ptr++ = opc;
343 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg1);
344 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg2);
345 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg3);
346 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I32(arg4);
347 *tcg_ctx.gen_opparam_ptr++ = arg5;
348 *tcg_ctx.gen_opparam_ptr++ = arg6;
349 }
350
351 static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 arg1,
352 TCGv_i64 arg2, TCGv_i64 arg3,
353 TCGv_i64 arg4, TCGArg arg5, TCGArg arg6)
354 {
355 *tcg_ctx.gen_opc_ptr++ = opc;
356 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg1);
357 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg2);
358 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg3);
359 *tcg_ctx.gen_opparam_ptr++ = GET_TCGV_I64(arg4);
360 *tcg_ctx.gen_opparam_ptr++ = arg5;
361 *tcg_ctx.gen_opparam_ptr++ = arg6;
362 }
363
364 static inline void gen_set_label(int n)
365 {
366 tcg_gen_op1i(INDEX_op_set_label, n);
367 }
368
369 static inline void tcg_gen_br(int label)
370 {
371 tcg_gen_op1i(INDEX_op_br, label);
372 }
373
374 static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg)
375 {
376 if (!TCGV_EQUAL_I32(ret, arg))
377 tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg);
378 }
379
380 static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg)
381 {
382 tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg);
383 }
384
385 /* A version of dh_sizemask from def-helper.h that doesn't rely on
386 preprocessor magic. */
387 static inline int tcg_gen_sizemask(int n, int is_64bit, int is_signed)
388 {
389 return (is_64bit << n*2) | (is_signed << (n*2 + 1));
390 }
391
392 /* helper calls */
393 static inline void tcg_gen_helperN(void *func, int flags, int sizemask,
394 TCGArg ret, int nargs, TCGArg *args)
395 {
396 TCGv_ptr fn;
397 fn = tcg_const_ptr(func);
398 tcg_gen_callN(&tcg_ctx, fn, flags, sizemask, ret,
399 nargs, args);
400 tcg_temp_free_ptr(fn);
401 }
402
403 /* Note: Both tcg_gen_helper32() and tcg_gen_helper64() are currently
404 reserved for helpers in tcg-runtime.c. These helpers all do not read
405 globals and do not have side effects, hence the call to tcg_gen_callN()
406 with TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_SIDE_EFFECTS. This may need
407 to be adjusted if these functions start to be used with other helpers. */
408 static inline void tcg_gen_helper32(void *func, int sizemask, TCGv_i32 ret,
409 TCGv_i32 a, TCGv_i32 b)
410 {
411 TCGv_ptr fn;
412 TCGArg args[2];
413 fn = tcg_const_ptr(func);
414 args[0] = GET_TCGV_I32(a);
415 args[1] = GET_TCGV_I32(b);
416 tcg_gen_callN(&tcg_ctx, fn,
417 TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_SIDE_EFFECTS,
418 sizemask, GET_TCGV_I32(ret), 2, args);
419 tcg_temp_free_ptr(fn);
420 }
421
422 static inline void tcg_gen_helper64(void *func, int sizemask, TCGv_i64 ret,
423 TCGv_i64 a, TCGv_i64 b)
424 {
425 TCGv_ptr fn;
426 TCGArg args[2];
427 fn = tcg_const_ptr(func);
428 args[0] = GET_TCGV_I64(a);
429 args[1] = GET_TCGV_I64(b);
430 tcg_gen_callN(&tcg_ctx, fn,
431 TCG_CALL_NO_READ_GLOBALS | TCG_CALL_NO_SIDE_EFFECTS,
432 sizemask, GET_TCGV_I64(ret), 2, args);
433 tcg_temp_free_ptr(fn);
434 }
435
436 /* 32 bit ops */
437
438 static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
439 {
440 tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset);
441 }
442
443 static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
444 {
445 tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset);
446 }
447
448 static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
449 {
450 tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset);
451 }
452
453 static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
454 {
455 tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset);
456 }
457
458 static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
459 {
460 tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset);
461 }
462
463 static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
464 {
465 tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset);
466 }
467
468 static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
469 {
470 tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset);
471 }
472
473 static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
474 {
475 tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset);
476 }
477
478 static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
479 {
480 tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2);
481 }
482
483 static inline void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
484 {
485 /* some cases can be optimized here */
486 if (arg2 == 0) {
487 tcg_gen_mov_i32(ret, arg1);
488 } else {
489 TCGv_i32 t0 = tcg_const_i32(arg2);
490 tcg_gen_add_i32(ret, arg1, t0);
491 tcg_temp_free_i32(t0);
492 }
493 }
494
495 static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
496 {
497 tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2);
498 }
499
500 static inline void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2)
501 {
502 TCGv_i32 t0 = tcg_const_i32(arg1);
503 tcg_gen_sub_i32(ret, t0, arg2);
504 tcg_temp_free_i32(t0);
505 }
506
507 static inline void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
508 {
509 /* some cases can be optimized here */
510 if (arg2 == 0) {
511 tcg_gen_mov_i32(ret, arg1);
512 } else {
513 TCGv_i32 t0 = tcg_const_i32(arg2);
514 tcg_gen_sub_i32(ret, arg1, t0);
515 tcg_temp_free_i32(t0);
516 }
517 }
518
519 static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
520 {
521 if (TCGV_EQUAL_I32(arg1, arg2)) {
522 tcg_gen_mov_i32(ret, arg1);
523 } else {
524 tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2);
525 }
526 }
527
528 static inline void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2)
529 {
530 TCGv_i32 t0;
531 /* Some cases can be optimized here. */
532 switch (arg2) {
533 case 0:
534 tcg_gen_movi_i32(ret, 0);
535 return;
536 case 0xffffffffu:
537 tcg_gen_mov_i32(ret, arg1);
538 return;
539 case 0xffu:
540 /* Don't recurse with tcg_gen_ext8u_i32. */
541 if (TCG_TARGET_HAS_ext8u_i32) {
542 tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg1);
543 return;
544 }
545 break;
546 case 0xffffu:
547 if (TCG_TARGET_HAS_ext16u_i32) {
548 tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg1);
549 return;
550 }
551 break;
552 }
553 t0 = tcg_const_i32(arg2);
554 tcg_gen_and_i32(ret, arg1, t0);
555 tcg_temp_free_i32(t0);
556 }
557
558 static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
559 {
560 if (TCGV_EQUAL_I32(arg1, arg2)) {
561 tcg_gen_mov_i32(ret, arg1);
562 } else {
563 tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2);
564 }
565 }
566
567 static inline void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
568 {
569 /* Some cases can be optimized here. */
570 if (arg2 == -1) {
571 tcg_gen_movi_i32(ret, -1);
572 } else if (arg2 == 0) {
573 tcg_gen_mov_i32(ret, arg1);
574 } else {
575 TCGv_i32 t0 = tcg_const_i32(arg2);
576 tcg_gen_or_i32(ret, arg1, t0);
577 tcg_temp_free_i32(t0);
578 }
579 }
580
581 static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
582 {
583 if (TCGV_EQUAL_I32(arg1, arg2)) {
584 tcg_gen_movi_i32(ret, 0);
585 } else {
586 tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2);
587 }
588 }
589
590 static inline void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
591 {
592 /* Some cases can be optimized here. */
593 if (arg2 == 0) {
594 tcg_gen_mov_i32(ret, arg1);
595 } else if (arg2 == -1 && TCG_TARGET_HAS_not_i32) {
596 /* Don't recurse with tcg_gen_not_i32. */
597 tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg1);
598 } else {
599 TCGv_i32 t0 = tcg_const_i32(arg2);
600 tcg_gen_xor_i32(ret, arg1, t0);
601 tcg_temp_free_i32(t0);
602 }
603 }
604
605 static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
606 {
607 tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2);
608 }
609
610 static inline void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
611 {
612 if (arg2 == 0) {
613 tcg_gen_mov_i32(ret, arg1);
614 } else {
615 TCGv_i32 t0 = tcg_const_i32(arg2);
616 tcg_gen_shl_i32(ret, arg1, t0);
617 tcg_temp_free_i32(t0);
618 }
619 }
620
621 static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
622 {
623 tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2);
624 }
625
626 static inline void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
627 {
628 if (arg2 == 0) {
629 tcg_gen_mov_i32(ret, arg1);
630 } else {
631 TCGv_i32 t0 = tcg_const_i32(arg2);
632 tcg_gen_shr_i32(ret, arg1, t0);
633 tcg_temp_free_i32(t0);
634 }
635 }
636
637 static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
638 {
639 tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2);
640 }
641
642 static inline void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
643 {
644 if (arg2 == 0) {
645 tcg_gen_mov_i32(ret, arg1);
646 } else {
647 TCGv_i32 t0 = tcg_const_i32(arg2);
648 tcg_gen_sar_i32(ret, arg1, t0);
649 tcg_temp_free_i32(t0);
650 }
651 }
652
653 static inline void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1,
654 TCGv_i32 arg2, int label_index)
655 {
656 if (cond == TCG_COND_ALWAYS) {
657 tcg_gen_br(label_index);
658 } else if (cond != TCG_COND_NEVER) {
659 tcg_gen_op4ii_i32(INDEX_op_brcond_i32, arg1, arg2, cond, label_index);
660 }
661 }
662
663 static inline void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1,
664 int32_t arg2, int label_index)
665 {
666 if (cond == TCG_COND_ALWAYS) {
667 tcg_gen_br(label_index);
668 } else if (cond != TCG_COND_NEVER) {
669 TCGv_i32 t0 = tcg_const_i32(arg2);
670 tcg_gen_brcond_i32(cond, arg1, t0, label_index);
671 tcg_temp_free_i32(t0);
672 }
673 }
674
675 static inline void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret,
676 TCGv_i32 arg1, TCGv_i32 arg2)
677 {
678 if (cond == TCG_COND_ALWAYS) {
679 tcg_gen_movi_i32(ret, 1);
680 } else if (cond == TCG_COND_NEVER) {
681 tcg_gen_movi_i32(ret, 0);
682 } else {
683 tcg_gen_op4i_i32(INDEX_op_setcond_i32, ret, arg1, arg2, cond);
684 }
685 }
686
687 static inline void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret,
688 TCGv_i32 arg1, int32_t arg2)
689 {
690 if (cond == TCG_COND_ALWAYS) {
691 tcg_gen_movi_i32(ret, 1);
692 } else if (cond == TCG_COND_NEVER) {
693 tcg_gen_movi_i32(ret, 0);
694 } else {
695 TCGv_i32 t0 = tcg_const_i32(arg2);
696 tcg_gen_setcond_i32(cond, ret, arg1, t0);
697 tcg_temp_free_i32(t0);
698 }
699 }
700
701 static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
702 {
703 tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2);
704 }
705
706 static inline void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
707 {
708 TCGv_i32 t0 = tcg_const_i32(arg2);
709 tcg_gen_mul_i32(ret, arg1, t0);
710 tcg_temp_free_i32(t0);
711 }
712
713 static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
714 {
715 if (TCG_TARGET_HAS_div_i32) {
716 tcg_gen_op3_i32(INDEX_op_div_i32, ret, arg1, arg2);
717 } else if (TCG_TARGET_HAS_div2_i32) {
718 TCGv_i32 t0 = tcg_temp_new_i32();
719 tcg_gen_sari_i32(t0, arg1, 31);
720 tcg_gen_op5_i32(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2);
721 tcg_temp_free_i32(t0);
722 } else {
723 int sizemask = 0;
724 /* Return value and both arguments are 32-bit and signed. */
725 sizemask |= tcg_gen_sizemask(0, 0, 1);
726 sizemask |= tcg_gen_sizemask(1, 0, 1);
727 sizemask |= tcg_gen_sizemask(2, 0, 1);
728 tcg_gen_helper32(tcg_helper_div_i32, sizemask, ret, arg1, arg2);
729 }
730 }
731
732 static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
733 {
734 if (TCG_TARGET_HAS_rem_i32) {
735 tcg_gen_op3_i32(INDEX_op_rem_i32, ret, arg1, arg2);
736 } else if (TCG_TARGET_HAS_div_i32) {
737 TCGv_i32 t0 = tcg_temp_new_i32();
738 tcg_gen_op3_i32(INDEX_op_div_i32, t0, arg1, arg2);
739 tcg_gen_mul_i32(t0, t0, arg2);
740 tcg_gen_sub_i32(ret, arg1, t0);
741 tcg_temp_free_i32(t0);
742 } else if (TCG_TARGET_HAS_div2_i32) {
743 TCGv_i32 t0 = tcg_temp_new_i32();
744 tcg_gen_sari_i32(t0, arg1, 31);
745 tcg_gen_op5_i32(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2);
746 tcg_temp_free_i32(t0);
747 } else {
748 int sizemask = 0;
749 /* Return value and both arguments are 32-bit and signed. */
750 sizemask |= tcg_gen_sizemask(0, 0, 1);
751 sizemask |= tcg_gen_sizemask(1, 0, 1);
752 sizemask |= tcg_gen_sizemask(2, 0, 1);
753 tcg_gen_helper32(tcg_helper_rem_i32, sizemask, ret, arg1, arg2);
754 }
755 }
756
757 static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
758 {
759 if (TCG_TARGET_HAS_div_i32) {
760 tcg_gen_op3_i32(INDEX_op_divu_i32, ret, arg1, arg2);
761 } else if (TCG_TARGET_HAS_div2_i32) {
762 TCGv_i32 t0 = tcg_temp_new_i32();
763 tcg_gen_movi_i32(t0, 0);
764 tcg_gen_op5_i32(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2);
765 tcg_temp_free_i32(t0);
766 } else {
767 int sizemask = 0;
768 /* Return value and both arguments are 32-bit and unsigned. */
769 sizemask |= tcg_gen_sizemask(0, 0, 0);
770 sizemask |= tcg_gen_sizemask(1, 0, 0);
771 sizemask |= tcg_gen_sizemask(2, 0, 0);
772 tcg_gen_helper32(tcg_helper_divu_i32, sizemask, ret, arg1, arg2);
773 }
774 }
775
776 static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
777 {
778 if (TCG_TARGET_HAS_rem_i32) {
779 tcg_gen_op3_i32(INDEX_op_remu_i32, ret, arg1, arg2);
780 } else if (TCG_TARGET_HAS_div_i32) {
781 TCGv_i32 t0 = tcg_temp_new_i32();
782 tcg_gen_op3_i32(INDEX_op_divu_i32, t0, arg1, arg2);
783 tcg_gen_mul_i32(t0, t0, arg2);
784 tcg_gen_sub_i32(ret, arg1, t0);
785 tcg_temp_free_i32(t0);
786 } else if (TCG_TARGET_HAS_div2_i32) {
787 TCGv_i32 t0 = tcg_temp_new_i32();
788 tcg_gen_movi_i32(t0, 0);
789 tcg_gen_op5_i32(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2);
790 tcg_temp_free_i32(t0);
791 } else {
792 int sizemask = 0;
793 /* Return value and both arguments are 32-bit and unsigned. */
794 sizemask |= tcg_gen_sizemask(0, 0, 0);
795 sizemask |= tcg_gen_sizemask(1, 0, 0);
796 sizemask |= tcg_gen_sizemask(2, 0, 0);
797 tcg_gen_helper32(tcg_helper_remu_i32, sizemask, ret, arg1, arg2);
798 }
799 }
800
801 #if TCG_TARGET_REG_BITS == 32
802
803 static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
804 {
805 if (!TCGV_EQUAL_I64(ret, arg)) {
806 tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
807 tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
808 }
809 }
810
811 static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
812 {
813 tcg_gen_movi_i32(TCGV_LOW(ret), arg);
814 tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32);
815 }
816
817 static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2,
818 tcg_target_long offset)
819 {
820 tcg_gen_ld8u_i32(TCGV_LOW(ret), arg2, offset);
821 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
822 }
823
824 static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2,
825 tcg_target_long offset)
826 {
827 tcg_gen_ld8s_i32(TCGV_LOW(ret), arg2, offset);
828 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), 31);
829 }
830
831 static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2,
832 tcg_target_long offset)
833 {
834 tcg_gen_ld16u_i32(TCGV_LOW(ret), arg2, offset);
835 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
836 }
837
838 static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2,
839 tcg_target_long offset)
840 {
841 tcg_gen_ld16s_i32(TCGV_LOW(ret), arg2, offset);
842 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
843 }
844
845 static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2,
846 tcg_target_long offset)
847 {
848 tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
849 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
850 }
851
852 static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2,
853 tcg_target_long offset)
854 {
855 tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
856 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
857 }
858
859 static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2,
860 tcg_target_long offset)
861 {
862 /* since arg2 and ret have different types, they cannot be the
863 same temporary */
864 #ifdef TCG_TARGET_WORDS_BIGENDIAN
865 tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset);
866 tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset + 4);
867 #else
868 tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
869 tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4);
870 #endif
871 }
872
873 static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
874 tcg_target_long offset)
875 {
876 tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset);
877 }
878
879 static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
880 tcg_target_long offset)
881 {
882 tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset);
883 }
884
885 static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
886 tcg_target_long offset)
887 {
888 tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
889 }
890
891 static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2,
892 tcg_target_long offset)
893 {
894 #ifdef TCG_TARGET_WORDS_BIGENDIAN
895 tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset);
896 tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset + 4);
897 #else
898 tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
899 tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4);
900 #endif
901 }
902
903 static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
904 {
905 tcg_gen_op6_i32(INDEX_op_add2_i32, TCGV_LOW(ret), TCGV_HIGH(ret),
906 TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
907 TCGV_HIGH(arg2));
908 /* Allow the optimizer room to replace add2 with two moves. */
909 tcg_gen_op0(INDEX_op_nop);
910 }
911
912 static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
913 {
914 tcg_gen_op6_i32(INDEX_op_sub2_i32, TCGV_LOW(ret), TCGV_HIGH(ret),
915 TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
916 TCGV_HIGH(arg2));
917 /* Allow the optimizer room to replace sub2 with two moves. */
918 tcg_gen_op0(INDEX_op_nop);
919 }
920
921 static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
922 {
923 tcg_gen_and_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
924 tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
925 }
926
927 static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
928 {
929 tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
930 tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
931 }
932
933 static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
934 {
935 tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
936 tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
937 }
938
939 static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
940 {
941 tcg_gen_ori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
942 tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
943 }
944
945 static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
946 {
947 tcg_gen_xor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
948 tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
949 }
950
951 static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
952 {
953 tcg_gen_xori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
954 tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
955 }
956
957 /* XXX: use generic code when basic block handling is OK or CPU
958 specific code (x86) */
959 static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
960 {
961 int sizemask = 0;
962 /* Return value and both arguments are 64-bit and signed. */
963 sizemask |= tcg_gen_sizemask(0, 1, 1);
964 sizemask |= tcg_gen_sizemask(1, 1, 1);
965 sizemask |= tcg_gen_sizemask(2, 1, 1);
966
967 tcg_gen_helper64(tcg_helper_shl_i64, sizemask, ret, arg1, arg2);
968 }
969
970 static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
971 {
972 tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0);
973 }
974
975 static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
976 {
977 int sizemask = 0;
978 /* Return value and both arguments are 64-bit and signed. */
979 sizemask |= tcg_gen_sizemask(0, 1, 1);
980 sizemask |= tcg_gen_sizemask(1, 1, 1);
981 sizemask |= tcg_gen_sizemask(2, 1, 1);
982
983 tcg_gen_helper64(tcg_helper_shr_i64, sizemask, ret, arg1, arg2);
984 }
985
986 static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
987 {
988 tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0);
989 }
990
991 static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
992 {
993 int sizemask = 0;
994 /* Return value and both arguments are 64-bit and signed. */
995 sizemask |= tcg_gen_sizemask(0, 1, 1);
996 sizemask |= tcg_gen_sizemask(1, 1, 1);
997 sizemask |= tcg_gen_sizemask(2, 1, 1);
998
999 tcg_gen_helper64(tcg_helper_sar_i64, sizemask, ret, arg1, arg2);
1000 }
1001
1002 static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1003 {
1004 tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1);
1005 }
1006
1007 static inline void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1,
1008 TCGv_i64 arg2, int label_index)
1009 {
1010 if (cond == TCG_COND_ALWAYS) {
1011 tcg_gen_br(label_index);
1012 } else if (cond != TCG_COND_NEVER) {
1013 tcg_gen_op6ii_i32(INDEX_op_brcond2_i32,
1014 TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
1015 TCGV_HIGH(arg2), cond, label_index);
1016 }
1017 }
1018
1019 static inline void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
1020 TCGv_i64 arg1, TCGv_i64 arg2)
1021 {
1022 if (cond == TCG_COND_ALWAYS) {
1023 tcg_gen_movi_i32(TCGV_LOW(ret), 1);
1024 } else if (cond == TCG_COND_NEVER) {
1025 tcg_gen_movi_i32(TCGV_LOW(ret), 0);
1026 } else {
1027 tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret),
1028 TCGV_LOW(arg1), TCGV_HIGH(arg1),
1029 TCGV_LOW(arg2), TCGV_HIGH(arg2), cond);
1030 }
1031 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1032 }
1033
1034 static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1035 {
1036 TCGv_i64 t0;
1037 TCGv_i32 t1;
1038
1039 t0 = tcg_temp_new_i64();
1040 t1 = tcg_temp_new_i32();
1041
1042 tcg_gen_op4_i32(INDEX_op_mulu2_i32, TCGV_LOW(t0), TCGV_HIGH(t0),
1043 TCGV_LOW(arg1), TCGV_LOW(arg2));
1044 /* Allow the optimizer room to replace mulu2 with two moves. */
1045 tcg_gen_op0(INDEX_op_nop);
1046
1047 tcg_gen_mul_i32(t1, TCGV_LOW(arg1), TCGV_HIGH(arg2));
1048 tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
1049 tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), TCGV_LOW(arg2));
1050 tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
1051
1052 tcg_gen_mov_i64(ret, t0);
1053 tcg_temp_free_i64(t0);
1054 tcg_temp_free_i32(t1);
1055 }
1056
1057 static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1058 {
1059 int sizemask = 0;
1060 /* Return value and both arguments are 64-bit and signed. */
1061 sizemask |= tcg_gen_sizemask(0, 1, 1);
1062 sizemask |= tcg_gen_sizemask(1, 1, 1);
1063 sizemask |= tcg_gen_sizemask(2, 1, 1);
1064
1065 tcg_gen_helper64(tcg_helper_div_i64, sizemask, ret, arg1, arg2);
1066 }
1067
1068 static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1069 {
1070 int sizemask = 0;
1071 /* Return value and both arguments are 64-bit and signed. */
1072 sizemask |= tcg_gen_sizemask(0, 1, 1);
1073 sizemask |= tcg_gen_sizemask(1, 1, 1);
1074 sizemask |= tcg_gen_sizemask(2, 1, 1);
1075
1076 tcg_gen_helper64(tcg_helper_rem_i64, sizemask, ret, arg1, arg2);
1077 }
1078
1079 static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1080 {
1081 int sizemask = 0;
1082 /* Return value and both arguments are 64-bit and unsigned. */
1083 sizemask |= tcg_gen_sizemask(0, 1, 0);
1084 sizemask |= tcg_gen_sizemask(1, 1, 0);
1085 sizemask |= tcg_gen_sizemask(2, 1, 0);
1086
1087 tcg_gen_helper64(tcg_helper_divu_i64, sizemask, ret, arg1, arg2);
1088 }
1089
1090 static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1091 {
1092 int sizemask = 0;
1093 /* Return value and both arguments are 64-bit and unsigned. */
1094 sizemask |= tcg_gen_sizemask(0, 1, 0);
1095 sizemask |= tcg_gen_sizemask(1, 1, 0);
1096 sizemask |= tcg_gen_sizemask(2, 1, 0);
1097
1098 tcg_gen_helper64(tcg_helper_remu_i64, sizemask, ret, arg1, arg2);
1099 }
1100
1101 #else
1102
1103 static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
1104 {
1105 if (!TCGV_EQUAL_I64(ret, arg))
1106 tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg);
1107 }
1108
1109 static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
1110 {
1111 tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg);
1112 }
1113
1114 static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2,
1115 tcg_target_long offset)
1116 {
1117 tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset);
1118 }
1119
1120 static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2,
1121 tcg_target_long offset)
1122 {
1123 tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset);
1124 }
1125
1126 static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2,
1127 tcg_target_long offset)
1128 {
1129 tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset);
1130 }
1131
1132 static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2,
1133 tcg_target_long offset)
1134 {
1135 tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset);
1136 }
1137
1138 static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2,
1139 tcg_target_long offset)
1140 {
1141 tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset);
1142 }
1143
1144 static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2,
1145 tcg_target_long offset)
1146 {
1147 tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset);
1148 }
1149
1150 static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset)
1151 {
1152 tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset);
1153 }
1154
1155 static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
1156 tcg_target_long offset)
1157 {
1158 tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset);
1159 }
1160
1161 static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
1162 tcg_target_long offset)
1163 {
1164 tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset);
1165 }
1166
1167 static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
1168 tcg_target_long offset)
1169 {
1170 tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset);
1171 }
1172
1173 static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset)
1174 {
1175 tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset);
1176 }
1177
1178 static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1179 {
1180 tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2);
1181 }
1182
1183 static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1184 {
1185 tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2);
1186 }
1187
1188 static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1189 {
1190 if (TCGV_EQUAL_I64(arg1, arg2)) {
1191 tcg_gen_mov_i64(ret, arg1);
1192 } else {
1193 tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2);
1194 }
1195 }
1196
1197 static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2)
1198 {
1199 TCGv_i64 t0;
1200 /* Some cases can be optimized here. */
1201 switch (arg2) {
1202 case 0:
1203 tcg_gen_movi_i64(ret, 0);
1204 return;
1205 case 0xffffffffffffffffull:
1206 tcg_gen_mov_i64(ret, arg1);
1207 return;
1208 case 0xffull:
1209 /* Don't recurse with tcg_gen_ext8u_i32. */
1210 if (TCG_TARGET_HAS_ext8u_i64) {
1211 tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg1);
1212 return;
1213 }
1214 break;
1215 case 0xffffu:
1216 if (TCG_TARGET_HAS_ext16u_i64) {
1217 tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg1);
1218 return;
1219 }
1220 break;
1221 case 0xffffffffull:
1222 if (TCG_TARGET_HAS_ext32u_i64) {
1223 tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg1);
1224 return;
1225 }
1226 break;
1227 }
1228 t0 = tcg_const_i64(arg2);
1229 tcg_gen_and_i64(ret, arg1, t0);
1230 tcg_temp_free_i64(t0);
1231 }
1232
1233 static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1234 {
1235 if (TCGV_EQUAL_I64(arg1, arg2)) {
1236 tcg_gen_mov_i64(ret, arg1);
1237 } else {
1238 tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2);
1239 }
1240 }
1241
1242 static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1243 {
1244 /* Some cases can be optimized here. */
1245 if (arg2 == -1) {
1246 tcg_gen_movi_i64(ret, -1);
1247 } else if (arg2 == 0) {
1248 tcg_gen_mov_i64(ret, arg1);
1249 } else {
1250 TCGv_i64 t0 = tcg_const_i64(arg2);
1251 tcg_gen_or_i64(ret, arg1, t0);
1252 tcg_temp_free_i64(t0);
1253 }
1254 }
1255
1256 static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1257 {
1258 if (TCGV_EQUAL_I64(arg1, arg2)) {
1259 tcg_gen_movi_i64(ret, 0);
1260 } else {
1261 tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2);
1262 }
1263 }
1264
1265 static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1266 {
1267 /* Some cases can be optimized here. */
1268 if (arg2 == 0) {
1269 tcg_gen_mov_i64(ret, arg1);
1270 } else if (arg2 == -1 && TCG_TARGET_HAS_not_i64) {
1271 /* Don't recurse with tcg_gen_not_i64. */
1272 tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg1);
1273 } else {
1274 TCGv_i64 t0 = tcg_const_i64(arg2);
1275 tcg_gen_xor_i64(ret, arg1, t0);
1276 tcg_temp_free_i64(t0);
1277 }
1278 }
1279
1280 static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1281 {
1282 tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2);
1283 }
1284
1285 static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1286 {
1287 if (arg2 == 0) {
1288 tcg_gen_mov_i64(ret, arg1);
1289 } else {
1290 TCGv_i64 t0 = tcg_const_i64(arg2);
1291 tcg_gen_shl_i64(ret, arg1, t0);
1292 tcg_temp_free_i64(t0);
1293 }
1294 }
1295
1296 static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1297 {
1298 tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2);
1299 }
1300
1301 static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1302 {
1303 if (arg2 == 0) {
1304 tcg_gen_mov_i64(ret, arg1);
1305 } else {
1306 TCGv_i64 t0 = tcg_const_i64(arg2);
1307 tcg_gen_shr_i64(ret, arg1, t0);
1308 tcg_temp_free_i64(t0);
1309 }
1310 }
1311
1312 static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1313 {
1314 tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2);
1315 }
1316
1317 static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1318 {
1319 if (arg2 == 0) {
1320 tcg_gen_mov_i64(ret, arg1);
1321 } else {
1322 TCGv_i64 t0 = tcg_const_i64(arg2);
1323 tcg_gen_sar_i64(ret, arg1, t0);
1324 tcg_temp_free_i64(t0);
1325 }
1326 }
1327
1328 static inline void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1,
1329 TCGv_i64 arg2, int label_index)
1330 {
1331 if (cond == TCG_COND_ALWAYS) {
1332 tcg_gen_br(label_index);
1333 } else if (cond != TCG_COND_NEVER) {
1334 tcg_gen_op4ii_i64(INDEX_op_brcond_i64, arg1, arg2, cond, label_index);
1335 }
1336 }
1337
1338 static inline void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
1339 TCGv_i64 arg1, TCGv_i64 arg2)
1340 {
1341 if (cond == TCG_COND_ALWAYS) {
1342 tcg_gen_movi_i64(ret, 1);
1343 } else if (cond == TCG_COND_NEVER) {
1344 tcg_gen_movi_i64(ret, 0);
1345 } else {
1346 tcg_gen_op4i_i64(INDEX_op_setcond_i64, ret, arg1, arg2, cond);
1347 }
1348 }
1349
1350 static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1351 {
1352 tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2);
1353 }
1354
1355 static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1356 {
1357 if (TCG_TARGET_HAS_div_i64) {
1358 tcg_gen_op3_i64(INDEX_op_div_i64, ret, arg1, arg2);
1359 } else if (TCG_TARGET_HAS_div2_i64) {
1360 TCGv_i64 t0 = tcg_temp_new_i64();
1361 tcg_gen_sari_i64(t0, arg1, 63);
1362 tcg_gen_op5_i64(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2);
1363 tcg_temp_free_i64(t0);
1364 } else {
1365 int sizemask = 0;
1366 /* Return value and both arguments are 64-bit and signed. */
1367 sizemask |= tcg_gen_sizemask(0, 1, 1);
1368 sizemask |= tcg_gen_sizemask(1, 1, 1);
1369 sizemask |= tcg_gen_sizemask(2, 1, 1);
1370 tcg_gen_helper64(tcg_helper_div_i64, sizemask, ret, arg1, arg2);
1371 }
1372 }
1373
1374 static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1375 {
1376 if (TCG_TARGET_HAS_rem_i64) {
1377 tcg_gen_op3_i64(INDEX_op_rem_i64, ret, arg1, arg2);
1378 } else if (TCG_TARGET_HAS_div_i64) {
1379 TCGv_i64 t0 = tcg_temp_new_i64();
1380 tcg_gen_op3_i64(INDEX_op_div_i64, t0, arg1, arg2);
1381 tcg_gen_mul_i64(t0, t0, arg2);
1382 tcg_gen_sub_i64(ret, arg1, t0);
1383 tcg_temp_free_i64(t0);
1384 } else if (TCG_TARGET_HAS_div2_i64) {
1385 TCGv_i64 t0 = tcg_temp_new_i64();
1386 tcg_gen_sari_i64(t0, arg1, 63);
1387 tcg_gen_op5_i64(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2);
1388 tcg_temp_free_i64(t0);
1389 } else {
1390 int sizemask = 0;
1391 /* Return value and both arguments are 64-bit and signed. */
1392 sizemask |= tcg_gen_sizemask(0, 1, 1);
1393 sizemask |= tcg_gen_sizemask(1, 1, 1);
1394 sizemask |= tcg_gen_sizemask(2, 1, 1);
1395 tcg_gen_helper64(tcg_helper_rem_i64, sizemask, ret, arg1, arg2);
1396 }
1397 }
1398
1399 static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1400 {
1401 if (TCG_TARGET_HAS_div_i64) {
1402 tcg_gen_op3_i64(INDEX_op_divu_i64, ret, arg1, arg2);
1403 } else if (TCG_TARGET_HAS_div2_i64) {
1404 TCGv_i64 t0 = tcg_temp_new_i64();
1405 tcg_gen_movi_i64(t0, 0);
1406 tcg_gen_op5_i64(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2);
1407 tcg_temp_free_i64(t0);
1408 } else {
1409 int sizemask = 0;
1410 /* Return value and both arguments are 64-bit and unsigned. */
1411 sizemask |= tcg_gen_sizemask(0, 1, 0);
1412 sizemask |= tcg_gen_sizemask(1, 1, 0);
1413 sizemask |= tcg_gen_sizemask(2, 1, 0);
1414 tcg_gen_helper64(tcg_helper_divu_i64, sizemask, ret, arg1, arg2);
1415 }
1416 }
1417
1418 static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1419 {
1420 if (TCG_TARGET_HAS_rem_i64) {
1421 tcg_gen_op3_i64(INDEX_op_remu_i64, ret, arg1, arg2);
1422 } else if (TCG_TARGET_HAS_div_i64) {
1423 TCGv_i64 t0 = tcg_temp_new_i64();
1424 tcg_gen_op3_i64(INDEX_op_divu_i64, t0, arg1, arg2);
1425 tcg_gen_mul_i64(t0, t0, arg2);
1426 tcg_gen_sub_i64(ret, arg1, t0);
1427 tcg_temp_free_i64(t0);
1428 } else if (TCG_TARGET_HAS_div2_i64) {
1429 TCGv_i64 t0 = tcg_temp_new_i64();
1430 tcg_gen_movi_i64(t0, 0);
1431 tcg_gen_op5_i64(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2);
1432 tcg_temp_free_i64(t0);
1433 } else {
1434 int sizemask = 0;
1435 /* Return value and both arguments are 64-bit and unsigned. */
1436 sizemask |= tcg_gen_sizemask(0, 1, 0);
1437 sizemask |= tcg_gen_sizemask(1, 1, 0);
1438 sizemask |= tcg_gen_sizemask(2, 1, 0);
1439 tcg_gen_helper64(tcg_helper_remu_i64, sizemask, ret, arg1, arg2);
1440 }
1441 }
1442 #endif /* TCG_TARGET_REG_BITS == 32 */
1443
1444 static inline void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1445 {
1446 /* some cases can be optimized here */
1447 if (arg2 == 0) {
1448 tcg_gen_mov_i64(ret, arg1);
1449 } else {
1450 TCGv_i64 t0 = tcg_const_i64(arg2);
1451 tcg_gen_add_i64(ret, arg1, t0);
1452 tcg_temp_free_i64(t0);
1453 }
1454 }
1455
1456 static inline void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2)
1457 {
1458 TCGv_i64 t0 = tcg_const_i64(arg1);
1459 tcg_gen_sub_i64(ret, t0, arg2);
1460 tcg_temp_free_i64(t0);
1461 }
1462
1463 static inline void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1464 {
1465 /* some cases can be optimized here */
1466 if (arg2 == 0) {
1467 tcg_gen_mov_i64(ret, arg1);
1468 } else {
1469 TCGv_i64 t0 = tcg_const_i64(arg2);
1470 tcg_gen_sub_i64(ret, arg1, t0);
1471 tcg_temp_free_i64(t0);
1472 }
1473 }
1474 static inline void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1,
1475 int64_t arg2, int label_index)
1476 {
1477 if (cond == TCG_COND_ALWAYS) {
1478 tcg_gen_br(label_index);
1479 } else if (cond != TCG_COND_NEVER) {
1480 TCGv_i64 t0 = tcg_const_i64(arg2);
1481 tcg_gen_brcond_i64(cond, arg1, t0, label_index);
1482 tcg_temp_free_i64(t0);
1483 }
1484 }
1485
1486 static inline void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
1487 TCGv_i64 arg1, int64_t arg2)
1488 {
1489 TCGv_i64 t0 = tcg_const_i64(arg2);
1490 tcg_gen_setcond_i64(cond, ret, arg1, t0);
1491 tcg_temp_free_i64(t0);
1492 }
1493
1494 static inline void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1495 {
1496 TCGv_i64 t0 = tcg_const_i64(arg2);
1497 tcg_gen_mul_i64(ret, arg1, t0);
1498 tcg_temp_free_i64(t0);
1499 }
1500
1501
1502 /***************************************/
1503 /* optional operations */
1504
1505 static inline void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg)
1506 {
1507 if (TCG_TARGET_HAS_ext8s_i32) {
1508 tcg_gen_op2_i32(INDEX_op_ext8s_i32, ret, arg);
1509 } else {
1510 tcg_gen_shli_i32(ret, arg, 24);
1511 tcg_gen_sari_i32(ret, ret, 24);
1512 }
1513 }
1514
1515 static inline void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg)
1516 {
1517 if (TCG_TARGET_HAS_ext16s_i32) {
1518 tcg_gen_op2_i32(INDEX_op_ext16s_i32, ret, arg);
1519 } else {
1520 tcg_gen_shli_i32(ret, arg, 16);
1521 tcg_gen_sari_i32(ret, ret, 16);
1522 }
1523 }
1524
1525 static inline void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg)
1526 {
1527 if (TCG_TARGET_HAS_ext8u_i32) {
1528 tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg);
1529 } else {
1530 tcg_gen_andi_i32(ret, arg, 0xffu);
1531 }
1532 }
1533
1534 static inline void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg)
1535 {
1536 if (TCG_TARGET_HAS_ext16u_i32) {
1537 tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg);
1538 } else {
1539 tcg_gen_andi_i32(ret, arg, 0xffffu);
1540 }
1541 }
1542
1543 /* Note: we assume the two high bytes are set to zero */
1544 static inline void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg)
1545 {
1546 if (TCG_TARGET_HAS_bswap16_i32) {
1547 tcg_gen_op2_i32(INDEX_op_bswap16_i32, ret, arg);
1548 } else {
1549 TCGv_i32 t0 = tcg_temp_new_i32();
1550
1551 tcg_gen_ext8u_i32(t0, arg);
1552 tcg_gen_shli_i32(t0, t0, 8);
1553 tcg_gen_shri_i32(ret, arg, 8);
1554 tcg_gen_or_i32(ret, ret, t0);
1555 tcg_temp_free_i32(t0);
1556 }
1557 }
1558
1559 static inline void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg)
1560 {
1561 if (TCG_TARGET_HAS_bswap32_i32) {
1562 tcg_gen_op2_i32(INDEX_op_bswap32_i32, ret, arg);
1563 } else {
1564 TCGv_i32 t0, t1;
1565 t0 = tcg_temp_new_i32();
1566 t1 = tcg_temp_new_i32();
1567
1568 tcg_gen_shli_i32(t0, arg, 24);
1569
1570 tcg_gen_andi_i32(t1, arg, 0x0000ff00);
1571 tcg_gen_shli_i32(t1, t1, 8);
1572 tcg_gen_or_i32(t0, t0, t1);
1573
1574 tcg_gen_shri_i32(t1, arg, 8);
1575 tcg_gen_andi_i32(t1, t1, 0x0000ff00);
1576 tcg_gen_or_i32(t0, t0, t1);
1577
1578 tcg_gen_shri_i32(t1, arg, 24);
1579 tcg_gen_or_i32(ret, t0, t1);
1580 tcg_temp_free_i32(t0);
1581 tcg_temp_free_i32(t1);
1582 }
1583 }
1584
1585 #if TCG_TARGET_REG_BITS == 32
1586 static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg)
1587 {
1588 tcg_gen_ext8s_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1589 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1590 }
1591
1592 static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg)
1593 {
1594 tcg_gen_ext16s_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1595 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1596 }
1597
1598 static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg)
1599 {
1600 tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1601 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1602 }
1603
1604 static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg)
1605 {
1606 tcg_gen_ext8u_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1607 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1608 }
1609
1610 static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg)
1611 {
1612 tcg_gen_ext16u_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1613 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1614 }
1615
1616 static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg)
1617 {
1618 tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1619 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1620 }
1621
1622 static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
1623 {
1624 tcg_gen_mov_i32(ret, TCGV_LOW(arg));
1625 }
1626
1627 static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1628 {
1629 tcg_gen_mov_i32(TCGV_LOW(ret), arg);
1630 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1631 }
1632
1633 static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1634 {
1635 tcg_gen_mov_i32(TCGV_LOW(ret), arg);
1636 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1637 }
1638
1639 /* Note: we assume the six high bytes are set to zero */
1640 static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg)
1641 {
1642 tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1643 tcg_gen_bswap16_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1644 }
1645
1646 /* Note: we assume the four high bytes are set to zero */
1647 static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg)
1648 {
1649 tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1650 tcg_gen_bswap32_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1651 }
1652
1653 static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
1654 {
1655 TCGv_i32 t0, t1;
1656 t0 = tcg_temp_new_i32();
1657 t1 = tcg_temp_new_i32();
1658
1659 tcg_gen_bswap32_i32(t0, TCGV_LOW(arg));
1660 tcg_gen_bswap32_i32(t1, TCGV_HIGH(arg));
1661 tcg_gen_mov_i32(TCGV_LOW(ret), t1);
1662 tcg_gen_mov_i32(TCGV_HIGH(ret), t0);
1663 tcg_temp_free_i32(t0);
1664 tcg_temp_free_i32(t1);
1665 }
1666 #else
1667
1668 static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg)
1669 {
1670 if (TCG_TARGET_HAS_ext8s_i64) {
1671 tcg_gen_op2_i64(INDEX_op_ext8s_i64, ret, arg);
1672 } else {
1673 tcg_gen_shli_i64(ret, arg, 56);
1674 tcg_gen_sari_i64(ret, ret, 56);
1675 }
1676 }
1677
1678 static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg)
1679 {
1680 if (TCG_TARGET_HAS_ext16s_i64) {
1681 tcg_gen_op2_i64(INDEX_op_ext16s_i64, ret, arg);
1682 } else {
1683 tcg_gen_shli_i64(ret, arg, 48);
1684 tcg_gen_sari_i64(ret, ret, 48);
1685 }
1686 }
1687
1688 static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg)
1689 {
1690 if (TCG_TARGET_HAS_ext32s_i64) {
1691 tcg_gen_op2_i64(INDEX_op_ext32s_i64, ret, arg);
1692 } else {
1693 tcg_gen_shli_i64(ret, arg, 32);
1694 tcg_gen_sari_i64(ret, ret, 32);
1695 }
1696 }
1697
1698 static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg)
1699 {
1700 if (TCG_TARGET_HAS_ext8u_i64) {
1701 tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg);
1702 } else {
1703 tcg_gen_andi_i64(ret, arg, 0xffu);
1704 }
1705 }
1706
1707 static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg)
1708 {
1709 if (TCG_TARGET_HAS_ext16u_i64) {
1710 tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg);
1711 } else {
1712 tcg_gen_andi_i64(ret, arg, 0xffffu);
1713 }
1714 }
1715
1716 static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg)
1717 {
1718 if (TCG_TARGET_HAS_ext32u_i64) {
1719 tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg);
1720 } else {
1721 tcg_gen_andi_i64(ret, arg, 0xffffffffu);
1722 }
1723 }
1724
1725 /* Note: we assume the target supports move between 32 and 64 bit
1726 registers. This will probably break MIPS64 targets. */
1727 static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
1728 {
1729 tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg)));
1730 }
1731
1732 /* Note: we assume the target supports move between 32 and 64 bit
1733 registers */
1734 static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1735 {
1736 tcg_gen_ext32u_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)));
1737 }
1738
1739 /* Note: we assume the target supports move between 32 and 64 bit
1740 registers */
1741 static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1742 {
1743 tcg_gen_ext32s_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)));
1744 }
1745
1746 /* Note: we assume the six high bytes are set to zero */
1747 static inline void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg)
1748 {
1749 if (TCG_TARGET_HAS_bswap16_i64) {
1750 tcg_gen_op2_i64(INDEX_op_bswap16_i64, ret, arg);
1751 } else {
1752 TCGv_i64 t0 = tcg_temp_new_i64();
1753
1754 tcg_gen_ext8u_i64(t0, arg);
1755 tcg_gen_shli_i64(t0, t0, 8);
1756 tcg_gen_shri_i64(ret, arg, 8);
1757 tcg_gen_or_i64(ret, ret, t0);
1758 tcg_temp_free_i64(t0);
1759 }
1760 }
1761
1762 /* Note: we assume the four high bytes are set to zero */
1763 static inline void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg)
1764 {
1765 if (TCG_TARGET_HAS_bswap32_i64) {
1766 tcg_gen_op2_i64(INDEX_op_bswap32_i64, ret, arg);
1767 } else {
1768 TCGv_i64 t0, t1;
1769 t0 = tcg_temp_new_i64();
1770 t1 = tcg_temp_new_i64();
1771
1772 tcg_gen_shli_i64(t0, arg, 24);
1773 tcg_gen_ext32u_i64(t0, t0);
1774
1775 tcg_gen_andi_i64(t1, arg, 0x0000ff00);
1776 tcg_gen_shli_i64(t1, t1, 8);
1777 tcg_gen_or_i64(t0, t0, t1);
1778
1779 tcg_gen_shri_i64(t1, arg, 8);
1780 tcg_gen_andi_i64(t1, t1, 0x0000ff00);
1781 tcg_gen_or_i64(t0, t0, t1);
1782
1783 tcg_gen_shri_i64(t1, arg, 24);
1784 tcg_gen_or_i64(ret, t0, t1);
1785 tcg_temp_free_i64(t0);
1786 tcg_temp_free_i64(t1);
1787 }
1788 }
1789
1790 static inline void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg)
1791 {
1792 if (TCG_TARGET_HAS_bswap64_i64) {
1793 tcg_gen_op2_i64(INDEX_op_bswap64_i64, ret, arg);
1794 } else {
1795 TCGv_i64 t0 = tcg_temp_new_i64();
1796 TCGv_i64 t1 = tcg_temp_new_i64();
1797
1798 tcg_gen_shli_i64(t0, arg, 56);
1799
1800 tcg_gen_andi_i64(t1, arg, 0x0000ff00);
1801 tcg_gen_shli_i64(t1, t1, 40);
1802 tcg_gen_or_i64(t0, t0, t1);
1803
1804 tcg_gen_andi_i64(t1, arg, 0x00ff0000);
1805 tcg_gen_shli_i64(t1, t1, 24);
1806 tcg_gen_or_i64(t0, t0, t1);
1807
1808 tcg_gen_andi_i64(t1, arg, 0xff000000);
1809 tcg_gen_shli_i64(t1, t1, 8);
1810 tcg_gen_or_i64(t0, t0, t1);
1811
1812 tcg_gen_shri_i64(t1, arg, 8);
1813 tcg_gen_andi_i64(t1, t1, 0xff000000);
1814 tcg_gen_or_i64(t0, t0, t1);
1815
1816 tcg_gen_shri_i64(t1, arg, 24);
1817 tcg_gen_andi_i64(t1, t1, 0x00ff0000);
1818 tcg_gen_or_i64(t0, t0, t1);
1819
1820 tcg_gen_shri_i64(t1, arg, 40);
1821 tcg_gen_andi_i64(t1, t1, 0x0000ff00);
1822 tcg_gen_or_i64(t0, t0, t1);
1823
1824 tcg_gen_shri_i64(t1, arg, 56);
1825 tcg_gen_or_i64(ret, t0, t1);
1826 tcg_temp_free_i64(t0);
1827 tcg_temp_free_i64(t1);
1828 }
1829 }
1830
1831 #endif
1832
1833 static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg)
1834 {
1835 if (TCG_TARGET_HAS_neg_i32) {
1836 tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg);
1837 } else {
1838 TCGv_i32 t0 = tcg_const_i32(0);
1839 tcg_gen_sub_i32(ret, t0, arg);
1840 tcg_temp_free_i32(t0);
1841 }
1842 }
1843
1844 static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg)
1845 {
1846 if (TCG_TARGET_HAS_neg_i64) {
1847 tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg);
1848 } else {
1849 TCGv_i64 t0 = tcg_const_i64(0);
1850 tcg_gen_sub_i64(ret, t0, arg);
1851 tcg_temp_free_i64(t0);
1852 }
1853 }
1854
1855 static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg)
1856 {
1857 if (TCG_TARGET_HAS_not_i32) {
1858 tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg);
1859 } else {
1860 tcg_gen_xori_i32(ret, arg, -1);
1861 }
1862 }
1863
1864 static inline void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg)
1865 {
1866 #if TCG_TARGET_REG_BITS == 64
1867 if (TCG_TARGET_HAS_not_i64) {
1868 tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg);
1869 } else {
1870 tcg_gen_xori_i64(ret, arg, -1);
1871 }
1872 #else
1873 tcg_gen_not_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1874 tcg_gen_not_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
1875 #endif
1876 }
1877
1878 static inline void tcg_gen_discard_i32(TCGv_i32 arg)
1879 {
1880 tcg_gen_op1_i32(INDEX_op_discard, arg);
1881 }
1882
1883 static inline void tcg_gen_discard_i64(TCGv_i64 arg)
1884 {
1885 #if TCG_TARGET_REG_BITS == 32
1886 tcg_gen_discard_i32(TCGV_LOW(arg));
1887 tcg_gen_discard_i32(TCGV_HIGH(arg));
1888 #else
1889 tcg_gen_op1_i64(INDEX_op_discard, arg);
1890 #endif
1891 }
1892
1893 static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1894 {
1895 if (TCG_TARGET_HAS_andc_i32) {
1896 tcg_gen_op3_i32(INDEX_op_andc_i32, ret, arg1, arg2);
1897 } else {
1898 TCGv_i32 t0 = tcg_temp_new_i32();
1899 tcg_gen_not_i32(t0, arg2);
1900 tcg_gen_and_i32(ret, arg1, t0);
1901 tcg_temp_free_i32(t0);
1902 }
1903 }
1904
1905 static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1906 {
1907 #if TCG_TARGET_REG_BITS == 64
1908 if (TCG_TARGET_HAS_andc_i64) {
1909 tcg_gen_op3_i64(INDEX_op_andc_i64, ret, arg1, arg2);
1910 } else {
1911 TCGv_i64 t0 = tcg_temp_new_i64();
1912 tcg_gen_not_i64(t0, arg2);
1913 tcg_gen_and_i64(ret, arg1, t0);
1914 tcg_temp_free_i64(t0);
1915 }
1916 #else
1917 tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1918 tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1919 #endif
1920 }
1921
1922 static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1923 {
1924 if (TCG_TARGET_HAS_eqv_i32) {
1925 tcg_gen_op3_i32(INDEX_op_eqv_i32, ret, arg1, arg2);
1926 } else {
1927 tcg_gen_xor_i32(ret, arg1, arg2);
1928 tcg_gen_not_i32(ret, ret);
1929 }
1930 }
1931
1932 static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1933 {
1934 #if TCG_TARGET_REG_BITS == 64
1935 if (TCG_TARGET_HAS_eqv_i64) {
1936 tcg_gen_op3_i64(INDEX_op_eqv_i64, ret, arg1, arg2);
1937 } else {
1938 tcg_gen_xor_i64(ret, arg1, arg2);
1939 tcg_gen_not_i64(ret, ret);
1940 }
1941 #else
1942 tcg_gen_eqv_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1943 tcg_gen_eqv_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1944 #endif
1945 }
1946
1947 static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1948 {
1949 if (TCG_TARGET_HAS_nand_i32) {
1950 tcg_gen_op3_i32(INDEX_op_nand_i32, ret, arg1, arg2);
1951 } else {
1952 tcg_gen_and_i32(ret, arg1, arg2);
1953 tcg_gen_not_i32(ret, ret);
1954 }
1955 }
1956
1957 static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1958 {
1959 #if TCG_TARGET_REG_BITS == 64
1960 if (TCG_TARGET_HAS_nand_i64) {
1961 tcg_gen_op3_i64(INDEX_op_nand_i64, ret, arg1, arg2);
1962 } else {
1963 tcg_gen_and_i64(ret, arg1, arg2);
1964 tcg_gen_not_i64(ret, ret);
1965 }
1966 #else
1967 tcg_gen_nand_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1968 tcg_gen_nand_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1969 #endif
1970 }
1971
1972 static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1973 {
1974 if (TCG_TARGET_HAS_nor_i32) {
1975 tcg_gen_op3_i32(INDEX_op_nor_i32, ret, arg1, arg2);
1976 } else {
1977 tcg_gen_or_i32(ret, arg1, arg2);
1978 tcg_gen_not_i32(ret, ret);
1979 }
1980 }
1981
1982 static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1983 {
1984 #if TCG_TARGET_REG_BITS == 64
1985 if (TCG_TARGET_HAS_nor_i64) {
1986 tcg_gen_op3_i64(INDEX_op_nor_i64, ret, arg1, arg2);
1987 } else {
1988 tcg_gen_or_i64(ret, arg1, arg2);
1989 tcg_gen_not_i64(ret, ret);
1990 }
1991 #else
1992 tcg_gen_nor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
1993 tcg_gen_nor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
1994 #endif
1995 }
1996
1997 static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1998 {
1999 if (TCG_TARGET_HAS_orc_i32) {
2000 tcg_gen_op3_i32(INDEX_op_orc_i32, ret, arg1, arg2);
2001 } else {
2002 TCGv_i32 t0 = tcg_temp_new_i32();
2003 tcg_gen_not_i32(t0, arg2);
2004 tcg_gen_or_i32(ret, arg1, t0);
2005 tcg_temp_free_i32(t0);
2006 }
2007 }
2008
2009 static inline void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
2010 {
2011 #if TCG_TARGET_REG_BITS == 64
2012 if (TCG_TARGET_HAS_orc_i64) {
2013 tcg_gen_op3_i64(INDEX_op_orc_i64, ret, arg1, arg2);
2014 } else {
2015 TCGv_i64 t0 = tcg_temp_new_i64();
2016 tcg_gen_not_i64(t0, arg2);
2017 tcg_gen_or_i64(ret, arg1, t0);
2018 tcg_temp_free_i64(t0);
2019 }
2020 #else
2021 tcg_gen_orc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
2022 tcg_gen_orc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
2023 #endif
2024 }
2025
2026 static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
2027 {
2028 if (TCG_TARGET_HAS_rot_i32) {
2029 tcg_gen_op3_i32(INDEX_op_rotl_i32, ret, arg1, arg2);
2030 } else {
2031 TCGv_i32 t0, t1;
2032
2033 t0 = tcg_temp_new_i32();
2034 t1 = tcg_temp_new_i32();
2035 tcg_gen_shl_i32(t0, arg1, arg2);
2036 tcg_gen_subfi_i32(t1, 32, arg2);
2037 tcg_gen_shr_i32(t1, arg1, t1);
2038 tcg_gen_or_i32(ret, t0, t1);
2039 tcg_temp_free_i32(t0);
2040 tcg_temp_free_i32(t1);
2041 }
2042 }
2043
2044 static inline void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
2045 {
2046 if (TCG_TARGET_HAS_rot_i64) {
2047 tcg_gen_op3_i64(INDEX_op_rotl_i64, ret, arg1, arg2);
2048 } else {
2049 TCGv_i64 t0, t1;
2050 t0 = tcg_temp_new_i64();
2051 t1 = tcg_temp_new_i64();
2052 tcg_gen_shl_i64(t0, arg1, arg2);
2053 tcg_gen_subfi_i64(t1, 64, arg2);
2054 tcg_gen_shr_i64(t1, arg1, t1);
2055 tcg_gen_or_i64(ret, t0, t1);
2056 tcg_temp_free_i64(t0);
2057 tcg_temp_free_i64(t1);
2058 }
2059 }
2060
2061 static inline void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
2062 {
2063 /* some cases can be optimized here */
2064 if (arg2 == 0) {
2065 tcg_gen_mov_i32(ret, arg1);
2066 } else if (TCG_TARGET_HAS_rot_i32) {
2067 TCGv_i32 t0 = tcg_const_i32(arg2);
2068 tcg_gen_rotl_i32(ret, arg1, t0);
2069 tcg_temp_free_i32(t0);
2070 } else {
2071 TCGv_i32 t0, t1;
2072 t0 = tcg_temp_new_i32();
2073 t1 = tcg_temp_new_i32();
2074 tcg_gen_shli_i32(t0, arg1, arg2);
2075 tcg_gen_shri_i32(t1, arg1, 32 - arg2);
2076 tcg_gen_or_i32(ret, t0, t1);
2077 tcg_temp_free_i32(t0);
2078 tcg_temp_free_i32(t1);
2079 }
2080 }
2081
2082 static inline void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
2083 {
2084 /* some cases can be optimized here */
2085 if (arg2 == 0) {
2086 tcg_gen_mov_i64(ret, arg1);
2087 } else if (TCG_TARGET_HAS_rot_i64) {
2088 TCGv_i64 t0 = tcg_const_i64(arg2);
2089 tcg_gen_rotl_i64(ret, arg1, t0);
2090 tcg_temp_free_i64(t0);
2091 } else {
2092 TCGv_i64 t0, t1;
2093 t0 = tcg_temp_new_i64();
2094 t1 = tcg_temp_new_i64();
2095 tcg_gen_shli_i64(t0, arg1, arg2);
2096 tcg_gen_shri_i64(t1, arg1, 64 - arg2);
2097 tcg_gen_or_i64(ret, t0, t1);
2098 tcg_temp_free_i64(t0);
2099 tcg_temp_free_i64(t1);
2100 }
2101 }
2102
2103 static inline void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
2104 {
2105 if (TCG_TARGET_HAS_rot_i32) {
2106 tcg_gen_op3_i32(INDEX_op_rotr_i32, ret, arg1, arg2);
2107 } else {
2108 TCGv_i32 t0, t1;
2109
2110 t0 = tcg_temp_new_i32();
2111 t1 = tcg_temp_new_i32();
2112 tcg_gen_shr_i32(t0, arg1, arg2);
2113 tcg_gen_subfi_i32(t1, 32, arg2);
2114 tcg_gen_shl_i32(t1, arg1, t1);
2115 tcg_gen_or_i32(ret, t0, t1);
2116 tcg_temp_free_i32(t0);
2117 tcg_temp_free_i32(t1);
2118 }
2119 }
2120
2121 static inline void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
2122 {
2123 if (TCG_TARGET_HAS_rot_i64) {
2124 tcg_gen_op3_i64(INDEX_op_rotr_i64, ret, arg1, arg2);
2125 } else {
2126 TCGv_i64 t0, t1;
2127 t0 = tcg_temp_new_i64();
2128 t1 = tcg_temp_new_i64();
2129 tcg_gen_shr_i64(t0, arg1, arg2);
2130 tcg_gen_subfi_i64(t1, 64, arg2);
2131 tcg_gen_shl_i64(t1, arg1, t1);
2132 tcg_gen_or_i64(ret, t0, t1);
2133 tcg_temp_free_i64(t0);
2134 tcg_temp_free_i64(t1);
2135 }
2136 }
2137
2138 static inline void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
2139 {
2140 /* some cases can be optimized here */
2141 if (arg2 == 0) {
2142 tcg_gen_mov_i32(ret, arg1);
2143 } else {
2144 tcg_gen_rotli_i32(ret, arg1, 32 - arg2);
2145 }
2146 }
2147
2148 static inline void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
2149 {
2150 /* some cases can be optimized here */
2151 if (arg2 == 0) {
2152 tcg_gen_mov_i64(ret, arg1);
2153 } else {
2154 tcg_gen_rotli_i64(ret, arg1, 64 - arg2);
2155 }
2156 }
2157
2158 static inline void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1,
2159 TCGv_i32 arg2, unsigned int ofs,
2160 unsigned int len)
2161 {
2162 uint32_t mask;
2163 TCGv_i32 t1;
2164
2165 tcg_debug_assert(ofs < 32);
2166 tcg_debug_assert(len <= 32);
2167 tcg_debug_assert(ofs + len <= 32);
2168
2169 if (ofs == 0 && len == 32) {
2170 tcg_gen_mov_i32(ret, arg2);
2171 return;
2172 }
2173 if (TCG_TARGET_HAS_deposit_i32 && TCG_TARGET_deposit_i32_valid(ofs, len)) {
2174 tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, arg1, arg2, ofs, len);
2175 return;
2176 }
2177
2178 mask = (1u << len) - 1;
2179 t1 = tcg_temp_new_i32();
2180
2181 if (ofs + len < 32) {
2182 tcg_gen_andi_i32(t1, arg2, mask);
2183 tcg_gen_shli_i32(t1, t1, ofs);
2184 } else {
2185 tcg_gen_shli_i32(t1, arg2, ofs);
2186 }
2187 tcg_gen_andi_i32(ret, arg1, ~(mask << ofs));
2188 tcg_gen_or_i32(ret, ret, t1);
2189
2190 tcg_temp_free_i32(t1);
2191 }
2192
2193 static inline void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1,
2194 TCGv_i64 arg2, unsigned int ofs,
2195 unsigned int len)
2196 {
2197 uint64_t mask;
2198 TCGv_i64 t1;
2199
2200 tcg_debug_assert(ofs < 64);
2201 tcg_debug_assert(len <= 64);
2202 tcg_debug_assert(ofs + len <= 64);
2203
2204 if (ofs == 0 && len == 64) {
2205 tcg_gen_mov_i64(ret, arg2);
2206 return;
2207 }
2208 if (TCG_TARGET_HAS_deposit_i64 && TCG_TARGET_deposit_i64_valid(ofs, len)) {
2209 tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, arg1, arg2, ofs, len);
2210 return;
2211 }
2212
2213 #if TCG_TARGET_REG_BITS == 32
2214 if (ofs >= 32) {
2215 tcg_gen_deposit_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1),
2216 TCGV_LOW(arg2), ofs - 32, len);
2217 tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg1));
2218 return;
2219 }
2220 if (ofs + len <= 32) {
2221 tcg_gen_deposit_i32(TCGV_LOW(ret), TCGV_LOW(arg1),
2222 TCGV_LOW(arg2), ofs, len);
2223 tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1));
2224 return;
2225 }
2226 #endif
2227
2228 mask = (1ull << len) - 1;
2229 t1 = tcg_temp_new_i64();
2230
2231 if (ofs + len < 64) {
2232 tcg_gen_andi_i64(t1, arg2, mask);
2233 tcg_gen_shli_i64(t1, t1, ofs);
2234 } else {
2235 tcg_gen_shli_i64(t1, arg2, ofs);
2236 }
2237 tcg_gen_andi_i64(ret, arg1, ~(mask << ofs));
2238 tcg_gen_or_i64(ret, ret, t1);
2239
2240 tcg_temp_free_i64(t1);
2241 }
2242
2243 static inline void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low,
2244 TCGv_i32 high)
2245 {
2246 #if TCG_TARGET_REG_BITS == 32
2247 tcg_gen_mov_i32(TCGV_LOW(dest), low);
2248 tcg_gen_mov_i32(TCGV_HIGH(dest), high);
2249 #else
2250 TCGv_i64 tmp = tcg_temp_new_i64();
2251 /* These extensions are only needed for type correctness.
2252 We may be able to do better given target specific information. */
2253 tcg_gen_extu_i32_i64(tmp, high);
2254 tcg_gen_extu_i32_i64(dest, low);
2255 /* If deposit is available, use it. Otherwise use the extra
2256 knowledge that we have of the zero-extensions above. */
2257 if (TCG_TARGET_HAS_deposit_i64 && TCG_TARGET_deposit_i64_valid(32, 32)) {
2258 tcg_gen_deposit_i64(dest, dest, tmp, 32, 32);
2259 } else {
2260 tcg_gen_shli_i64(tmp, tmp, 32);
2261 tcg_gen_or_i64(dest, dest, tmp);
2262 }
2263 tcg_temp_free_i64(tmp);
2264 #endif
2265 }
2266
2267 static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low,
2268 TCGv_i64 high)
2269 {
2270 tcg_gen_deposit_i64(dest, low, high, 32, 32);
2271 }
2272
2273 static inline void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg)
2274 {
2275 #if TCG_TARGET_REG_BITS == 32
2276 tcg_gen_mov_i32(lo, TCGV_LOW(arg));
2277 tcg_gen_mov_i32(hi, TCGV_HIGH(arg));
2278 #else
2279 TCGv_i64 t0 = tcg_temp_new_i64();
2280 tcg_gen_trunc_i64_i32(lo, arg);
2281 tcg_gen_shri_i64(t0, arg, 32);
2282 tcg_gen_trunc_i64_i32(hi, t0);
2283 tcg_temp_free_i64(t0);
2284 #endif
2285 }
2286
2287 static inline void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg)
2288 {
2289 tcg_gen_ext32u_i64(lo, arg);
2290 tcg_gen_shri_i64(hi, arg, 32);
2291 }
2292
2293 static inline void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret,
2294 TCGv_i32 c1, TCGv_i32 c2,
2295 TCGv_i32 v1, TCGv_i32 v2)
2296 {
2297 if (TCG_TARGET_HAS_movcond_i32) {
2298 tcg_gen_op6i_i32(INDEX_op_movcond_i32, ret, c1, c2, v1, v2, cond);
2299 } else {
2300 TCGv_i32 t0 = tcg_temp_new_i32();
2301 TCGv_i32 t1 = tcg_temp_new_i32();
2302 tcg_gen_setcond_i32(cond, t0, c1, c2);
2303 tcg_gen_neg_i32(t0, t0);
2304 tcg_gen_and_i32(t1, v1, t0);
2305 tcg_gen_andc_i32(ret, v2, t0);
2306 tcg_gen_or_i32(ret, ret, t1);
2307 tcg_temp_free_i32(t0);
2308 tcg_temp_free_i32(t1);
2309 }
2310 }
2311
2312 static inline void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret,
2313 TCGv_i64 c1, TCGv_i64 c2,
2314 TCGv_i64 v1, TCGv_i64 v2)
2315 {
2316 #if TCG_TARGET_REG_BITS == 32
2317 TCGv_i32 t0 = tcg_temp_new_i32();
2318 TCGv_i32 t1 = tcg_temp_new_i32();
2319 tcg_gen_op6i_i32(INDEX_op_setcond2_i32, t0,
2320 TCGV_LOW(c1), TCGV_HIGH(c1),
2321 TCGV_LOW(c2), TCGV_HIGH(c2), cond);
2322
2323 if (TCG_TARGET_HAS_movcond_i32) {
2324 tcg_gen_movi_i32(t1, 0);
2325 tcg_gen_movcond_i32(TCG_COND_NE, TCGV_LOW(ret), t0, t1,
2326 TCGV_LOW(v1), TCGV_LOW(v2));
2327 tcg_gen_movcond_i32(TCG_COND_NE, TCGV_HIGH(ret), t0, t1,
2328 TCGV_HIGH(v1), TCGV_HIGH(v2));
2329 } else {
2330 tcg_gen_neg_i32(t0, t0);
2331
2332 tcg_gen_and_i32(t1, TCGV_LOW(v1), t0);
2333 tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(v2), t0);
2334 tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(ret), t1);
2335
2336 tcg_gen_and_i32(t1, TCGV_HIGH(v1), t0);
2337 tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(v2), t0);
2338 tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), t1);
2339 }
2340 tcg_temp_free_i32(t0);
2341 tcg_temp_free_i32(t1);
2342 #else
2343 if (TCG_TARGET_HAS_movcond_i64) {
2344 tcg_gen_op6i_i64(INDEX_op_movcond_i64, ret, c1, c2, v1, v2, cond);
2345 } else {
2346 TCGv_i64 t0 = tcg_temp_new_i64();
2347 TCGv_i64 t1 = tcg_temp_new_i64();
2348 tcg_gen_setcond_i64(cond, t0, c1, c2);
2349 tcg_gen_neg_i64(t0, t0);
2350 tcg_gen_and_i64(t1, v1, t0);
2351 tcg_gen_andc_i64(ret, v2, t0);
2352 tcg_gen_or_i64(ret, ret, t1);
2353 tcg_temp_free_i64(t0);
2354 tcg_temp_free_i64(t1);
2355 }
2356 #endif
2357 }
2358
2359 static inline void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
2360 TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh)
2361 {
2362 if (TCG_TARGET_HAS_add2_i32) {
2363 tcg_gen_op6_i32(INDEX_op_add2_i32, rl, rh, al, ah, bl, bh);
2364 /* Allow the optimizer room to replace add2 with two moves. */
2365 tcg_gen_op0(INDEX_op_nop);
2366 } else {
2367 TCGv_i64 t0 = tcg_temp_new_i64();
2368 TCGv_i64 t1 = tcg_temp_new_i64();
2369 tcg_gen_concat_i32_i64(t0, al, ah);
2370 tcg_gen_concat_i32_i64(t1, bl, bh);
2371 tcg_gen_add_i64(t0, t0, t1);
2372 tcg_gen_extr_i64_i32(rl, rh, t0);
2373 tcg_temp_free_i64(t0);
2374 tcg_temp_free_i64(t1);
2375 }
2376 }
2377
2378 static inline void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
2379 TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh)
2380 {
2381 if (TCG_TARGET_HAS_sub2_i32) {
2382 tcg_gen_op6_i32(INDEX_op_sub2_i32, rl, rh, al, ah, bl, bh);
2383 /* Allow the optimizer room to replace sub2 with two moves. */
2384 tcg_gen_op0(INDEX_op_nop);
2385 } else {
2386 TCGv_i64 t0 = tcg_temp_new_i64();
2387 TCGv_i64 t1 = tcg_temp_new_i64();
2388 tcg_gen_concat_i32_i64(t0, al, ah);
2389 tcg_gen_concat_i32_i64(t1, bl, bh);
2390 tcg_gen_sub_i64(t0, t0, t1);
2391 tcg_gen_extr_i64_i32(rl, rh, t0);
2392 tcg_temp_free_i64(t0);
2393 tcg_temp_free_i64(t1);
2394 }
2395 }
2396
2397 static inline void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh,
2398 TCGv_i32 arg1, TCGv_i32 arg2)
2399 {
2400 if (TCG_TARGET_HAS_mulu2_i32) {
2401 tcg_gen_op4_i32(INDEX_op_mulu2_i32, rl, rh, arg1, arg2);
2402 /* Allow the optimizer room to replace mulu2 with two moves. */
2403 tcg_gen_op0(INDEX_op_nop);
2404 } else {
2405 TCGv_i64 t0 = tcg_temp_new_i64();
2406 TCGv_i64 t1 = tcg_temp_new_i64();
2407 tcg_gen_extu_i32_i64(t0, arg1);
2408 tcg_gen_extu_i32_i64(t1, arg2);
2409 tcg_gen_mul_i64(t0, t0, t1);
2410 tcg_gen_extr_i64_i32(rl, rh, t0);
2411 tcg_temp_free_i64(t0);
2412 tcg_temp_free_i64(t1);
2413 }
2414 }
2415
2416 static inline void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh,
2417 TCGv_i32 arg1, TCGv_i32 arg2)
2418 {
2419 if (TCG_TARGET_HAS_muls2_i32) {
2420 tcg_gen_op4_i32(INDEX_op_muls2_i32, rl, rh, arg1, arg2);
2421 /* Allow the optimizer room to replace muls2 with two moves. */
2422 tcg_gen_op0(INDEX_op_nop);
2423 } else if (TCG_TARGET_REG_BITS == 32 && TCG_TARGET_HAS_mulu2_i32) {
2424 TCGv_i32 t0 = tcg_temp_new_i32();
2425 TCGv_i32 t1 = tcg_temp_new_i32();
2426 TCGv_i32 t2 = tcg_temp_new_i32();
2427 TCGv_i32 t3 = tcg_temp_new_i32();
2428 tcg_gen_op4_i32(INDEX_op_mulu2_i32, t0, t1, arg1, arg2);
2429 /* Allow the optimizer room to replace mulu2 with two moves. */
2430 tcg_gen_op0(INDEX_op_nop);
2431 /* Adjust for negative inputs. */
2432 tcg_gen_sari_i32(t2, arg1, 31);
2433 tcg_gen_sari_i32(t3, arg2, 31);
2434 tcg_gen_and_i32(t2, t2, arg2);
2435 tcg_gen_and_i32(t3, t3, arg1);
2436 tcg_gen_sub_i32(rh, t1, t2);
2437 tcg_gen_sub_i32(rh, rh, t3);
2438 tcg_gen_mov_i32(rl, t0);
2439 tcg_temp_free_i32(t0);
2440 tcg_temp_free_i32(t1);
2441 tcg_temp_free_i32(t2);
2442 tcg_temp_free_i32(t3);
2443 } else {
2444 TCGv_i64 t0 = tcg_temp_new_i64();
2445 TCGv_i64 t1 = tcg_temp_new_i64();
2446 tcg_gen_ext_i32_i64(t0, arg1);
2447 tcg_gen_ext_i32_i64(t1, arg2);
2448 tcg_gen_mul_i64(t0, t0, t1);
2449 tcg_gen_extr_i64_i32(rl, rh, t0);
2450 tcg_temp_free_i64(t0);
2451 tcg_temp_free_i64(t1);
2452 }
2453 }
2454
2455 static inline void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
2456 TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh)
2457 {
2458 if (TCG_TARGET_HAS_add2_i64) {
2459 tcg_gen_op6_i64(INDEX_op_add2_i64, rl, rh, al, ah, bl, bh);
2460 /* Allow the optimizer room to replace add2 with two moves. */
2461 tcg_gen_op0(INDEX_op_nop);
2462 } else {
2463 TCGv_i64 t0 = tcg_temp_new_i64();
2464 TCGv_i64 t1 = tcg_temp_new_i64();
2465 tcg_gen_add_i64(t0, al, bl);
2466 tcg_gen_setcond_i64(TCG_COND_LTU, t1, t0, al);
2467 tcg_gen_add_i64(rh, ah, bh);
2468 tcg_gen_add_i64(rh, rh, t1);
2469 tcg_gen_mov_i64(rl, t0);
2470 tcg_temp_free_i64(t0);
2471 tcg_temp_free_i64(t1);
2472 }
2473 }
2474
2475 static inline void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
2476 TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh)
2477 {
2478 if (TCG_TARGET_HAS_sub2_i64) {
2479 tcg_gen_op6_i64(INDEX_op_sub2_i64, rl, rh, al, ah, bl, bh);
2480 /* Allow the optimizer room to replace sub2 with two moves. */
2481 tcg_gen_op0(INDEX_op_nop);
2482 } else {
2483 TCGv_i64 t0 = tcg_temp_new_i64();
2484 TCGv_i64 t1 = tcg_temp_new_i64();
2485 tcg_gen_sub_i64(t0, al, bl);
2486 tcg_gen_setcond_i64(TCG_COND_LTU, t1, al, bl);
2487 tcg_gen_sub_i64(rh, ah, bh);
2488 tcg_gen_sub_i64(rh, rh, t1);
2489 tcg_gen_mov_i64(rl, t0);
2490 tcg_temp_free_i64(t0);
2491 tcg_temp_free_i64(t1);
2492 }
2493 }
2494
2495 static inline void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh,
2496 TCGv_i64 arg1, TCGv_i64 arg2)
2497 {
2498 if (TCG_TARGET_HAS_mulu2_i64) {
2499 tcg_gen_op4_i64(INDEX_op_mulu2_i64, rl, rh, arg1, arg2);
2500 /* Allow the optimizer room to replace mulu2 with two moves. */
2501 tcg_gen_op0(INDEX_op_nop);
2502 } else if (TCG_TARGET_HAS_mulu2_i64) {
2503 TCGv_i64 t0 = tcg_temp_new_i64();
2504 TCGv_i64 t1 = tcg_temp_new_i64();
2505 TCGv_i64 t2 = tcg_temp_new_i64();
2506 TCGv_i64 t3 = tcg_temp_new_i64();
2507 tcg_gen_op4_i64(INDEX_op_mulu2_i64, t0, t1, arg1, arg2);
2508 /* Allow the optimizer room to replace mulu2 with two moves. */
2509 tcg_gen_op0(INDEX_op_nop);
2510 /* Adjust for negative inputs. */
2511 tcg_gen_sari_i64(t2, arg1, 63);
2512 tcg_gen_sari_i64(t3, arg2, 63);
2513 tcg_gen_and_i64(t2, t2, arg2);
2514 tcg_gen_and_i64(t3, t3, arg1);
2515 tcg_gen_sub_i64(rh, t1, t2);
2516 tcg_gen_sub_i64(rh, rh, t3);
2517 tcg_gen_mov_i64(rl, t0);
2518 tcg_temp_free_i64(t0);
2519 tcg_temp_free_i64(t1);
2520 tcg_temp_free_i64(t2);
2521 tcg_temp_free_i64(t3);
2522 } else {
2523 TCGv_i64 t0 = tcg_temp_new_i64();
2524 int sizemask = 0;
2525 /* Return value and both arguments are 64-bit and unsigned. */
2526 sizemask |= tcg_gen_sizemask(0, 1, 0);
2527 sizemask |= tcg_gen_sizemask(1, 1, 0);
2528 sizemask |= tcg_gen_sizemask(2, 1, 0);
2529 tcg_gen_mul_i64(t0, arg1, arg2);
2530 tcg_gen_helper64(tcg_helper_muluh_i64, sizemask, rh, arg1, arg2);
2531 tcg_gen_mov_i64(rl, t0);
2532 tcg_temp_free_i64(t0);
2533 }
2534 }
2535
2536 static inline void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh,
2537 TCGv_i64 arg1, TCGv_i64 arg2)
2538 {
2539 if (TCG_TARGET_HAS_muls2_i64) {
2540 tcg_gen_op4_i64(INDEX_op_muls2_i64, rl, rh, arg1, arg2);
2541 /* Allow the optimizer room to replace muls2 with two moves. */
2542 tcg_gen_op0(INDEX_op_nop);
2543 } else {
2544 TCGv_i64 t0 = tcg_temp_new_i64();
2545 int sizemask = 0;
2546 /* Return value and both arguments are 64-bit and signed. */
2547 sizemask |= tcg_gen_sizemask(0, 1, 1);
2548 sizemask |= tcg_gen_sizemask(1, 1, 1);
2549 sizemask |= tcg_gen_sizemask(2, 1, 1);
2550 tcg_gen_mul_i64(t0, arg1, arg2);
2551 tcg_gen_helper64(tcg_helper_mulsh_i64, sizemask, rh, arg1, arg2);
2552 tcg_gen_mov_i64(rl, t0);
2553 tcg_temp_free_i64(t0);
2554 }
2555 }
2556
2557 /***************************************/
2558 /* QEMU specific operations. Their type depend on the QEMU CPU
2559 type. */
2560 #ifndef TARGET_LONG_BITS
2561 #error must include QEMU headers
2562 #endif
2563
2564 #if TARGET_LONG_BITS == 32
2565 #define TCGv TCGv_i32
2566 #define tcg_temp_new() tcg_temp_new_i32()
2567 #define tcg_global_reg_new tcg_global_reg_new_i32
2568 #define tcg_global_mem_new tcg_global_mem_new_i32
2569 #define tcg_temp_local_new() tcg_temp_local_new_i32()
2570 #define tcg_temp_free tcg_temp_free_i32
2571 #define tcg_gen_qemu_ldst_op tcg_gen_op3i_i32
2572 #define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i32
2573 #define TCGV_UNUSED(x) TCGV_UNUSED_I32(x)
2574 #define TCGV_IS_UNUSED(x) TCGV_IS_UNUSED_I32(x)
2575 #define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b)
2576 #else
2577 #define TCGv TCGv_i64
2578 #define tcg_temp_new() tcg_temp_new_i64()
2579 #define tcg_global_reg_new tcg_global_reg_new_i64
2580 #define tcg_global_mem_new tcg_global_mem_new_i64
2581 #define tcg_temp_local_new() tcg_temp_local_new_i64()
2582 #define tcg_temp_free tcg_temp_free_i64
2583 #define tcg_gen_qemu_ldst_op tcg_gen_op3i_i64
2584 #define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i64
2585 #define TCGV_UNUSED(x) TCGV_UNUSED_I64(x)
2586 #define TCGV_IS_UNUSED(x) TCGV_IS_UNUSED_I64(x)
2587 #define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b)
2588 #endif
2589
2590 /* debug info: write the PC of the corresponding QEMU CPU instruction */
2591 static inline void tcg_gen_debug_insn_start(uint64_t pc)
2592 {
2593 /* XXX: must really use a 32 bit size for TCGArg in all cases */
2594 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
2595 tcg_gen_op2ii(INDEX_op_debug_insn_start,
2596 (uint32_t)(pc), (uint32_t)(pc >> 32));
2597 #else
2598 tcg_gen_op1i(INDEX_op_debug_insn_start, pc);
2599 #endif
2600 }
2601
2602 static inline void tcg_gen_exit_tb(tcg_target_long val)
2603 {
2604 tcg_gen_op1i(INDEX_op_exit_tb, val);
2605 }
2606
2607 static inline void tcg_gen_goto_tb(unsigned idx)
2608 {
2609 /* We only support two chained exits. */
2610 tcg_debug_assert(idx <= 1);
2611 #ifdef CONFIG_DEBUG_TCG
2612 /* Verify that we havn't seen this numbered exit before. */
2613 tcg_debug_assert((tcg_ctx.goto_tb_issue_mask & (1 << idx)) == 0);
2614 tcg_ctx.goto_tb_issue_mask |= 1 << idx;
2615 #endif
2616 tcg_gen_op1i(INDEX_op_goto_tb, idx);
2617 }
2618
2619 #if TCG_TARGET_REG_BITS == 32
2620 static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
2621 {
2622 #if TARGET_LONG_BITS == 32
2623 tcg_gen_op3i_i32(INDEX_op_qemu_ld8u, ret, addr, mem_index);
2624 #else
2625 tcg_gen_op4i_i32(INDEX_op_qemu_ld8u, TCGV_LOW(ret), TCGV_LOW(addr),
2626 TCGV_HIGH(addr), mem_index);
2627 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
2628 #endif
2629 }
2630
2631 static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
2632 {
2633 #if TARGET_LONG_BITS == 32
2634 tcg_gen_op3i_i32(INDEX_op_qemu_ld8s, ret, addr, mem_index);
2635 #else
2636 tcg_gen_op4i_i32(INDEX_op_qemu_ld8s, TCGV_LOW(ret), TCGV_LOW(addr),
2637 TCGV_HIGH(addr), mem_index);
2638 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
2639 #endif
2640 }
2641
2642 static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
2643 {
2644 #if TARGET_LONG_BITS == 32
2645 tcg_gen_op3i_i32(INDEX_op_qemu_ld16u, ret, addr, mem_index);
2646 #else
2647 tcg_gen_op4i_i32(INDEX_op_qemu_ld16u, TCGV_LOW(ret), TCGV_LOW(addr),
2648 TCGV_HIGH(addr), mem_index);
2649 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
2650 #endif
2651 }
2652
2653 static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
2654 {
2655 #if TARGET_LONG_BITS == 32
2656 tcg_gen_op3i_i32(INDEX_op_qemu_ld16s, ret, addr, mem_index);
2657 #else
2658 tcg_gen_op4i_i32(INDEX_op_qemu_ld16s, TCGV_LOW(ret), TCGV_LOW(addr),
2659 TCGV_HIGH(addr), mem_index);
2660 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
2661 #endif
2662 }
2663
2664 static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
2665 {
2666 #if TARGET_LONG_BITS == 32
2667 tcg_gen_op3i_i32(INDEX_op_qemu_ld32, ret, addr, mem_index);
2668 #else
2669 tcg_gen_op4i_i32(INDEX_op_qemu_ld32, TCGV_LOW(ret), TCGV_LOW(addr),
2670 TCGV_HIGH(addr), mem_index);
2671 tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
2672 #endif
2673 }
2674
2675 static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
2676 {
2677 #if TARGET_LONG_BITS == 32
2678 tcg_gen_op3i_i32(INDEX_op_qemu_ld32, ret, addr, mem_index);
2679 #else
2680 tcg_gen_op4i_i32(INDEX_op_qemu_ld32, TCGV_LOW(ret), TCGV_LOW(addr),
2681 TCGV_HIGH(addr), mem_index);
2682 tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
2683 #endif
2684 }
2685
2686 static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
2687 {
2688 #if TARGET_LONG_BITS == 32
2689 tcg_gen_op4i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), addr, mem_index);
2690 #else
2691 tcg_gen_op5i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret),
2692 TCGV_LOW(addr), TCGV_HIGH(addr), mem_index);
2693 #endif
2694 }
2695
2696 static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
2697 {
2698 #if TARGET_LONG_BITS == 32
2699 tcg_gen_op3i_i32(INDEX_op_qemu_st8, arg, addr, mem_index);
2700 #else
2701 tcg_gen_op4i_i32(INDEX_op_qemu_st8, TCGV_LOW(arg), TCGV_LOW(addr),
2702 TCGV_HIGH(addr), mem_index);
2703 #endif
2704 }
2705
2706 static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
2707 {
2708 #if TARGET_LONG_BITS == 32
2709 tcg_gen_op3i_i32(INDEX_op_qemu_st16, arg, addr, mem_index);
2710 #else
2711 tcg_gen_op4i_i32(INDEX_op_qemu_st16, TCGV_LOW(arg), TCGV_LOW(addr),
2712 TCGV_HIGH(addr), mem_index);
2713 #endif
2714 }
2715
2716 static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
2717 {
2718 #if TARGET_LONG_BITS == 32
2719 tcg_gen_op3i_i32(INDEX_op_qemu_st32, arg, addr, mem_index);
2720 #else
2721 tcg_gen_op4i_i32(INDEX_op_qemu_st32, TCGV_LOW(arg), TCGV_LOW(addr),
2722 TCGV_HIGH(addr), mem_index);
2723 #endif
2724 }
2725
2726 static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
2727 {
2728 #if TARGET_LONG_BITS == 32
2729 tcg_gen_op4i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), addr,
2730 mem_index);
2731 #else
2732 tcg_gen_op5i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg),
2733 TCGV_LOW(addr), TCGV_HIGH(addr), mem_index);
2734 #endif
2735 }
2736
2737 #define tcg_gen_ld_ptr(R, A, O) tcg_gen_ld_i32(TCGV_PTR_TO_NAT(R), (A), (O))
2738 #define tcg_gen_discard_ptr(A) tcg_gen_discard_i32(TCGV_PTR_TO_NAT(A))
2739
2740 #else /* TCG_TARGET_REG_BITS == 32 */
2741
2742 static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
2743 {
2744 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8u, ret, addr, mem_index);
2745 }
2746
2747 static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
2748 {
2749 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8s, ret, addr, mem_index);
2750 }
2751
2752 static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
2753 {
2754 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16u, ret, addr, mem_index);
2755 }
2756
2757 static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
2758 {
2759 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16s, ret, addr, mem_index);
2760 }
2761
2762 static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
2763 {
2764 #if TARGET_LONG_BITS == 32
2765 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32, ret, addr, mem_index);
2766 #else
2767 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32u, ret, addr, mem_index);
2768 #endif
2769 }
2770
2771 static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
2772 {
2773 #if TARGET_LONG_BITS == 32
2774 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32, ret, addr, mem_index);
2775 #else
2776 tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32s, ret, addr, mem_index);
2777 #endif
2778 }
2779
2780 static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
2781 {
2782 tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_ld64, ret, addr, mem_index);
2783 }
2784
2785 static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
2786 {
2787 tcg_gen_qemu_ldst_op(INDEX_op_qemu_st8, arg, addr, mem_index);
2788 }
2789
2790 static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
2791 {
2792 tcg_gen_qemu_ldst_op(INDEX_op_qemu_st16, arg, addr, mem_index);
2793 }
2794
2795 static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
2796 {
2797 tcg_gen_qemu_ldst_op(INDEX_op_qemu_st32, arg, addr, mem_index);
2798 }
2799
2800 static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
2801 {
2802 tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_st64, arg, addr, mem_index);
2803 }
2804
2805 #define tcg_gen_ld_ptr(R, A, O) tcg_gen_ld_i64(TCGV_PTR_TO_NAT(R), (A), (O))
2806 #define tcg_gen_discard_ptr(A) tcg_gen_discard_i64(TCGV_PTR_TO_NAT(A))
2807
2808 #endif /* TCG_TARGET_REG_BITS != 32 */
2809
2810 #if TARGET_LONG_BITS == 64
2811 #define tcg_gen_movi_tl tcg_gen_movi_i64
2812 #define tcg_gen_mov_tl tcg_gen_mov_i64
2813 #define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
2814 #define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
2815 #define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
2816 #define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
2817 #define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
2818 #define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
2819 #define tcg_gen_ld_tl tcg_gen_ld_i64
2820 #define tcg_gen_st8_tl tcg_gen_st8_i64
2821 #define tcg_gen_st16_tl tcg_gen_st16_i64
2822 #define tcg_gen_st32_tl tcg_gen_st32_i64
2823 #define tcg_gen_st_tl tcg_gen_st_i64
2824 #define tcg_gen_add_tl tcg_gen_add_i64
2825 #define tcg_gen_addi_tl tcg_gen_addi_i64
2826 #define tcg_gen_sub_tl tcg_gen_sub_i64
2827 #define tcg_gen_neg_tl tcg_gen_neg_i64
2828 #define tcg_gen_subfi_tl tcg_gen_subfi_i64
2829 #define tcg_gen_subi_tl tcg_gen_subi_i64
2830 #define tcg_gen_and_tl tcg_gen_and_i64
2831 #define tcg_gen_andi_tl tcg_gen_andi_i64
2832 #define tcg_gen_or_tl tcg_gen_or_i64
2833 #define tcg_gen_ori_tl tcg_gen_ori_i64
2834 #define tcg_gen_xor_tl tcg_gen_xor_i64
2835 #define tcg_gen_xori_tl tcg_gen_xori_i64
2836 #define tcg_gen_not_tl tcg_gen_not_i64
2837 #define tcg_gen_shl_tl tcg_gen_shl_i64
2838 #define tcg_gen_shli_tl tcg_gen_shli_i64
2839 #define tcg_gen_shr_tl tcg_gen_shr_i64
2840 #define tcg_gen_shri_tl tcg_gen_shri_i64
2841 #define tcg_gen_sar_tl tcg_gen_sar_i64
2842 #define tcg_gen_sari_tl tcg_gen_sari_i64
2843 #define tcg_gen_brcond_tl tcg_gen_brcond_i64
2844 #define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
2845 #define tcg_gen_setcond_tl tcg_gen_setcond_i64
2846 #define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
2847 #define tcg_gen_mul_tl tcg_gen_mul_i64
2848 #define tcg_gen_muli_tl tcg_gen_muli_i64
2849 #define tcg_gen_div_tl tcg_gen_div_i64
2850 #define tcg_gen_rem_tl tcg_gen_rem_i64
2851 #define tcg_gen_divu_tl tcg_gen_divu_i64
2852 #define tcg_gen_remu_tl tcg_gen_remu_i64
2853 #define tcg_gen_discard_tl tcg_gen_discard_i64
2854 #define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32
2855 #define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
2856 #define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
2857 #define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
2858 #define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
2859 #define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
2860 #define tcg_gen_ext8u_tl tcg_gen_ext8u_i64
2861 #define tcg_gen_ext8s_tl tcg_gen_ext8s_i64
2862 #define tcg_gen_ext16u_tl tcg_gen_ext16u_i64
2863 #define tcg_gen_ext16s_tl tcg_gen_ext16s_i64
2864 #define tcg_gen_ext32u_tl tcg_gen_ext32u_i64
2865 #define tcg_gen_ext32s_tl tcg_gen_ext32s_i64
2866 #define tcg_gen_bswap16_tl tcg_gen_bswap16_i64
2867 #define tcg_gen_bswap32_tl tcg_gen_bswap32_i64
2868 #define tcg_gen_bswap64_tl tcg_gen_bswap64_i64
2869 #define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
2870 #define tcg_gen_extr_i64_tl tcg_gen_extr32_i64
2871 #define tcg_gen_andc_tl tcg_gen_andc_i64
2872 #define tcg_gen_eqv_tl tcg_gen_eqv_i64
2873 #define tcg_gen_nand_tl tcg_gen_nand_i64
2874 #define tcg_gen_nor_tl tcg_gen_nor_i64
2875 #define tcg_gen_orc_tl tcg_gen_orc_i64
2876 #define tcg_gen_rotl_tl tcg_gen_rotl_i64
2877 #define tcg_gen_rotli_tl tcg_gen_rotli_i64
2878 #define tcg_gen_rotr_tl tcg_gen_rotr_i64
2879 #define tcg_gen_rotri_tl tcg_gen_rotri_i64
2880 #define tcg_gen_deposit_tl tcg_gen_deposit_i64
2881 #define tcg_const_tl tcg_const_i64
2882 #define tcg_const_local_tl tcg_const_local_i64
2883 #define tcg_gen_movcond_tl tcg_gen_movcond_i64
2884 #define tcg_gen_add2_tl tcg_gen_add2_i64
2885 #define tcg_gen_sub2_tl tcg_gen_sub2_i64
2886 #define tcg_gen_mulu2_tl tcg_gen_mulu2_i64
2887 #define tcg_gen_muls2_tl tcg_gen_muls2_i64
2888 #else
2889 #define tcg_gen_movi_tl tcg_gen_movi_i32
2890 #define tcg_gen_mov_tl tcg_gen_mov_i32
2891 #define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
2892 #define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
2893 #define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
2894 #define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
2895 #define tcg_gen_ld32u_tl tcg_gen_ld_i32
2896 #define tcg_gen_ld32s_tl tcg_gen_ld_i32
2897 #define tcg_gen_ld_tl tcg_gen_ld_i32
2898 #define tcg_gen_st8_tl tcg_gen_st8_i32
2899 #define tcg_gen_st16_tl tcg_gen_st16_i32
2900 #define tcg_gen_st32_tl tcg_gen_st_i32
2901 #define tcg_gen_st_tl tcg_gen_st_i32
2902 #define tcg_gen_add_tl tcg_gen_add_i32
2903 #define tcg_gen_addi_tl tcg_gen_addi_i32
2904 #define tcg_gen_sub_tl tcg_gen_sub_i32
2905 #define tcg_gen_neg_tl tcg_gen_neg_i32
2906 #define tcg_gen_subfi_tl tcg_gen_subfi_i32
2907 #define tcg_gen_subi_tl tcg_gen_subi_i32
2908 #define tcg_gen_and_tl tcg_gen_and_i32
2909 #define tcg_gen_andi_tl tcg_gen_andi_i32
2910 #define tcg_gen_or_tl tcg_gen_or_i32
2911 #define tcg_gen_ori_tl tcg_gen_ori_i32
2912 #define tcg_gen_xor_tl tcg_gen_xor_i32
2913 #define tcg_gen_xori_tl tcg_gen_xori_i32
2914 #define tcg_gen_not_tl tcg_gen_not_i32
2915 #define tcg_gen_shl_tl tcg_gen_shl_i32
2916 #define tcg_gen_shli_tl tcg_gen_shli_i32
2917 #define tcg_gen_shr_tl tcg_gen_shr_i32
2918 #define tcg_gen_shri_tl tcg_gen_shri_i32
2919 #define tcg_gen_sar_tl tcg_gen_sar_i32
2920 #define tcg_gen_sari_tl tcg_gen_sari_i32
2921 #define tcg_gen_brcond_tl tcg_gen_brcond_i32
2922 #define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
2923 #define tcg_gen_setcond_tl tcg_gen_setcond_i32
2924 #define tcg_gen_setcondi_tl tcg_gen_setcondi_i32
2925 #define tcg_gen_mul_tl tcg_gen_mul_i32
2926 #define tcg_gen_muli_tl tcg_gen_muli_i32
2927 #define tcg_gen_div_tl tcg_gen_div_i32
2928 #define tcg_gen_rem_tl tcg_gen_rem_i32
2929 #define tcg_gen_divu_tl tcg_gen_divu_i32
2930 #define tcg_gen_remu_tl tcg_gen_remu_i32
2931 #define tcg_gen_discard_tl tcg_gen_discard_i32
2932 #define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
2933 #define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32
2934 #define tcg_gen_extu_i32_tl tcg_gen_mov_i32
2935 #define tcg_gen_ext_i32_tl tcg_gen_mov_i32
2936 #define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
2937 #define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
2938 #define tcg_gen_ext8u_tl tcg_gen_ext8u_i32
2939 #define tcg_gen_ext8s_tl tcg_gen_ext8s_i32
2940 #define tcg_gen_ext16u_tl tcg_gen_ext16u_i32
2941 #define tcg_gen_ext16s_tl tcg_gen_ext16s_i32
2942 #define tcg_gen_ext32u_tl tcg_gen_mov_i32
2943 #define tcg_gen_ext32s_tl tcg_gen_mov_i32
2944 #define tcg_gen_bswap16_tl tcg_gen_bswap16_i32
2945 #define tcg_gen_bswap32_tl tcg_gen_bswap32_i32
2946 #define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
2947 #define tcg_gen_extr_tl_i64 tcg_gen_extr_i32_i64
2948 #define tcg_gen_andc_tl tcg_gen_andc_i32
2949 #define tcg_gen_eqv_tl tcg_gen_eqv_i32
2950 #define tcg_gen_nand_tl tcg_gen_nand_i32
2951 #define tcg_gen_nor_tl tcg_gen_nor_i32
2952 #define tcg_gen_orc_tl tcg_gen_orc_i32
2953 #define tcg_gen_rotl_tl tcg_gen_rotl_i32
2954 #define tcg_gen_rotli_tl tcg_gen_rotli_i32
2955 #define tcg_gen_rotr_tl tcg_gen_rotr_i32
2956 #define tcg_gen_rotri_tl tcg_gen_rotri_i32
2957 #define tcg_gen_deposit_tl tcg_gen_deposit_i32
2958 #define tcg_const_tl tcg_const_i32
2959 #define tcg_const_local_tl tcg_const_local_i32
2960 #define tcg_gen_movcond_tl tcg_gen_movcond_i32
2961 #define tcg_gen_add2_tl tcg_gen_add2_i32
2962 #define tcg_gen_sub2_tl tcg_gen_sub2_i32
2963 #define tcg_gen_mulu2_tl tcg_gen_mulu2_i32
2964 #define tcg_gen_muls2_tl tcg_gen_muls2_i32
2965 #endif
2966
2967 #if TCG_TARGET_REG_BITS == 32
2968 #define tcg_gen_add_ptr(R, A, B) tcg_gen_add_i32(TCGV_PTR_TO_NAT(R), \
2969 TCGV_PTR_TO_NAT(A), \
2970 TCGV_PTR_TO_NAT(B))
2971 #define tcg_gen_addi_ptr(R, A, B) tcg_gen_addi_i32(TCGV_PTR_TO_NAT(R), \
2972 TCGV_PTR_TO_NAT(A), (B))
2973 #define tcg_gen_ext_i32_ptr(R, A) tcg_gen_mov_i32(TCGV_PTR_TO_NAT(R), (A))
2974 #else /* TCG_TARGET_REG_BITS == 32 */
2975 #define tcg_gen_add_ptr(R, A, B) tcg_gen_add_i64(TCGV_PTR_TO_NAT(R), \
2976 TCGV_PTR_TO_NAT(A), \
2977 TCGV_PTR_TO_NAT(B))
2978 #define tcg_gen_addi_ptr(R, A, B) tcg_gen_addi_i64(TCGV_PTR_TO_NAT(R), \
2979 TCGV_PTR_TO_NAT(A), (B))
2980 #define tcg_gen_ext_i32_ptr(R, A) tcg_gen_ext_i32_i64(TCGV_PTR_TO_NAT(R), (A))
2981 #endif /* TCG_TARGET_REG_BITS != 32 */
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