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numa: consolidate cpu_preplug fixups/checks for pc/arm/spapr
[qemu/kevin.git] / hw / ppc / spapr.c
blob94563cd8f531deaa0ec1fb30142da7cd153991be
1 /*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
27 #include "qemu/osdep.h"
28 #include "qapi/error.h"
29 #include "sysemu/sysemu.h"
30 #include "sysemu/numa.h"
31 #include "hw/hw.h"
32 #include "qemu/log.h"
33 #include "hw/fw-path-provider.h"
34 #include "elf.h"
35 #include "net/net.h"
36 #include "sysemu/device_tree.h"
37 #include "sysemu/block-backend.h"
38 #include "sysemu/cpus.h"
39 #include "sysemu/hw_accel.h"
40 #include "kvm_ppc.h"
41 #include "migration/migration.h"
42 #include "mmu-hash64.h"
43 #include "mmu-book3s-v3.h"
44 #include "qom/cpu.h"
45
46 #include "hw/boards.h"
47 #include "hw/ppc/ppc.h"
48 #include "hw/loader.h"
49
50 #include "hw/ppc/fdt.h"
51 #include "hw/ppc/spapr.h"
52 #include "hw/ppc/spapr_vio.h"
53 #include "hw/pci-host/spapr.h"
54 #include "hw/ppc/xics.h"
55 #include "hw/pci/msi.h"
56
57 #include "hw/pci/pci.h"
58 #include "hw/scsi/scsi.h"
59 #include "hw/virtio/virtio-scsi.h"
60
61 #include "exec/address-spaces.h"
62 #include "hw/usb.h"
63 #include "qemu/config-file.h"
64 #include "qemu/error-report.h"
65 #include "trace.h"
66 #include "hw/nmi.h"
67 #include "hw/intc/intc.h"
68
69 #include "hw/compat.h"
70 #include "qemu/cutils.h"
71 #include "hw/ppc/spapr_cpu_core.h"
72 #include "qmp-commands.h"
73
74 #include <libfdt.h>
75
76 /* SLOF memory layout:
77 *
78 * SLOF raw image loaded at 0, copies its romfs right below the flat
79 * device-tree, then position SLOF itself 31M below that
80 *
81 * So we set FW_OVERHEAD to 40MB which should account for all of that
82 * and more
83 *
84 * We load our kernel at 4M, leaving space for SLOF initial image
85 */
86 #define FDT_MAX_SIZE 0x100000
87 #define RTAS_MAX_SIZE 0x10000
88 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
89 #define FW_MAX_SIZE 0x400000
90 #define FW_FILE_NAME "slof.bin"
91 #define FW_OVERHEAD 0x2800000
92 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
93
94 #define MIN_RMA_SLOF 128UL
95
96 #define PHANDLE_XICP 0x00001111
97
98 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
99
100 static ICSState *spapr_ics_create(sPAPRMachineState *spapr,
101 const char *type_ics,
102 int nr_irqs, Error **errp)
103 {
104 Error *local_err = NULL;
105 Object *obj;
106
107 obj = object_new(type_ics);
108 object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort);
109 object_property_add_const_link(obj, "xics", OBJECT(spapr), &error_abort);
110 object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err);
111 if (local_err) {
112 goto error;
113 }
114 object_property_set_bool(obj, true, "realized", &local_err);
115 if (local_err) {
116 goto error;
117 }
118
119 return ICS_SIMPLE(obj);
120
121 error:
122 error_propagate(errp, local_err);
123 return NULL;
124 }
125
126 static void xics_system_init(MachineState *machine, int nr_irqs, Error **errp)
127 {
128 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
129
130 if (kvm_enabled()) {
131 if (machine_kernel_irqchip_allowed(machine) &&
132 !xics_kvm_init(spapr, errp)) {
133 spapr->icp_type = TYPE_KVM_ICP;
134 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs, errp);
135 }
136 if (machine_kernel_irqchip_required(machine) && !spapr->ics) {
137 error_prepend(errp, "kernel_irqchip requested but unavailable: ");
138 return;
139 }
140 }
141
142 if (!spapr->ics) {
143 xics_spapr_init(spapr);
144 spapr->icp_type = TYPE_ICP;
145 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs, errp);
146 if (!spapr->ics) {
147 return;
148 }
149 }
150 }
151
152 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
153 int smt_threads)
154 {
155 int i, ret = 0;
156 uint32_t servers_prop[smt_threads];
157 uint32_t gservers_prop[smt_threads * 2];
158 int index = ppc_get_vcpu_dt_id(cpu);
159
160 if (cpu->compat_pvr) {
161 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr);
162 if (ret < 0) {
163 return ret;
164 }
165 }
166
167 /* Build interrupt servers and gservers properties */
168 for (i = 0; i < smt_threads; i++) {
169 servers_prop[i] = cpu_to_be32(index + i);
170 /* Hack, direct the group queues back to cpu 0 */
171 gservers_prop[i*2] = cpu_to_be32(index + i);
172 gservers_prop[i*2 + 1] = 0;
173 }
174 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
175 servers_prop, sizeof(servers_prop));
176 if (ret < 0) {
177 return ret;
178 }
179 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
180 gservers_prop, sizeof(gservers_prop));
181
182 return ret;
183 }
184
185 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs)
186 {
187 int ret = 0;
188 PowerPCCPU *cpu = POWERPC_CPU(cs);
189 int index = ppc_get_vcpu_dt_id(cpu);
190 uint32_t associativity[] = {cpu_to_be32(0x5),
191 cpu_to_be32(0x0),
192 cpu_to_be32(0x0),
193 cpu_to_be32(0x0),
194 cpu_to_be32(cs->numa_node),
195 cpu_to_be32(index)};
196
197 /* Advertise NUMA via ibm,associativity */
198 if (nb_numa_nodes > 1) {
199 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity,
200 sizeof(associativity));
201 }
202
203 return ret;
204 }
205
206 /* Populate the "ibm,pa-features" property */
207 static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset,
208 bool legacy_guest)
209 {
210 uint8_t pa_features_206[] = { 6, 0,
211 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
212 uint8_t pa_features_207[] = { 24, 0,
213 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
214 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
215 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
216 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
217 uint8_t pa_features_300[] = { 66, 0,
218 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
219 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */
220 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
221 /* 6: DS207 */
222 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
223 /* 16: Vector */
224 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
225 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
226 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
227 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
228 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
229 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
230 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
231 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */
232 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */
233 /* 42: PM, 44: PC RA, 46: SC vec'd */
234 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
235 /* 48: SIMD, 50: QP BFP, 52: String */
236 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
237 /* 54: DecFP, 56: DecI, 58: SHA */
238 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
239 /* 60: NM atomic, 62: RNG */
240 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
241 };
242 uint8_t *pa_features;
243 size_t pa_size;
244
245 switch (POWERPC_MMU_VER(env->mmu_model)) {
246 case POWERPC_MMU_VER_2_06:
247 pa_features = pa_features_206;
248 pa_size = sizeof(pa_features_206);
249 break;
250 case POWERPC_MMU_VER_2_07:
251 pa_features = pa_features_207;
252 pa_size = sizeof(pa_features_207);
253 break;
254 case POWERPC_MMU_VER_3_00:
255 pa_features = pa_features_300;
256 pa_size = sizeof(pa_features_300);
257 break;
258 default:
259 return;
260 }
261
262 if (env->ci_large_pages) {
263 /*
264 * Note: we keep CI large pages off by default because a 64K capable
265 * guest provisioned with large pages might otherwise try to map a qemu
266 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
267 * even if that qemu runs on a 4k host.
268 * We dd this bit back here if we are confident this is not an issue
269 */
270 pa_features[3] |= 0x20;
271 }
272 if (kvmppc_has_cap_htm() && pa_size > 24) {
273 pa_features[24] |= 0x80; /* Transactional memory support */
274 }
275 if (legacy_guest && pa_size > 40) {
276 /* Workaround for broken kernels that attempt (guest) radix
277 * mode when they can't handle it, if they see the radix bit set
278 * in pa-features. So hide it from them. */
279 pa_features[40 + 2] &= ~0x80; /* Radix MMU */
280 }
281
282 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
283 }
284
285 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
286 {
287 int ret = 0, offset, cpus_offset;
288 CPUState *cs;
289 char cpu_model[32];
290 int smt = kvmppc_smt_threads();
291 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
292
293 CPU_FOREACH(cs) {
294 PowerPCCPU *cpu = POWERPC_CPU(cs);
295 CPUPPCState *env = &cpu->env;
296 DeviceClass *dc = DEVICE_GET_CLASS(cs);
297 int index = ppc_get_vcpu_dt_id(cpu);
298 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu));
299
300 if ((index % smt) != 0) {
301 continue;
302 }
303
304 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
305
306 cpus_offset = fdt_path_offset(fdt, "/cpus");
307 if (cpus_offset < 0) {
308 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"),
309 "cpus");
310 if (cpus_offset < 0) {
311 return cpus_offset;
312 }
313 }
314 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
315 if (offset < 0) {
316 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
317 if (offset < 0) {
318 return offset;
319 }
320 }
321
322 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
323 pft_size_prop, sizeof(pft_size_prop));
324 if (ret < 0) {
325 return ret;
326 }
327
328 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs);
329 if (ret < 0) {
330 return ret;
331 }
332
333 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt);
334 if (ret < 0) {
335 return ret;
336 }
337
338 spapr_populate_pa_features(env, fdt, offset,
339 spapr->cas_legacy_guest_workaround);
340 }
341 return ret;
342 }
343
344 static hwaddr spapr_node0_size(void)
345 {
346 MachineState *machine = MACHINE(qdev_get_machine());
347
348 if (nb_numa_nodes) {
349 int i;
350 for (i = 0; i < nb_numa_nodes; ++i) {
351 if (numa_info[i].node_mem) {
352 return MIN(pow2floor(numa_info[i].node_mem),
353 machine->ram_size);
354 }
355 }
356 }
357 return machine->ram_size;
358 }
359
360 static void add_str(GString *s, const gchar *s1)
361 {
362 g_string_append_len(s, s1, strlen(s1) + 1);
363 }
364
365 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
366 hwaddr size)
367 {
368 uint32_t associativity[] = {
369 cpu_to_be32(0x4), /* length */
370 cpu_to_be32(0x0), cpu_to_be32(0x0),
371 cpu_to_be32(0x0), cpu_to_be32(nodeid)
372 };
373 char mem_name[32];
374 uint64_t mem_reg_property[2];
375 int off;
376
377 mem_reg_property[0] = cpu_to_be64(start);
378 mem_reg_property[1] = cpu_to_be64(size);
379
380 sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
381 off = fdt_add_subnode(fdt, 0, mem_name);
382 _FDT(off);
383 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
384 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
385 sizeof(mem_reg_property))));
386 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
387 sizeof(associativity))));
388 return off;
389 }
390
391 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt)
392 {
393 MachineState *machine = MACHINE(spapr);
394 hwaddr mem_start, node_size;
395 int i, nb_nodes = nb_numa_nodes;
396 NodeInfo *nodes = numa_info;
397 NodeInfo ramnode;
398
399 /* No NUMA nodes, assume there is just one node with whole RAM */
400 if (!nb_numa_nodes) {
401 nb_nodes = 1;
402 ramnode.node_mem = machine->ram_size;
403 nodes = &ramnode;
404 }
405
406 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
407 if (!nodes[i].node_mem) {
408 continue;
409 }
410 if (mem_start >= machine->ram_size) {
411 node_size = 0;
412 } else {
413 node_size = nodes[i].node_mem;
414 if (node_size > machine->ram_size - mem_start) {
415 node_size = machine->ram_size - mem_start;
416 }
417 }
418 if (!mem_start) {
419 /* ppc_spapr_init() checks for rma_size <= node0_size already */
420 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
421 mem_start += spapr->rma_size;
422 node_size -= spapr->rma_size;
423 }
424 for ( ; node_size; ) {
425 hwaddr sizetmp = pow2floor(node_size);
426
427 /* mem_start != 0 here */
428 if (ctzl(mem_start) < ctzl(sizetmp)) {
429 sizetmp = 1ULL << ctzl(mem_start);
430 }
431
432 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
433 node_size -= sizetmp;
434 mem_start += sizetmp;
435 }
436 }
437
438 return 0;
439 }
440
441 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
442 sPAPRMachineState *spapr)
443 {
444 PowerPCCPU *cpu = POWERPC_CPU(cs);
445 CPUPPCState *env = &cpu->env;
446 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
447 int index = ppc_get_vcpu_dt_id(cpu);
448 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
449 0xffffffff, 0xffffffff};
450 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
451 : SPAPR_TIMEBASE_FREQ;
452 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
453 uint32_t page_sizes_prop[64];
454 size_t page_sizes_prop_size;
455 uint32_t vcpus_per_socket = smp_threads * smp_cores;
456 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
457 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu));
458 sPAPRDRConnector *drc;
459 sPAPRDRConnectorClass *drck;
460 int drc_index;
461 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ];
462 int i;
463
464 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index);
465 if (drc) {
466 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
467 drc_index = drck->get_index(drc);
468 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));
469 }
470
471 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
472 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
473
474 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
475 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
476 env->dcache_line_size)));
477 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
478 env->dcache_line_size)));
479 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
480 env->icache_line_size)));
481 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
482 env->icache_line_size)));
483
484 if (pcc->l1_dcache_size) {
485 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
486 pcc->l1_dcache_size)));
487 } else {
488 error_report("Warning: Unknown L1 dcache size for cpu");
489 }
490 if (pcc->l1_icache_size) {
491 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
492 pcc->l1_icache_size)));
493 } else {
494 error_report("Warning: Unknown L1 icache size for cpu");
495 }
496
497 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
498 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
499 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr)));
500 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
501 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
502 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
503
504 if (env->spr_cb[SPR_PURR].oea_read) {
505 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
506 }
507
508 if (env->mmu_model & POWERPC_MMU_1TSEG) {
509 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
510 segs, sizeof(segs))));
511 }
512
513 /* Advertise VMX/VSX (vector extensions) if available
514 * 0 / no property == no vector extensions
515 * 1 == VMX / Altivec available
516 * 2 == VSX available */
517 if (env->insns_flags & PPC_ALTIVEC) {
518 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
519
520 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
521 }
522
523 /* Advertise DFP (Decimal Floating Point) if available
524 * 0 / no property == no DFP
525 * 1 == DFP available */
526 if (env->insns_flags2 & PPC2_DFP) {
527 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
528 }
529
530 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop,
531 sizeof(page_sizes_prop));
532 if (page_sizes_prop_size) {
533 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
534 page_sizes_prop, page_sizes_prop_size)));
535 }
536
537 spapr_populate_pa_features(env, fdt, offset, false);
538
539 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
540 cs->cpu_index / vcpus_per_socket)));
541
542 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
543 pft_size_prop, sizeof(pft_size_prop))));
544
545 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs));
546
547 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt));
548
549 if (pcc->radix_page_info) {
550 for (i = 0; i < pcc->radix_page_info->count; i++) {
551 radix_AP_encodings[i] =
552 cpu_to_be32(pcc->radix_page_info->entries[i]);
553 }
554 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings",
555 radix_AP_encodings,
556 pcc->radix_page_info->count *
557 sizeof(radix_AP_encodings[0]))));
558 }
559 }
560
561 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
562 {
563 CPUState *cs;
564 int cpus_offset;
565 char *nodename;
566 int smt = kvmppc_smt_threads();
567
568 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
569 _FDT(cpus_offset);
570 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
571 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
572
573 /*
574 * We walk the CPUs in reverse order to ensure that CPU DT nodes
575 * created by fdt_add_subnode() end up in the right order in FDT
576 * for the guest kernel the enumerate the CPUs correctly.
577 */
578 CPU_FOREACH_REVERSE(cs) {
579 PowerPCCPU *cpu = POWERPC_CPU(cs);
580 int index = ppc_get_vcpu_dt_id(cpu);
581 DeviceClass *dc = DEVICE_GET_CLASS(cs);
582 int offset;
583
584 if ((index % smt) != 0) {
585 continue;
586 }
587
588 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
589 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
590 g_free(nodename);
591 _FDT(offset);
592 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
593 }
594
595 }
596
597 /*
598 * Adds ibm,dynamic-reconfiguration-memory node.
599 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
600 * of this device tree node.
601 */
602 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
603 {
604 MachineState *machine = MACHINE(spapr);
605 int ret, i, offset;
606 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
607 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
608 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size;
609 uint32_t nr_lmbs = (spapr->hotplug_memory.base +
610 memory_region_size(&spapr->hotplug_memory.mr)) /
611 lmb_size;
612 uint32_t *int_buf, *cur_index, buf_len;
613 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
614
615 /*
616 * Don't create the node if there is no hotpluggable memory
617 */
618 if (machine->ram_size == machine->maxram_size) {
619 return 0;
620 }
621
622 /*
623 * Allocate enough buffer size to fit in ibm,dynamic-memory
624 * or ibm,associativity-lookup-arrays
625 */
626 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2)
627 * sizeof(uint32_t);
628 cur_index = int_buf = g_malloc0(buf_len);
629
630 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
631
632 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
633 sizeof(prop_lmb_size));
634 if (ret < 0) {
635 goto out;
636 }
637
638 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
639 if (ret < 0) {
640 goto out;
641 }
642
643 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
644 if (ret < 0) {
645 goto out;
646 }
647
648 /* ibm,dynamic-memory */
649 int_buf[0] = cpu_to_be32(nr_lmbs);
650 cur_index++;
651 for (i = 0; i < nr_lmbs; i++) {
652 uint64_t addr = i * lmb_size;
653 uint32_t *dynamic_memory = cur_index;
654
655 if (i >= hotplug_lmb_start) {
656 sPAPRDRConnector *drc;
657 sPAPRDRConnectorClass *drck;
658
659 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, i);
660 g_assert(drc);
661 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
662
663 dynamic_memory[0] = cpu_to_be32(addr >> 32);
664 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
665 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc));
666 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
667 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL));
668 if (memory_region_present(get_system_memory(), addr)) {
669 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
670 } else {
671 dynamic_memory[5] = cpu_to_be32(0);
672 }
673 } else {
674 /*
675 * LMB information for RMA, boot time RAM and gap b/n RAM and
676 * hotplug memory region -- all these are marked as reserved
677 * and as having no valid DRC.
678 */
679 dynamic_memory[0] = cpu_to_be32(addr >> 32);
680 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
681 dynamic_memory[2] = cpu_to_be32(0);
682 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
683 dynamic_memory[4] = cpu_to_be32(-1);
684 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
685 SPAPR_LMB_FLAGS_DRC_INVALID);
686 }
687
688 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
689 }
690 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
691 if (ret < 0) {
692 goto out;
693 }
694
695 /* ibm,associativity-lookup-arrays */
696 cur_index = int_buf;
697 int_buf[0] = cpu_to_be32(nr_nodes);
698 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */
699 cur_index += 2;
700 for (i = 0; i < nr_nodes; i++) {
701 uint32_t associativity[] = {
702 cpu_to_be32(0x0),
703 cpu_to_be32(0x0),
704 cpu_to_be32(0x0),
705 cpu_to_be32(i)
706 };
707 memcpy(cur_index, associativity, sizeof(associativity));
708 cur_index += 4;
709 }
710 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
711 (cur_index - int_buf) * sizeof(uint32_t));
712 out:
713 g_free(int_buf);
714 return ret;
715 }
716
717 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt,
718 sPAPROptionVector *ov5_updates)
719 {
720 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
721 int ret = 0, offset;
722
723 /* Generate ibm,dynamic-reconfiguration-memory node if required */
724 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) {
725 g_assert(smc->dr_lmb_enabled);
726 ret = spapr_populate_drconf_memory(spapr, fdt);
727 if (ret) {
728 goto out;
729 }
730 }
731
732 offset = fdt_path_offset(fdt, "/chosen");
733 if (offset < 0) {
734 offset = fdt_add_subnode(fdt, 0, "chosen");
735 if (offset < 0) {
736 return offset;
737 }
738 }
739 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas,
740 "ibm,architecture-vec-5");
741
742 out:
743 return ret;
744 }
745
746 int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
747 target_ulong addr, target_ulong size,
748 sPAPROptionVector *ov5_updates)
749 {
750 void *fdt, *fdt_skel;
751 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };
752
753 size -= sizeof(hdr);
754
755 /* Create sceleton */
756 fdt_skel = g_malloc0(size);
757 _FDT((fdt_create(fdt_skel, size)));
758 _FDT((fdt_begin_node(fdt_skel, "")));
759 _FDT((fdt_end_node(fdt_skel)));
760 _FDT((fdt_finish(fdt_skel)));
761 fdt = g_malloc0(size);
762 _FDT((fdt_open_into(fdt_skel, fdt, size)));
763 g_free(fdt_skel);
764
765 /* Fixup cpu nodes */
766 _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
767
768 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) {
769 return -1;
770 }
771
772 /* Pack resulting tree */
773 _FDT((fdt_pack(fdt)));
774
775 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
776 trace_spapr_cas_failed(size);
777 return -1;
778 }
779
780 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
781 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
782 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
783 g_free(fdt);
784
785 return 0;
786 }
787
788 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt)
789 {
790 int rtas;
791 GString *hypertas = g_string_sized_new(256);
792 GString *qemu_hypertas = g_string_sized_new(256);
793 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
794 uint64_t max_hotplug_addr = spapr->hotplug_memory.base +
795 memory_region_size(&spapr->hotplug_memory.mr);
796 uint32_t lrdr_capacity[] = {
797 cpu_to_be32(max_hotplug_addr >> 32),
798 cpu_to_be32(max_hotplug_addr & 0xffffffff),
799 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE),
800 cpu_to_be32(max_cpus / smp_threads),
801 };
802
803 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas"));
804
805 /* hypertas */
806 add_str(hypertas, "hcall-pft");
807 add_str(hypertas, "hcall-term");
808 add_str(hypertas, "hcall-dabr");
809 add_str(hypertas, "hcall-interrupt");
810 add_str(hypertas, "hcall-tce");
811 add_str(hypertas, "hcall-vio");
812 add_str(hypertas, "hcall-splpar");
813 add_str(hypertas, "hcall-bulk");
814 add_str(hypertas, "hcall-set-mode");
815 add_str(hypertas, "hcall-sprg0");
816 add_str(hypertas, "hcall-copy");
817 add_str(hypertas, "hcall-debug");
818 add_str(qemu_hypertas, "hcall-memop1");
819
820 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
821 add_str(hypertas, "hcall-multi-tce");
822 }
823 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions",
824 hypertas->str, hypertas->len));
825 g_string_free(hypertas, TRUE);
826 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions",
827 qemu_hypertas->str, qemu_hypertas->len));
828 g_string_free(qemu_hypertas, TRUE);
829
830 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points",
831 refpoints, sizeof(refpoints)));
832
833 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max",
834 RTAS_ERROR_LOG_MAX));
835 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate",
836 RTAS_EVENT_SCAN_RATE));
837
838 if (msi_nonbroken) {
839 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0));
840 }
841
842 /*
843 * According to PAPR, rtas ibm,os-term does not guarantee a return
844 * back to the guest cpu.
845 *
846 * While an additional ibm,extended-os-term property indicates
847 * that rtas call return will always occur. Set this property.
848 */
849 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0));
850
851 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity",
852 lrdr_capacity, sizeof(lrdr_capacity)));
853
854 spapr_dt_rtas_tokens(fdt, rtas);
855 }
856
857 /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features
858 * that the guest may request and thus the valid values for bytes 24..26 of
859 * option vector 5: */
860 static void spapr_dt_ov5_platform_support(void *fdt, int chosen)
861 {
862 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
863
864 char val[2 * 3] = {
865 24, 0x00, /* Hash/Radix, filled in below. */
866 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */
867 26, 0x40, /* Radix options: GTSE == yes. */
868 };
869
870 if (kvm_enabled()) {
871 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
872 val[1] = 0x80; /* OV5_MMU_BOTH */
873 } else if (kvmppc_has_cap_mmu_radix()) {
874 val[1] = 0x40; /* OV5_MMU_RADIX_300 */
875 } else {
876 val[1] = 0x00; /* Hash */
877 }
878 } else {
879 if (first_ppc_cpu->env.mmu_model & POWERPC_MMU_V3) {
880 /* V3 MMU supports both hash and radix (with dynamic switching) */
881 val[1] = 0xC0;
882 } else {
883 /* Otherwise we can only do hash */
884 val[1] = 0x00;
885 }
886 }
887 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support",
888 val, sizeof(val)));
889 }
890
891 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt)
892 {
893 MachineState *machine = MACHINE(spapr);
894 int chosen;
895 const char *boot_device = machine->boot_order;
896 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus);
897 size_t cb = 0;
898 char *bootlist = get_boot_devices_list(&cb, true);
899
900 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen"));
901
902 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline));
903 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start",
904 spapr->initrd_base));
905 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end",
906 spapr->initrd_base + spapr->initrd_size));
907
908 if (spapr->kernel_size) {
909 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
910 cpu_to_be64(spapr->kernel_size) };
911
912 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel",
913 &kprop, sizeof(kprop)));
914 if (spapr->kernel_le) {
915 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0));
916 }
917 }
918 if (boot_menu) {
919 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu)));
920 }
921 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width));
922 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height));
923 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth));
924
925 if (cb && bootlist) {
926 int i;
927
928 for (i = 0; i < cb; i++) {
929 if (bootlist[i] == '\n') {
930 bootlist[i] = ' ';
931 }
932 }
933 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist));
934 }
935
936 if (boot_device && strlen(boot_device)) {
937 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device));
938 }
939
940 if (!spapr->has_graphics && stdout_path) {
941 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path));
942 }
943
944 spapr_dt_ov5_platform_support(fdt, chosen);
945
946 g_free(stdout_path);
947 g_free(bootlist);
948 }
949
950 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt)
951 {
952 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
953 * KVM to work under pHyp with some guest co-operation */
954 int hypervisor;
955 uint8_t hypercall[16];
956
957 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor"));
958 /* indicate KVM hypercall interface */
959 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm"));
960 if (kvmppc_has_cap_fixup_hcalls()) {
961 /*
962 * Older KVM versions with older guest kernels were broken
963 * with the magic page, don't allow the guest to map it.
964 */
965 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
966 sizeof(hypercall))) {
967 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions",
968 hypercall, sizeof(hypercall)));
969 }
970 }
971 }
972
973 static void *spapr_build_fdt(sPAPRMachineState *spapr,
974 hwaddr rtas_addr,
975 hwaddr rtas_size)
976 {
977 MachineState *machine = MACHINE(qdev_get_machine());
978 MachineClass *mc = MACHINE_GET_CLASS(machine);
979 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
980 int ret;
981 void *fdt;
982 sPAPRPHBState *phb;
983 char *buf;
984 int smt = kvmppc_smt_threads();
985
986 fdt = g_malloc0(FDT_MAX_SIZE);
987 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
988
989 /* Root node */
990 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp"));
991 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)"));
992 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries"));
993
994 /*
995 * Add info to guest to indentify which host is it being run on
996 * and what is the uuid of the guest
997 */
998 if (kvmppc_get_host_model(&buf)) {
999 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf));
1000 g_free(buf);
1001 }
1002 if (kvmppc_get_host_serial(&buf)) {
1003 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf));
1004 g_free(buf);
1005 }
1006
1007 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
1008
1009 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf));
1010 if (qemu_uuid_set) {
1011 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf));
1012 }
1013 g_free(buf);
1014
1015 if (qemu_get_vm_name()) {
1016 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name",
1017 qemu_get_vm_name()));
1018 }
1019
1020 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2));
1021 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2));
1022
1023 /* /interrupt controller */
1024 spapr_dt_xics(DIV_ROUND_UP(max_cpus * smt, smp_threads), fdt, PHANDLE_XICP);
1025
1026 ret = spapr_populate_memory(spapr, fdt);
1027 if (ret < 0) {
1028 error_report("couldn't setup memory nodes in fdt");
1029 exit(1);
1030 }
1031
1032 /* /vdevice */
1033 spapr_dt_vdevice(spapr->vio_bus, fdt);
1034
1035 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
1036 ret = spapr_rng_populate_dt(fdt);
1037 if (ret < 0) {
1038 error_report("could not set up rng device in the fdt");
1039 exit(1);
1040 }
1041 }
1042
1043 QLIST_FOREACH(phb, &spapr->phbs, list) {
1044 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
1045 if (ret < 0) {
1046 error_report("couldn't setup PCI devices in fdt");
1047 exit(1);
1048 }
1049 }
1050
1051 /* cpus */
1052 spapr_populate_cpus_dt_node(fdt, spapr);
1053
1054 if (smc->dr_lmb_enabled) {
1055 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
1056 }
1057
1058 if (mc->has_hotpluggable_cpus) {
1059 int offset = fdt_path_offset(fdt, "/cpus");
1060 ret = spapr_drc_populate_dt(fdt, offset, NULL,
1061 SPAPR_DR_CONNECTOR_TYPE_CPU);
1062 if (ret < 0) {
1063 error_report("Couldn't set up CPU DR device tree properties");
1064 exit(1);
1065 }
1066 }
1067
1068 /* /event-sources */
1069 spapr_dt_events(spapr, fdt);
1070
1071 /* /rtas */
1072 spapr_dt_rtas(spapr, fdt);
1073
1074 /* /chosen */
1075 spapr_dt_chosen(spapr, fdt);
1076
1077 /* /hypervisor */
1078 if (kvm_enabled()) {
1079 spapr_dt_hypervisor(spapr, fdt);
1080 }
1081
1082 /* Build memory reserve map */
1083 if (spapr->kernel_size) {
1084 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size)));
1085 }
1086 if (spapr->initrd_size) {
1087 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size)));
1088 }
1089
1090 /* ibm,client-architecture-support updates */
1091 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas);
1092 if (ret < 0) {
1093 error_report("couldn't setup CAS properties fdt");
1094 exit(1);
1095 }
1096
1097 return fdt;
1098 }
1099
1100 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1101 {
1102 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
1103 }
1104
1105 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp,
1106 PowerPCCPU *cpu)
1107 {
1108 CPUPPCState *env = &cpu->env;
1109
1110 /* The TCG path should also be holding the BQL at this point */
1111 g_assert(qemu_mutex_iothread_locked());
1112
1113 if (msr_pr) {
1114 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1115 env->gpr[3] = H_PRIVILEGE;
1116 } else {
1117 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
1118 }
1119 }
1120
1121 static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp)
1122 {
1123 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1124
1125 return spapr->patb_entry;
1126 }
1127
1128 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1129 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1130 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1131 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1132 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1133
1134 /*
1135 * Get the fd to access the kernel htab, re-opening it if necessary
1136 */
1137 static int get_htab_fd(sPAPRMachineState *spapr)
1138 {
1139 if (spapr->htab_fd >= 0) {
1140 return spapr->htab_fd;
1141 }
1142
1143 spapr->htab_fd = kvmppc_get_htab_fd(false);
1144 if (spapr->htab_fd < 0) {
1145 error_report("Unable to open fd for reading hash table from KVM: %s",
1146 strerror(errno));
1147 }
1148
1149 return spapr->htab_fd;
1150 }
1151
1152 void close_htab_fd(sPAPRMachineState *spapr)
1153 {
1154 if (spapr->htab_fd >= 0) {
1155 close(spapr->htab_fd);
1156 }
1157 spapr->htab_fd = -1;
1158 }
1159
1160 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp)
1161 {
1162 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1163
1164 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1;
1165 }
1166
1167 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp,
1168 hwaddr ptex, int n)
1169 {
1170 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1171 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64;
1172
1173 if (!spapr->htab) {
1174 /*
1175 * HTAB is controlled by KVM. Fetch into temporary buffer
1176 */
1177 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64);
1178 kvmppc_read_hptes(hptes, ptex, n);
1179 return hptes;
1180 }
1181
1182 /*
1183 * HTAB is controlled by QEMU. Just point to the internally
1184 * accessible PTEG.
1185 */
1186 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset);
1187 }
1188
1189 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp,
1190 const ppc_hash_pte64_t *hptes,
1191 hwaddr ptex, int n)
1192 {
1193 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1194
1195 if (!spapr->htab) {
1196 g_free((void *)hptes);
1197 }
1198
1199 /* Nothing to do for qemu managed HPT */
1200 }
1201
1202 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1203 uint64_t pte0, uint64_t pte1)
1204 {
1205 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1206 hwaddr offset = ptex * HASH_PTE_SIZE_64;
1207
1208 if (!spapr->htab) {
1209 kvmppc_write_hpte(ptex, pte0, pte1);
1210 } else {
1211 stq_p(spapr->htab + offset, pte0);
1212 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1213 }
1214 }
1215
1216 static int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1217 {
1218 int shift;
1219
1220 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1221 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1222 * that's much more than is needed for Linux guests */
1223 shift = ctz64(pow2ceil(ramsize)) - 7;
1224 shift = MAX(shift, 18); /* Minimum architected size */
1225 shift = MIN(shift, 46); /* Maximum architected size */
1226 return shift;
1227 }
1228
1229 void spapr_free_hpt(sPAPRMachineState *spapr)
1230 {
1231 g_free(spapr->htab);
1232 spapr->htab = NULL;
1233 spapr->htab_shift = 0;
1234 close_htab_fd(spapr);
1235 }
1236
1237 static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
1238 Error **errp)
1239 {
1240 long rc;
1241
1242 /* Clean up any HPT info from a previous boot */
1243 spapr_free_hpt(spapr);
1244
1245 rc = kvmppc_reset_htab(shift);
1246 if (rc < 0) {
1247 /* kernel-side HPT needed, but couldn't allocate one */
1248 error_setg_errno(errp, errno,
1249 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1250 shift);
1251 /* This is almost certainly fatal, but if the caller really
1252 * wants to carry on with shift == 0, it's welcome to try */
1253 } else if (rc > 0) {
1254 /* kernel-side HPT allocated */
1255 if (rc != shift) {
1256 error_setg(errp,
1257 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1258 shift, rc);
1259 }
1260
1261 spapr->htab_shift = shift;
1262 spapr->htab = NULL;
1263 } else {
1264 /* kernel-side HPT not needed, allocate in userspace instead */
1265 size_t size = 1ULL << shift;
1266 int i;
1267
1268 spapr->htab = qemu_memalign(size, size);
1269 if (!spapr->htab) {
1270 error_setg_errno(errp, errno,
1271 "Could not allocate HPT of order %d", shift);
1272 return;
1273 }
1274
1275 memset(spapr->htab, 0, size);
1276 spapr->htab_shift = shift;
1277
1278 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1279 DIRTY_HPTE(HPTE(spapr->htab, i));
1280 }
1281 }
1282 }
1283
1284 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr)
1285 {
1286 spapr_reallocate_hpt(spapr,
1287 spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size),
1288 &error_fatal);
1289 if (spapr->vrma_adjust) {
1290 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(),
1291 spapr->htab_shift);
1292 }
1293 /* We're setting up a hash table, so that means we're not radix */
1294 spapr->patb_entry = 0;
1295 }
1296
1297 static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque)
1298 {
1299 bool matched = false;
1300
1301 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
1302 matched = true;
1303 }
1304
1305 if (!matched) {
1306 error_report("Device %s is not supported by this machine yet.",
1307 qdev_fw_name(DEVICE(sbdev)));
1308 exit(1);
1309 }
1310 }
1311
1312 static void ppc_spapr_reset(void)
1313 {
1314 MachineState *machine = MACHINE(qdev_get_machine());
1315 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1316 PowerPCCPU *first_ppc_cpu;
1317 uint32_t rtas_limit;
1318 hwaddr rtas_addr, fdt_addr;
1319 void *fdt;
1320 int rc;
1321
1322 /* Check for unknown sysbus devices */
1323 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL);
1324
1325 if (kvm_enabled() && kvmppc_has_cap_mmu_radix()) {
1326 /* If using KVM with radix mode available, VCPUs can be started
1327 * without a HPT because KVM will start them in radix mode.
1328 * Set the GR bit in PATB so that we know there is no HPT. */
1329 spapr->patb_entry = PATBE1_GR;
1330 } else {
1331 spapr->patb_entry = 0;
1332 spapr_setup_hpt_and_vrma(spapr);
1333 }
1334
1335 qemu_devices_reset();
1336
1337 /*
1338 * We place the device tree and RTAS just below either the top of the RMA,
1339 * or just below 2GB, whichever is lowere, so that it can be
1340 * processed with 32-bit real mode code if necessary
1341 */
1342 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
1343 rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1344 fdt_addr = rtas_addr - FDT_MAX_SIZE;
1345
1346 /* if this reset wasn't generated by CAS, we should reset our
1347 * negotiated options and start from scratch */
1348 if (!spapr->cas_reboot) {
1349 spapr_ovec_cleanup(spapr->ov5_cas);
1350 spapr->ov5_cas = spapr_ovec_new();
1351 }
1352
1353 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size);
1354
1355 spapr_load_rtas(spapr, fdt, rtas_addr);
1356
1357 rc = fdt_pack(fdt);
1358
1359 /* Should only fail if we've built a corrupted tree */
1360 assert(rc == 0);
1361
1362 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
1363 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1364 fdt_totalsize(fdt), FDT_MAX_SIZE);
1365 exit(1);
1366 }
1367
1368 /* Load the fdt */
1369 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
1370 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
1371 g_free(fdt);
1372
1373 /* Set up the entry state */
1374 first_ppc_cpu = POWERPC_CPU(first_cpu);
1375 first_ppc_cpu->env.gpr[3] = fdt_addr;
1376 first_ppc_cpu->env.gpr[5] = 0;
1377 first_cpu->halted = 0;
1378 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT;
1379
1380 spapr->cas_reboot = false;
1381 }
1382
1383 static void spapr_create_nvram(sPAPRMachineState *spapr)
1384 {
1385 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
1386 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1387
1388 if (dinfo) {
1389 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1390 &error_fatal);
1391 }
1392
1393 qdev_init_nofail(dev);
1394
1395 spapr->nvram = (struct sPAPRNVRAM *)dev;
1396 }
1397
1398 static void spapr_rtc_create(sPAPRMachineState *spapr)
1399 {
1400 object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC);
1401 object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc),
1402 &error_fatal);
1403 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized",
1404 &error_fatal);
1405 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc),
1406 "date", &error_fatal);
1407 }
1408
1409 /* Returns whether we want to use VGA or not */
1410 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
1411 {
1412 switch (vga_interface_type) {
1413 case VGA_NONE:
1414 return false;
1415 case VGA_DEVICE:
1416 return true;
1417 case VGA_STD:
1418 case VGA_VIRTIO:
1419 return pci_vga_init(pci_bus) != NULL;
1420 default:
1421 error_setg(errp,
1422 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1423 return false;
1424 }
1425 }
1426
1427 static int spapr_post_load(void *opaque, int version_id)
1428 {
1429 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1430 int err = 0;
1431
1432 if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) {
1433 CPUState *cs;
1434 CPU_FOREACH(cs) {
1435 PowerPCCPU *cpu = POWERPC_CPU(cs);
1436 icp_resend(ICP(cpu->intc));
1437 }
1438 }
1439
1440 /* In earlier versions, there was no separate qdev for the PAPR
1441 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1442 * So when migrating from those versions, poke the incoming offset
1443 * value into the RTC device */
1444 if (version_id < 3) {
1445 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset);
1446 }
1447
1448 return err;
1449 }
1450
1451 static bool version_before_3(void *opaque, int version_id)
1452 {
1453 return version_id < 3;
1454 }
1455
1456 static bool spapr_ov5_cas_needed(void *opaque)
1457 {
1458 sPAPRMachineState *spapr = opaque;
1459 sPAPROptionVector *ov5_mask = spapr_ovec_new();
1460 sPAPROptionVector *ov5_legacy = spapr_ovec_new();
1461 sPAPROptionVector *ov5_removed = spapr_ovec_new();
1462 bool cas_needed;
1463
1464 /* Prior to the introduction of sPAPROptionVector, we had two option
1465 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1466 * Both of these options encode machine topology into the device-tree
1467 * in such a way that the now-booted OS should still be able to interact
1468 * appropriately with QEMU regardless of what options were actually
1469 * negotiatied on the source side.
1470 *
1471 * As such, we can avoid migrating the CAS-negotiated options if these
1472 * are the only options available on the current machine/platform.
1473 * Since these are the only options available for pseries-2.7 and
1474 * earlier, this allows us to maintain old->new/new->old migration
1475 * compatibility.
1476 *
1477 * For QEMU 2.8+, there are additional CAS-negotiatable options available
1478 * via default pseries-2.8 machines and explicit command-line parameters.
1479 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
1480 * of the actual CAS-negotiated values to continue working properly. For
1481 * example, availability of memory unplug depends on knowing whether
1482 * OV5_HP_EVT was negotiated via CAS.
1483 *
1484 * Thus, for any cases where the set of available CAS-negotiatable
1485 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
1486 * include the CAS-negotiated options in the migration stream.
1487 */
1488 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY);
1489 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY);
1490
1491 /* spapr_ovec_diff returns true if bits were removed. we avoid using
1492 * the mask itself since in the future it's possible "legacy" bits may be
1493 * removed via machine options, which could generate a false positive
1494 * that breaks migration.
1495 */
1496 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask);
1497 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy);
1498
1499 spapr_ovec_cleanup(ov5_mask);
1500 spapr_ovec_cleanup(ov5_legacy);
1501 spapr_ovec_cleanup(ov5_removed);
1502
1503 return cas_needed;
1504 }
1505
1506 static const VMStateDescription vmstate_spapr_ov5_cas = {
1507 .name = "spapr_option_vector_ov5_cas",
1508 .version_id = 1,
1509 .minimum_version_id = 1,
1510 .needed = spapr_ov5_cas_needed,
1511 .fields = (VMStateField[]) {
1512 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1,
1513 vmstate_spapr_ovec, sPAPROptionVector),
1514 VMSTATE_END_OF_LIST()
1515 },
1516 };
1517
1518 static bool spapr_patb_entry_needed(void *opaque)
1519 {
1520 sPAPRMachineState *spapr = opaque;
1521
1522 return !!spapr->patb_entry;
1523 }
1524
1525 static const VMStateDescription vmstate_spapr_patb_entry = {
1526 .name = "spapr_patb_entry",
1527 .version_id = 1,
1528 .minimum_version_id = 1,
1529 .needed = spapr_patb_entry_needed,
1530 .fields = (VMStateField[]) {
1531 VMSTATE_UINT64(patb_entry, sPAPRMachineState),
1532 VMSTATE_END_OF_LIST()
1533 },
1534 };
1535
1536 static const VMStateDescription vmstate_spapr = {
1537 .name = "spapr",
1538 .version_id = 3,
1539 .minimum_version_id = 1,
1540 .post_load = spapr_post_load,
1541 .fields = (VMStateField[]) {
1542 /* used to be @next_irq */
1543 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
1544
1545 /* RTC offset */
1546 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3),
1547
1548 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2),
1549 VMSTATE_END_OF_LIST()
1550 },
1551 .subsections = (const VMStateDescription*[]) {
1552 &vmstate_spapr_ov5_cas,
1553 &vmstate_spapr_patb_entry,
1554 NULL
1555 }
1556 };
1557
1558 static int htab_save_setup(QEMUFile *f, void *opaque)
1559 {
1560 sPAPRMachineState *spapr = opaque;
1561
1562 /* "Iteration" header */
1563 qemu_put_be32(f, spapr->htab_shift);
1564
1565 if (spapr->htab) {
1566 spapr->htab_save_index = 0;
1567 spapr->htab_first_pass = true;
1568 } else {
1569 assert(kvm_enabled());
1570 }
1571
1572
1573 return 0;
1574 }
1575
1576 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr,
1577 int64_t max_ns)
1578 {
1579 bool has_timeout = max_ns != -1;
1580 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1581 int index = spapr->htab_save_index;
1582 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1583
1584 assert(spapr->htab_first_pass);
1585
1586 do {
1587 int chunkstart;
1588
1589 /* Consume invalid HPTEs */
1590 while ((index < htabslots)
1591 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1592 CLEAN_HPTE(HPTE(spapr->htab, index));
1593 index++;
1594 }
1595
1596 /* Consume valid HPTEs */
1597 chunkstart = index;
1598 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1599 && HPTE_VALID(HPTE(spapr->htab, index))) {
1600 CLEAN_HPTE(HPTE(spapr->htab, index));
1601 index++;
1602 }
1603
1604 if (index > chunkstart) {
1605 int n_valid = index - chunkstart;
1606
1607 qemu_put_be32(f, chunkstart);
1608 qemu_put_be16(f, n_valid);
1609 qemu_put_be16(f, 0);
1610 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1611 HASH_PTE_SIZE_64 * n_valid);
1612
1613 if (has_timeout &&
1614 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1615 break;
1616 }
1617 }
1618 } while ((index < htabslots) && !qemu_file_rate_limit(f));
1619
1620 if (index >= htabslots) {
1621 assert(index == htabslots);
1622 index = 0;
1623 spapr->htab_first_pass = false;
1624 }
1625 spapr->htab_save_index = index;
1626 }
1627
1628 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr,
1629 int64_t max_ns)
1630 {
1631 bool final = max_ns < 0;
1632 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1633 int examined = 0, sent = 0;
1634 int index = spapr->htab_save_index;
1635 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1636
1637 assert(!spapr->htab_first_pass);
1638
1639 do {
1640 int chunkstart, invalidstart;
1641
1642 /* Consume non-dirty HPTEs */
1643 while ((index < htabslots)
1644 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
1645 index++;
1646 examined++;
1647 }
1648
1649 chunkstart = index;
1650 /* Consume valid dirty HPTEs */
1651 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1652 && HPTE_DIRTY(HPTE(spapr->htab, index))
1653 && HPTE_VALID(HPTE(spapr->htab, index))) {
1654 CLEAN_HPTE(HPTE(spapr->htab, index));
1655 index++;
1656 examined++;
1657 }
1658
1659 invalidstart = index;
1660 /* Consume invalid dirty HPTEs */
1661 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
1662 && HPTE_DIRTY(HPTE(spapr->htab, index))
1663 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1664 CLEAN_HPTE(HPTE(spapr->htab, index));
1665 index++;
1666 examined++;
1667 }
1668
1669 if (index > chunkstart) {
1670 int n_valid = invalidstart - chunkstart;
1671 int n_invalid = index - invalidstart;
1672
1673 qemu_put_be32(f, chunkstart);
1674 qemu_put_be16(f, n_valid);
1675 qemu_put_be16(f, n_invalid);
1676 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1677 HASH_PTE_SIZE_64 * n_valid);
1678 sent += index - chunkstart;
1679
1680 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1681 break;
1682 }
1683 }
1684
1685 if (examined >= htabslots) {
1686 break;
1687 }
1688
1689 if (index >= htabslots) {
1690 assert(index == htabslots);
1691 index = 0;
1692 }
1693 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
1694
1695 if (index >= htabslots) {
1696 assert(index == htabslots);
1697 index = 0;
1698 }
1699
1700 spapr->htab_save_index = index;
1701
1702 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
1703 }
1704
1705 #define MAX_ITERATION_NS 5000000 /* 5 ms */
1706 #define MAX_KVM_BUF_SIZE 2048
1707
1708 static int htab_save_iterate(QEMUFile *f, void *opaque)
1709 {
1710 sPAPRMachineState *spapr = opaque;
1711 int fd;
1712 int rc = 0;
1713
1714 /* Iteration header */
1715 qemu_put_be32(f, 0);
1716
1717 if (!spapr->htab) {
1718 assert(kvm_enabled());
1719
1720 fd = get_htab_fd(spapr);
1721 if (fd < 0) {
1722 return fd;
1723 }
1724
1725 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
1726 if (rc < 0) {
1727 return rc;
1728 }
1729 } else if (spapr->htab_first_pass) {
1730 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
1731 } else {
1732 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
1733 }
1734
1735 /* End marker */
1736 qemu_put_be32(f, 0);
1737 qemu_put_be16(f, 0);
1738 qemu_put_be16(f, 0);
1739
1740 return rc;
1741 }
1742
1743 static int htab_save_complete(QEMUFile *f, void *opaque)
1744 {
1745 sPAPRMachineState *spapr = opaque;
1746 int fd;
1747
1748 /* Iteration header */
1749 qemu_put_be32(f, 0);
1750
1751 if (!spapr->htab) {
1752 int rc;
1753
1754 assert(kvm_enabled());
1755
1756 fd = get_htab_fd(spapr);
1757 if (fd < 0) {
1758 return fd;
1759 }
1760
1761 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
1762 if (rc < 0) {
1763 return rc;
1764 }
1765 } else {
1766 if (spapr->htab_first_pass) {
1767 htab_save_first_pass(f, spapr, -1);
1768 }
1769 htab_save_later_pass(f, spapr, -1);
1770 }
1771
1772 /* End marker */
1773 qemu_put_be32(f, 0);
1774 qemu_put_be16(f, 0);
1775 qemu_put_be16(f, 0);
1776
1777 return 0;
1778 }
1779
1780 static int htab_load(QEMUFile *f, void *opaque, int version_id)
1781 {
1782 sPAPRMachineState *spapr = opaque;
1783 uint32_t section_hdr;
1784 int fd = -1;
1785
1786 if (version_id < 1 || version_id > 1) {
1787 error_report("htab_load() bad version");
1788 return -EINVAL;
1789 }
1790
1791 section_hdr = qemu_get_be32(f);
1792
1793 if (section_hdr) {
1794 Error *local_err = NULL;
1795
1796 /* First section gives the htab size */
1797 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
1798 if (local_err) {
1799 error_report_err(local_err);
1800 return -EINVAL;
1801 }
1802 return 0;
1803 }
1804
1805 if (!spapr->htab) {
1806 assert(kvm_enabled());
1807
1808 fd = kvmppc_get_htab_fd(true);
1809 if (fd < 0) {
1810 error_report("Unable to open fd to restore KVM hash table: %s",
1811 strerror(errno));
1812 }
1813 }
1814
1815 while (true) {
1816 uint32_t index;
1817 uint16_t n_valid, n_invalid;
1818
1819 index = qemu_get_be32(f);
1820 n_valid = qemu_get_be16(f);
1821 n_invalid = qemu_get_be16(f);
1822
1823 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
1824 /* End of Stream */
1825 break;
1826 }
1827
1828 if ((index + n_valid + n_invalid) >
1829 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
1830 /* Bad index in stream */
1831 error_report(
1832 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
1833 index, n_valid, n_invalid, spapr->htab_shift);
1834 return -EINVAL;
1835 }
1836
1837 if (spapr->htab) {
1838 if (n_valid) {
1839 qemu_get_buffer(f, HPTE(spapr->htab, index),
1840 HASH_PTE_SIZE_64 * n_valid);
1841 }
1842 if (n_invalid) {
1843 memset(HPTE(spapr->htab, index + n_valid), 0,
1844 HASH_PTE_SIZE_64 * n_invalid);
1845 }
1846 } else {
1847 int rc;
1848
1849 assert(fd >= 0);
1850
1851 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
1852 if (rc < 0) {
1853 return rc;
1854 }
1855 }
1856 }
1857
1858 if (!spapr->htab) {
1859 assert(fd >= 0);
1860 close(fd);
1861 }
1862
1863 return 0;
1864 }
1865
1866 static void htab_cleanup(void *opaque)
1867 {
1868 sPAPRMachineState *spapr = opaque;
1869
1870 close_htab_fd(spapr);
1871 }
1872
1873 static SaveVMHandlers savevm_htab_handlers = {
1874 .save_live_setup = htab_save_setup,
1875 .save_live_iterate = htab_save_iterate,
1876 .save_live_complete_precopy = htab_save_complete,
1877 .cleanup = htab_cleanup,
1878 .load_state = htab_load,
1879 };
1880
1881 static void spapr_boot_set(void *opaque, const char *boot_device,
1882 Error **errp)
1883 {
1884 MachineState *machine = MACHINE(qdev_get_machine());
1885 machine->boot_order = g_strdup(boot_device);
1886 }
1887
1888 /*
1889 * Reset routine for LMB DR devices.
1890 *
1891 * Unlike PCI DR devices, LMB DR devices explicitly register this reset
1892 * routine. Reset for PCI DR devices will be handled by PHB reset routine
1893 * when it walks all its children devices. LMB devices reset occurs
1894 * as part of spapr_ppc_reset().
1895 */
1896 static void spapr_drc_reset(void *opaque)
1897 {
1898 sPAPRDRConnector *drc = opaque;
1899 DeviceState *d = DEVICE(drc);
1900
1901 if (d) {
1902 device_reset(d);
1903 }
1904 }
1905
1906 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr)
1907 {
1908 MachineState *machine = MACHINE(spapr);
1909 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
1910 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
1911 int i;
1912
1913 for (i = 0; i < nr_lmbs; i++) {
1914 sPAPRDRConnector *drc;
1915 uint64_t addr;
1916
1917 addr = i * lmb_size + spapr->hotplug_memory.base;
1918 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB,
1919 addr/lmb_size);
1920 qemu_register_reset(spapr_drc_reset, drc);
1921 }
1922 }
1923
1924 /*
1925 * If RAM size, maxmem size and individual node mem sizes aren't aligned
1926 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
1927 * since we can't support such unaligned sizes with DRCONF_MEMORY.
1928 */
1929 static void spapr_validate_node_memory(MachineState *machine, Error **errp)
1930 {
1931 int i;
1932
1933 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1934 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
1935 " is not aligned to %llu MiB",
1936 machine->ram_size,
1937 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1938 return;
1939 }
1940
1941 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1942 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
1943 " is not aligned to %llu MiB",
1944 machine->ram_size,
1945 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1946 return;
1947 }
1948
1949 for (i = 0; i < nb_numa_nodes; i++) {
1950 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
1951 error_setg(errp,
1952 "Node %d memory size 0x%" PRIx64
1953 " is not aligned to %llu MiB",
1954 i, numa_info[i].node_mem,
1955 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1956 return;
1957 }
1958 }
1959 }
1960
1961 /* find cpu slot in machine->possible_cpus by core_id */
1962 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
1963 {
1964 int index = id / smp_threads;
1965
1966 if (index >= ms->possible_cpus->len) {
1967 return NULL;
1968 }
1969 if (idx) {
1970 *idx = index;
1971 }
1972 return &ms->possible_cpus->cpus[index];
1973 }
1974
1975 static void spapr_init_cpus(sPAPRMachineState *spapr)
1976 {
1977 MachineState *machine = MACHINE(spapr);
1978 MachineClass *mc = MACHINE_GET_CLASS(machine);
1979 char *type = spapr_get_cpu_core_type(machine->cpu_model);
1980 int smt = kvmppc_smt_threads();
1981 const CPUArchIdList *possible_cpus;
1982 int boot_cores_nr = smp_cpus / smp_threads;
1983 int i;
1984
1985 if (!type) {
1986 error_report("Unable to find sPAPR CPU Core definition");
1987 exit(1);
1988 }
1989
1990 possible_cpus = mc->possible_cpu_arch_ids(machine);
1991 if (mc->has_hotpluggable_cpus) {
1992 if (smp_cpus % smp_threads) {
1993 error_report("smp_cpus (%u) must be multiple of threads (%u)",
1994 smp_cpus, smp_threads);
1995 exit(1);
1996 }
1997 if (max_cpus % smp_threads) {
1998 error_report("max_cpus (%u) must be multiple of threads (%u)",
1999 max_cpus, smp_threads);
2000 exit(1);
2001 }
2002 } else {
2003 if (max_cpus != smp_cpus) {
2004 error_report("This machine version does not support CPU hotplug");
2005 exit(1);
2006 }
2007 boot_cores_nr = possible_cpus->len;
2008 }
2009
2010 for (i = 0; i < possible_cpus->len; i++) {
2011 int core_id = i * smp_threads;
2012
2013 if (mc->has_hotpluggable_cpus) {
2014 sPAPRDRConnector *drc =
2015 spapr_dr_connector_new(OBJECT(spapr),
2016 SPAPR_DR_CONNECTOR_TYPE_CPU,
2017 (core_id / smp_threads) * smt);
2018
2019 qemu_register_reset(spapr_drc_reset, drc);
2020 }
2021
2022 if (i < boot_cores_nr) {
2023 Object *core = object_new(type);
2024 int nr_threads = smp_threads;
2025
2026 /* Handle the partially filled core for older machine types */
2027 if ((i + 1) * smp_threads >= smp_cpus) {
2028 nr_threads = smp_cpus - i * smp_threads;
2029 }
2030
2031 object_property_set_int(core, nr_threads, "nr-threads",
2032 &error_fatal);
2033 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID,
2034 &error_fatal);
2035 object_property_set_bool(core, true, "realized", &error_fatal);
2036 }
2037 }
2038 g_free(type);
2039 }
2040
2041 /* pSeries LPAR / sPAPR hardware init */
2042 static void ppc_spapr_init(MachineState *machine)
2043 {
2044 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
2045 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2046 const char *kernel_filename = machine->kernel_filename;
2047 const char *initrd_filename = machine->initrd_filename;
2048 PCIHostState *phb;
2049 int i;
2050 MemoryRegion *sysmem = get_system_memory();
2051 MemoryRegion *ram = g_new(MemoryRegion, 1);
2052 MemoryRegion *rma_region;
2053 void *rma = NULL;
2054 hwaddr rma_alloc_size;
2055 hwaddr node0_size = spapr_node0_size();
2056 long load_limit, fw_size;
2057 char *filename;
2058
2059 msi_nonbroken = true;
2060
2061 QLIST_INIT(&spapr->phbs);
2062 QTAILQ_INIT(&spapr->pending_dimm_unplugs);
2063
2064 /* Allocate RMA if necessary */
2065 rma_alloc_size = kvmppc_alloc_rma(&rma);
2066
2067 if (rma_alloc_size == -1) {
2068 error_report("Unable to create RMA");
2069 exit(1);
2070 }
2071
2072 if (rma_alloc_size && (rma_alloc_size < node0_size)) {
2073 spapr->rma_size = rma_alloc_size;
2074 } else {
2075 spapr->rma_size = node0_size;
2076
2077 /* With KVM, we don't actually know whether KVM supports an
2078 * unbounded RMA (PR KVM) or is limited by the hash table size
2079 * (HV KVM using VRMA), so we always assume the latter
2080 *
2081 * In that case, we also limit the initial allocations for RTAS
2082 * etc... to 256M since we have no way to know what the VRMA size
2083 * is going to be as it depends on the size of the hash table
2084 * isn't determined yet.
2085 */
2086 if (kvm_enabled()) {
2087 spapr->vrma_adjust = 1;
2088 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
2089 }
2090
2091 /* Actually we don't support unbounded RMA anymore since we
2092 * added proper emulation of HV mode. The max we can get is
2093 * 16G which also happens to be what we configure for PAPR
2094 * mode so make sure we don't do anything bigger than that
2095 */
2096 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull);
2097 }
2098
2099 if (spapr->rma_size > node0_size) {
2100 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
2101 spapr->rma_size);
2102 exit(1);
2103 }
2104
2105 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
2106 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
2107
2108 /* Set up Interrupt Controller before we create the VCPUs */
2109 xics_system_init(machine, XICS_IRQS_SPAPR, &error_fatal);
2110
2111 /* Set up containers for ibm,client-set-architecture negotiated options */
2112 spapr->ov5 = spapr_ovec_new();
2113 spapr->ov5_cas = spapr_ovec_new();
2114
2115 if (smc->dr_lmb_enabled) {
2116 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY);
2117 spapr_validate_node_memory(machine, &error_fatal);
2118 }
2119
2120 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY);
2121 if (!kvm_enabled() || kvmppc_has_cap_mmu_radix()) {
2122 /* KVM and TCG always allow GTSE with radix... */
2123 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE);
2124 }
2125 /* ... but not with hash (currently). */
2126
2127 /* advertise support for dedicated HP event source to guests */
2128 if (spapr->use_hotplug_event_source) {
2129 spapr_ovec_set(spapr->ov5, OV5_HP_EVT);
2130 }
2131
2132 /* init CPUs */
2133 if (machine->cpu_model == NULL) {
2134 machine->cpu_model = kvm_enabled() ? "host" : smc->tcg_default_cpu;
2135 }
2136
2137 ppc_cpu_parse_features(machine->cpu_model);
2138
2139 spapr_init_cpus(spapr);
2140
2141 if (kvm_enabled()) {
2142 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
2143 kvmppc_enable_logical_ci_hcalls();
2144 kvmppc_enable_set_mode_hcall();
2145
2146 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
2147 kvmppc_enable_clear_ref_mod_hcalls();
2148 }
2149
2150 /* allocate RAM */
2151 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
2152 machine->ram_size);
2153 memory_region_add_subregion(sysmem, 0, ram);
2154
2155 if (rma_alloc_size && rma) {
2156 rma_region = g_new(MemoryRegion, 1);
2157 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma",
2158 rma_alloc_size, rma);
2159 vmstate_register_ram_global(rma_region);
2160 memory_region_add_subregion(sysmem, 0, rma_region);
2161 }
2162
2163 /* initialize hotplug memory address space */
2164 if (machine->ram_size < machine->maxram_size) {
2165 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size;
2166 /*
2167 * Limit the number of hotpluggable memory slots to half the number
2168 * slots that KVM supports, leaving the other half for PCI and other
2169 * devices. However ensure that number of slots doesn't drop below 32.
2170 */
2171 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
2172 SPAPR_MAX_RAM_SLOTS;
2173
2174 if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
2175 max_memslots = SPAPR_MAX_RAM_SLOTS;
2176 }
2177 if (machine->ram_slots > max_memslots) {
2178 error_report("Specified number of memory slots %"
2179 PRIu64" exceeds max supported %d",
2180 machine->ram_slots, max_memslots);
2181 exit(1);
2182 }
2183
2184 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size,
2185 SPAPR_HOTPLUG_MEM_ALIGN);
2186 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr),
2187 "hotplug-memory", hotplug_mem_size);
2188 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base,
2189 &spapr->hotplug_memory.mr);
2190 }
2191
2192 if (smc->dr_lmb_enabled) {
2193 spapr_create_lmb_dr_connectors(spapr);
2194 }
2195
2196 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
2197 if (!filename) {
2198 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
2199 exit(1);
2200 }
2201 spapr->rtas_size = get_image_size(filename);
2202 if (spapr->rtas_size < 0) {
2203 error_report("Could not get size of LPAR rtas '%s'", filename);
2204 exit(1);
2205 }
2206 spapr->rtas_blob = g_malloc(spapr->rtas_size);
2207 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
2208 error_report("Could not load LPAR rtas '%s'", filename);
2209 exit(1);
2210 }
2211 if (spapr->rtas_size > RTAS_MAX_SIZE) {
2212 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
2213 (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
2214 exit(1);
2215 }
2216 g_free(filename);
2217
2218 /* Set up RTAS event infrastructure */
2219 spapr_events_init(spapr);
2220
2221 /* Set up the RTC RTAS interfaces */
2222 spapr_rtc_create(spapr);
2223
2224 /* Set up VIO bus */
2225 spapr->vio_bus = spapr_vio_bus_init();
2226
2227 for (i = 0; i < MAX_SERIAL_PORTS; i++) {
2228 if (serial_hds[i]) {
2229 spapr_vty_create(spapr->vio_bus, serial_hds[i]);
2230 }
2231 }
2232
2233 /* We always have at least the nvram device on VIO */
2234 spapr_create_nvram(spapr);
2235
2236 /* Set up PCI */
2237 spapr_pci_rtas_init();
2238
2239 phb = spapr_create_phb(spapr, 0);
2240
2241 for (i = 0; i < nb_nics; i++) {
2242 NICInfo *nd = &nd_table[i];
2243
2244 if (!nd->model) {
2245 nd->model = g_strdup("ibmveth");
2246 }
2247
2248 if (strcmp(nd->model, "ibmveth") == 0) {
2249 spapr_vlan_create(spapr->vio_bus, nd);
2250 } else {
2251 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
2252 }
2253 }
2254
2255 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
2256 spapr_vscsi_create(spapr->vio_bus);
2257 }
2258
2259 /* Graphics */
2260 if (spapr_vga_init(phb->bus, &error_fatal)) {
2261 spapr->has_graphics = true;
2262 machine->usb |= defaults_enabled() && !machine->usb_disabled;
2263 }
2264
2265 if (machine->usb) {
2266 if (smc->use_ohci_by_default) {
2267 pci_create_simple(phb->bus, -1, "pci-ohci");
2268 } else {
2269 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
2270 }
2271
2272 if (spapr->has_graphics) {
2273 USBBus *usb_bus = usb_bus_find(-1);
2274
2275 usb_create_simple(usb_bus, "usb-kbd");
2276 usb_create_simple(usb_bus, "usb-mouse");
2277 }
2278 }
2279
2280 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) {
2281 error_report(
2282 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
2283 MIN_RMA_SLOF);
2284 exit(1);
2285 }
2286
2287 if (kernel_filename) {
2288 uint64_t lowaddr = 0;
2289
2290 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address,
2291 NULL, NULL, &lowaddr, NULL, 1,
2292 PPC_ELF_MACHINE, 0, 0);
2293 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) {
2294 spapr->kernel_size = load_elf(kernel_filename,
2295 translate_kernel_address, NULL, NULL,
2296 &lowaddr, NULL, 0, PPC_ELF_MACHINE,
2297 0, 0);
2298 spapr->kernel_le = spapr->kernel_size > 0;
2299 }
2300 if (spapr->kernel_size < 0) {
2301 error_report("error loading %s: %s", kernel_filename,
2302 load_elf_strerror(spapr->kernel_size));
2303 exit(1);
2304 }
2305
2306 /* load initrd */
2307 if (initrd_filename) {
2308 /* Try to locate the initrd in the gap between the kernel
2309 * and the firmware. Add a bit of space just in case
2310 */
2311 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size
2312 + 0x1ffff) & ~0xffff;
2313 spapr->initrd_size = load_image_targphys(initrd_filename,
2314 spapr->initrd_base,
2315 load_limit
2316 - spapr->initrd_base);
2317 if (spapr->initrd_size < 0) {
2318 error_report("could not load initial ram disk '%s'",
2319 initrd_filename);
2320 exit(1);
2321 }
2322 }
2323 }
2324
2325 if (bios_name == NULL) {
2326 bios_name = FW_FILE_NAME;
2327 }
2328 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
2329 if (!filename) {
2330 error_report("Could not find LPAR firmware '%s'", bios_name);
2331 exit(1);
2332 }
2333 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
2334 if (fw_size <= 0) {
2335 error_report("Could not load LPAR firmware '%s'", filename);
2336 exit(1);
2337 }
2338 g_free(filename);
2339
2340 /* FIXME: Should register things through the MachineState's qdev
2341 * interface, this is a legacy from the sPAPREnvironment structure
2342 * which predated MachineState but had a similar function */
2343 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
2344 register_savevm_live(NULL, "spapr/htab", -1, 1,
2345 &savevm_htab_handlers, spapr);
2346
2347 /* used by RTAS */
2348 QTAILQ_INIT(&spapr->ccs_list);
2349 qemu_register_reset(spapr_ccs_reset_hook, spapr);
2350
2351 qemu_register_boot_set(spapr_boot_set, spapr);
2352
2353 if (kvm_enabled()) {
2354 /* to stop and start vmclock */
2355 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change,
2356 &spapr->tb);
2357
2358 kvmppc_spapr_enable_inkernel_multitce();
2359 }
2360 }
2361
2362 static int spapr_kvm_type(const char *vm_type)
2363 {
2364 if (!vm_type) {
2365 return 0;
2366 }
2367
2368 if (!strcmp(vm_type, "HV")) {
2369 return 1;
2370 }
2371
2372 if (!strcmp(vm_type, "PR")) {
2373 return 2;
2374 }
2375
2376 error_report("Unknown kvm-type specified '%s'", vm_type);
2377 exit(1);
2378 }
2379
2380 /*
2381 * Implementation of an interface to adjust firmware path
2382 * for the bootindex property handling.
2383 */
2384 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
2385 DeviceState *dev)
2386 {
2387 #define CAST(type, obj, name) \
2388 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
2389 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
2390 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
2391
2392 if (d) {
2393 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
2394 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
2395 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
2396
2397 if (spapr) {
2398 /*
2399 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
2400 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
2401 * in the top 16 bits of the 64-bit LUN
2402 */
2403 unsigned id = 0x8000 | (d->id << 8) | d->lun;
2404 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2405 (uint64_t)id << 48);
2406 } else if (virtio) {
2407 /*
2408 * We use SRP luns of the form 01000000 | (target << 8) | lun
2409 * in the top 32 bits of the 64-bit LUN
2410 * Note: the quote above is from SLOF and it is wrong,
2411 * the actual binding is:
2412 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
2413 */
2414 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
2415 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2416 (uint64_t)id << 32);
2417 } else if (usb) {
2418 /*
2419 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
2420 * in the top 32 bits of the 64-bit LUN
2421 */
2422 unsigned usb_port = atoi(usb->port->path);
2423 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
2424 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2425 (uint64_t)id << 32);
2426 }
2427 }
2428
2429 /*
2430 * SLOF probes the USB devices, and if it recognizes that the device is a
2431 * storage device, it changes its name to "storage" instead of "usb-host",
2432 * and additionally adds a child node for the SCSI LUN, so the correct
2433 * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
2434 */
2435 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) {
2436 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE);
2437 if (usb_host_dev_is_scsi_storage(usbdev)) {
2438 return g_strdup_printf("storage@%s/disk", usbdev->port->path);
2439 }
2440 }
2441
2442 if (phb) {
2443 /* Replace "pci" with "pci@800000020000000" */
2444 return g_strdup_printf("pci@%"PRIX64, phb->buid);
2445 }
2446
2447 return NULL;
2448 }
2449
2450 static char *spapr_get_kvm_type(Object *obj, Error **errp)
2451 {
2452 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2453
2454 return g_strdup(spapr->kvm_type);
2455 }
2456
2457 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
2458 {
2459 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2460
2461 g_free(spapr->kvm_type);
2462 spapr->kvm_type = g_strdup(value);
2463 }
2464
2465 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp)
2466 {
2467 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2468
2469 return spapr->use_hotplug_event_source;
2470 }
2471
2472 static void spapr_set_modern_hotplug_events(Object *obj, bool value,
2473 Error **errp)
2474 {
2475 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2476
2477 spapr->use_hotplug_event_source = value;
2478 }
2479
2480 static void spapr_machine_initfn(Object *obj)
2481 {
2482 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2483
2484 spapr->htab_fd = -1;
2485 spapr->use_hotplug_event_source = true;
2486 object_property_add_str(obj, "kvm-type",
2487 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
2488 object_property_set_description(obj, "kvm-type",
2489 "Specifies the KVM virtualization mode (HV, PR)",
2490 NULL);
2491 object_property_add_bool(obj, "modern-hotplug-events",
2492 spapr_get_modern_hotplug_events,
2493 spapr_set_modern_hotplug_events,
2494 NULL);
2495 object_property_set_description(obj, "modern-hotplug-events",
2496 "Use dedicated hotplug event mechanism in"
2497 " place of standard EPOW events when possible"
2498 " (required for memory hot-unplug support)",
2499 NULL);
2500 }
2501
2502 static void spapr_machine_finalizefn(Object *obj)
2503 {
2504 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2505
2506 g_free(spapr->kvm_type);
2507 }
2508
2509 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg)
2510 {
2511 cpu_synchronize_state(cs);
2512 ppc_cpu_do_system_reset(cs);
2513 }
2514
2515 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
2516 {
2517 CPUState *cs;
2518
2519 CPU_FOREACH(cs) {
2520 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
2521 }
2522 }
2523
2524 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size,
2525 uint32_t node, bool dedicated_hp_event_source,
2526 Error **errp)
2527 {
2528 sPAPRDRConnector *drc;
2529 sPAPRDRConnectorClass *drck;
2530 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
2531 int i, fdt_offset, fdt_size;
2532 void *fdt;
2533 uint64_t addr = addr_start;
2534
2535 for (i = 0; i < nr_lmbs; i++) {
2536 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2537 addr/SPAPR_MEMORY_BLOCK_SIZE);
2538 g_assert(drc);
2539
2540 fdt = create_device_tree(&fdt_size);
2541 fdt_offset = spapr_populate_memory_node(fdt, node, addr,
2542 SPAPR_MEMORY_BLOCK_SIZE);
2543
2544 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2545 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp);
2546 addr += SPAPR_MEMORY_BLOCK_SIZE;
2547 if (!dev->hotplugged) {
2548 /* guests expect coldplugged LMBs to be pre-allocated */
2549 drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE);
2550 drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED);
2551 }
2552 }
2553 /* send hotplug notification to the
2554 * guest only in case of hotplugged memory
2555 */
2556 if (dev->hotplugged) {
2557 if (dedicated_hp_event_source) {
2558 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2559 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
2560 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2561 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
2562 nr_lmbs,
2563 drck->get_index(drc));
2564 } else {
2565 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB,
2566 nr_lmbs);
2567 }
2568 }
2569 }
2570
2571 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2572 uint32_t node, Error **errp)
2573 {
2574 Error *local_err = NULL;
2575 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
2576 PCDIMMDevice *dimm = PC_DIMM(dev);
2577 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2578 MemoryRegion *mr = ddc->get_memory_region(dimm);
2579 uint64_t align = memory_region_get_alignment(mr);
2580 uint64_t size = memory_region_size(mr);
2581 uint64_t addr;
2582
2583 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err);
2584 if (local_err) {
2585 goto out;
2586 }
2587
2588 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err);
2589 if (local_err) {
2590 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr);
2591 goto out;
2592 }
2593
2594 spapr_add_lmbs(dev, addr, size, node,
2595 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT),
2596 &error_abort);
2597
2598 out:
2599 error_propagate(errp, local_err);
2600 }
2601
2602 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2603 Error **errp)
2604 {
2605 PCDIMMDevice *dimm = PC_DIMM(dev);
2606 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2607 MemoryRegion *mr = ddc->get_memory_region(dimm);
2608 uint64_t size = memory_region_size(mr);
2609 char *mem_dev;
2610
2611 if (size % SPAPR_MEMORY_BLOCK_SIZE) {
2612 error_setg(errp, "Hotplugged memory size must be a multiple of "
2613 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
2614 return;
2615 }
2616
2617 mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL);
2618 if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) {
2619 error_setg(errp, "Memory backend has bad page size. "
2620 "Use 'memory-backend-file' with correct mem-path.");
2621 return;
2622 }
2623 }
2624
2625 struct sPAPRDIMMState {
2626 PCDIMMDevice *dimm;
2627 uint32_t nr_lmbs;
2628 QTAILQ_ENTRY(sPAPRDIMMState) next;
2629 };
2630
2631 static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s,
2632 PCDIMMDevice *dimm)
2633 {
2634 sPAPRDIMMState *dimm_state = NULL;
2635
2636 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) {
2637 if (dimm_state->dimm == dimm) {
2638 break;
2639 }
2640 }
2641 return dimm_state;
2642 }
2643
2644 static void spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr,
2645 sPAPRDIMMState *dimm_state)
2646 {
2647 g_assert(!spapr_pending_dimm_unplugs_find(spapr, dimm_state->dimm));
2648 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, dimm_state, next);
2649 }
2650
2651 static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr,
2652 sPAPRDIMMState *dimm_state)
2653 {
2654 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next);
2655 g_free(dimm_state);
2656 }
2657
2658 static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms,
2659 PCDIMMDevice *dimm)
2660 {
2661 sPAPRDRConnector *drc;
2662 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2663 MemoryRegion *mr = ddc->get_memory_region(dimm);
2664 uint64_t size = memory_region_size(mr);
2665 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
2666 uint32_t avail_lmbs = 0;
2667 uint64_t addr_start, addr;
2668 int i;
2669 sPAPRDIMMState *ds;
2670
2671 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP,
2672 &error_abort);
2673
2674 addr = addr_start;
2675 for (i = 0; i < nr_lmbs; i++) {
2676 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2677 addr / SPAPR_MEMORY_BLOCK_SIZE);
2678 g_assert(drc);
2679 if (drc->indicator_state != SPAPR_DR_INDICATOR_STATE_INACTIVE) {
2680 avail_lmbs++;
2681 }
2682 addr += SPAPR_MEMORY_BLOCK_SIZE;
2683 }
2684
2685 ds = g_malloc0(sizeof(sPAPRDIMMState));
2686 ds->nr_lmbs = avail_lmbs;
2687 ds->dimm = dimm;
2688 spapr_pending_dimm_unplugs_add(ms, ds);
2689 return ds;
2690 }
2691
2692 /* Callback to be called during DRC release. */
2693 void spapr_lmb_release(DeviceState *dev)
2694 {
2695 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev);
2696 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl);
2697 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev));
2698
2699 /* This information will get lost if a migration occurs
2700 * during the unplug process. In this case recover it. */
2701 if (ds == NULL) {
2702 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev));
2703 if (ds->nr_lmbs) {
2704 return;
2705 }
2706 } else if (--ds->nr_lmbs) {
2707 return;
2708 }
2709
2710 spapr_pending_dimm_unplugs_remove(spapr, ds);
2711
2712 /*
2713 * Now that all the LMBs have been removed by the guest, call the
2714 * pc-dimm unplug handler to cleanup up the pc-dimm device.
2715 */
2716 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
2717 }
2718
2719 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev,
2720 Error **errp)
2721 {
2722 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
2723 PCDIMMDevice *dimm = PC_DIMM(dev);
2724 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2725 MemoryRegion *mr = ddc->get_memory_region(dimm);
2726
2727 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr);
2728 object_unparent(OBJECT(dev));
2729 }
2730
2731 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev,
2732 DeviceState *dev, Error **errp)
2733 {
2734 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
2735 Error *local_err = NULL;
2736 PCDIMMDevice *dimm = PC_DIMM(dev);
2737 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2738 MemoryRegion *mr = ddc->get_memory_region(dimm);
2739 uint64_t size = memory_region_size(mr);
2740 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
2741 uint64_t addr_start, addr;
2742 int i;
2743 sPAPRDRConnector *drc;
2744 sPAPRDRConnectorClass *drck;
2745 sPAPRDIMMState *ds;
2746
2747 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP,
2748 &local_err);
2749 if (local_err) {
2750 goto out;
2751 }
2752
2753 ds = g_malloc0(sizeof(sPAPRDIMMState));
2754 ds->nr_lmbs = nr_lmbs;
2755 ds->dimm = dimm;
2756 spapr_pending_dimm_unplugs_add(spapr, ds);
2757
2758 addr = addr_start;
2759 for (i = 0; i < nr_lmbs; i++) {
2760 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2761 addr / SPAPR_MEMORY_BLOCK_SIZE);
2762 g_assert(drc);
2763
2764 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2765 drck->detach(drc, dev, errp);
2766 addr += SPAPR_MEMORY_BLOCK_SIZE;
2767 }
2768
2769 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2770 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
2771 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2772 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
2773 nr_lmbs,
2774 drck->get_index(drc));
2775 out:
2776 error_propagate(errp, local_err);
2777 }
2778
2779 void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
2780 sPAPRMachineState *spapr)
2781 {
2782 PowerPCCPU *cpu = POWERPC_CPU(cs);
2783 DeviceClass *dc = DEVICE_GET_CLASS(cs);
2784 int id = ppc_get_vcpu_dt_id(cpu);
2785 void *fdt;
2786 int offset, fdt_size;
2787 char *nodename;
2788
2789 fdt = create_device_tree(&fdt_size);
2790 nodename = g_strdup_printf("%s@%x", dc->fw_name, id);
2791 offset = fdt_add_subnode(fdt, 0, nodename);
2792
2793 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
2794 g_free(nodename);
2795
2796 *fdt_offset = offset;
2797 return fdt;
2798 }
2799
2800 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev,
2801 Error **errp)
2802 {
2803 MachineState *ms = MACHINE(qdev_get_machine());
2804 CPUCore *cc = CPU_CORE(dev);
2805 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL);
2806
2807 assert(core_slot);
2808 core_slot->cpu = NULL;
2809 object_unparent(OBJECT(dev));
2810 }
2811
2812 /* Callback to be called during DRC release. */
2813 void spapr_core_release(DeviceState *dev)
2814 {
2815 HotplugHandler *hotplug_ctrl;
2816
2817 hotplug_ctrl = qdev_get_hotplug_handler(dev);
2818 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
2819 }
2820
2821 static
2822 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev,
2823 Error **errp)
2824 {
2825 int index;
2826 sPAPRDRConnector *drc;
2827 sPAPRDRConnectorClass *drck;
2828 Error *local_err = NULL;
2829 CPUCore *cc = CPU_CORE(dev);
2830 int smt = kvmppc_smt_threads();
2831
2832 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) {
2833 error_setg(errp, "Unable to find CPU core with core-id: %d",
2834 cc->core_id);
2835 return;
2836 }
2837 if (index == 0) {
2838 error_setg(errp, "Boot CPU core may not be unplugged");
2839 return;
2840 }
2841
2842 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
2843 g_assert(drc);
2844
2845 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2846 drck->detach(drc, dev, &local_err);
2847 if (local_err) {
2848 error_propagate(errp, local_err);
2849 return;
2850 }
2851
2852 spapr_hotplug_req_remove_by_index(drc);
2853 }
2854
2855 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2856 Error **errp)
2857 {
2858 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
2859 MachineClass *mc = MACHINE_GET_CLASS(spapr);
2860 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev));
2861 CPUCore *cc = CPU_CORE(dev);
2862 CPUState *cs = CPU(core->threads);
2863 sPAPRDRConnector *drc;
2864 Error *local_err = NULL;
2865 void *fdt = NULL;
2866 int fdt_offset = 0;
2867 int smt = kvmppc_smt_threads();
2868 CPUArchId *core_slot;
2869 int index;
2870
2871 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
2872 if (!core_slot) {
2873 error_setg(errp, "Unable to find CPU core with core-id: %d",
2874 cc->core_id);
2875 return;
2876 }
2877 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
2878
2879 g_assert(drc || !mc->has_hotpluggable_cpus);
2880
2881 /*
2882 * Setup CPU DT entries only for hotplugged CPUs. For boot time or
2883 * coldplugged CPUs DT entries are setup in spapr_build_fdt().
2884 */
2885 if (dev->hotplugged) {
2886 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr);
2887 }
2888
2889 if (drc) {
2890 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2891 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, &local_err);
2892 if (local_err) {
2893 g_free(fdt);
2894 error_propagate(errp, local_err);
2895 return;
2896 }
2897 }
2898
2899 if (dev->hotplugged) {
2900 /*
2901 * Send hotplug notification interrupt to the guest only in case
2902 * of hotplugged CPUs.
2903 */
2904 spapr_hotplug_req_add_by_index(drc);
2905 } else {
2906 /*
2907 * Set the right DRC states for cold plugged CPU.
2908 */
2909 if (drc) {
2910 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2911 drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE);
2912 drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED);
2913 }
2914 }
2915 core_slot->cpu = OBJECT(dev);
2916 }
2917
2918 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2919 Error **errp)
2920 {
2921 MachineState *machine = MACHINE(OBJECT(hotplug_dev));
2922 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev);
2923 Error *local_err = NULL;
2924 CPUCore *cc = CPU_CORE(dev);
2925 char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model);
2926 const char *type = object_get_typename(OBJECT(dev));
2927 CPUArchId *core_slot;
2928 int index;
2929
2930 if (dev->hotplugged && !mc->has_hotpluggable_cpus) {
2931 error_setg(&local_err, "CPU hotplug not supported for this machine");
2932 goto out;
2933 }
2934
2935 if (strcmp(base_core_type, type)) {
2936 error_setg(&local_err, "CPU core type should be %s", base_core_type);
2937 goto out;
2938 }
2939
2940 if (cc->core_id % smp_threads) {
2941 error_setg(&local_err, "invalid core id %d", cc->core_id);
2942 goto out;
2943 }
2944
2945 /*
2946 * In general we should have homogeneous threads-per-core, but old
2947 * (pre hotplug support) machine types allow the last core to have
2948 * reduced threads as a compatibility hack for when we allowed
2949 * total vcpus not a multiple of threads-per-core.
2950 */
2951 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) {
2952 error_setg(errp, "invalid nr-threads %d, must be %d",
2953 cc->nr_threads, smp_threads);
2954 return;
2955 }
2956
2957 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
2958 if (!core_slot) {
2959 error_setg(&local_err, "core id %d out of range", cc->core_id);
2960 goto out;
2961 }
2962
2963 if (core_slot->cpu) {
2964 error_setg(&local_err, "core %d already populated", cc->core_id);
2965 goto out;
2966 }
2967
2968 numa_cpu_pre_plug(core_slot, dev, &local_err);
2969
2970 out:
2971 g_free(base_core_type);
2972 error_propagate(errp, local_err);
2973 }
2974
2975 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
2976 DeviceState *dev, Error **errp)
2977 {
2978 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
2979
2980 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2981 int node;
2982
2983 if (!smc->dr_lmb_enabled) {
2984 error_setg(errp, "Memory hotplug not supported for this machine");
2985 return;
2986 }
2987 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp);
2988 if (*errp) {
2989 return;
2990 }
2991 if (node < 0 || node >= MAX_NODES) {
2992 error_setg(errp, "Invaild node %d", node);
2993 return;
2994 }
2995
2996 /*
2997 * Currently PowerPC kernel doesn't allow hot-adding memory to
2998 * memory-less node, but instead will silently add the memory
2999 * to the first node that has some memory. This causes two
3000 * unexpected behaviours for the user.
3001 *
3002 * - Memory gets hotplugged to a different node than what the user
3003 * specified.
3004 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs
3005 * to memory-less node, a reboot will set things accordingly
3006 * and the previously hotplugged memory now ends in the right node.
3007 * This appears as if some memory moved from one node to another.
3008 *
3009 * So until kernel starts supporting memory hotplug to memory-less
3010 * nodes, just prevent such attempts upfront in QEMU.
3011 */
3012 if (nb_numa_nodes && !numa_info[node].node_mem) {
3013 error_setg(errp, "Can't hotplug memory to memory-less node %d",
3014 node);
3015 return;
3016 }
3017
3018 spapr_memory_plug(hotplug_dev, dev, node, errp);
3019 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3020 spapr_core_plug(hotplug_dev, dev, errp);
3021 }
3022 }
3023
3024 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev,
3025 DeviceState *dev, Error **errp)
3026 {
3027 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine());
3028 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
3029
3030 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3031 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) {
3032 spapr_memory_unplug(hotplug_dev, dev, errp);
3033 } else {
3034 error_setg(errp, "Memory hot unplug not supported for this guest");
3035 }
3036 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3037 if (!mc->has_hotpluggable_cpus) {
3038 error_setg(errp, "CPU hot unplug not supported on this machine");
3039 return;
3040 }
3041 spapr_core_unplug(hotplug_dev, dev, errp);
3042 }
3043 }
3044
3045 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev,
3046 DeviceState *dev, Error **errp)
3047 {
3048 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine());
3049 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
3050
3051 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3052 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) {
3053 spapr_memory_unplug_request(hotplug_dev, dev, errp);
3054 } else {
3055 /* NOTE: this means there is a window after guest reset, prior to
3056 * CAS negotiation, where unplug requests will fail due to the
3057 * capability not being detected yet. This is a bit different than
3058 * the case with PCI unplug, where the events will be queued and
3059 * eventually handled by the guest after boot
3060 */
3061 error_setg(errp, "Memory hot unplug not supported for this guest");
3062 }
3063 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3064 if (!mc->has_hotpluggable_cpus) {
3065 error_setg(errp, "CPU hot unplug not supported on this machine");
3066 return;
3067 }
3068 spapr_core_unplug_request(hotplug_dev, dev, errp);
3069 }
3070 }
3071
3072 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev,
3073 DeviceState *dev, Error **errp)
3074 {
3075 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3076 spapr_memory_pre_plug(hotplug_dev, dev, errp);
3077 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3078 spapr_core_pre_plug(hotplug_dev, dev, errp);
3079 }
3080 }
3081
3082 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine,
3083 DeviceState *dev)
3084 {
3085 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
3086 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3087 return HOTPLUG_HANDLER(machine);
3088 }
3089 return NULL;
3090 }
3091
3092 static CpuInstanceProperties
3093 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index)
3094 {
3095 CPUArchId *core_slot;
3096 MachineClass *mc = MACHINE_GET_CLASS(machine);
3097
3098 /* make sure possible_cpu are intialized */
3099 mc->possible_cpu_arch_ids(machine);
3100 /* get CPU core slot containing thread that matches cpu_index */
3101 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL);
3102 assert(core_slot);
3103 return core_slot->props;
3104 }
3105
3106 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine)
3107 {
3108 int i;
3109 int spapr_max_cores = max_cpus / smp_threads;
3110 MachineClass *mc = MACHINE_GET_CLASS(machine);
3111
3112 if (!mc->has_hotpluggable_cpus) {
3113 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads;
3114 }
3115 if (machine->possible_cpus) {
3116 assert(machine->possible_cpus->len == spapr_max_cores);
3117 return machine->possible_cpus;
3118 }
3119
3120 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
3121 sizeof(CPUArchId) * spapr_max_cores);
3122 machine->possible_cpus->len = spapr_max_cores;
3123 for (i = 0; i < machine->possible_cpus->len; i++) {
3124 int core_id = i * smp_threads;
3125
3126 machine->possible_cpus->cpus[i].vcpus_count = smp_threads;
3127 machine->possible_cpus->cpus[i].arch_id = core_id;
3128 machine->possible_cpus->cpus[i].props.has_core_id = true;
3129 machine->possible_cpus->cpus[i].props.core_id = core_id;
3130
3131 /* default distribution of CPUs over NUMA nodes */
3132 if (nb_numa_nodes) {
3133 /* preset values but do not enable them i.e. 'has_node_id = false',
3134 * numa init code will enable them later if manual mapping wasn't
3135 * present on CLI */
3136 machine->possible_cpus->cpus[i].props.node_id =
3137 core_id / smp_threads / smp_cores % nb_numa_nodes;
3138 }
3139 }
3140 return machine->possible_cpus;
3141 }
3142
3143 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index,
3144 uint64_t *buid, hwaddr *pio,
3145 hwaddr *mmio32, hwaddr *mmio64,
3146 unsigned n_dma, uint32_t *liobns, Error **errp)
3147 {
3148 /*
3149 * New-style PHB window placement.
3150 *
3151 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window
3152 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO
3153 * windows.
3154 *
3155 * Some guest kernels can't work with MMIO windows above 1<<46
3156 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB
3157 *
3158 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each
3159 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the
3160 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the
3161 * 1TiB 64-bit MMIO windows for each PHB.
3162 */
3163 const uint64_t base_buid = 0x800000020000000ULL;
3164 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \
3165 SPAPR_PCI_MEM64_WIN_SIZE - 1)
3166 int i;
3167
3168 /* Sanity check natural alignments */
3169 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
3170 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
3171 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0);
3172 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0);
3173 /* Sanity check bounds */
3174 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) >
3175 SPAPR_PCI_MEM32_WIN_SIZE);
3176 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) >
3177 SPAPR_PCI_MEM64_WIN_SIZE);
3178
3179 if (index >= SPAPR_MAX_PHBS) {
3180 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)",
3181 SPAPR_MAX_PHBS - 1);
3182 return;
3183 }
3184
3185 *buid = base_buid + index;
3186 for (i = 0; i < n_dma; ++i) {
3187 liobns[i] = SPAPR_PCI_LIOBN(index, i);
3188 }
3189
3190 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE;
3191 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE;
3192 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE;
3193 }
3194
3195 static ICSState *spapr_ics_get(XICSFabric *dev, int irq)
3196 {
3197 sPAPRMachineState *spapr = SPAPR_MACHINE(dev);
3198
3199 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL;
3200 }
3201
3202 static void spapr_ics_resend(XICSFabric *dev)
3203 {
3204 sPAPRMachineState *spapr = SPAPR_MACHINE(dev);
3205
3206 ics_resend(spapr->ics);
3207 }
3208
3209 static ICPState *spapr_icp_get(XICSFabric *xi, int cpu_dt_id)
3210 {
3211 PowerPCCPU *cpu = ppc_get_vcpu_by_dt_id(cpu_dt_id);
3212
3213 return cpu ? ICP(cpu->intc) : NULL;
3214 }
3215
3216 static void spapr_pic_print_info(InterruptStatsProvider *obj,
3217 Monitor *mon)
3218 {
3219 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
3220 CPUState *cs;
3221
3222 CPU_FOREACH(cs) {
3223 PowerPCCPU *cpu = POWERPC_CPU(cs);
3224
3225 icp_pic_print_info(ICP(cpu->intc), mon);
3226 }
3227
3228 ics_pic_print_info(spapr->ics, mon);
3229 }
3230
3231 static void spapr_machine_class_init(ObjectClass *oc, void *data)
3232 {
3233 MachineClass *mc = MACHINE_CLASS(oc);
3234 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
3235 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
3236 NMIClass *nc = NMI_CLASS(oc);
3237 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
3238 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc);
3239 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
3240 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
3241
3242 mc->desc = "pSeries Logical Partition (PAPR compliant)";
3243
3244 /*
3245 * We set up the default / latest behaviour here. The class_init
3246 * functions for the specific versioned machine types can override
3247 * these details for backwards compatibility
3248 */
3249 mc->init = ppc_spapr_init;
3250 mc->reset = ppc_spapr_reset;
3251 mc->block_default_type = IF_SCSI;
3252 mc->max_cpus = 1024;
3253 mc->no_parallel = 1;
3254 mc->default_boot_order = "";
3255 mc->default_ram_size = 512 * M_BYTE;
3256 mc->kvm_type = spapr_kvm_type;
3257 mc->has_dynamic_sysbus = true;
3258 mc->pci_allow_0_address = true;
3259 mc->get_hotplug_handler = spapr_get_hotplug_handler;
3260 hc->pre_plug = spapr_machine_device_pre_plug;
3261 hc->plug = spapr_machine_device_plug;
3262 hc->unplug = spapr_machine_device_unplug;
3263 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props;
3264 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids;
3265 hc->unplug_request = spapr_machine_device_unplug_request;
3266
3267 smc->dr_lmb_enabled = true;
3268 smc->tcg_default_cpu = "POWER8";
3269 mc->has_hotpluggable_cpus = true;
3270 fwc->get_dev_path = spapr_get_fw_dev_path;
3271 nc->nmi_monitor_handler = spapr_nmi;
3272 smc->phb_placement = spapr_phb_placement;
3273 vhc->hypercall = emulate_spapr_hypercall;
3274 vhc->hpt_mask = spapr_hpt_mask;
3275 vhc->map_hptes = spapr_map_hptes;
3276 vhc->unmap_hptes = spapr_unmap_hptes;
3277 vhc->store_hpte = spapr_store_hpte;
3278 vhc->get_patbe = spapr_get_patbe;
3279 xic->ics_get = spapr_ics_get;
3280 xic->ics_resend = spapr_ics_resend;
3281 xic->icp_get = spapr_icp_get;
3282 ispc->print_info = spapr_pic_print_info;
3283 /* Force NUMA node memory size to be a multiple of
3284 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity
3285 * in which LMBs are represented and hot-added
3286 */
3287 mc->numa_mem_align_shift = 28;
3288 }
3289
3290 static const TypeInfo spapr_machine_info = {
3291 .name = TYPE_SPAPR_MACHINE,
3292 .parent = TYPE_MACHINE,
3293 .abstract = true,
3294 .instance_size = sizeof(sPAPRMachineState),
3295 .instance_init = spapr_machine_initfn,
3296 .instance_finalize = spapr_machine_finalizefn,
3297 .class_size = sizeof(sPAPRMachineClass),
3298 .class_init = spapr_machine_class_init,
3299 .interfaces = (InterfaceInfo[]) {
3300 { TYPE_FW_PATH_PROVIDER },
3301 { TYPE_NMI },
3302 { TYPE_HOTPLUG_HANDLER },
3303 { TYPE_PPC_VIRTUAL_HYPERVISOR },
3304 { TYPE_XICS_FABRIC },
3305 { TYPE_INTERRUPT_STATS_PROVIDER },
3306 { }
3307 },
3308 };
3309
3310 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
3311 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
3312 void *data) \
3313 { \
3314 MachineClass *mc = MACHINE_CLASS(oc); \
3315 spapr_machine_##suffix##_class_options(mc); \
3316 if (latest) { \
3317 mc->alias = "pseries"; \
3318 mc->is_default = 1; \
3319 } \
3320 } \
3321 static void spapr_machine_##suffix##_instance_init(Object *obj) \
3322 { \
3323 MachineState *machine = MACHINE(obj); \
3324 spapr_machine_##suffix##_instance_options(machine); \
3325 } \
3326 static const TypeInfo spapr_machine_##suffix##_info = { \
3327 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
3328 .parent = TYPE_SPAPR_MACHINE, \
3329 .class_init = spapr_machine_##suffix##_class_init, \
3330 .instance_init = spapr_machine_##suffix##_instance_init, \
3331 }; \
3332 static void spapr_machine_register_##suffix(void) \
3333 { \
3334 type_register(&spapr_machine_##suffix##_info); \
3335 } \
3336 type_init(spapr_machine_register_##suffix)
3337
3338 /*
3339 * pseries-2.10
3340 */
3341 static void spapr_machine_2_10_instance_options(MachineState *machine)
3342 {
3343 }
3344
3345 static void spapr_machine_2_10_class_options(MachineClass *mc)
3346 {
3347 /* Defaults for the latest behaviour inherited from the base class */
3348 }
3349
3350 DEFINE_SPAPR_MACHINE(2_10, "2.10", true);
3351
3352 /*
3353 * pseries-2.9
3354 */
3355 #define SPAPR_COMPAT_2_9 \
3356 HW_COMPAT_2_9
3357
3358 static void spapr_machine_2_9_instance_options(MachineState *machine)
3359 {
3360 spapr_machine_2_10_instance_options(machine);
3361 }
3362
3363 static void spapr_machine_2_9_class_options(MachineClass *mc)
3364 {
3365 spapr_machine_2_10_class_options(mc);
3366 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9);
3367 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram;
3368 }
3369
3370 DEFINE_SPAPR_MACHINE(2_9, "2.9", false);
3371
3372 /*
3373 * pseries-2.8
3374 */
3375 #define SPAPR_COMPAT_2_8 \
3376 HW_COMPAT_2_8 \
3377 { \
3378 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3379 .property = "pcie-extended-configuration-space", \
3380 .value = "off", \
3381 },
3382
3383 static void spapr_machine_2_8_instance_options(MachineState *machine)
3384 {
3385 spapr_machine_2_9_instance_options(machine);
3386 }
3387
3388 static void spapr_machine_2_8_class_options(MachineClass *mc)
3389 {
3390 spapr_machine_2_9_class_options(mc);
3391 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8);
3392 mc->numa_mem_align_shift = 23;
3393 }
3394
3395 DEFINE_SPAPR_MACHINE(2_8, "2.8", false);
3396
3397 /*
3398 * pseries-2.7
3399 */
3400 #define SPAPR_COMPAT_2_7 \
3401 HW_COMPAT_2_7 \
3402 { \
3403 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3404 .property = "mem_win_size", \
3405 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\
3406 }, \
3407 { \
3408 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3409 .property = "mem64_win_size", \
3410 .value = "0", \
3411 }, \
3412 { \
3413 .driver = TYPE_POWERPC_CPU, \
3414 .property = "pre-2.8-migration", \
3415 .value = "on", \
3416 }, \
3417 { \
3418 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3419 .property = "pre-2.8-migration", \
3420 .value = "on", \
3421 },
3422
3423 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index,
3424 uint64_t *buid, hwaddr *pio,
3425 hwaddr *mmio32, hwaddr *mmio64,
3426 unsigned n_dma, uint32_t *liobns, Error **errp)
3427 {
3428 /* Legacy PHB placement for pseries-2.7 and earlier machine types */
3429 const uint64_t base_buid = 0x800000020000000ULL;
3430 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */
3431 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */
3432 const hwaddr pio_offset = 0x80000000; /* 2 GiB */
3433 const uint32_t max_index = 255;
3434 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */
3435
3436 uint64_t ram_top = MACHINE(spapr)->ram_size;
3437 hwaddr phb0_base, phb_base;
3438 int i;
3439
3440 /* Do we have hotpluggable memory? */
3441 if (MACHINE(spapr)->maxram_size > ram_top) {
3442 /* Can't just use maxram_size, because there may be an
3443 * alignment gap between normal and hotpluggable memory
3444 * regions */
3445 ram_top = spapr->hotplug_memory.base +
3446 memory_region_size(&spapr->hotplug_memory.mr);
3447 }
3448
3449 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment);
3450
3451 if (index > max_index) {
3452 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)",
3453 max_index);
3454 return;
3455 }
3456
3457 *buid = base_buid + index;
3458 for (i = 0; i < n_dma; ++i) {
3459 liobns[i] = SPAPR_PCI_LIOBN(index, i);
3460 }
3461
3462 phb_base = phb0_base + index * phb_spacing;
3463 *pio = phb_base + pio_offset;
3464 *mmio32 = phb_base + mmio_offset;
3465 /*
3466 * We don't set the 64-bit MMIO window, relying on the PHB's
3467 * fallback behaviour of automatically splitting a large "32-bit"
3468 * window into contiguous 32-bit and 64-bit windows
3469 */
3470 }
3471
3472 static void spapr_machine_2_7_instance_options(MachineState *machine)
3473 {
3474 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
3475
3476 spapr_machine_2_8_instance_options(machine);
3477 spapr->use_hotplug_event_source = false;
3478 }
3479
3480 static void spapr_machine_2_7_class_options(MachineClass *mc)
3481 {
3482 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3483
3484 spapr_machine_2_8_class_options(mc);
3485 smc->tcg_default_cpu = "POWER7";
3486 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7);
3487 smc->phb_placement = phb_placement_2_7;
3488 }
3489
3490 DEFINE_SPAPR_MACHINE(2_7, "2.7", false);
3491
3492 /*
3493 * pseries-2.6
3494 */
3495 #define SPAPR_COMPAT_2_6 \
3496 HW_COMPAT_2_6 \
3497 { \
3498 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
3499 .property = "ddw",\
3500 .value = stringify(off),\
3501 },
3502
3503 static void spapr_machine_2_6_instance_options(MachineState *machine)
3504 {
3505 spapr_machine_2_7_instance_options(machine);
3506 }
3507
3508 static void spapr_machine_2_6_class_options(MachineClass *mc)
3509 {
3510 spapr_machine_2_7_class_options(mc);
3511 mc->has_hotpluggable_cpus = false;
3512 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6);
3513 }
3514
3515 DEFINE_SPAPR_MACHINE(2_6, "2.6", false);
3516
3517 /*
3518 * pseries-2.5
3519 */
3520 #define SPAPR_COMPAT_2_5 \
3521 HW_COMPAT_2_5 \
3522 { \
3523 .driver = "spapr-vlan", \
3524 .property = "use-rx-buffer-pools", \
3525 .value = "off", \
3526 },
3527
3528 static void spapr_machine_2_5_instance_options(MachineState *machine)
3529 {
3530 spapr_machine_2_6_instance_options(machine);
3531 }
3532
3533 static void spapr_machine_2_5_class_options(MachineClass *mc)
3534 {
3535 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3536
3537 spapr_machine_2_6_class_options(mc);
3538 smc->use_ohci_by_default = true;
3539 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5);
3540 }
3541
3542 DEFINE_SPAPR_MACHINE(2_5, "2.5", false);
3543
3544 /*
3545 * pseries-2.4
3546 */
3547 #define SPAPR_COMPAT_2_4 \
3548 HW_COMPAT_2_4
3549
3550 static void spapr_machine_2_4_instance_options(MachineState *machine)
3551 {
3552 spapr_machine_2_5_instance_options(machine);
3553 }
3554
3555 static void spapr_machine_2_4_class_options(MachineClass *mc)
3556 {
3557 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3558
3559 spapr_machine_2_5_class_options(mc);
3560 smc->dr_lmb_enabled = false;
3561 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4);
3562 }
3563
3564 DEFINE_SPAPR_MACHINE(2_4, "2.4", false);
3565
3566 /*
3567 * pseries-2.3
3568 */
3569 #define SPAPR_COMPAT_2_3 \
3570 HW_COMPAT_2_3 \
3571 {\
3572 .driver = "spapr-pci-host-bridge",\
3573 .property = "dynamic-reconfiguration",\
3574 .value = "off",\
3575 },
3576
3577 static void spapr_machine_2_3_instance_options(MachineState *machine)
3578 {
3579 spapr_machine_2_4_instance_options(machine);
3580 savevm_skip_section_footers();
3581 global_state_set_optional();
3582 savevm_skip_configuration();
3583 }
3584
3585 static void spapr_machine_2_3_class_options(MachineClass *mc)
3586 {
3587 spapr_machine_2_4_class_options(mc);
3588 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3);
3589 }
3590 DEFINE_SPAPR_MACHINE(2_3, "2.3", false);
3591
3592 /*
3593 * pseries-2.2
3594 */
3595
3596 #define SPAPR_COMPAT_2_2 \
3597 HW_COMPAT_2_2 \
3598 {\
3599 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
3600 .property = "mem_win_size",\
3601 .value = "0x20000000",\
3602 },
3603
3604 static void spapr_machine_2_2_instance_options(MachineState *machine)
3605 {
3606 spapr_machine_2_3_instance_options(machine);
3607 machine->suppress_vmdesc = true;
3608 }
3609
3610 static void spapr_machine_2_2_class_options(MachineClass *mc)
3611 {
3612 spapr_machine_2_3_class_options(mc);
3613 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2);
3614 }
3615 DEFINE_SPAPR_MACHINE(2_2, "2.2", false);
3616
3617 /*
3618 * pseries-2.1
3619 */
3620 #define SPAPR_COMPAT_2_1 \
3621 HW_COMPAT_2_1
3622
3623 static void spapr_machine_2_1_instance_options(MachineState *machine)
3624 {
3625 spapr_machine_2_2_instance_options(machine);
3626 }
3627
3628 static void spapr_machine_2_1_class_options(MachineClass *mc)
3629 {
3630 spapr_machine_2_2_class_options(mc);
3631 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1);
3632 }
3633 DEFINE_SPAPR_MACHINE(2_1, "2.1", false);
3634
3635 static void spapr_machine_register_types(void)
3636 {
3637 type_register_static(&spapr_machine_info);
3638 }
3639
3640 type_init(spapr_machine_register_types)
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