2 * QEMU PowerPC 440 embedded processors emulation
4 * Copyright (c) 2012 François Revol
5 * Copyright (c) 2016-2019 BALATON Zoltan
7 * This work is licensed under the GNU GPL license version 2 or later.
11 #include "qemu/osdep.h"
12 #include "qemu/units.h"
13 #include "qapi/error.h"
16 #include "hw/ppc/ppc4xx.h"
17 #include "hw/pci-host/ppc4xx.h"
18 #include "hw/qdev-properties.h"
19 #include "hw/pci/pci.h"
20 #include "sysemu/reset.h"
24 /*****************************************************************************/
25 /* L2 Cache as SRAM */
28 DCR_L2CACHE_BASE
= 0x30,
29 DCR_L2CACHE_CFG
= DCR_L2CACHE_BASE
,
37 DCR_L2CACHE_END
= DCR_L2CACHE_SNP1
,
40 /* base is 460ex-specific, cf. U-Boot, ppc4xx-isram.h */
42 DCR_ISRAM0_BASE
= 0x20,
43 DCR_ISRAM0_SB0CR
= DCR_ISRAM0_BASE
,
54 DCR_ISRAM0_END
= DCR_ISRAM0_DPC
58 DCR_ISRAM1_BASE
= 0xb0,
59 DCR_ISRAM1_SB0CR
= DCR_ISRAM1_BASE
,
61 DCR_ISRAM1_BEAR
= DCR_ISRAM1_BASE
+ 0x04,
68 DCR_ISRAM1_END
= DCR_ISRAM1_DPC
71 typedef struct ppc4xx_l2sram_t
{
77 static uint32_t dcr_read_l2sram(void *opaque
, int dcrn
)
79 ppc4xx_l2sram_t
*l2sram
= opaque
;
85 case DCR_L2CACHE_ADDR
:
86 case DCR_L2CACHE_DATA
:
87 case DCR_L2CACHE_STAT
:
88 case DCR_L2CACHE_CVER
:
89 case DCR_L2CACHE_SNP0
:
90 case DCR_L2CACHE_SNP1
:
91 ret
= l2sram
->l2cache
[dcrn
- DCR_L2CACHE_BASE
];
94 case DCR_ISRAM0_SB0CR
:
95 case DCR_ISRAM0_SB1CR
:
96 case DCR_ISRAM0_SB2CR
:
97 case DCR_ISRAM0_SB3CR
:
99 case DCR_ISRAM0_BESR0
:
100 case DCR_ISRAM0_BESR1
:
101 case DCR_ISRAM0_PMEG
:
103 case DCR_ISRAM0_REVID
:
105 ret
= l2sram
->isram0
[dcrn
- DCR_ISRAM0_BASE
];
115 static void dcr_write_l2sram(void *opaque
, int dcrn
, uint32_t val
)
117 /*ppc4xx_l2sram_t *l2sram = opaque;*/
118 /* FIXME: Actually handle L2 cache mapping */
121 case DCR_L2CACHE_CFG
:
122 case DCR_L2CACHE_CMD
:
123 case DCR_L2CACHE_ADDR
:
124 case DCR_L2CACHE_DATA
:
125 case DCR_L2CACHE_STAT
:
126 case DCR_L2CACHE_CVER
:
127 case DCR_L2CACHE_SNP0
:
128 case DCR_L2CACHE_SNP1
:
129 /*l2sram->l2cache[dcrn - DCR_L2CACHE_BASE] = val;*/
132 case DCR_ISRAM0_SB0CR
:
133 case DCR_ISRAM0_SB1CR
:
134 case DCR_ISRAM0_SB2CR
:
135 case DCR_ISRAM0_SB3CR
:
136 case DCR_ISRAM0_BEAR
:
137 case DCR_ISRAM0_BESR0
:
138 case DCR_ISRAM0_BESR1
:
139 case DCR_ISRAM0_PMEG
:
141 case DCR_ISRAM0_REVID
:
143 /*l2sram->isram0[dcrn - DCR_L2CACHE_BASE] = val;*/
146 case DCR_ISRAM1_SB0CR
:
147 case DCR_ISRAM1_BEAR
:
148 case DCR_ISRAM1_BESR0
:
149 case DCR_ISRAM1_BESR1
:
150 case DCR_ISRAM1_PMEG
:
152 case DCR_ISRAM1_REVID
:
154 /*l2sram->isram1[dcrn - DCR_L2CACHE_BASE] = val;*/
159 static void l2sram_reset(void *opaque
)
161 ppc4xx_l2sram_t
*l2sram
= opaque
;
163 memset(l2sram
->l2cache
, 0, sizeof(l2sram
->l2cache
));
164 l2sram
->l2cache
[DCR_L2CACHE_STAT
- DCR_L2CACHE_BASE
] = 0x80000000;
165 memset(l2sram
->isram0
, 0, sizeof(l2sram
->isram0
));
168 void ppc4xx_l2sram_init(CPUPPCState
*env
)
170 ppc4xx_l2sram_t
*l2sram
;
172 l2sram
= g_malloc0(sizeof(*l2sram
));
173 /* XXX: Size is 4*64kB for 460ex, cf. U-Boot, ppc4xx-isram.h */
174 memory_region_init_ram(&l2sram
->bank
[0], NULL
, "ppc4xx.l2sram_bank0",
175 64 * KiB
, &error_abort
);
176 memory_region_init_ram(&l2sram
->bank
[1], NULL
, "ppc4xx.l2sram_bank1",
177 64 * KiB
, &error_abort
);
178 memory_region_init_ram(&l2sram
->bank
[2], NULL
, "ppc4xx.l2sram_bank2",
179 64 * KiB
, &error_abort
);
180 memory_region_init_ram(&l2sram
->bank
[3], NULL
, "ppc4xx.l2sram_bank3",
181 64 * KiB
, &error_abort
);
182 qemu_register_reset(&l2sram_reset
, l2sram
);
183 ppc_dcr_register(env
, DCR_L2CACHE_CFG
,
184 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
185 ppc_dcr_register(env
, DCR_L2CACHE_CMD
,
186 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
187 ppc_dcr_register(env
, DCR_L2CACHE_ADDR
,
188 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
189 ppc_dcr_register(env
, DCR_L2CACHE_DATA
,
190 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
191 ppc_dcr_register(env
, DCR_L2CACHE_STAT
,
192 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
193 ppc_dcr_register(env
, DCR_L2CACHE_CVER
,
194 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
195 ppc_dcr_register(env
, DCR_L2CACHE_SNP0
,
196 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
197 ppc_dcr_register(env
, DCR_L2CACHE_SNP1
,
198 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
200 ppc_dcr_register(env
, DCR_ISRAM0_SB0CR
,
201 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
202 ppc_dcr_register(env
, DCR_ISRAM0_SB1CR
,
203 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
204 ppc_dcr_register(env
, DCR_ISRAM0_SB2CR
,
205 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
206 ppc_dcr_register(env
, DCR_ISRAM0_SB3CR
,
207 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
208 ppc_dcr_register(env
, DCR_ISRAM0_PMEG
,
209 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
210 ppc_dcr_register(env
, DCR_ISRAM0_DPC
,
211 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
213 ppc_dcr_register(env
, DCR_ISRAM1_SB0CR
,
214 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
215 ppc_dcr_register(env
, DCR_ISRAM1_PMEG
,
216 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
217 ppc_dcr_register(env
, DCR_ISRAM1_DPC
,
218 l2sram
, &dcr_read_l2sram
, &dcr_write_l2sram
);
221 /*****************************************************************************/
222 /* Clocking Power on Reset */
234 typedef struct ppc4xx_cpr_t
{
238 static uint32_t dcr_read_cpr(void *opaque
, int dcrn
)
240 ppc4xx_cpr_t
*cpr
= opaque
;
250 ret
= (0xb5 << 24) | (1 << 16) | (9 << 8);
273 static void dcr_write_cpr(void *opaque
, int dcrn
, uint32_t val
)
275 ppc4xx_cpr_t
*cpr
= opaque
;
288 static void ppc4xx_cpr_reset(void *opaque
)
290 ppc4xx_cpr_t
*cpr
= opaque
;
295 void ppc4xx_cpr_init(CPUPPCState
*env
)
299 cpr
= g_malloc0(sizeof(*cpr
));
300 ppc_dcr_register(env
, CPR0_CFGADDR
, cpr
, &dcr_read_cpr
, &dcr_write_cpr
);
301 ppc_dcr_register(env
, CPR0_CFGDATA
, cpr
, &dcr_read_cpr
, &dcr_write_cpr
);
302 qemu_register_reset(ppc4xx_cpr_reset
, cpr
);
305 /*****************************************************************************/
307 typedef struct ppc4xx_sdr_t ppc4xx_sdr_t
;
308 struct ppc4xx_sdr_t
{
313 SDR0_CFGADDR
= 0x00e,
329 PESDR0_RSTSTA
= 0x310,
333 PESDR1_RSTSTA
= 0x365,
336 static uint32_t dcr_read_sdr(void *opaque
, int dcrn
)
338 ppc4xx_sdr_t
*sdr
= opaque
;
348 ret
= (0xb5 << 8) | (1 << 4) | 9;
351 ret
= (5 << 29) | (2 << 26) | (1 << 24);
354 ret
= 1 << 20; /* No Security/Kasumi support */
357 ret
= SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1
;
361 ret
= (1 << 24) | (1 << 16);
365 ret
= (1 << 16) | (1 << 12);
386 static void dcr_write_sdr(void *opaque
, int dcrn
, uint32_t val
)
388 ppc4xx_sdr_t
*sdr
= opaque
;
396 case 0x00: /* B0CR */
407 static void sdr_reset(void *opaque
)
409 ppc4xx_sdr_t
*sdr
= opaque
;
414 void ppc4xx_sdr_init(CPUPPCState
*env
)
418 sdr
= g_malloc0(sizeof(*sdr
));
419 qemu_register_reset(&sdr_reset
, sdr
);
420 ppc_dcr_register(env
, SDR0_CFGADDR
,
421 sdr
, &dcr_read_sdr
, &dcr_write_sdr
);
422 ppc_dcr_register(env
, SDR0_CFGDATA
,
423 sdr
, &dcr_read_sdr
, &dcr_write_sdr
);
424 ppc_dcr_register(env
, SDR0_102
,
425 sdr
, &dcr_read_sdr
, &dcr_write_sdr
);
426 ppc_dcr_register(env
, SDR0_103
,
427 sdr
, &dcr_read_sdr
, &dcr_write_sdr
);
428 ppc_dcr_register(env
, SDR0_128
,
429 sdr
, &dcr_read_sdr
, &dcr_write_sdr
);
430 ppc_dcr_register(env
, SDR0_USB0
,
431 sdr
, &dcr_read_sdr
, &dcr_write_sdr
);
434 /*****************************************************************************/
435 /* PLB to AHB bridge */
441 typedef struct ppc4xx_ahb_t
{
446 static uint32_t dcr_read_ahb(void *opaque
, int dcrn
)
448 ppc4xx_ahb_t
*ahb
= opaque
;
465 static void dcr_write_ahb(void *opaque
, int dcrn
, uint32_t val
)
467 ppc4xx_ahb_t
*ahb
= opaque
;
479 static void ppc4xx_ahb_reset(void *opaque
)
481 ppc4xx_ahb_t
*ahb
= opaque
;
488 void ppc4xx_ahb_init(CPUPPCState
*env
)
492 ahb
= g_malloc0(sizeof(*ahb
));
493 ppc_dcr_register(env
, AHB_TOP
, ahb
, &dcr_read_ahb
, &dcr_write_ahb
);
494 ppc_dcr_register(env
, AHB_BOT
, ahb
, &dcr_read_ahb
, &dcr_write_ahb
);
495 qemu_register_reset(ppc4xx_ahb_reset
, ahb
);
498 /*****************************************************************************/
501 #define DMA0_CR_CE (1 << 31)
502 #define DMA0_CR_PW (1 << 26 | 1 << 25)
503 #define DMA0_CR_DAI (1 << 24)
504 #define DMA0_CR_SAI (1 << 23)
505 #define DMA0_CR_DEC (1 << 2)
537 static uint32_t dcr_read_dma(void *opaque
, int dcrn
)
539 PPC4xxDmaState
*dma
= opaque
;
541 int addr
= dcrn
- dma
->base
;
548 val
= dma
->ch
[chnl
].cr
;
551 val
= dma
->ch
[chnl
].ct
;
554 val
= dma
->ch
[chnl
].sa
>> 32;
557 val
= dma
->ch
[chnl
].sa
;
560 val
= dma
->ch
[chnl
].da
>> 32;
563 val
= dma
->ch
[chnl
].da
;
566 val
= dma
->ch
[chnl
].sg
>> 32;
569 val
= dma
->ch
[chnl
].sg
;
577 qemu_log_mask(LOG_UNIMP
, "%s: unimplemented register %x (%d, %x)\n",
578 __func__
, dcrn
, chnl
, addr
);
584 static void dcr_write_dma(void *opaque
, int dcrn
, uint32_t val
)
586 PPC4xxDmaState
*dma
= opaque
;
587 int addr
= dcrn
- dma
->base
;
594 dma
->ch
[chnl
].cr
= val
;
595 if (val
& DMA0_CR_CE
) {
596 int count
= dma
->ch
[chnl
].ct
& 0xffff;
599 int width
, i
, sidx
, didx
;
600 uint8_t *rptr
, *wptr
;
605 width
= 1 << ((val
& DMA0_CR_PW
) >> 25);
606 xferlen
= count
* width
;
607 wlen
= rlen
= xferlen
;
608 rptr
= cpu_physical_memory_map(dma
->ch
[chnl
].sa
, &rlen
,
610 wptr
= cpu_physical_memory_map(dma
->ch
[chnl
].da
, &wlen
,
612 if (rptr
&& rlen
== xferlen
&& wptr
&& wlen
== xferlen
) {
613 if (!(val
& DMA0_CR_DEC
) &&
614 val
& DMA0_CR_SAI
&& val
& DMA0_CR_DAI
) {
615 /* optimise common case */
616 memmove(wptr
, rptr
, count
* width
);
617 sidx
= didx
= count
* width
;
619 /* do it the slow way */
620 for (sidx
= didx
= i
= 0; i
< count
; i
++) {
621 uint64_t v
= ldn_le_p(rptr
+ sidx
, width
);
622 stn_le_p(wptr
+ didx
, width
, v
);
623 if (val
& DMA0_CR_SAI
) {
626 if (val
& DMA0_CR_DAI
) {
633 cpu_physical_memory_unmap(wptr
, wlen
, 1, didx
);
636 cpu_physical_memory_unmap(rptr
, rlen
, 0, sidx
);
642 dma
->ch
[chnl
].ct
= val
;
645 dma
->ch
[chnl
].sa
&= 0xffffffffULL
;
646 dma
->ch
[chnl
].sa
|= (uint64_t)val
<< 32;
649 dma
->ch
[chnl
].sa
&= 0xffffffff00000000ULL
;
650 dma
->ch
[chnl
].sa
|= val
;
653 dma
->ch
[chnl
].da
&= 0xffffffffULL
;
654 dma
->ch
[chnl
].da
|= (uint64_t)val
<< 32;
657 dma
->ch
[chnl
].da
&= 0xffffffff00000000ULL
;
658 dma
->ch
[chnl
].da
|= val
;
661 dma
->ch
[chnl
].sg
&= 0xffffffffULL
;
662 dma
->ch
[chnl
].sg
|= (uint64_t)val
<< 32;
665 dma
->ch
[chnl
].sg
&= 0xffffffff00000000ULL
;
666 dma
->ch
[chnl
].sg
|= val
;
674 qemu_log_mask(LOG_UNIMP
, "%s: unimplemented register %x (%d, %x)\n",
675 __func__
, dcrn
, chnl
, addr
);
679 static void ppc4xx_dma_reset(void *opaque
)
681 PPC4xxDmaState
*dma
= opaque
;
682 int dma_base
= dma
->base
;
684 memset(dma
, 0, sizeof(*dma
));
685 dma
->base
= dma_base
;
688 void ppc4xx_dma_init(CPUPPCState
*env
, int dcr_base
)
693 dma
= g_malloc0(sizeof(*dma
));
694 dma
->base
= dcr_base
;
695 qemu_register_reset(&ppc4xx_dma_reset
, dma
);
696 for (i
= 0; i
< 4; i
++) {
697 ppc_dcr_register(env
, dcr_base
+ i
* 8 + DMA0_CR
,
698 dma
, &dcr_read_dma
, &dcr_write_dma
);
699 ppc_dcr_register(env
, dcr_base
+ i
* 8 + DMA0_CT
,
700 dma
, &dcr_read_dma
, &dcr_write_dma
);
701 ppc_dcr_register(env
, dcr_base
+ i
* 8 + DMA0_SAH
,
702 dma
, &dcr_read_dma
, &dcr_write_dma
);
703 ppc_dcr_register(env
, dcr_base
+ i
* 8 + DMA0_SAL
,
704 dma
, &dcr_read_dma
, &dcr_write_dma
);
705 ppc_dcr_register(env
, dcr_base
+ i
* 8 + DMA0_DAH
,
706 dma
, &dcr_read_dma
, &dcr_write_dma
);
707 ppc_dcr_register(env
, dcr_base
+ i
* 8 + DMA0_DAL
,
708 dma
, &dcr_read_dma
, &dcr_write_dma
);
709 ppc_dcr_register(env
, dcr_base
+ i
* 8 + DMA0_SGH
,
710 dma
, &dcr_read_dma
, &dcr_write_dma
);
711 ppc_dcr_register(env
, dcr_base
+ i
* 8 + DMA0_SGL
,
712 dma
, &dcr_read_dma
, &dcr_write_dma
);
714 ppc_dcr_register(env
, dcr_base
+ DMA0_SR
,
715 dma
, &dcr_read_dma
, &dcr_write_dma
);
716 ppc_dcr_register(env
, dcr_base
+ DMA0_SGC
,
717 dma
, &dcr_read_dma
, &dcr_write_dma
);
718 ppc_dcr_register(env
, dcr_base
+ DMA0_SLP
,
719 dma
, &dcr_read_dma
, &dcr_write_dma
);
720 ppc_dcr_register(env
, dcr_base
+ DMA0_POL
,
721 dma
, &dcr_read_dma
, &dcr_write_dma
);
724 /*****************************************************************************/
725 /* PCI Express controller */
727 * FIXME: This is not complete and does not work, only implemented partially
728 * to allow firmware and guests to find an empty bus. Cards should use PCI.
730 #include "hw/pci/pcie_host.h"
732 OBJECT_DECLARE_SIMPLE_TYPE(PPC460EXPCIEState
, PPC460EX_PCIE_HOST
)
734 struct PPC460EXPCIEState
{
735 PCIExpressHost parent_obj
;
786 static uint32_t dcr_read_pcie(void *opaque
, int dcrn
)
788 PPC460EXPCIEState
*s
= opaque
;
791 switch (dcrn
- s
->dcrn_base
) {
793 ret
= s
->cfg_base
>> 32;
802 ret
= s
->msg_base
>> 32;
811 ret
= s
->omr1_base
>> 32;
817 ret
= s
->omr1_mask
>> 32;
823 ret
= s
->omr2_base
>> 32;
829 ret
= s
->omr2_mask
>> 32;
835 ret
= s
->omr3_base
>> 32;
841 ret
= s
->omr3_mask
>> 32;
847 ret
= s
->reg_base
>> 32;
866 static void dcr_write_pcie(void *opaque
, int dcrn
, uint32_t val
)
868 PPC460EXPCIEState
*s
= opaque
;
871 switch (dcrn
- s
->dcrn_base
) {
873 s
->cfg_base
= ((uint64_t)val
<< 32) | (s
->cfg_base
& 0xffffffff);
876 s
->cfg_base
= (s
->cfg_base
& 0xffffffff00000000ULL
) | val
;
880 size
= ~(val
& 0xfffffffe) + 1;
882 * Firmware sets this register to E0000001. Why we are not sure,
883 * but the current guess is anything above PCIE_MMCFG_SIZE_MAX is
886 if (size
> PCIE_MMCFG_SIZE_MAX
) {
887 size
= PCIE_MMCFG_SIZE_MAX
;
889 pcie_host_mmcfg_update(PCIE_HOST_BRIDGE(s
), val
& 1, s
->cfg_base
, size
);
892 s
->msg_base
= ((uint64_t)val
<< 32) | (s
->msg_base
& 0xffffffff);
895 s
->msg_base
= (s
->msg_base
& 0xffffffff00000000ULL
) | val
;
901 s
->omr1_base
= ((uint64_t)val
<< 32) | (s
->omr1_base
& 0xffffffff);
904 s
->omr1_base
= (s
->omr1_base
& 0xffffffff00000000ULL
) | val
;
907 s
->omr1_mask
= ((uint64_t)val
<< 32) | (s
->omr1_mask
& 0xffffffff);
910 s
->omr1_mask
= (s
->omr1_mask
& 0xffffffff00000000ULL
) | val
;
913 s
->omr2_base
= ((uint64_t)val
<< 32) | (s
->omr2_base
& 0xffffffff);
916 s
->omr2_base
= (s
->omr2_base
& 0xffffffff00000000ULL
) | val
;
919 s
->omr2_mask
= ((uint64_t)val
<< 32) | (s
->omr2_mask
& 0xffffffff);
922 s
->omr2_mask
= (s
->omr2_mask
& 0xffffffff00000000ULL
) | val
;
925 s
->omr3_base
= ((uint64_t)val
<< 32) | (s
->omr3_base
& 0xffffffff);
928 s
->omr3_base
= (s
->omr3_base
& 0xffffffff00000000ULL
) | val
;
931 s
->omr3_mask
= ((uint64_t)val
<< 32) | (s
->omr3_mask
& 0xffffffff);
934 s
->omr3_mask
= (s
->omr3_mask
& 0xffffffff00000000ULL
) | val
;
937 s
->reg_base
= ((uint64_t)val
<< 32) | (s
->reg_base
& 0xffffffff);
940 s
->reg_base
= (s
->reg_base
& 0xffffffff00000000ULL
) | val
;
944 /* FIXME: how is size encoded? */
945 size
= (val
== 0x7001 ? 4096 : ~(val
& 0xfffffffe) + 1);
956 static void ppc460ex_set_irq(void *opaque
, int irq_num
, int level
)
958 PPC460EXPCIEState
*s
= opaque
;
959 qemu_set_irq(s
->irq
[irq_num
], level
);
962 #define PPC440_PCIE_DCR(s, dcrn) \
963 ppc_dcr_register(&(s)->cpu->env, (s)->dcrn_base + (dcrn), (s), \
964 &dcr_read_pcie, &dcr_write_pcie)
967 static void ppc460ex_pcie_register_dcrs(PPC460EXPCIEState
*s
)
969 PPC440_PCIE_DCR(s
, PEGPL_CFGBAH
);
970 PPC440_PCIE_DCR(s
, PEGPL_CFGBAL
);
971 PPC440_PCIE_DCR(s
, PEGPL_CFGMSK
);
972 PPC440_PCIE_DCR(s
, PEGPL_MSGBAH
);
973 PPC440_PCIE_DCR(s
, PEGPL_MSGBAL
);
974 PPC440_PCIE_DCR(s
, PEGPL_MSGMSK
);
975 PPC440_PCIE_DCR(s
, PEGPL_OMR1BAH
);
976 PPC440_PCIE_DCR(s
, PEGPL_OMR1BAL
);
977 PPC440_PCIE_DCR(s
, PEGPL_OMR1MSKH
);
978 PPC440_PCIE_DCR(s
, PEGPL_OMR1MSKL
);
979 PPC440_PCIE_DCR(s
, PEGPL_OMR2BAH
);
980 PPC440_PCIE_DCR(s
, PEGPL_OMR2BAL
);
981 PPC440_PCIE_DCR(s
, PEGPL_OMR2MSKH
);
982 PPC440_PCIE_DCR(s
, PEGPL_OMR2MSKL
);
983 PPC440_PCIE_DCR(s
, PEGPL_OMR3BAH
);
984 PPC440_PCIE_DCR(s
, PEGPL_OMR3BAL
);
985 PPC440_PCIE_DCR(s
, PEGPL_OMR3MSKH
);
986 PPC440_PCIE_DCR(s
, PEGPL_OMR3MSKL
);
987 PPC440_PCIE_DCR(s
, PEGPL_REGBAH
);
988 PPC440_PCIE_DCR(s
, PEGPL_REGBAL
);
989 PPC440_PCIE_DCR(s
, PEGPL_REGMSK
);
990 PPC440_PCIE_DCR(s
, PEGPL_SPECIAL
);
991 PPC440_PCIE_DCR(s
, PEGPL_CFG
);
994 static void ppc460ex_pcie_realize(DeviceState
*dev
, Error
**errp
)
996 PPC460EXPCIEState
*s
= PPC460EX_PCIE_HOST(dev
);
997 PCIHostState
*pci
= PCI_HOST_BRIDGE(dev
);
1002 error_setg(errp
, "cpu link property must be set");
1005 if (s
->num
< 0 || s
->dcrn_base
< 0) {
1006 error_setg(errp
, "busnum and dcrn-base properties must be set");
1009 snprintf(buf
, sizeof(buf
), "pcie%d-mem", s
->num
);
1010 memory_region_init(&s
->busmem
, OBJECT(s
), buf
, UINT64_MAX
);
1011 snprintf(buf
, sizeof(buf
), "pcie%d-io", s
->num
);
1012 memory_region_init(&s
->iomem
, OBJECT(s
), buf
, 64 * KiB
);
1013 for (i
= 0; i
< 4; i
++) {
1014 sysbus_init_irq(SYS_BUS_DEVICE(dev
), &s
->irq
[i
]);
1016 snprintf(buf
, sizeof(buf
), "pcie.%d", s
->num
);
1017 pci
->bus
= pci_register_root_bus(DEVICE(s
), buf
, ppc460ex_set_irq
,
1018 pci_swizzle_map_irq_fn
, s
, &s
->busmem
,
1019 &s
->iomem
, 0, 4, TYPE_PCIE_BUS
);
1020 ppc460ex_pcie_register_dcrs(s
);
1023 static Property ppc460ex_pcie_props
[] = {
1024 DEFINE_PROP_INT32("busnum", PPC460EXPCIEState
, num
, -1),
1025 DEFINE_PROP_INT32("dcrn-base", PPC460EXPCIEState
, dcrn_base
, -1),
1026 DEFINE_PROP_LINK("cpu", PPC460EXPCIEState
, cpu
, TYPE_POWERPC_CPU
,
1028 DEFINE_PROP_END_OF_LIST(),
1031 static void ppc460ex_pcie_class_init(ObjectClass
*klass
, void *data
)
1033 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1035 set_bit(DEVICE_CATEGORY_BRIDGE
, dc
->categories
);
1036 dc
->realize
= ppc460ex_pcie_realize
;
1037 device_class_set_props(dc
, ppc460ex_pcie_props
);
1038 dc
->hotpluggable
= false;
1041 static const TypeInfo ppc460ex_pcie_host_info
= {
1042 .name
= TYPE_PPC460EX_PCIE_HOST
,
1043 .parent
= TYPE_PCIE_HOST_BRIDGE
,
1044 .instance_size
= sizeof(PPC460EXPCIEState
),
1045 .class_init
= ppc460ex_pcie_class_init
,
1048 static void ppc460ex_pcie_register(void)
1050 type_register_static(&ppc460ex_pcie_host_info
);
1053 type_init(ppc460ex_pcie_register
)