2 * Nuvoton NPCM7xx System Global Control Registers.
4 * Copyright 2020 Google LLC
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 #include "qemu/osdep.h"
19 #include "hw/misc/npcm7xx_gcr.h"
20 #include "hw/qdev-properties.h"
21 #include "migration/vmstate.h"
22 #include "qapi/error.h"
23 #include "qemu/cutils.h"
25 #include "qemu/module.h"
26 #include "qemu/units.h"
30 #define NPCM7XX_GCR_MIN_DRAM_SIZE (128 * MiB)
31 #define NPCM7XX_GCR_MAX_DRAM_SIZE (2 * GiB)
33 enum NPCM7xxGCRRegisters
{
36 NPCM7XX_GCR_MFSEL1
= 0x0c / sizeof(uint32_t),
39 NPCM7XX_GCR_SPSWC
= 0x038 / sizeof(uint32_t),
42 NPCM7XX_GCR_HIFCR
= 0x050 / sizeof(uint32_t),
43 NPCM7XX_GCR_INTCR2
= 0x060 / sizeof(uint32_t),
53 NPCM7XX_GCR_DAVCLVLR
= 0x098 / sizeof(uint32_t),
55 NPCM7XX_GCR_VSINTR
= 0x0ac / sizeof(uint32_t),
57 NPCM7XX_GCR_CPBPNTR
= 0x0c4 / sizeof(uint32_t),
58 NPCM7XX_GCR_CPCTL
= 0x0d0 / sizeof(uint32_t),
62 NPCM7XX_GCR_I2CSEGSEL
,
63 NPCM7XX_GCR_I2CSEGCTL
,
66 NPCM7XX_GCR_SCRPAD
= 0x013c / sizeof(uint32_t),
67 NPCM7XX_GCR_USB1PHYCTL
,
68 NPCM7XX_GCR_USB2PHYCTL
,
72 static const uint32_t cold_reset_values
[NPCM7XX_GCR_NR_REGS
] = {
73 [NPCM7XX_GCR_PDID
] = 0x04a92750, /* Poleg A1 */
74 [NPCM7XX_GCR_MISCPE
] = 0x0000ffff,
75 [NPCM7XX_GCR_SPSWC
] = 0x00000003,
76 [NPCM7XX_GCR_INTCR
] = 0x0000035e,
77 [NPCM7XX_GCR_HIFCR
] = 0x0000004e,
78 [NPCM7XX_GCR_INTCR2
] = (1U << 19), /* DDR initialized */
79 [NPCM7XX_GCR_RESSR
] = 0x80000000,
80 [NPCM7XX_GCR_DSCNT
] = 0x000000c0,
81 [NPCM7XX_GCR_DAVCLVLR
] = 0x5a00f3cf,
82 [NPCM7XX_GCR_SCRPAD
] = 0x00000008,
83 [NPCM7XX_GCR_USB1PHYCTL
] = 0x034730e4,
84 [NPCM7XX_GCR_USB2PHYCTL
] = 0x034730e4,
87 static uint64_t npcm7xx_gcr_read(void *opaque
, hwaddr offset
, unsigned size
)
89 uint32_t reg
= offset
/ sizeof(uint32_t);
90 NPCM7xxGCRState
*s
= opaque
;
92 if (reg
>= NPCM7XX_GCR_NR_REGS
) {
93 qemu_log_mask(LOG_GUEST_ERROR
,
94 "%s: offset 0x%04" HWADDR_PRIx
" out of range\n",
99 trace_npcm7xx_gcr_read(offset
, s
->regs
[reg
]);
104 static void npcm7xx_gcr_write(void *opaque
, hwaddr offset
,
105 uint64_t v
, unsigned size
)
107 uint32_t reg
= offset
/ sizeof(uint32_t);
108 NPCM7xxGCRState
*s
= opaque
;
111 trace_npcm7xx_gcr_write(offset
, value
);
113 if (reg
>= NPCM7XX_GCR_NR_REGS
) {
114 qemu_log_mask(LOG_GUEST_ERROR
,
115 "%s: offset 0x%04" HWADDR_PRIx
" out of range\n",
121 case NPCM7XX_GCR_PDID
:
122 case NPCM7XX_GCR_PWRON
:
123 case NPCM7XX_GCR_INTSR
:
124 qemu_log_mask(LOG_GUEST_ERROR
,
125 "%s: register @ 0x%04" HWADDR_PRIx
" is read-only\n",
129 case NPCM7XX_GCR_RESSR
:
130 case NPCM7XX_GCR_CP2BST
:
131 /* Write 1 to clear */
132 value
= s
->regs
[reg
] & ~value
;
135 case NPCM7XX_GCR_RLOCKR1
:
136 case NPCM7XX_GCR_MDLR
:
138 value
|= s
->regs
[reg
];
142 s
->regs
[reg
] = value
;
145 static const struct MemoryRegionOps npcm7xx_gcr_ops
= {
146 .read
= npcm7xx_gcr_read
,
147 .write
= npcm7xx_gcr_write
,
148 .endianness
= DEVICE_LITTLE_ENDIAN
,
150 .min_access_size
= 4,
151 .max_access_size
= 4,
156 static void npcm7xx_gcr_enter_reset(Object
*obj
, ResetType type
)
158 NPCM7xxGCRState
*s
= NPCM7XX_GCR(obj
);
160 QEMU_BUILD_BUG_ON(sizeof(s
->regs
) != sizeof(cold_reset_values
));
162 memcpy(s
->regs
, cold_reset_values
, sizeof(s
->regs
));
163 s
->regs
[NPCM7XX_GCR_PWRON
] = s
->reset_pwron
;
164 s
->regs
[NPCM7XX_GCR_MDLR
] = s
->reset_mdlr
;
165 s
->regs
[NPCM7XX_GCR_INTCR3
] = s
->reset_intcr3
;
168 static void npcm7xx_gcr_realize(DeviceState
*dev
, Error
**errp
)
171 NPCM7xxGCRState
*s
= NPCM7XX_GCR(dev
);
175 obj
= object_property_get_link(OBJECT(dev
), "dram-mr", errp
);
177 error_prepend(errp
, "%s: required dram-mr link not found: ", __func__
);
180 dram_size
= memory_region_size(MEMORY_REGION(obj
));
181 if (!is_power_of_2(dram_size
) ||
182 dram_size
< NPCM7XX_GCR_MIN_DRAM_SIZE
||
183 dram_size
> NPCM7XX_GCR_MAX_DRAM_SIZE
) {
184 g_autofree
char *sz
= size_to_str(dram_size
);
185 g_autofree
char *min_sz
= size_to_str(NPCM7XX_GCR_MIN_DRAM_SIZE
);
186 g_autofree
char *max_sz
= size_to_str(NPCM7XX_GCR_MAX_DRAM_SIZE
);
187 error_setg(errp
, "%s: unsupported DRAM size %s", __func__
, sz
);
188 error_append_hint(errp
,
189 "DRAM size must be a power of two between %s and %s,"
190 " inclusive.\n", min_sz
, max_sz
);
194 /* Power-on reset value */
195 s
->reset_intcr3
= 0x00001002;
198 * The GMMAP (Graphics Memory Map) field is used by u-boot to detect the
199 * DRAM size, and is normally initialized by the boot block as part of DRAM
200 * training. However, since we don't have a complete emulation of the
201 * memory controller and try to make it look like it has already been
202 * initialized, the boot block will skip this initialization, and we need
203 * to make sure this field is set correctly up front.
205 * WARNING: some versions of u-boot only looks at bits 8 and 9, so 2 GiB of
206 * DRAM will be interpreted as 128 MiB.
208 * https://github.com/Nuvoton-Israel/u-boot/blob/2aef993bd2aafeb5408dbaad0f3ce099ee40c4aa/board/nuvoton/poleg/poleg.c#L244
210 s
->reset_intcr3
|= ctz64(dram_size
/ NPCM7XX_GCR_MIN_DRAM_SIZE
) << 8;
213 static void npcm7xx_gcr_init(Object
*obj
)
215 NPCM7xxGCRState
*s
= NPCM7XX_GCR(obj
);
217 memory_region_init_io(&s
->iomem
, obj
, &npcm7xx_gcr_ops
, s
,
218 TYPE_NPCM7XX_GCR
, 4 * KiB
);
219 sysbus_init_mmio(SYS_BUS_DEVICE(s
), &s
->iomem
);
222 static const VMStateDescription vmstate_npcm7xx_gcr
= {
223 .name
= "npcm7xx-gcr",
225 .minimum_version_id
= 0,
226 .fields
= (const VMStateField
[]) {
227 VMSTATE_UINT32_ARRAY(regs
, NPCM7xxGCRState
, NPCM7XX_GCR_NR_REGS
),
228 VMSTATE_END_OF_LIST(),
232 static Property npcm7xx_gcr_properties
[] = {
233 DEFINE_PROP_UINT32("disabled-modules", NPCM7xxGCRState
, reset_mdlr
, 0),
234 DEFINE_PROP_UINT32("power-on-straps", NPCM7xxGCRState
, reset_pwron
, 0),
235 DEFINE_PROP_END_OF_LIST(),
238 static void npcm7xx_gcr_class_init(ObjectClass
*klass
, void *data
)
240 ResettableClass
*rc
= RESETTABLE_CLASS(klass
);
241 DeviceClass
*dc
= DEVICE_CLASS(klass
);
243 QEMU_BUILD_BUG_ON(NPCM7XX_GCR_REGS_END
> NPCM7XX_GCR_NR_REGS
);
245 dc
->desc
= "NPCM7xx System Global Control Registers";
246 dc
->realize
= npcm7xx_gcr_realize
;
247 dc
->vmsd
= &vmstate_npcm7xx_gcr
;
248 rc
->phases
.enter
= npcm7xx_gcr_enter_reset
;
250 device_class_set_props(dc
, npcm7xx_gcr_properties
);
253 static const TypeInfo npcm7xx_gcr_info
= {
254 .name
= TYPE_NPCM7XX_GCR
,
255 .parent
= TYPE_SYS_BUS_DEVICE
,
256 .instance_size
= sizeof(NPCM7xxGCRState
),
257 .instance_init
= npcm7xx_gcr_init
,
258 .class_init
= npcm7xx_gcr_class_init
,
261 static void npcm7xx_gcr_register_type(void)
263 type_register_static(&npcm7xx_gcr_info
);
265 type_init(npcm7xx_gcr_register_type
);