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[qemu/kevin.git] / target-arm / cpu.h
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1 /*
2 * ARM virtual CPU header
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #ifndef ARM_CPU_H
21 #define ARM_CPU_H
23 #include "kvm-consts.h"
25 #if defined(TARGET_AARCH64)
26 /* AArch64 definitions */
27 # define TARGET_LONG_BITS 64
28 #else
29 # define TARGET_LONG_BITS 32
30 #endif
32 #define CPUArchState struct CPUARMState
34 #include "qemu-common.h"
35 #include "cpu-qom.h"
36 #include "exec/cpu-defs.h"
38 #include "fpu/softfloat.h"
40 #define EXCP_UDEF 1 /* undefined instruction */
41 #define EXCP_SWI 2 /* software interrupt */
42 #define EXCP_PREFETCH_ABORT 3
43 #define EXCP_DATA_ABORT 4
44 #define EXCP_IRQ 5
45 #define EXCP_FIQ 6
46 #define EXCP_BKPT 7
47 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */
48 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */
49 #define EXCP_STREX 10
50 #define EXCP_HVC 11 /* HyperVisor Call */
51 #define EXCP_HYP_TRAP 12
52 #define EXCP_SMC 13 /* Secure Monitor Call */
53 #define EXCP_VIRQ 14
54 #define EXCP_VFIQ 15
55 #define EXCP_SEMIHOST 16 /* semihosting call (A64 only) */
57 #define ARMV7M_EXCP_RESET 1
58 #define ARMV7M_EXCP_NMI 2
59 #define ARMV7M_EXCP_HARD 3
60 #define ARMV7M_EXCP_MEM 4
61 #define ARMV7M_EXCP_BUS 5
62 #define ARMV7M_EXCP_USAGE 6
63 #define ARMV7M_EXCP_SVC 11
64 #define ARMV7M_EXCP_DEBUG 12
65 #define ARMV7M_EXCP_PENDSV 14
66 #define ARMV7M_EXCP_SYSTICK 15
68 /* ARM-specific interrupt pending bits. */
69 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
70 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
71 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
73 /* The usual mapping for an AArch64 system register to its AArch32
74 * counterpart is for the 32 bit world to have access to the lower
75 * half only (with writes leaving the upper half untouched). It's
76 * therefore useful to be able to pass TCG the offset of the least
77 * significant half of a uint64_t struct member.
79 #ifdef HOST_WORDS_BIGENDIAN
80 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
81 #define offsetofhigh32(S, M) offsetof(S, M)
82 #else
83 #define offsetoflow32(S, M) offsetof(S, M)
84 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
85 #endif
87 /* Meanings of the ARMCPU object's four inbound GPIO lines */
88 #define ARM_CPU_IRQ 0
89 #define ARM_CPU_FIQ 1
90 #define ARM_CPU_VIRQ 2
91 #define ARM_CPU_VFIQ 3
93 #define NB_MMU_MODES 7
94 /* ARM-specific extra insn start words:
95 * 1: Conditional execution bits
96 * 2: Partial exception syndrome for data aborts
98 #define TARGET_INSN_START_EXTRA_WORDS 2
100 /* The 2nd extra word holding syndrome info for data aborts does not use
101 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to
102 * help the sleb128 encoder do a better job.
103 * When restoring the CPU state, we shift it back up.
105 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
106 #define ARM_INSN_START_WORD2_SHIFT 14
108 /* We currently assume float and double are IEEE single and double
109 precision respectively.
110 Doing runtime conversions is tricky because VFP registers may contain
111 integer values (eg. as the result of a FTOSI instruction).
112 s<2n> maps to the least significant half of d<n>
113 s<2n+1> maps to the most significant half of d<n>
116 /* CPU state for each instance of a generic timer (in cp15 c14) */
117 typedef struct ARMGenericTimer {
118 uint64_t cval; /* Timer CompareValue register */
119 uint64_t ctl; /* Timer Control register */
120 } ARMGenericTimer;
122 #define GTIMER_PHYS 0
123 #define GTIMER_VIRT 1
124 #define GTIMER_HYP 2
125 #define GTIMER_SEC 3
126 #define NUM_GTIMERS 4
128 typedef struct {
129 uint64_t raw_tcr;
130 uint32_t mask;
131 uint32_t base_mask;
132 } TCR;
134 typedef struct CPUARMState {
135 /* Regs for current mode. */
136 uint32_t regs[16];
138 /* 32/64 switch only happens when taking and returning from
139 * exceptions so the overlap semantics are taken care of then
140 * instead of having a complicated union.
142 /* Regs for A64 mode. */
143 uint64_t xregs[32];
144 uint64_t pc;
145 /* PSTATE isn't an architectural register for ARMv8. However, it is
146 * convenient for us to assemble the underlying state into a 32 bit format
147 * identical to the architectural format used for the SPSR. (This is also
148 * what the Linux kernel's 'pstate' field in signal handlers and KVM's
149 * 'pstate' register are.) Of the PSTATE bits:
150 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same
151 * semantics as for AArch32, as described in the comments on each field)
152 * nRW (also known as M[4]) is kept, inverted, in env->aarch64
153 * DAIF (exception masks) are kept in env->daif
154 * all other bits are stored in their correct places in env->pstate
156 uint32_t pstate;
157 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */
159 /* Frequently accessed CPSR bits are stored separately for efficiency.
160 This contains all the other bits. Use cpsr_{read,write} to access
161 the whole CPSR. */
162 uint32_t uncached_cpsr;
163 uint32_t spsr;
165 /* Banked registers. */
166 uint64_t banked_spsr[8];
167 uint32_t banked_r13[8];
168 uint32_t banked_r14[8];
170 /* These hold r8-r12. */
171 uint32_t usr_regs[5];
172 uint32_t fiq_regs[5];
174 /* cpsr flag cache for faster execution */
175 uint32_t CF; /* 0 or 1 */
176 uint32_t VF; /* V is the bit 31. All other bits are undefined */
177 uint32_t NF; /* N is bit 31. All other bits are undefined. */
178 uint32_t ZF; /* Z set if zero. */
179 uint32_t QF; /* 0 or 1 */
180 uint32_t GE; /* cpsr[19:16] */
181 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
182 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */
183 uint64_t daif; /* exception masks, in the bits they are in PSTATE */
185 uint64_t elr_el[4]; /* AArch64 exception link regs */
186 uint64_t sp_el[4]; /* AArch64 banked stack pointers */
188 /* System control coprocessor (cp15) */
189 struct {
190 uint32_t c0_cpuid;
191 union { /* Cache size selection */
192 struct {
193 uint64_t _unused_csselr0;
194 uint64_t csselr_ns;
195 uint64_t _unused_csselr1;
196 uint64_t csselr_s;
198 uint64_t csselr_el[4];
200 union { /* System control register. */
201 struct {
202 uint64_t _unused_sctlr;
203 uint64_t sctlr_ns;
204 uint64_t hsctlr;
205 uint64_t sctlr_s;
207 uint64_t sctlr_el[4];
209 uint64_t cpacr_el1; /* Architectural feature access control register */
210 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */
211 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
212 uint64_t sder; /* Secure debug enable register. */
213 uint32_t nsacr; /* Non-secure access control register. */
214 union { /* MMU translation table base 0. */
215 struct {
216 uint64_t _unused_ttbr0_0;
217 uint64_t ttbr0_ns;
218 uint64_t _unused_ttbr0_1;
219 uint64_t ttbr0_s;
221 uint64_t ttbr0_el[4];
223 union { /* MMU translation table base 1. */
224 struct {
225 uint64_t _unused_ttbr1_0;
226 uint64_t ttbr1_ns;
227 uint64_t _unused_ttbr1_1;
228 uint64_t ttbr1_s;
230 uint64_t ttbr1_el[4];
232 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */
233 /* MMU translation table base control. */
234 TCR tcr_el[4];
235 TCR vtcr_el2; /* Virtualization Translation Control. */
236 uint32_t c2_data; /* MPU data cacheable bits. */
237 uint32_t c2_insn; /* MPU instruction cacheable bits. */
238 union { /* MMU domain access control register
239 * MPU write buffer control.
241 struct {
242 uint64_t dacr_ns;
243 uint64_t dacr_s;
245 struct {
246 uint64_t dacr32_el2;
249 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */
250 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */
251 uint64_t hcr_el2; /* Hypervisor configuration register */
252 uint64_t scr_el3; /* Secure configuration register. */
253 union { /* Fault status registers. */
254 struct {
255 uint64_t ifsr_ns;
256 uint64_t ifsr_s;
258 struct {
259 uint64_t ifsr32_el2;
262 union {
263 struct {
264 uint64_t _unused_dfsr;
265 uint64_t dfsr_ns;
266 uint64_t hsr;
267 uint64_t dfsr_s;
269 uint64_t esr_el[4];
271 uint32_t c6_region[8]; /* MPU base/size registers. */
272 union { /* Fault address registers. */
273 struct {
274 uint64_t _unused_far0;
275 #ifdef HOST_WORDS_BIGENDIAN
276 uint32_t ifar_ns;
277 uint32_t dfar_ns;
278 uint32_t ifar_s;
279 uint32_t dfar_s;
280 #else
281 uint32_t dfar_ns;
282 uint32_t ifar_ns;
283 uint32_t dfar_s;
284 uint32_t ifar_s;
285 #endif
286 uint64_t _unused_far3;
288 uint64_t far_el[4];
290 uint64_t hpfar_el2;
291 uint64_t hstr_el2;
292 union { /* Translation result. */
293 struct {
294 uint64_t _unused_par_0;
295 uint64_t par_ns;
296 uint64_t _unused_par_1;
297 uint64_t par_s;
299 uint64_t par_el[4];
302 uint32_t c6_rgnr;
304 uint32_t c9_insn; /* Cache lockdown registers. */
305 uint32_t c9_data;
306 uint64_t c9_pmcr; /* performance monitor control register */
307 uint64_t c9_pmcnten; /* perf monitor counter enables */
308 uint32_t c9_pmovsr; /* perf monitor overflow status */
309 uint32_t c9_pmxevtyper; /* perf monitor event type */
310 uint32_t c9_pmuserenr; /* perf monitor user enable */
311 uint32_t c9_pminten; /* perf monitor interrupt enables */
312 union { /* Memory attribute redirection */
313 struct {
314 #ifdef HOST_WORDS_BIGENDIAN
315 uint64_t _unused_mair_0;
316 uint32_t mair1_ns;
317 uint32_t mair0_ns;
318 uint64_t _unused_mair_1;
319 uint32_t mair1_s;
320 uint32_t mair0_s;
321 #else
322 uint64_t _unused_mair_0;
323 uint32_t mair0_ns;
324 uint32_t mair1_ns;
325 uint64_t _unused_mair_1;
326 uint32_t mair0_s;
327 uint32_t mair1_s;
328 #endif
330 uint64_t mair_el[4];
332 union { /* vector base address register */
333 struct {
334 uint64_t _unused_vbar;
335 uint64_t vbar_ns;
336 uint64_t hvbar;
337 uint64_t vbar_s;
339 uint64_t vbar_el[4];
341 uint32_t mvbar; /* (monitor) vector base address register */
342 struct { /* FCSE PID. */
343 uint32_t fcseidr_ns;
344 uint32_t fcseidr_s;
346 union { /* Context ID. */
347 struct {
348 uint64_t _unused_contextidr_0;
349 uint64_t contextidr_ns;
350 uint64_t _unused_contextidr_1;
351 uint64_t contextidr_s;
353 uint64_t contextidr_el[4];
355 union { /* User RW Thread register. */
356 struct {
357 uint64_t tpidrurw_ns;
358 uint64_t tpidrprw_ns;
359 uint64_t htpidr;
360 uint64_t _tpidr_el3;
362 uint64_t tpidr_el[4];
364 /* The secure banks of these registers don't map anywhere */
365 uint64_t tpidrurw_s;
366 uint64_t tpidrprw_s;
367 uint64_t tpidruro_s;
369 union { /* User RO Thread register. */
370 uint64_t tpidruro_ns;
371 uint64_t tpidrro_el[1];
373 uint64_t c14_cntfrq; /* Counter Frequency register */
374 uint64_t c14_cntkctl; /* Timer Control register */
375 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */
376 uint64_t cntvoff_el2; /* Counter Virtual Offset register */
377 ARMGenericTimer c14_timer[NUM_GTIMERS];
378 uint32_t c15_cpar; /* XScale Coprocessor Access Register */
379 uint32_t c15_ticonfig; /* TI925T configuration byte. */
380 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
381 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
382 uint32_t c15_threadid; /* TI debugger thread-ID. */
383 uint32_t c15_config_base_address; /* SCU base address. */
384 uint32_t c15_diagnostic; /* diagnostic register */
385 uint32_t c15_power_diagnostic;
386 uint32_t c15_power_control; /* power control */
387 uint64_t dbgbvr[16]; /* breakpoint value registers */
388 uint64_t dbgbcr[16]; /* breakpoint control registers */
389 uint64_t dbgwvr[16]; /* watchpoint value registers */
390 uint64_t dbgwcr[16]; /* watchpoint control registers */
391 uint64_t mdscr_el1;
392 uint64_t oslsr_el1; /* OS Lock Status */
393 uint64_t mdcr_el2;
394 uint64_t mdcr_el3;
395 /* If the counter is enabled, this stores the last time the counter
396 * was reset. Otherwise it stores the counter value
398 uint64_t c15_ccnt;
399 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */
400 uint64_t vpidr_el2; /* Virtualization Processor ID Register */
401 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */
402 } cp15;
404 struct {
405 uint32_t other_sp;
406 uint32_t vecbase;
407 uint32_t basepri;
408 uint32_t control;
409 int current_sp;
410 int exception;
411 } v7m;
413 /* Information associated with an exception about to be taken:
414 * code which raises an exception must set cs->exception_index and
415 * the relevant parts of this structure; the cpu_do_interrupt function
416 * will then set the guest-visible registers as part of the exception
417 * entry process.
419 struct {
420 uint32_t syndrome; /* AArch64 format syndrome register */
421 uint32_t fsr; /* AArch32 format fault status register info */
422 uint64_t vaddress; /* virtual addr associated with exception, if any */
423 uint32_t target_el; /* EL the exception should be targeted for */
424 /* If we implement EL2 we will also need to store information
425 * about the intermediate physical address for stage 2 faults.
427 } exception;
429 /* Thumb-2 EE state. */
430 uint32_t teecr;
431 uint32_t teehbr;
433 /* VFP coprocessor state. */
434 struct {
435 /* VFP/Neon register state. Note that the mapping between S, D and Q
436 * views of the register bank differs between AArch64 and AArch32:
437 * In AArch32:
438 * Qn = regs[2n+1]:regs[2n]
439 * Dn = regs[n]
440 * Sn = regs[n/2] bits 31..0 for even n, and bits 63..32 for odd n
441 * (and regs[32] to regs[63] are inaccessible)
442 * In AArch64:
443 * Qn = regs[2n+1]:regs[2n]
444 * Dn = regs[2n]
445 * Sn = regs[2n] bits 31..0
446 * This corresponds to the architecturally defined mapping between
447 * the two execution states, and means we do not need to explicitly
448 * map these registers when changing states.
450 float64 regs[64];
452 uint32_t xregs[16];
453 /* We store these fpcsr fields separately for convenience. */
454 int vec_len;
455 int vec_stride;
457 /* scratch space when Tn are not sufficient. */
458 uint32_t scratch[8];
460 /* fp_status is the "normal" fp status. standard_fp_status retains
461 * values corresponding to the ARM "Standard FPSCR Value", ie
462 * default-NaN, flush-to-zero, round-to-nearest and is used by
463 * any operations (generally Neon) which the architecture defines
464 * as controlled by the standard FPSCR value rather than the FPSCR.
466 * To avoid having to transfer exception bits around, we simply
467 * say that the FPSCR cumulative exception flags are the logical
468 * OR of the flags in the two fp statuses. This relies on the
469 * only thing which needs to read the exception flags being
470 * an explicit FPSCR read.
472 float_status fp_status;
473 float_status standard_fp_status;
474 } vfp;
475 uint64_t exclusive_addr;
476 uint64_t exclusive_val;
477 uint64_t exclusive_high;
478 #if defined(CONFIG_USER_ONLY)
479 uint64_t exclusive_test;
480 uint32_t exclusive_info;
481 #endif
483 /* iwMMXt coprocessor state. */
484 struct {
485 uint64_t regs[16];
486 uint64_t val;
488 uint32_t cregs[16];
489 } iwmmxt;
491 #if defined(CONFIG_USER_ONLY)
492 /* For usermode syscall translation. */
493 int eabi;
494 #endif
496 struct CPUBreakpoint *cpu_breakpoint[16];
497 struct CPUWatchpoint *cpu_watchpoint[16];
499 CPU_COMMON
501 /* These fields after the common ones so they are preserved on reset. */
503 /* Internal CPU feature flags. */
504 uint64_t features;
506 /* PMSAv7 MPU */
507 struct {
508 uint32_t *drbar;
509 uint32_t *drsr;
510 uint32_t *dracr;
511 } pmsav7;
513 void *nvic;
514 const struct arm_boot_info *boot_info;
515 } CPUARMState;
518 * ARMELChangeHook:
519 * type of a function which can be registered via arm_register_el_change_hook()
520 * to get callbacks when the CPU changes its exception level or mode.
522 typedef void ARMELChangeHook(ARMCPU *cpu, void *opaque);
525 * ARMCPU:
526 * @env: #CPUARMState
528 * An ARM CPU core.
530 struct ARMCPU {
531 /*< private >*/
532 CPUState parent_obj;
533 /*< public >*/
535 CPUARMState env;
537 /* Coprocessor information */
538 GHashTable *cp_regs;
539 /* For marshalling (mostly coprocessor) register state between the
540 * kernel and QEMU (for KVM) and between two QEMUs (for migration),
541 * we use these arrays.
543 /* List of register indexes managed via these arrays; (full KVM style
544 * 64 bit indexes, not CPRegInfo 32 bit indexes)
546 uint64_t *cpreg_indexes;
547 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */
548 uint64_t *cpreg_values;
549 /* Length of the indexes, values, reset_values arrays */
550 int32_t cpreg_array_len;
551 /* These are used only for migration: incoming data arrives in
552 * these fields and is sanity checked in post_load before copying
553 * to the working data structures above.
555 uint64_t *cpreg_vmstate_indexes;
556 uint64_t *cpreg_vmstate_values;
557 int32_t cpreg_vmstate_array_len;
559 /* Timers used by the generic (architected) timer */
560 QEMUTimer *gt_timer[NUM_GTIMERS];
561 /* GPIO outputs for generic timer */
562 qemu_irq gt_timer_outputs[NUM_GTIMERS];
564 /* MemoryRegion to use for secure physical accesses */
565 MemoryRegion *secure_memory;
567 /* 'compatible' string for this CPU for Linux device trees */
568 const char *dtb_compatible;
570 /* PSCI version for this CPU
571 * Bits[31:16] = Major Version
572 * Bits[15:0] = Minor Version
574 uint32_t psci_version;
576 /* Should CPU start in PSCI powered-off state? */
577 bool start_powered_off;
578 /* CPU currently in PSCI powered-off state */
579 bool powered_off;
580 /* CPU has security extension */
581 bool has_el3;
582 /* CPU has PMU (Performance Monitor Unit) */
583 bool has_pmu;
585 /* CPU has memory protection unit */
586 bool has_mpu;
587 /* PMSAv7 MPU number of supported regions */
588 uint32_t pmsav7_dregion;
590 /* PSCI conduit used to invoke PSCI methods
591 * 0 - disabled, 1 - smc, 2 - hvc
593 uint32_t psci_conduit;
595 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or
596 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type.
598 uint32_t kvm_target;
600 /* KVM init features for this CPU */
601 uint32_t kvm_init_features[7];
603 /* Uniprocessor system with MP extensions */
604 bool mp_is_up;
606 /* The instance init functions for implementation-specific subclasses
607 * set these fields to specify the implementation-dependent values of
608 * various constant registers and reset values of non-constant
609 * registers.
610 * Some of these might become QOM properties eventually.
611 * Field names match the official register names as defined in the
612 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix
613 * is used for reset values of non-constant registers; no reset_
614 * prefix means a constant register.
616 uint32_t midr;
617 uint32_t revidr;
618 uint32_t reset_fpsid;
619 uint32_t mvfr0;
620 uint32_t mvfr1;
621 uint32_t mvfr2;
622 uint32_t ctr;
623 uint32_t reset_sctlr;
624 uint32_t id_pfr0;
625 uint32_t id_pfr1;
626 uint32_t id_dfr0;
627 uint32_t pmceid0;
628 uint32_t pmceid1;
629 uint32_t id_afr0;
630 uint32_t id_mmfr0;
631 uint32_t id_mmfr1;
632 uint32_t id_mmfr2;
633 uint32_t id_mmfr3;
634 uint32_t id_mmfr4;
635 uint32_t id_isar0;
636 uint32_t id_isar1;
637 uint32_t id_isar2;
638 uint32_t id_isar3;
639 uint32_t id_isar4;
640 uint32_t id_isar5;
641 uint64_t id_aa64pfr0;
642 uint64_t id_aa64pfr1;
643 uint64_t id_aa64dfr0;
644 uint64_t id_aa64dfr1;
645 uint64_t id_aa64afr0;
646 uint64_t id_aa64afr1;
647 uint64_t id_aa64isar0;
648 uint64_t id_aa64isar1;
649 uint64_t id_aa64mmfr0;
650 uint64_t id_aa64mmfr1;
651 uint32_t dbgdidr;
652 uint32_t clidr;
653 uint64_t mp_affinity; /* MP ID without feature bits */
654 /* The elements of this array are the CCSIDR values for each cache,
655 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
657 uint32_t ccsidr[16];
658 uint64_t reset_cbar;
659 uint32_t reset_auxcr;
660 bool reset_hivecs;
661 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
662 uint32_t dcz_blocksize;
663 uint64_t rvbar;
665 ARMELChangeHook *el_change_hook;
666 void *el_change_hook_opaque;
669 static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
671 return container_of(env, ARMCPU, env);
674 #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e))
676 #define ENV_OFFSET offsetof(ARMCPU, env)
678 #ifndef CONFIG_USER_ONLY
679 extern const struct VMStateDescription vmstate_arm_cpu;
680 #endif
682 void arm_cpu_do_interrupt(CPUState *cpu);
683 void arm_v7m_cpu_do_interrupt(CPUState *cpu);
684 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req);
686 void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
687 int flags);
689 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
690 MemTxAttrs *attrs);
692 int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
693 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
695 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
696 int cpuid, void *opaque);
697 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
698 int cpuid, void *opaque);
700 #ifdef TARGET_AARCH64
701 int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
702 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
703 #endif
705 ARMCPU *cpu_arm_init(const char *cpu_model);
706 target_ulong do_arm_semihosting(CPUARMState *env);
707 void aarch64_sync_32_to_64(CPUARMState *env);
708 void aarch64_sync_64_to_32(CPUARMState *env);
710 static inline bool is_a64(CPUARMState *env)
712 return env->aarch64;
715 /* you can call this signal handler from your SIGBUS and SIGSEGV
716 signal handlers to inform the virtual CPU of exceptions. non zero
717 is returned if the signal was handled by the virtual CPU. */
718 int cpu_arm_signal_handler(int host_signum, void *pinfo,
719 void *puc);
722 * pmccntr_sync
723 * @env: CPUARMState
725 * Synchronises the counter in the PMCCNTR. This must always be called twice,
726 * once before any action that might affect the timer and again afterwards.
727 * The function is used to swap the state of the register if required.
728 * This only happens when not in user mode (!CONFIG_USER_ONLY)
730 void pmccntr_sync(CPUARMState *env);
732 /* SCTLR bit meanings. Several bits have been reused in newer
733 * versions of the architecture; in that case we define constants
734 * for both old and new bit meanings. Code which tests against those
735 * bits should probably check or otherwise arrange that the CPU
736 * is the architectural version it expects.
738 #define SCTLR_M (1U << 0)
739 #define SCTLR_A (1U << 1)
740 #define SCTLR_C (1U << 2)
741 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */
742 #define SCTLR_SA (1U << 3)
743 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */
744 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */
745 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */
746 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */
747 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */
748 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */
749 #define SCTLR_ITD (1U << 7) /* v8 onward */
750 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */
751 #define SCTLR_SED (1U << 8) /* v8 onward */
752 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */
753 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */
754 #define SCTLR_F (1U << 10) /* up to v6 */
755 #define SCTLR_SW (1U << 10) /* v7 onward */
756 #define SCTLR_Z (1U << 11)
757 #define SCTLR_I (1U << 12)
758 #define SCTLR_V (1U << 13)
759 #define SCTLR_RR (1U << 14) /* up to v7 */
760 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */
761 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */
762 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */
763 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */
764 #define SCTLR_nTWI (1U << 16) /* v8 onward */
765 #define SCTLR_HA (1U << 17)
766 #define SCTLR_BR (1U << 17) /* PMSA only */
767 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */
768 #define SCTLR_nTWE (1U << 18) /* v8 onward */
769 #define SCTLR_WXN (1U << 19)
770 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */
771 #define SCTLR_UWXN (1U << 20) /* v7 onward */
772 #define SCTLR_FI (1U << 21)
773 #define SCTLR_U (1U << 22)
774 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */
775 #define SCTLR_VE (1U << 24) /* up to v7 */
776 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */
777 #define SCTLR_EE (1U << 25)
778 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */
779 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */
780 #define SCTLR_NMFI (1U << 27)
781 #define SCTLR_TRE (1U << 28)
782 #define SCTLR_AFE (1U << 29)
783 #define SCTLR_TE (1U << 30)
785 #define CPTR_TCPAC (1U << 31)
786 #define CPTR_TTA (1U << 20)
787 #define CPTR_TFP (1U << 10)
789 #define MDCR_EPMAD (1U << 21)
790 #define MDCR_EDAD (1U << 20)
791 #define MDCR_SPME (1U << 17)
792 #define MDCR_SDD (1U << 16)
793 #define MDCR_SPD (3U << 14)
794 #define MDCR_TDRA (1U << 11)
795 #define MDCR_TDOSA (1U << 10)
796 #define MDCR_TDA (1U << 9)
797 #define MDCR_TDE (1U << 8)
798 #define MDCR_HPME (1U << 7)
799 #define MDCR_TPM (1U << 6)
800 #define MDCR_TPMCR (1U << 5)
802 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
803 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
805 #define CPSR_M (0x1fU)
806 #define CPSR_T (1U << 5)
807 #define CPSR_F (1U << 6)
808 #define CPSR_I (1U << 7)
809 #define CPSR_A (1U << 8)
810 #define CPSR_E (1U << 9)
811 #define CPSR_IT_2_7 (0xfc00U)
812 #define CPSR_GE (0xfU << 16)
813 #define CPSR_IL (1U << 20)
814 /* Note that the RESERVED bits include bit 21, which is PSTATE_SS in
815 * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use
816 * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32,
817 * where it is live state but not accessible to the AArch32 code.
819 #define CPSR_RESERVED (0x7U << 21)
820 #define CPSR_J (1U << 24)
821 #define CPSR_IT_0_1 (3U << 25)
822 #define CPSR_Q (1U << 27)
823 #define CPSR_V (1U << 28)
824 #define CPSR_C (1U << 29)
825 #define CPSR_Z (1U << 30)
826 #define CPSR_N (1U << 31)
827 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
828 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
830 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
831 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
832 | CPSR_NZCV)
833 /* Bits writable in user mode. */
834 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
835 /* Execution state bits. MRS read as zero, MSR writes ignored. */
836 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
837 /* Mask of bits which may be set by exception return copying them from SPSR */
838 #define CPSR_ERET_MASK (~CPSR_RESERVED)
840 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */
841 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */
842 #define TTBCR_PD0 (1U << 4)
843 #define TTBCR_PD1 (1U << 5)
844 #define TTBCR_EPD0 (1U << 7)
845 #define TTBCR_IRGN0 (3U << 8)
846 #define TTBCR_ORGN0 (3U << 10)
847 #define TTBCR_SH0 (3U << 12)
848 #define TTBCR_T1SZ (3U << 16)
849 #define TTBCR_A1 (1U << 22)
850 #define TTBCR_EPD1 (1U << 23)
851 #define TTBCR_IRGN1 (3U << 24)
852 #define TTBCR_ORGN1 (3U << 26)
853 #define TTBCR_SH1 (1U << 28)
854 #define TTBCR_EAE (1U << 31)
856 /* Bit definitions for ARMv8 SPSR (PSTATE) format.
857 * Only these are valid when in AArch64 mode; in
858 * AArch32 mode SPSRs are basically CPSR-format.
860 #define PSTATE_SP (1U)
861 #define PSTATE_M (0xFU)
862 #define PSTATE_nRW (1U << 4)
863 #define PSTATE_F (1U << 6)
864 #define PSTATE_I (1U << 7)
865 #define PSTATE_A (1U << 8)
866 #define PSTATE_D (1U << 9)
867 #define PSTATE_IL (1U << 20)
868 #define PSTATE_SS (1U << 21)
869 #define PSTATE_V (1U << 28)
870 #define PSTATE_C (1U << 29)
871 #define PSTATE_Z (1U << 30)
872 #define PSTATE_N (1U << 31)
873 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
874 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
875 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF)
876 /* Mode values for AArch64 */
877 #define PSTATE_MODE_EL3h 13
878 #define PSTATE_MODE_EL3t 12
879 #define PSTATE_MODE_EL2h 9
880 #define PSTATE_MODE_EL2t 8
881 #define PSTATE_MODE_EL1h 5
882 #define PSTATE_MODE_EL1t 4
883 #define PSTATE_MODE_EL0t 0
885 /* Map EL and handler into a PSTATE_MODE. */
886 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler)
888 return (el << 2) | handler;
891 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit
892 * interprocessing, so we don't attempt to sync with the cpsr state used by
893 * the 32 bit decoder.
895 static inline uint32_t pstate_read(CPUARMState *env)
897 int ZF;
899 ZF = (env->ZF == 0);
900 return (env->NF & 0x80000000) | (ZF << 30)
901 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3)
902 | env->pstate | env->daif;
905 static inline void pstate_write(CPUARMState *env, uint32_t val)
907 env->ZF = (~val) & PSTATE_Z;
908 env->NF = val;
909 env->CF = (val >> 29) & 1;
910 env->VF = (val << 3) & 0x80000000;
911 env->daif = val & PSTATE_DAIF;
912 env->pstate = val & ~CACHED_PSTATE_BITS;
915 /* Return the current CPSR value. */
916 uint32_t cpsr_read(CPUARMState *env);
918 typedef enum CPSRWriteType {
919 CPSRWriteByInstr = 0, /* from guest MSR or CPS */
920 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */
921 CPSRWriteRaw = 2, /* trust values, do not switch reg banks */
922 CPSRWriteByGDBStub = 3, /* from the GDB stub */
923 } CPSRWriteType;
925 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/
926 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
927 CPSRWriteType write_type);
929 /* Return the current xPSR value. */
930 static inline uint32_t xpsr_read(CPUARMState *env)
932 int ZF;
933 ZF = (env->ZF == 0);
934 return (env->NF & 0x80000000) | (ZF << 30)
935 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
936 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
937 | ((env->condexec_bits & 0xfc) << 8)
938 | env->v7m.exception;
941 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
942 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
944 if (mask & CPSR_NZCV) {
945 env->ZF = (~val) & CPSR_Z;
946 env->NF = val;
947 env->CF = (val >> 29) & 1;
948 env->VF = (val << 3) & 0x80000000;
950 if (mask & CPSR_Q)
951 env->QF = ((val & CPSR_Q) != 0);
952 if (mask & (1 << 24))
953 env->thumb = ((val & (1 << 24)) != 0);
954 if (mask & CPSR_IT_0_1) {
955 env->condexec_bits &= ~3;
956 env->condexec_bits |= (val >> 25) & 3;
958 if (mask & CPSR_IT_2_7) {
959 env->condexec_bits &= 3;
960 env->condexec_bits |= (val >> 8) & 0xfc;
962 if (mask & 0x1ff) {
963 env->v7m.exception = val & 0x1ff;
967 #define HCR_VM (1ULL << 0)
968 #define HCR_SWIO (1ULL << 1)
969 #define HCR_PTW (1ULL << 2)
970 #define HCR_FMO (1ULL << 3)
971 #define HCR_IMO (1ULL << 4)
972 #define HCR_AMO (1ULL << 5)
973 #define HCR_VF (1ULL << 6)
974 #define HCR_VI (1ULL << 7)
975 #define HCR_VSE (1ULL << 8)
976 #define HCR_FB (1ULL << 9)
977 #define HCR_BSU_MASK (3ULL << 10)
978 #define HCR_DC (1ULL << 12)
979 #define HCR_TWI (1ULL << 13)
980 #define HCR_TWE (1ULL << 14)
981 #define HCR_TID0 (1ULL << 15)
982 #define HCR_TID1 (1ULL << 16)
983 #define HCR_TID2 (1ULL << 17)
984 #define HCR_TID3 (1ULL << 18)
985 #define HCR_TSC (1ULL << 19)
986 #define HCR_TIDCP (1ULL << 20)
987 #define HCR_TACR (1ULL << 21)
988 #define HCR_TSW (1ULL << 22)
989 #define HCR_TPC (1ULL << 23)
990 #define HCR_TPU (1ULL << 24)
991 #define HCR_TTLB (1ULL << 25)
992 #define HCR_TVM (1ULL << 26)
993 #define HCR_TGE (1ULL << 27)
994 #define HCR_TDZ (1ULL << 28)
995 #define HCR_HCD (1ULL << 29)
996 #define HCR_TRVM (1ULL << 30)
997 #define HCR_RW (1ULL << 31)
998 #define HCR_CD (1ULL << 32)
999 #define HCR_ID (1ULL << 33)
1000 #define HCR_MASK ((1ULL << 34) - 1)
1002 #define SCR_NS (1U << 0)
1003 #define SCR_IRQ (1U << 1)
1004 #define SCR_FIQ (1U << 2)
1005 #define SCR_EA (1U << 3)
1006 #define SCR_FW (1U << 4)
1007 #define SCR_AW (1U << 5)
1008 #define SCR_NET (1U << 6)
1009 #define SCR_SMD (1U << 7)
1010 #define SCR_HCE (1U << 8)
1011 #define SCR_SIF (1U << 9)
1012 #define SCR_RW (1U << 10)
1013 #define SCR_ST (1U << 11)
1014 #define SCR_TWI (1U << 12)
1015 #define SCR_TWE (1U << 13)
1016 #define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST))
1017 #define SCR_AARCH64_MASK (0x3fff & ~SCR_NET)
1019 /* Return the current FPSCR value. */
1020 uint32_t vfp_get_fpscr(CPUARMState *env);
1021 void vfp_set_fpscr(CPUARMState *env, uint32_t val);
1023 /* For A64 the FPSCR is split into two logically distinct registers,
1024 * FPCR and FPSR. However since they still use non-overlapping bits
1025 * we store the underlying state in fpscr and just mask on read/write.
1027 #define FPSR_MASK 0xf800009f
1028 #define FPCR_MASK 0x07f79f00
1029 static inline uint32_t vfp_get_fpsr(CPUARMState *env)
1031 return vfp_get_fpscr(env) & FPSR_MASK;
1034 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val)
1036 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK);
1037 vfp_set_fpscr(env, new_fpscr);
1040 static inline uint32_t vfp_get_fpcr(CPUARMState *env)
1042 return vfp_get_fpscr(env) & FPCR_MASK;
1045 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val)
1047 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK);
1048 vfp_set_fpscr(env, new_fpscr);
1051 enum arm_cpu_mode {
1052 ARM_CPU_MODE_USR = 0x10,
1053 ARM_CPU_MODE_FIQ = 0x11,
1054 ARM_CPU_MODE_IRQ = 0x12,
1055 ARM_CPU_MODE_SVC = 0x13,
1056 ARM_CPU_MODE_MON = 0x16,
1057 ARM_CPU_MODE_ABT = 0x17,
1058 ARM_CPU_MODE_HYP = 0x1a,
1059 ARM_CPU_MODE_UND = 0x1b,
1060 ARM_CPU_MODE_SYS = 0x1f
1063 /* VFP system registers. */
1064 #define ARM_VFP_FPSID 0
1065 #define ARM_VFP_FPSCR 1
1066 #define ARM_VFP_MVFR2 5
1067 #define ARM_VFP_MVFR1 6
1068 #define ARM_VFP_MVFR0 7
1069 #define ARM_VFP_FPEXC 8
1070 #define ARM_VFP_FPINST 9
1071 #define ARM_VFP_FPINST2 10
1073 /* iwMMXt coprocessor control registers. */
1074 #define ARM_IWMMXT_wCID 0
1075 #define ARM_IWMMXT_wCon 1
1076 #define ARM_IWMMXT_wCSSF 2
1077 #define ARM_IWMMXT_wCASF 3
1078 #define ARM_IWMMXT_wCGR0 8
1079 #define ARM_IWMMXT_wCGR1 9
1080 #define ARM_IWMMXT_wCGR2 10
1081 #define ARM_IWMMXT_wCGR3 11
1083 /* If adding a feature bit which corresponds to a Linux ELF
1084 * HWCAP bit, remember to update the feature-bit-to-hwcap
1085 * mapping in linux-user/elfload.c:get_elf_hwcap().
1087 enum arm_features {
1088 ARM_FEATURE_VFP,
1089 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
1090 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
1091 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
1092 ARM_FEATURE_V6,
1093 ARM_FEATURE_V6K,
1094 ARM_FEATURE_V7,
1095 ARM_FEATURE_THUMB2,
1096 ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */
1097 ARM_FEATURE_VFP3,
1098 ARM_FEATURE_VFP_FP16,
1099 ARM_FEATURE_NEON,
1100 ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */
1101 ARM_FEATURE_M, /* Microcontroller profile. */
1102 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */
1103 ARM_FEATURE_THUMB2EE,
1104 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */
1105 ARM_FEATURE_V4T,
1106 ARM_FEATURE_V5,
1107 ARM_FEATURE_STRONGARM,
1108 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
1109 ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */
1110 ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */
1111 ARM_FEATURE_GENERIC_TIMER,
1112 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
1113 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
1114 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
1115 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
1116 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
1117 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
1118 ARM_FEATURE_PXN, /* has Privileged Execute Never bit */
1119 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
1120 ARM_FEATURE_V8,
1121 ARM_FEATURE_AARCH64, /* supports 64 bit mode */
1122 ARM_FEATURE_V8_AES, /* implements AES part of v8 Crypto Extensions */
1123 ARM_FEATURE_CBAR, /* has cp15 CBAR */
1124 ARM_FEATURE_CRC, /* ARMv8 CRC instructions */
1125 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */
1126 ARM_FEATURE_EL2, /* has EL2 Virtualization support */
1127 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */
1128 ARM_FEATURE_V8_SHA1, /* implements SHA1 part of v8 Crypto Extensions */
1129 ARM_FEATURE_V8_SHA256, /* implements SHA256 part of v8 Crypto Extensions */
1130 ARM_FEATURE_V8_PMULL, /* implements PMULL part of v8 Crypto Extensions */
1131 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */
1134 static inline int arm_feature(CPUARMState *env, int feature)
1136 return (env->features & (1ULL << feature)) != 0;
1139 #if !defined(CONFIG_USER_ONLY)
1140 /* Return true if exception levels below EL3 are in secure state,
1141 * or would be following an exception return to that level.
1142 * Unlike arm_is_secure() (which is always a question about the
1143 * _current_ state of the CPU) this doesn't care about the current
1144 * EL or mode.
1146 static inline bool arm_is_secure_below_el3(CPUARMState *env)
1148 if (arm_feature(env, ARM_FEATURE_EL3)) {
1149 return !(env->cp15.scr_el3 & SCR_NS);
1150 } else {
1151 /* If EL3 is not supported then the secure state is implementation
1152 * defined, in which case QEMU defaults to non-secure.
1154 return false;
1158 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */
1159 static inline bool arm_is_el3_or_mon(CPUARMState *env)
1161 if (arm_feature(env, ARM_FEATURE_EL3)) {
1162 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
1163 /* CPU currently in AArch64 state and EL3 */
1164 return true;
1165 } else if (!is_a64(env) &&
1166 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
1167 /* CPU currently in AArch32 state and monitor mode */
1168 return true;
1171 return false;
1174 /* Return true if the processor is in secure state */
1175 static inline bool arm_is_secure(CPUARMState *env)
1177 if (arm_is_el3_or_mon(env)) {
1178 return true;
1180 return arm_is_secure_below_el3(env);
1183 #else
1184 static inline bool arm_is_secure_below_el3(CPUARMState *env)
1186 return false;
1189 static inline bool arm_is_secure(CPUARMState *env)
1191 return false;
1193 #endif
1195 /* Return true if the specified exception level is running in AArch64 state. */
1196 static inline bool arm_el_is_aa64(CPUARMState *env, int el)
1198 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want,
1199 * and if we're not in EL0 then the state of EL0 isn't well defined.)
1201 assert(el >= 1 && el <= 3);
1202 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64);
1204 /* The highest exception level is always at the maximum supported
1205 * register width, and then lower levels have a register width controlled
1206 * by bits in the SCR or HCR registers.
1208 if (el == 3) {
1209 return aa64;
1212 if (arm_feature(env, ARM_FEATURE_EL3)) {
1213 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW);
1216 if (el == 2) {
1217 return aa64;
1220 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) {
1221 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW);
1224 return aa64;
1227 /* Function for determing whether guest cp register reads and writes should
1228 * access the secure or non-secure bank of a cp register. When EL3 is
1229 * operating in AArch32 state, the NS-bit determines whether the secure
1230 * instance of a cp register should be used. When EL3 is AArch64 (or if
1231 * it doesn't exist at all) then there is no register banking, and all
1232 * accesses are to the non-secure version.
1234 static inline bool access_secure_reg(CPUARMState *env)
1236 bool ret = (arm_feature(env, ARM_FEATURE_EL3) &&
1237 !arm_el_is_aa64(env, 3) &&
1238 !(env->cp15.scr_el3 & SCR_NS));
1240 return ret;
1243 /* Macros for accessing a specified CP register bank */
1244 #define A32_BANKED_REG_GET(_env, _regname, _secure) \
1245 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
1247 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \
1248 do { \
1249 if (_secure) { \
1250 (_env)->cp15._regname##_s = (_val); \
1251 } else { \
1252 (_env)->cp15._regname##_ns = (_val); \
1254 } while (0)
1256 /* Macros for automatically accessing a specific CP register bank depending on
1257 * the current secure state of the system. These macros are not intended for
1258 * supporting instruction translation reads/writes as these are dependent
1259 * solely on the SCR.NS bit and not the mode.
1261 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \
1262 A32_BANKED_REG_GET((_env), _regname, \
1263 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)))
1265 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \
1266 A32_BANKED_REG_SET((_env), _regname, \
1267 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \
1268 (_val))
1270 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
1271 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
1272 uint32_t cur_el, bool secure);
1274 /* Interface between CPU and Interrupt controller. */
1275 void armv7m_nvic_set_pending(void *opaque, int irq);
1276 int armv7m_nvic_acknowledge_irq(void *opaque);
1277 void armv7m_nvic_complete_irq(void *opaque, int irq);
1279 /* Interface for defining coprocessor registers.
1280 * Registers are defined in tables of arm_cp_reginfo structs
1281 * which are passed to define_arm_cp_regs().
1284 /* When looking up a coprocessor register we look for it
1285 * via an integer which encodes all of:
1286 * coprocessor number
1287 * Crn, Crm, opc1, opc2 fields
1288 * 32 or 64 bit register (ie is it accessed via MRC/MCR
1289 * or via MRRC/MCRR?)
1290 * non-secure/secure bank (AArch32 only)
1291 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
1292 * (In this case crn and opc2 should be zero.)
1293 * For AArch64, there is no 32/64 bit size distinction;
1294 * instead all registers have a 2 bit op0, 3 bit op1 and op2,
1295 * and 4 bit CRn and CRm. The encoding patterns are chosen
1296 * to be easy to convert to and from the KVM encodings, and also
1297 * so that the hashtable can contain both AArch32 and AArch64
1298 * registers (to allow for interprocessing where we might run
1299 * 32 bit code on a 64 bit core).
1301 /* This bit is private to our hashtable cpreg; in KVM register
1302 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
1303 * in the upper bits of the 64 bit ID.
1305 #define CP_REG_AA64_SHIFT 28
1306 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
1308 /* To enable banking of coprocessor registers depending on ns-bit we
1309 * add a bit to distinguish between secure and non-secure cpregs in the
1310 * hashtable.
1312 #define CP_REG_NS_SHIFT 29
1313 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
1315 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \
1316 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \
1317 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
1319 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
1320 (CP_REG_AA64_MASK | \
1321 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \
1322 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
1323 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
1324 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
1325 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
1326 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
1328 /* Convert a full 64 bit KVM register ID to the truncated 32 bit
1329 * version used as a key for the coprocessor register hashtable
1331 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
1333 uint32_t cpregid = kvmid;
1334 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
1335 cpregid |= CP_REG_AA64_MASK;
1336 } else {
1337 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
1338 cpregid |= (1 << 15);
1341 /* KVM is always non-secure so add the NS flag on AArch32 register
1342 * entries.
1344 cpregid |= 1 << CP_REG_NS_SHIFT;
1346 return cpregid;
1349 /* Convert a truncated 32 bit hashtable key into the full
1350 * 64 bit KVM register ID.
1352 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
1354 uint64_t kvmid;
1356 if (cpregid & CP_REG_AA64_MASK) {
1357 kvmid = cpregid & ~CP_REG_AA64_MASK;
1358 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
1359 } else {
1360 kvmid = cpregid & ~(1 << 15);
1361 if (cpregid & (1 << 15)) {
1362 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
1363 } else {
1364 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
1367 return kvmid;
1370 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
1371 * special-behaviour cp reg and bits [15..8] indicate what behaviour
1372 * it has. Otherwise it is a simple cp reg, where CONST indicates that
1373 * TCG can assume the value to be constant (ie load at translate time)
1374 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
1375 * indicates that the TB should not be ended after a write to this register
1376 * (the default is that the TB ends after cp writes). OVERRIDE permits
1377 * a register definition to override a previous definition for the
1378 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
1379 * old must have the OVERRIDE bit set.
1380 * ALIAS indicates that this register is an alias view of some underlying
1381 * state which is also visible via another register, and that the other
1382 * register is handling migration and reset; registers marked ALIAS will not be
1383 * migrated but may have their state set by syncing of register state from KVM.
1384 * NO_RAW indicates that this register has no underlying state and does not
1385 * support raw access for state saving/loading; it will not be used for either
1386 * migration or KVM state synchronization. (Typically this is for "registers"
1387 * which are actually used as instructions for cache maintenance and so on.)
1388 * IO indicates that this register does I/O and therefore its accesses
1389 * need to be surrounded by gen_io_start()/gen_io_end(). In particular,
1390 * registers which implement clocks or timers require this.
1392 #define ARM_CP_SPECIAL 1
1393 #define ARM_CP_CONST 2
1394 #define ARM_CP_64BIT 4
1395 #define ARM_CP_SUPPRESS_TB_END 8
1396 #define ARM_CP_OVERRIDE 16
1397 #define ARM_CP_ALIAS 32
1398 #define ARM_CP_IO 64
1399 #define ARM_CP_NO_RAW 128
1400 #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8))
1401 #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8))
1402 #define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8))
1403 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8))
1404 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8))
1405 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA
1406 /* Used only as a terminator for ARMCPRegInfo lists */
1407 #define ARM_CP_SENTINEL 0xffff
1408 /* Mask of only the flag bits in a type field */
1409 #define ARM_CP_FLAG_MASK 0xff
1411 /* Valid values for ARMCPRegInfo state field, indicating which of
1412 * the AArch32 and AArch64 execution states this register is visible in.
1413 * If the reginfo doesn't explicitly specify then it is AArch32 only.
1414 * If the reginfo is declared to be visible in both states then a second
1415 * reginfo is synthesised for the AArch32 view of the AArch64 register,
1416 * such that the AArch32 view is the lower 32 bits of the AArch64 one.
1417 * Note that we rely on the values of these enums as we iterate through
1418 * the various states in some places.
1420 enum {
1421 ARM_CP_STATE_AA32 = 0,
1422 ARM_CP_STATE_AA64 = 1,
1423 ARM_CP_STATE_BOTH = 2,
1426 /* ARM CP register secure state flags. These flags identify security state
1427 * attributes for a given CP register entry.
1428 * The existence of both or neither secure and non-secure flags indicates that
1429 * the register has both a secure and non-secure hash entry. A single one of
1430 * these flags causes the register to only be hashed for the specified
1431 * security state.
1432 * Although definitions may have any combination of the S/NS bits, each
1433 * registered entry will only have one to identify whether the entry is secure
1434 * or non-secure.
1436 enum {
1437 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */
1438 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */
1441 /* Return true if cptype is a valid type field. This is used to try to
1442 * catch errors where the sentinel has been accidentally left off the end
1443 * of a list of registers.
1445 static inline bool cptype_valid(int cptype)
1447 return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
1448 || ((cptype & ARM_CP_SPECIAL) &&
1449 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
1452 /* Access rights:
1453 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
1454 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
1455 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
1456 * (ie any of the privileged modes in Secure state, or Monitor mode).
1457 * If a register is accessible in one privilege level it's always accessible
1458 * in higher privilege levels too. Since "Secure PL1" also follows this rule
1459 * (ie anything visible in PL2 is visible in S-PL1, some things are only
1460 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
1461 * terminology a little and call this PL3.
1462 * In AArch64 things are somewhat simpler as the PLx bits line up exactly
1463 * with the ELx exception levels.
1465 * If access permissions for a register are more complex than can be
1466 * described with these bits, then use a laxer set of restrictions, and
1467 * do the more restrictive/complex check inside a helper function.
1469 #define PL3_R 0x80
1470 #define PL3_W 0x40
1471 #define PL2_R (0x20 | PL3_R)
1472 #define PL2_W (0x10 | PL3_W)
1473 #define PL1_R (0x08 | PL2_R)
1474 #define PL1_W (0x04 | PL2_W)
1475 #define PL0_R (0x02 | PL1_R)
1476 #define PL0_W (0x01 | PL1_W)
1478 #define PL3_RW (PL3_R | PL3_W)
1479 #define PL2_RW (PL2_R | PL2_W)
1480 #define PL1_RW (PL1_R | PL1_W)
1481 #define PL0_RW (PL0_R | PL0_W)
1483 /* Return the highest implemented Exception Level */
1484 static inline int arm_highest_el(CPUARMState *env)
1486 if (arm_feature(env, ARM_FEATURE_EL3)) {
1487 return 3;
1489 if (arm_feature(env, ARM_FEATURE_EL2)) {
1490 return 2;
1492 return 1;
1495 /* Return the current Exception Level (as per ARMv8; note that this differs
1496 * from the ARMv7 Privilege Level).
1498 static inline int arm_current_el(CPUARMState *env)
1500 if (arm_feature(env, ARM_FEATURE_M)) {
1501 return !((env->v7m.exception == 0) && (env->v7m.control & 1));
1504 if (is_a64(env)) {
1505 return extract32(env->pstate, 2, 2);
1508 switch (env->uncached_cpsr & 0x1f) {
1509 case ARM_CPU_MODE_USR:
1510 return 0;
1511 case ARM_CPU_MODE_HYP:
1512 return 2;
1513 case ARM_CPU_MODE_MON:
1514 return 3;
1515 default:
1516 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
1517 /* If EL3 is 32-bit then all secure privileged modes run in
1518 * EL3
1520 return 3;
1523 return 1;
1527 typedef struct ARMCPRegInfo ARMCPRegInfo;
1529 typedef enum CPAccessResult {
1530 /* Access is permitted */
1531 CP_ACCESS_OK = 0,
1532 /* Access fails due to a configurable trap or enable which would
1533 * result in a categorized exception syndrome giving information about
1534 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
1535 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or
1536 * PL1 if in EL0, otherwise to the current EL).
1538 CP_ACCESS_TRAP = 1,
1539 /* Access fails and results in an exception syndrome 0x0 ("uncategorized").
1540 * Note that this is not a catch-all case -- the set of cases which may
1541 * result in this failure is specifically defined by the architecture.
1543 CP_ACCESS_TRAP_UNCATEGORIZED = 2,
1544 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */
1545 CP_ACCESS_TRAP_EL2 = 3,
1546 CP_ACCESS_TRAP_EL3 = 4,
1547 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */
1548 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
1549 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
1550 /* Access fails and results in an exception syndrome for an FP access,
1551 * trapped directly to EL2 or EL3
1553 CP_ACCESS_TRAP_FP_EL2 = 7,
1554 CP_ACCESS_TRAP_FP_EL3 = 8,
1555 } CPAccessResult;
1557 /* Access functions for coprocessor registers. These cannot fail and
1558 * may not raise exceptions.
1560 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
1561 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
1562 uint64_t value);
1563 /* Access permission check functions for coprocessor registers. */
1564 typedef CPAccessResult CPAccessFn(CPUARMState *env,
1565 const ARMCPRegInfo *opaque,
1566 bool isread);
1567 /* Hook function for register reset */
1568 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
1570 #define CP_ANY 0xff
1572 /* Definition of an ARM coprocessor register */
1573 struct ARMCPRegInfo {
1574 /* Name of register (useful mainly for debugging, need not be unique) */
1575 const char *name;
1576 /* Location of register: coprocessor number and (crn,crm,opc1,opc2)
1577 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
1578 * 'wildcard' field -- any value of that field in the MRC/MCR insn
1579 * will be decoded to this register. The register read and write
1580 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
1581 * used by the program, so it is possible to register a wildcard and
1582 * then behave differently on read/write if necessary.
1583 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
1584 * must both be zero.
1585 * For AArch64-visible registers, opc0 is also used.
1586 * Since there are no "coprocessors" in AArch64, cp is purely used as a
1587 * way to distinguish (for KVM's benefit) guest-visible system registers
1588 * from demuxed ones provided to preserve the "no side effects on
1589 * KVM register read/write from QEMU" semantics. cp==0x13 is guest
1590 * visible (to match KVM's encoding); cp==0 will be converted to
1591 * cp==0x13 when the ARMCPRegInfo is registered, for convenience.
1593 uint8_t cp;
1594 uint8_t crn;
1595 uint8_t crm;
1596 uint8_t opc0;
1597 uint8_t opc1;
1598 uint8_t opc2;
1599 /* Execution state in which this register is visible: ARM_CP_STATE_* */
1600 int state;
1601 /* Register type: ARM_CP_* bits/values */
1602 int type;
1603 /* Access rights: PL*_[RW] */
1604 int access;
1605 /* Security state: ARM_CP_SECSTATE_* bits/values */
1606 int secure;
1607 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
1608 * this register was defined: can be used to hand data through to the
1609 * register read/write functions, since they are passed the ARMCPRegInfo*.
1611 void *opaque;
1612 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if
1613 * fieldoffset is non-zero, the reset value of the register.
1615 uint64_t resetvalue;
1616 /* Offset of the field in CPUARMState for this register.
1618 * This is not needed if either:
1619 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
1620 * 2. both readfn and writefn are specified
1622 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
1624 /* Offsets of the secure and non-secure fields in CPUARMState for the
1625 * register if it is banked. These fields are only used during the static
1626 * registration of a register. During hashing the bank associated
1627 * with a given security state is copied to fieldoffset which is used from
1628 * there on out.
1630 * It is expected that register definitions use either fieldoffset or
1631 * bank_fieldoffsets in the definition but not both. It is also expected
1632 * that both bank offsets are set when defining a banked register. This
1633 * use indicates that a register is banked.
1635 ptrdiff_t bank_fieldoffsets[2];
1637 /* Function for making any access checks for this register in addition to
1638 * those specified by the 'access' permissions bits. If NULL, no extra
1639 * checks required. The access check is performed at runtime, not at
1640 * translate time.
1642 CPAccessFn *accessfn;
1643 /* Function for handling reads of this register. If NULL, then reads
1644 * will be done by loading from the offset into CPUARMState specified
1645 * by fieldoffset.
1647 CPReadFn *readfn;
1648 /* Function for handling writes of this register. If NULL, then writes
1649 * will be done by writing to the offset into CPUARMState specified
1650 * by fieldoffset.
1652 CPWriteFn *writefn;
1653 /* Function for doing a "raw" read; used when we need to copy
1654 * coprocessor state to the kernel for KVM or out for
1655 * migration. This only needs to be provided if there is also a
1656 * readfn and it has side effects (for instance clear-on-read bits).
1658 CPReadFn *raw_readfn;
1659 /* Function for doing a "raw" write; used when we need to copy KVM
1660 * kernel coprocessor state into userspace, or for inbound
1661 * migration. This only needs to be provided if there is also a
1662 * writefn and it masks out "unwritable" bits or has write-one-to-clear
1663 * or similar behaviour.
1665 CPWriteFn *raw_writefn;
1666 /* Function for resetting the register. If NULL, then reset will be done
1667 * by writing resetvalue to the field specified in fieldoffset. If
1668 * fieldoffset is 0 then no reset will be done.
1670 CPResetFn *resetfn;
1673 /* Macros which are lvalues for the field in CPUARMState for the
1674 * ARMCPRegInfo *ri.
1676 #define CPREG_FIELD32(env, ri) \
1677 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
1678 #define CPREG_FIELD64(env, ri) \
1679 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
1681 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
1683 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
1684 const ARMCPRegInfo *regs, void *opaque);
1685 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
1686 const ARMCPRegInfo *regs, void *opaque);
1687 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
1689 define_arm_cp_regs_with_opaque(cpu, regs, 0);
1691 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
1693 define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
1695 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
1697 /* CPWriteFn that can be used to implement writes-ignored behaviour */
1698 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
1699 uint64_t value);
1700 /* CPReadFn that can be used for read-as-zero behaviour */
1701 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
1703 /* CPResetFn that does nothing, for use if no reset is required even
1704 * if fieldoffset is non zero.
1706 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
1708 /* Return true if this reginfo struct's field in the cpu state struct
1709 * is 64 bits wide.
1711 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
1713 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
1716 static inline bool cp_access_ok(int current_el,
1717 const ARMCPRegInfo *ri, int isread)
1719 return (ri->access >> ((current_el * 2) + isread)) & 1;
1722 /* Raw read of a coprocessor register (as needed for migration, etc) */
1723 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri);
1726 * write_list_to_cpustate
1727 * @cpu: ARMCPU
1729 * For each register listed in the ARMCPU cpreg_indexes list, write
1730 * its value from the cpreg_values list into the ARMCPUState structure.
1731 * This updates TCG's working data structures from KVM data or
1732 * from incoming migration state.
1734 * Returns: true if all register values were updated correctly,
1735 * false if some register was unknown or could not be written.
1736 * Note that we do not stop early on failure -- we will attempt
1737 * writing all registers in the list.
1739 bool write_list_to_cpustate(ARMCPU *cpu);
1742 * write_cpustate_to_list:
1743 * @cpu: ARMCPU
1745 * For each register listed in the ARMCPU cpreg_indexes list, write
1746 * its value from the ARMCPUState structure into the cpreg_values list.
1747 * This is used to copy info from TCG's working data structures into
1748 * KVM or for outbound migration.
1750 * Returns: true if all register values were read correctly,
1751 * false if some register was unknown or could not be read.
1752 * Note that we do not stop early on failure -- we will attempt
1753 * reading all registers in the list.
1755 bool write_cpustate_to_list(ARMCPU *cpu);
1757 /* Does the core conform to the "MicroController" profile. e.g. Cortex-M3.
1758 Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
1759 conventional cores (ie. Application or Realtime profile). */
1761 #define IS_M(env) arm_feature(env, ARM_FEATURE_M)
1763 #define ARM_CPUID_TI915T 0x54029152
1764 #define ARM_CPUID_TI925T 0x54029252
1766 #if defined(CONFIG_USER_ONLY)
1767 #define TARGET_PAGE_BITS 12
1768 #else
1769 /* The ARM MMU allows 1k pages. */
1770 /* ??? Linux doesn't actually use these, and they're deprecated in recent
1771 architecture revisions. Maybe a configure option to disable them. */
1772 #define TARGET_PAGE_BITS 10
1773 #endif
1775 #if defined(TARGET_AARCH64)
1776 # define TARGET_PHYS_ADDR_SPACE_BITS 48
1777 # define TARGET_VIRT_ADDR_SPACE_BITS 64
1778 #else
1779 # define TARGET_PHYS_ADDR_SPACE_BITS 40
1780 # define TARGET_VIRT_ADDR_SPACE_BITS 32
1781 #endif
1783 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
1784 unsigned int target_el)
1786 CPUARMState *env = cs->env_ptr;
1787 unsigned int cur_el = arm_current_el(env);
1788 bool secure = arm_is_secure(env);
1789 bool pstate_unmasked;
1790 int8_t unmasked = 0;
1792 /* Don't take exceptions if they target a lower EL.
1793 * This check should catch any exceptions that would not be taken but left
1794 * pending.
1796 if (cur_el > target_el) {
1797 return false;
1800 switch (excp_idx) {
1801 case EXCP_FIQ:
1802 pstate_unmasked = !(env->daif & PSTATE_F);
1803 break;
1805 case EXCP_IRQ:
1806 pstate_unmasked = !(env->daif & PSTATE_I);
1807 break;
1809 case EXCP_VFIQ:
1810 if (secure || !(env->cp15.hcr_el2 & HCR_FMO)) {
1811 /* VFIQs are only taken when hypervized and non-secure. */
1812 return false;
1814 return !(env->daif & PSTATE_F);
1815 case EXCP_VIRQ:
1816 if (secure || !(env->cp15.hcr_el2 & HCR_IMO)) {
1817 /* VIRQs are only taken when hypervized and non-secure. */
1818 return false;
1820 return !(env->daif & PSTATE_I);
1821 default:
1822 g_assert_not_reached();
1825 /* Use the target EL, current execution state and SCR/HCR settings to
1826 * determine whether the corresponding CPSR bit is used to mask the
1827 * interrupt.
1829 if ((target_el > cur_el) && (target_el != 1)) {
1830 /* Exceptions targeting a higher EL may not be maskable */
1831 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
1832 /* 64-bit masking rules are simple: exceptions to EL3
1833 * can't be masked, and exceptions to EL2 can only be
1834 * masked from Secure state. The HCR and SCR settings
1835 * don't affect the masking logic, only the interrupt routing.
1837 if (target_el == 3 || !secure) {
1838 unmasked = 1;
1840 } else {
1841 /* The old 32-bit-only environment has a more complicated
1842 * masking setup. HCR and SCR bits not only affect interrupt
1843 * routing but also change the behaviour of masking.
1845 bool hcr, scr;
1847 switch (excp_idx) {
1848 case EXCP_FIQ:
1849 /* If FIQs are routed to EL3 or EL2 then there are cases where
1850 * we override the CPSR.F in determining if the exception is
1851 * masked or not. If neither of these are set then we fall back
1852 * to the CPSR.F setting otherwise we further assess the state
1853 * below.
1855 hcr = (env->cp15.hcr_el2 & HCR_FMO);
1856 scr = (env->cp15.scr_el3 & SCR_FIQ);
1858 /* When EL3 is 32-bit, the SCR.FW bit controls whether the
1859 * CPSR.F bit masks FIQ interrupts when taken in non-secure
1860 * state. If SCR.FW is set then FIQs can be masked by CPSR.F
1861 * when non-secure but only when FIQs are only routed to EL3.
1863 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr);
1864 break;
1865 case EXCP_IRQ:
1866 /* When EL3 execution state is 32-bit, if HCR.IMO is set then
1867 * we may override the CPSR.I masking when in non-secure state.
1868 * The SCR.IRQ setting has already been taken into consideration
1869 * when setting the target EL, so it does not have a further
1870 * affect here.
1872 hcr = (env->cp15.hcr_el2 & HCR_IMO);
1873 scr = false;
1874 break;
1875 default:
1876 g_assert_not_reached();
1879 if ((scr || hcr) && !secure) {
1880 unmasked = 1;
1885 /* The PSTATE bits only mask the interrupt if we have not overriden the
1886 * ability above.
1888 return unmasked || pstate_unmasked;
1891 #define cpu_init(cpu_model) CPU(cpu_arm_init(cpu_model))
1893 #define cpu_signal_handler cpu_arm_signal_handler
1894 #define cpu_list arm_cpu_list
1896 /* ARM has the following "translation regimes" (as the ARM ARM calls them):
1898 * If EL3 is 64-bit:
1899 * + NonSecure EL1 & 0 stage 1
1900 * + NonSecure EL1 & 0 stage 2
1901 * + NonSecure EL2
1902 * + Secure EL1 & EL0
1903 * + Secure EL3
1904 * If EL3 is 32-bit:
1905 * + NonSecure PL1 & 0 stage 1
1906 * + NonSecure PL1 & 0 stage 2
1907 * + NonSecure PL2
1908 * + Secure PL0 & PL1
1909 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.)
1911 * For QEMU, an mmu_idx is not quite the same as a translation regime because:
1912 * 1. we need to split the "EL1 & 0" regimes into two mmu_idxes, because they
1913 * may differ in access permissions even if the VA->PA map is the same
1914 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2
1915 * translation, which means that we have one mmu_idx that deals with two
1916 * concatenated translation regimes [this sort of combined s1+2 TLB is
1917 * architecturally permitted]
1918 * 3. we don't need to allocate an mmu_idx to translations that we won't be
1919 * handling via the TLB. The only way to do a stage 1 translation without
1920 * the immediate stage 2 translation is via the ATS or AT system insns,
1921 * which can be slow-pathed and always do a page table walk.
1922 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3"
1923 * translation regimes, because they map reasonably well to each other
1924 * and they can't both be active at the same time.
1925 * This gives us the following list of mmu_idx values:
1927 * NS EL0 (aka NS PL0) stage 1+2
1928 * NS EL1 (aka NS PL1) stage 1+2
1929 * NS EL2 (aka NS PL2)
1930 * S EL3 (aka S PL1)
1931 * S EL0 (aka S PL0)
1932 * S EL1 (not used if EL3 is 32 bit)
1933 * NS EL0+1 stage 2
1935 * (The last of these is an mmu_idx because we want to be able to use the TLB
1936 * for the accesses done as part of a stage 1 page table walk, rather than
1937 * having to walk the stage 2 page table over and over.)
1939 * Our enumeration includes at the end some entries which are not "true"
1940 * mmu_idx values in that they don't have corresponding TLBs and are only
1941 * valid for doing slow path page table walks.
1943 * The constant names here are patterned after the general style of the names
1944 * of the AT/ATS operations.
1945 * The values used are carefully arranged to make mmu_idx => EL lookup easy.
1947 typedef enum ARMMMUIdx {
1948 ARMMMUIdx_S12NSE0 = 0,
1949 ARMMMUIdx_S12NSE1 = 1,
1950 ARMMMUIdx_S1E2 = 2,
1951 ARMMMUIdx_S1E3 = 3,
1952 ARMMMUIdx_S1SE0 = 4,
1953 ARMMMUIdx_S1SE1 = 5,
1954 ARMMMUIdx_S2NS = 6,
1955 /* Indexes below here don't have TLBs and are used only for AT system
1956 * instructions or for the first stage of an S12 page table walk.
1958 ARMMMUIdx_S1NSE0 = 7,
1959 ARMMMUIdx_S1NSE1 = 8,
1960 } ARMMMUIdx;
1962 #define MMU_USER_IDX 0
1964 /* Return the exception level we're running at if this is our mmu_idx */
1965 static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
1967 assert(mmu_idx < ARMMMUIdx_S2NS);
1968 return mmu_idx & 3;
1971 /* Determine the current mmu_idx to use for normal loads/stores */
1972 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
1974 int el = arm_current_el(env);
1976 if (el < 2 && arm_is_secure_below_el3(env)) {
1977 return ARMMMUIdx_S1SE0 + el;
1979 return el;
1982 /* Indexes used when registering address spaces with cpu_address_space_init */
1983 typedef enum ARMASIdx {
1984 ARMASIdx_NS = 0,
1985 ARMASIdx_S = 1,
1986 } ARMASIdx;
1988 /* Return the Exception Level targeted by debug exceptions. */
1989 static inline int arm_debug_target_el(CPUARMState *env)
1991 bool secure = arm_is_secure(env);
1992 bool route_to_el2 = false;
1994 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) {
1995 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE ||
1996 env->cp15.mdcr_el2 & (1 << 8);
1999 if (route_to_el2) {
2000 return 2;
2001 } else if (arm_feature(env, ARM_FEATURE_EL3) &&
2002 !arm_el_is_aa64(env, 3) && secure) {
2003 return 3;
2004 } else {
2005 return 1;
2009 static inline bool aa64_generate_debug_exceptions(CPUARMState *env)
2011 if (arm_is_secure(env)) {
2012 /* MDCR_EL3.SDD disables debug events from Secure state */
2013 if (extract32(env->cp15.mdcr_el3, 16, 1) != 0
2014 || arm_current_el(env) == 3) {
2015 return false;
2019 if (arm_current_el(env) == arm_debug_target_el(env)) {
2020 if ((extract32(env->cp15.mdscr_el1, 13, 1) == 0)
2021 || (env->daif & PSTATE_D)) {
2022 return false;
2025 return true;
2028 static inline bool aa32_generate_debug_exceptions(CPUARMState *env)
2030 int el = arm_current_el(env);
2032 if (el == 0 && arm_el_is_aa64(env, 1)) {
2033 return aa64_generate_debug_exceptions(env);
2036 if (arm_is_secure(env)) {
2037 int spd;
2039 if (el == 0 && (env->cp15.sder & 1)) {
2040 /* SDER.SUIDEN means debug exceptions from Secure EL0
2041 * are always enabled. Otherwise they are controlled by
2042 * SDCR.SPD like those from other Secure ELs.
2044 return true;
2047 spd = extract32(env->cp15.mdcr_el3, 14, 2);
2048 switch (spd) {
2049 case 1:
2050 /* SPD == 0b01 is reserved, but behaves as 0b00. */
2051 case 0:
2052 /* For 0b00 we return true if external secure invasive debug
2053 * is enabled. On real hardware this is controlled by external
2054 * signals to the core. QEMU always permits debug, and behaves
2055 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high.
2057 return true;
2058 case 2:
2059 return false;
2060 case 3:
2061 return true;
2065 return el != 2;
2068 /* Return true if debugging exceptions are currently enabled.
2069 * This corresponds to what in ARM ARM pseudocode would be
2070 * if UsingAArch32() then
2071 * return AArch32.GenerateDebugExceptions()
2072 * else
2073 * return AArch64.GenerateDebugExceptions()
2074 * We choose to push the if() down into this function for clarity,
2075 * since the pseudocode has it at all callsites except for the one in
2076 * CheckSoftwareStep(), where it is elided because both branches would
2077 * always return the same value.
2079 * Parts of the pseudocode relating to EL2 and EL3 are omitted because we
2080 * don't yet implement those exception levels or their associated trap bits.
2082 static inline bool arm_generate_debug_exceptions(CPUARMState *env)
2084 if (env->aarch64) {
2085 return aa64_generate_debug_exceptions(env);
2086 } else {
2087 return aa32_generate_debug_exceptions(env);
2091 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check
2092 * implicitly means this always returns false in pre-v8 CPUs.)
2094 static inline bool arm_singlestep_active(CPUARMState *env)
2096 return extract32(env->cp15.mdscr_el1, 0, 1)
2097 && arm_el_is_aa64(env, arm_debug_target_el(env))
2098 && arm_generate_debug_exceptions(env);
2101 static inline bool arm_sctlr_b(CPUARMState *env)
2103 return
2104 /* We need not implement SCTLR.ITD in user-mode emulation, so
2105 * let linux-user ignore the fact that it conflicts with SCTLR_B.
2106 * This lets people run BE32 binaries with "-cpu any".
2108 #ifndef CONFIG_USER_ONLY
2109 !arm_feature(env, ARM_FEATURE_V7) &&
2110 #endif
2111 (env->cp15.sctlr_el[1] & SCTLR_B) != 0;
2114 /* Return true if the processor is in big-endian mode. */
2115 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
2117 int cur_el;
2119 /* In 32bit endianness is determined by looking at CPSR's E bit */
2120 if (!is_a64(env)) {
2121 return
2122 #ifdef CONFIG_USER_ONLY
2123 /* In system mode, BE32 is modelled in line with the
2124 * architecture (as word-invariant big-endianness), where loads
2125 * and stores are done little endian but from addresses which
2126 * are adjusted by XORing with the appropriate constant. So the
2127 * endianness to use for the raw data access is not affected by
2128 * SCTLR.B.
2129 * In user mode, however, we model BE32 as byte-invariant
2130 * big-endianness (because user-only code cannot tell the
2131 * difference), and so we need to use a data access endianness
2132 * that depends on SCTLR.B.
2134 arm_sctlr_b(env) ||
2135 #endif
2136 ((env->uncached_cpsr & CPSR_E) ? 1 : 0);
2139 cur_el = arm_current_el(env);
2141 if (cur_el == 0) {
2142 return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0;
2145 return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0;
2148 #include "exec/cpu-all.h"
2150 /* Bit usage in the TB flags field: bit 31 indicates whether we are
2151 * in 32 or 64 bit mode. The meaning of the other bits depends on that.
2152 * We put flags which are shared between 32 and 64 bit mode at the top
2153 * of the word, and flags which apply to only one mode at the bottom.
2155 #define ARM_TBFLAG_AARCH64_STATE_SHIFT 31
2156 #define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT)
2157 #define ARM_TBFLAG_MMUIDX_SHIFT 28
2158 #define ARM_TBFLAG_MMUIDX_MASK (0x7 << ARM_TBFLAG_MMUIDX_SHIFT)
2159 #define ARM_TBFLAG_SS_ACTIVE_SHIFT 27
2160 #define ARM_TBFLAG_SS_ACTIVE_MASK (1 << ARM_TBFLAG_SS_ACTIVE_SHIFT)
2161 #define ARM_TBFLAG_PSTATE_SS_SHIFT 26
2162 #define ARM_TBFLAG_PSTATE_SS_MASK (1 << ARM_TBFLAG_PSTATE_SS_SHIFT)
2163 /* Target EL if we take a floating-point-disabled exception */
2164 #define ARM_TBFLAG_FPEXC_EL_SHIFT 24
2165 #define ARM_TBFLAG_FPEXC_EL_MASK (0x3 << ARM_TBFLAG_FPEXC_EL_SHIFT)
2167 /* Bit usage when in AArch32 state: */
2168 #define ARM_TBFLAG_THUMB_SHIFT 0
2169 #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT)
2170 #define ARM_TBFLAG_VECLEN_SHIFT 1
2171 #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
2172 #define ARM_TBFLAG_VECSTRIDE_SHIFT 4
2173 #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
2174 #define ARM_TBFLAG_VFPEN_SHIFT 7
2175 #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT)
2176 #define ARM_TBFLAG_CONDEXEC_SHIFT 8
2177 #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
2178 #define ARM_TBFLAG_SCTLR_B_SHIFT 16
2179 #define ARM_TBFLAG_SCTLR_B_MASK (1 << ARM_TBFLAG_SCTLR_B_SHIFT)
2180 /* We store the bottom two bits of the CPAR as TB flags and handle
2181 * checks on the other bits at runtime
2183 #define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17
2184 #define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT)
2185 /* Indicates whether cp register reads and writes by guest code should access
2186 * the secure or nonsecure bank of banked registers; note that this is not
2187 * the same thing as the current security state of the processor!
2189 #define ARM_TBFLAG_NS_SHIFT 19
2190 #define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT)
2191 #define ARM_TBFLAG_BE_DATA_SHIFT 20
2192 #define ARM_TBFLAG_BE_DATA_MASK (1 << ARM_TBFLAG_BE_DATA_SHIFT)
2194 /* Bit usage when in AArch64 state: currently we have no A64 specific bits */
2196 /* some convenience accessor macros */
2197 #define ARM_TBFLAG_AARCH64_STATE(F) \
2198 (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT)
2199 #define ARM_TBFLAG_MMUIDX(F) \
2200 (((F) & ARM_TBFLAG_MMUIDX_MASK) >> ARM_TBFLAG_MMUIDX_SHIFT)
2201 #define ARM_TBFLAG_SS_ACTIVE(F) \
2202 (((F) & ARM_TBFLAG_SS_ACTIVE_MASK) >> ARM_TBFLAG_SS_ACTIVE_SHIFT)
2203 #define ARM_TBFLAG_PSTATE_SS(F) \
2204 (((F) & ARM_TBFLAG_PSTATE_SS_MASK) >> ARM_TBFLAG_PSTATE_SS_SHIFT)
2205 #define ARM_TBFLAG_FPEXC_EL(F) \
2206 (((F) & ARM_TBFLAG_FPEXC_EL_MASK) >> ARM_TBFLAG_FPEXC_EL_SHIFT)
2207 #define ARM_TBFLAG_THUMB(F) \
2208 (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
2209 #define ARM_TBFLAG_VECLEN(F) \
2210 (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
2211 #define ARM_TBFLAG_VECSTRIDE(F) \
2212 (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
2213 #define ARM_TBFLAG_VFPEN(F) \
2214 (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
2215 #define ARM_TBFLAG_CONDEXEC(F) \
2216 (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
2217 #define ARM_TBFLAG_SCTLR_B(F) \
2218 (((F) & ARM_TBFLAG_SCTLR_B_MASK) >> ARM_TBFLAG_SCTLR_B_SHIFT)
2219 #define ARM_TBFLAG_XSCALE_CPAR(F) \
2220 (((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT)
2221 #define ARM_TBFLAG_NS(F) \
2222 (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT)
2223 #define ARM_TBFLAG_BE_DATA(F) \
2224 (((F) & ARM_TBFLAG_BE_DATA_MASK) >> ARM_TBFLAG_BE_DATA_SHIFT)
2226 static inline bool bswap_code(bool sctlr_b)
2228 #ifdef CONFIG_USER_ONLY
2229 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian.
2230 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0
2231 * would also end up as a mixed-endian mode with BE code, LE data.
2233 return
2234 #ifdef TARGET_WORDS_BIGENDIAN
2236 #endif
2237 sctlr_b;
2238 #else
2239 /* All code access in ARM is little endian, and there are no loaders
2240 * doing swaps that need to be reversed
2242 return 0;
2243 #endif
2246 /* Return the exception level to which FP-disabled exceptions should
2247 * be taken, or 0 if FP is enabled.
2249 static inline int fp_exception_el(CPUARMState *env)
2251 int fpen;
2252 int cur_el = arm_current_el(env);
2254 /* CPACR and the CPTR registers don't exist before v6, so FP is
2255 * always accessible
2257 if (!arm_feature(env, ARM_FEATURE_V6)) {
2258 return 0;
2261 /* The CPACR controls traps to EL1, or PL1 if we're 32 bit:
2262 * 0, 2 : trap EL0 and EL1/PL1 accesses
2263 * 1 : trap only EL0 accesses
2264 * 3 : trap no accesses
2266 fpen = extract32(env->cp15.cpacr_el1, 20, 2);
2267 switch (fpen) {
2268 case 0:
2269 case 2:
2270 if (cur_el == 0 || cur_el == 1) {
2271 /* Trap to PL1, which might be EL1 or EL3 */
2272 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
2273 return 3;
2275 return 1;
2277 if (cur_el == 3 && !is_a64(env)) {
2278 /* Secure PL1 running at EL3 */
2279 return 3;
2281 break;
2282 case 1:
2283 if (cur_el == 0) {
2284 return 1;
2286 break;
2287 case 3:
2288 break;
2291 /* For the CPTR registers we don't need to guard with an ARM_FEATURE
2292 * check because zero bits in the registers mean "don't trap".
2295 /* CPTR_EL2 : present in v7VE or v8 */
2296 if (cur_el <= 2 && extract32(env->cp15.cptr_el[2], 10, 1)
2297 && !arm_is_secure_below_el3(env)) {
2298 /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */
2299 return 2;
2302 /* CPTR_EL3 : present in v8 */
2303 if (extract32(env->cp15.cptr_el[3], 10, 1)) {
2304 /* Trap all FP ops to EL3 */
2305 return 3;
2308 return 0;
2311 #ifdef CONFIG_USER_ONLY
2312 static inline bool arm_cpu_bswap_data(CPUARMState *env)
2314 return
2315 #ifdef TARGET_WORDS_BIGENDIAN
2317 #endif
2318 arm_cpu_data_is_big_endian(env);
2320 #endif
2322 static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
2323 target_ulong *cs_base, uint32_t *flags)
2325 if (is_a64(env)) {
2326 *pc = env->pc;
2327 *flags = ARM_TBFLAG_AARCH64_STATE_MASK;
2328 } else {
2329 *pc = env->regs[15];
2330 *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
2331 | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
2332 | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
2333 | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT)
2334 | (arm_sctlr_b(env) << ARM_TBFLAG_SCTLR_B_SHIFT);
2335 if (!(access_secure_reg(env))) {
2336 *flags |= ARM_TBFLAG_NS_MASK;
2338 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)
2339 || arm_el_is_aa64(env, 1)) {
2340 *flags |= ARM_TBFLAG_VFPEN_MASK;
2342 *flags |= (extract32(env->cp15.c15_cpar, 0, 2)
2343 << ARM_TBFLAG_XSCALE_CPAR_SHIFT);
2346 *flags |= (cpu_mmu_index(env, false) << ARM_TBFLAG_MMUIDX_SHIFT);
2347 /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
2348 * states defined in the ARM ARM for software singlestep:
2349 * SS_ACTIVE PSTATE.SS State
2350 * 0 x Inactive (the TB flag for SS is always 0)
2351 * 1 0 Active-pending
2352 * 1 1 Active-not-pending
2354 if (arm_singlestep_active(env)) {
2355 *flags |= ARM_TBFLAG_SS_ACTIVE_MASK;
2356 if (is_a64(env)) {
2357 if (env->pstate & PSTATE_SS) {
2358 *flags |= ARM_TBFLAG_PSTATE_SS_MASK;
2360 } else {
2361 if (env->uncached_cpsr & PSTATE_SS) {
2362 *flags |= ARM_TBFLAG_PSTATE_SS_MASK;
2366 if (arm_cpu_data_is_big_endian(env)) {
2367 *flags |= ARM_TBFLAG_BE_DATA_MASK;
2369 *flags |= fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT;
2371 *cs_base = 0;
2374 enum {
2375 QEMU_PSCI_CONDUIT_DISABLED = 0,
2376 QEMU_PSCI_CONDUIT_SMC = 1,
2377 QEMU_PSCI_CONDUIT_HVC = 2,
2380 #ifndef CONFIG_USER_ONLY
2381 /* Return the address space index to use for a memory access */
2382 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
2384 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS;
2387 /* Return the AddressSpace to use for a memory access
2388 * (which depends on whether the access is S or NS, and whether
2389 * the board gave us a separate AddressSpace for S accesses).
2391 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs)
2393 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs));
2395 #endif
2398 * arm_register_el_change_hook:
2399 * Register a hook function which will be called back whenever this
2400 * CPU changes exception level or mode. The hook function will be
2401 * passed a pointer to the ARMCPU and the opaque data pointer passed
2402 * to this function when the hook was registered.
2404 * Note that we currently only support registering a single hook function,
2405 * and will assert if this function is called twice.
2406 * This facility is intended for the use of the GICv3 emulation.
2408 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook,
2409 void *opaque);
2412 * arm_get_el_change_hook_opaque:
2413 * Return the opaque data that will be used by the el_change_hook
2414 * for this CPU.
2416 static inline void *arm_get_el_change_hook_opaque(ARMCPU *cpu)
2418 return cpu->el_change_hook_opaque;
2421 #endif