disas/riscv.c

   1 /*
   2  * QEMU RISC-V Disassembler
   3  *
   4  * Copyright (c) 2016-2017 Michael Clark <michaeljclark@mac.com>
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "disas/dis-asm.h"
  22
  23
  24 /* types */
  25
  26 typedef uint64_t rv_inst;
  27 typedef uint16_t rv_opcode;
  28
  29 /* enums */
  30
  31 typedef enum {
  32     rv32,
  33     rv64,
  34     rv128
  35 } rv_isa;
  36
  37 typedef enum {
  38     rv_rm_rne = 0,
  39     rv_rm_rtz = 1,
  40     rv_rm_rdn = 2,
  41     rv_rm_rup = 3,
  42     rv_rm_rmm = 4,
  43     rv_rm_dyn = 7,
  44 } rv_rm;
  45
  46 typedef enum {
  47     rv_fence_i = 8,
  48     rv_fence_o = 4,
  49     rv_fence_r = 2,
  50     rv_fence_w = 1,
  51 } rv_fence;
  52
  53 typedef enum {
  54     rv_ireg_zero,
  55     rv_ireg_ra,
  56     rv_ireg_sp,
  57     rv_ireg_gp,
  58     rv_ireg_tp,
  59     rv_ireg_t0,
  60     rv_ireg_t1,
  61     rv_ireg_t2,
  62     rv_ireg_s0,
  63     rv_ireg_s1,
  64     rv_ireg_a0,
  65     rv_ireg_a1,
  66     rv_ireg_a2,
  67     rv_ireg_a3,
  68     rv_ireg_a4,
  69     rv_ireg_a5,
  70     rv_ireg_a6,
  71     rv_ireg_a7,
  72     rv_ireg_s2,
  73     rv_ireg_s3,
  74     rv_ireg_s4,
  75     rv_ireg_s5,
  76     rv_ireg_s6,
  77     rv_ireg_s7,
  78     rv_ireg_s8,
  79     rv_ireg_s9,
  80     rv_ireg_s10,
  81     rv_ireg_s11,
  82     rv_ireg_t3,
  83     rv_ireg_t4,
  84     rv_ireg_t5,
  85     rv_ireg_t6,
  86 } rv_ireg;
  87
  88 typedef enum {
  89     rvc_end,
  90     rvc_rd_eq_ra,
  91     rvc_rd_eq_x0,
  92     rvc_rs1_eq_x0,
  93     rvc_rs2_eq_x0,
  94     rvc_rs2_eq_rs1,
  95     rvc_rs1_eq_ra,
  96     rvc_imm_eq_zero,
  97     rvc_imm_eq_n1,
  98     rvc_imm_eq_p1,
  99     rvc_csr_eq_0x001,
 100     rvc_csr_eq_0x002,
 101     rvc_csr_eq_0x003,
 102     rvc_csr_eq_0xc00,
 103     rvc_csr_eq_0xc01,
 104     rvc_csr_eq_0xc02,
 105     rvc_csr_eq_0xc80,
 106     rvc_csr_eq_0xc81,
 107     rvc_csr_eq_0xc82,
 108 } rvc_constraint;
 109
 110 typedef enum {
 111     rv_codec_illegal,
 112     rv_codec_none,
 113     rv_codec_u,
 114     rv_codec_uj,
 115     rv_codec_i,
 116     rv_codec_i_sh5,
 117     rv_codec_i_sh6,
 118     rv_codec_i_sh7,
 119     rv_codec_i_csr,
 120     rv_codec_s,
 121     rv_codec_sb,
 122     rv_codec_r,
 123     rv_codec_r_m,
 124     rv_codec_r4_m,
 125     rv_codec_r_a,
 126     rv_codec_r_l,
 127     rv_codec_r_f,
 128     rv_codec_cb,
 129     rv_codec_cb_imm,
 130     rv_codec_cb_sh5,
 131     rv_codec_cb_sh6,
 132     rv_codec_ci,
 133     rv_codec_ci_sh5,
 134     rv_codec_ci_sh6,
 135     rv_codec_ci_16sp,
 136     rv_codec_ci_lwsp,
 137     rv_codec_ci_ldsp,
 138     rv_codec_ci_lqsp,
 139     rv_codec_ci_li,
 140     rv_codec_ci_lui,
 141     rv_codec_ci_none,
 142     rv_codec_ciw_4spn,
 143     rv_codec_cj,
 144     rv_codec_cj_jal,
 145     rv_codec_cl_lw,
 146     rv_codec_cl_ld,
 147     rv_codec_cl_lq,
 148     rv_codec_cr,
 149     rv_codec_cr_mv,
 150     rv_codec_cr_jalr,
 151     rv_codec_cr_jr,
 152     rv_codec_cs,
 153     rv_codec_cs_sw,
 154     rv_codec_cs_sd,
 155     rv_codec_cs_sq,
 156     rv_codec_css_swsp,
 157     rv_codec_css_sdsp,
 158     rv_codec_css_sqsp,
 159     rv_codec_k_bs,
 160     rv_codec_k_rnum,
 161     rv_codec_v_r,
 162     rv_codec_v_ldst,
 163     rv_codec_v_i,
 164     rv_codec_vsetvli,
 165     rv_codec_vsetivli,
 166     rv_codec_zcb_ext,
 167     rv_codec_zcb_mul,
 168     rv_codec_zcb_lb,
 169     rv_codec_zcb_lh,
 170     rv_codec_zcmp_cm_pushpop,
 171     rv_codec_zcmp_cm_mv,
 172     rv_codec_zcmt_jt,
 173 } rv_codec;
 174
 175 typedef enum {
 176     rv_op_illegal = 0,
 177     rv_op_lui = 1,
 178     rv_op_auipc = 2,
 179     rv_op_jal = 3,
 180     rv_op_jalr = 4,
 181     rv_op_beq = 5,
 182     rv_op_bne = 6,
 183     rv_op_blt = 7,
 184     rv_op_bge = 8,
 185     rv_op_bltu = 9,
 186     rv_op_bgeu = 10,
 187     rv_op_lb = 11,
 188     rv_op_lh = 12,
 189     rv_op_lw = 13,
 190     rv_op_lbu = 14,
 191     rv_op_lhu = 15,
 192     rv_op_sb = 16,
 193     rv_op_sh = 17,
 194     rv_op_sw = 18,
 195     rv_op_addi = 19,
 196     rv_op_slti = 20,
 197     rv_op_sltiu = 21,
 198     rv_op_xori = 22,
 199     rv_op_ori = 23,
 200     rv_op_andi = 24,
 201     rv_op_slli = 25,
 202     rv_op_srli = 26,
 203     rv_op_srai = 27,
 204     rv_op_add = 28,
 205     rv_op_sub = 29,
 206     rv_op_sll = 30,
 207     rv_op_slt = 31,
 208     rv_op_sltu = 32,
 209     rv_op_xor = 33,
 210     rv_op_srl = 34,
 211     rv_op_sra = 35,
 212     rv_op_or = 36,
 213     rv_op_and = 37,
 214     rv_op_fence = 38,
 215     rv_op_fence_i = 39,
 216     rv_op_lwu = 40,
 217     rv_op_ld = 41,
 218     rv_op_sd = 42,
 219     rv_op_addiw = 43,
 220     rv_op_slliw = 44,
 221     rv_op_srliw = 45,
 222     rv_op_sraiw = 46,
 223     rv_op_addw = 47,
 224     rv_op_subw = 48,
 225     rv_op_sllw = 49,
 226     rv_op_srlw = 50,
 227     rv_op_sraw = 51,
 228     rv_op_ldu = 52,
 229     rv_op_lq = 53,
 230     rv_op_sq = 54,
 231     rv_op_addid = 55,
 232     rv_op_sllid = 56,
 233     rv_op_srlid = 57,
 234     rv_op_sraid = 58,
 235     rv_op_addd = 59,
 236     rv_op_subd = 60,
 237     rv_op_slld = 61,
 238     rv_op_srld = 62,
 239     rv_op_srad = 63,
 240     rv_op_mul = 64,
 241     rv_op_mulh = 65,
 242     rv_op_mulhsu = 66,
 243     rv_op_mulhu = 67,
 244     rv_op_div = 68,
 245     rv_op_divu = 69,
 246     rv_op_rem = 70,
 247     rv_op_remu = 71,
 248     rv_op_mulw = 72,
 249     rv_op_divw = 73,
 250     rv_op_divuw = 74,
 251     rv_op_remw = 75,
 252     rv_op_remuw = 76,
 253     rv_op_muld = 77,
 254     rv_op_divd = 78,
 255     rv_op_divud = 79,
 256     rv_op_remd = 80,
 257     rv_op_remud = 81,
 258     rv_op_lr_w = 82,
 259     rv_op_sc_w = 83,
 260     rv_op_amoswap_w = 84,
 261     rv_op_amoadd_w = 85,
 262     rv_op_amoxor_w = 86,
 263     rv_op_amoor_w = 87,
 264     rv_op_amoand_w = 88,
 265     rv_op_amomin_w = 89,
 266     rv_op_amomax_w = 90,
 267     rv_op_amominu_w = 91,
 268     rv_op_amomaxu_w = 92,
 269     rv_op_lr_d = 93,
 270     rv_op_sc_d = 94,
 271     rv_op_amoswap_d = 95,
 272     rv_op_amoadd_d = 96,
 273     rv_op_amoxor_d = 97,
 274     rv_op_amoor_d = 98,
 275     rv_op_amoand_d = 99,
 276     rv_op_amomin_d = 100,
 277     rv_op_amomax_d = 101,
 278     rv_op_amominu_d = 102,
 279     rv_op_amomaxu_d = 103,
 280     rv_op_lr_q = 104,
 281     rv_op_sc_q = 105,
 282     rv_op_amoswap_q = 106,
 283     rv_op_amoadd_q = 107,
 284     rv_op_amoxor_q = 108,
 285     rv_op_amoor_q = 109,
 286     rv_op_amoand_q = 110,
 287     rv_op_amomin_q = 111,
 288     rv_op_amomax_q = 112,
 289     rv_op_amominu_q = 113,
 290     rv_op_amomaxu_q = 114,
 291     rv_op_ecall = 115,
 292     rv_op_ebreak = 116,
 293     rv_op_uret = 117,
 294     rv_op_sret = 118,
 295     rv_op_hret = 119,
 296     rv_op_mret = 120,
 297     rv_op_dret = 121,
 298     rv_op_sfence_vm = 122,
 299     rv_op_sfence_vma = 123,
 300     rv_op_wfi = 124,
 301     rv_op_csrrw = 125,
 302     rv_op_csrrs = 126,
 303     rv_op_csrrc = 127,
 304     rv_op_csrrwi = 128,
 305     rv_op_csrrsi = 129,
 306     rv_op_csrrci = 130,
 307     rv_op_flw = 131,
 308     rv_op_fsw = 132,
 309     rv_op_fmadd_s = 133,
 310     rv_op_fmsub_s = 134,
 311     rv_op_fnmsub_s = 135,
 312     rv_op_fnmadd_s = 136,
 313     rv_op_fadd_s = 137,
 314     rv_op_fsub_s = 138,
 315     rv_op_fmul_s = 139,
 316     rv_op_fdiv_s = 140,
 317     rv_op_fsgnj_s = 141,
 318     rv_op_fsgnjn_s = 142,
 319     rv_op_fsgnjx_s = 143,
 320     rv_op_fmin_s = 144,
 321     rv_op_fmax_s = 145,
 322     rv_op_fsqrt_s = 146,
 323     rv_op_fle_s = 147,
 324     rv_op_flt_s = 148,
 325     rv_op_feq_s = 149,
 326     rv_op_fcvt_w_s = 150,
 327     rv_op_fcvt_wu_s = 151,
 328     rv_op_fcvt_s_w = 152,
 329     rv_op_fcvt_s_wu = 153,
 330     rv_op_fmv_x_s = 154,
 331     rv_op_fclass_s = 155,
 332     rv_op_fmv_s_x = 156,
 333     rv_op_fcvt_l_s = 157,
 334     rv_op_fcvt_lu_s = 158,
 335     rv_op_fcvt_s_l = 159,
 336     rv_op_fcvt_s_lu = 160,
 337     rv_op_fld = 161,
 338     rv_op_fsd = 162,
 339     rv_op_fmadd_d = 163,
 340     rv_op_fmsub_d = 164,
 341     rv_op_fnmsub_d = 165,
 342     rv_op_fnmadd_d = 166,
 343     rv_op_fadd_d = 167,
 344     rv_op_fsub_d = 168,
 345     rv_op_fmul_d = 169,
 346     rv_op_fdiv_d = 170,
 347     rv_op_fsgnj_d = 171,
 348     rv_op_fsgnjn_d = 172,
 349     rv_op_fsgnjx_d = 173,
 350     rv_op_fmin_d = 174,
 351     rv_op_fmax_d = 175,
 352     rv_op_fcvt_s_d = 176,
 353     rv_op_fcvt_d_s = 177,
 354     rv_op_fsqrt_d = 178,
 355     rv_op_fle_d = 179,
 356     rv_op_flt_d = 180,
 357     rv_op_feq_d = 181,
 358     rv_op_fcvt_w_d = 182,
 359     rv_op_fcvt_wu_d = 183,
 360     rv_op_fcvt_d_w = 184,
 361     rv_op_fcvt_d_wu = 185,
 362     rv_op_fclass_d = 186,
 363     rv_op_fcvt_l_d = 187,
 364     rv_op_fcvt_lu_d = 188,
 365     rv_op_fmv_x_d = 189,
 366     rv_op_fcvt_d_l = 190,
 367     rv_op_fcvt_d_lu = 191,
 368     rv_op_fmv_d_x = 192,
 369     rv_op_flq = 193,
 370     rv_op_fsq = 194,
 371     rv_op_fmadd_q = 195,
 372     rv_op_fmsub_q = 196,
 373     rv_op_fnmsub_q = 197,
 374     rv_op_fnmadd_q = 198,
 375     rv_op_fadd_q = 199,
 376     rv_op_fsub_q = 200,
 377     rv_op_fmul_q = 201,
 378     rv_op_fdiv_q = 202,
 379     rv_op_fsgnj_q = 203,
 380     rv_op_fsgnjn_q = 204,
 381     rv_op_fsgnjx_q = 205,
 382     rv_op_fmin_q = 206,
 383     rv_op_fmax_q = 207,
 384     rv_op_fcvt_s_q = 208,
 385     rv_op_fcvt_q_s = 209,
 386     rv_op_fcvt_d_q = 210,
 387     rv_op_fcvt_q_d = 211,
 388     rv_op_fsqrt_q = 212,
 389     rv_op_fle_q = 213,
 390     rv_op_flt_q = 214,
 391     rv_op_feq_q = 215,
 392     rv_op_fcvt_w_q = 216,
 393     rv_op_fcvt_wu_q = 217,
 394     rv_op_fcvt_q_w = 218,
 395     rv_op_fcvt_q_wu = 219,
 396     rv_op_fclass_q = 220,
 397     rv_op_fcvt_l_q = 221,
 398     rv_op_fcvt_lu_q = 222,
 399     rv_op_fcvt_q_l = 223,
 400     rv_op_fcvt_q_lu = 224,
 401     rv_op_fmv_x_q = 225,
 402     rv_op_fmv_q_x = 226,
 403     rv_op_c_addi4spn = 227,
 404     rv_op_c_fld = 228,
 405     rv_op_c_lw = 229,
 406     rv_op_c_flw = 230,
 407     rv_op_c_fsd = 231,
 408     rv_op_c_sw = 232,
 409     rv_op_c_fsw = 233,
 410     rv_op_c_nop = 234,
 411     rv_op_c_addi = 235,
 412     rv_op_c_jal = 236,
 413     rv_op_c_li = 237,
 414     rv_op_c_addi16sp = 238,
 415     rv_op_c_lui = 239,
 416     rv_op_c_srli = 240,
 417     rv_op_c_srai = 241,
 418     rv_op_c_andi = 242,
 419     rv_op_c_sub = 243,
 420     rv_op_c_xor = 244,
 421     rv_op_c_or = 245,
 422     rv_op_c_and = 246,
 423     rv_op_c_subw = 247,
 424     rv_op_c_addw = 248,
 425     rv_op_c_j = 249,
 426     rv_op_c_beqz = 250,
 427     rv_op_c_bnez = 251,
 428     rv_op_c_slli = 252,
 429     rv_op_c_fldsp = 253,
 430     rv_op_c_lwsp = 254,
 431     rv_op_c_flwsp = 255,
 432     rv_op_c_jr = 256,
 433     rv_op_c_mv = 257,
 434     rv_op_c_ebreak = 258,
 435     rv_op_c_jalr = 259,
 436     rv_op_c_add = 260,
 437     rv_op_c_fsdsp = 261,
 438     rv_op_c_swsp = 262,
 439     rv_op_c_fswsp = 263,
 440     rv_op_c_ld = 264,
 441     rv_op_c_sd = 265,
 442     rv_op_c_addiw = 266,
 443     rv_op_c_ldsp = 267,
 444     rv_op_c_sdsp = 268,
 445     rv_op_c_lq = 269,
 446     rv_op_c_sq = 270,
 447     rv_op_c_lqsp = 271,
 448     rv_op_c_sqsp = 272,
 449     rv_op_nop = 273,
 450     rv_op_mv = 274,
 451     rv_op_not = 275,
 452     rv_op_neg = 276,
 453     rv_op_negw = 277,
 454     rv_op_sext_w = 278,
 455     rv_op_seqz = 279,
 456     rv_op_snez = 280,
 457     rv_op_sltz = 281,
 458     rv_op_sgtz = 282,
 459     rv_op_fmv_s = 283,
 460     rv_op_fabs_s = 284,
 461     rv_op_fneg_s = 285,
 462     rv_op_fmv_d = 286,
 463     rv_op_fabs_d = 287,
 464     rv_op_fneg_d = 288,
 465     rv_op_fmv_q = 289,
 466     rv_op_fabs_q = 290,
 467     rv_op_fneg_q = 291,
 468     rv_op_beqz = 292,
 469     rv_op_bnez = 293,
 470     rv_op_blez = 294,
 471     rv_op_bgez = 295,
 472     rv_op_bltz = 296,
 473     rv_op_bgtz = 297,
 474     rv_op_ble = 298,
 475     rv_op_bleu = 299,
 476     rv_op_bgt = 300,
 477     rv_op_bgtu = 301,
 478     rv_op_j = 302,
 479     rv_op_ret = 303,
 480     rv_op_jr = 304,
 481     rv_op_rdcycle = 305,
 482     rv_op_rdtime = 306,
 483     rv_op_rdinstret = 307,
 484     rv_op_rdcycleh = 308,
 485     rv_op_rdtimeh = 309,
 486     rv_op_rdinstreth = 310,
 487     rv_op_frcsr = 311,
 488     rv_op_frrm = 312,
 489     rv_op_frflags = 313,
 490     rv_op_fscsr = 314,
 491     rv_op_fsrm = 315,
 492     rv_op_fsflags = 316,
 493     rv_op_fsrmi = 317,
 494     rv_op_fsflagsi = 318,
 495     rv_op_bseti = 319,
 496     rv_op_bclri = 320,
 497     rv_op_binvi = 321,
 498     rv_op_bexti = 322,
 499     rv_op_rori = 323,
 500     rv_op_clz = 324,
 501     rv_op_ctz = 325,
 502     rv_op_cpop = 326,
 503     rv_op_sext_h = 327,
 504     rv_op_sext_b = 328,
 505     rv_op_xnor = 329,
 506     rv_op_orn = 330,
 507     rv_op_andn = 331,
 508     rv_op_rol = 332,
 509     rv_op_ror = 333,
 510     rv_op_sh1add = 334,
 511     rv_op_sh2add = 335,
 512     rv_op_sh3add = 336,
 513     rv_op_sh1add_uw = 337,
 514     rv_op_sh2add_uw = 338,
 515     rv_op_sh3add_uw = 339,
 516     rv_op_clmul = 340,
 517     rv_op_clmulr = 341,
 518     rv_op_clmulh = 342,
 519     rv_op_min = 343,
 520     rv_op_minu = 344,
 521     rv_op_max = 345,
 522     rv_op_maxu = 346,
 523     rv_op_clzw = 347,
 524     rv_op_ctzw = 348,
 525     rv_op_cpopw = 349,
 526     rv_op_slli_uw = 350,
 527     rv_op_add_uw = 351,
 528     rv_op_rolw = 352,
 529     rv_op_rorw = 353,
 530     rv_op_rev8 = 354,
 531     rv_op_zext_h = 355,
 532     rv_op_roriw = 356,
 533     rv_op_orc_b = 357,
 534     rv_op_bset = 358,
 535     rv_op_bclr = 359,
 536     rv_op_binv = 360,
 537     rv_op_bext = 361,
 538     rv_op_aes32esmi = 362,
 539     rv_op_aes32esi = 363,
 540     rv_op_aes32dsmi = 364,
 541     rv_op_aes32dsi = 365,
 542     rv_op_aes64ks1i = 366,
 543     rv_op_aes64ks2 = 367,
 544     rv_op_aes64im = 368,
 545     rv_op_aes64esm = 369,
 546     rv_op_aes64es = 370,
 547     rv_op_aes64dsm = 371,
 548     rv_op_aes64ds = 372,
 549     rv_op_sha256sig0 = 373,
 550     rv_op_sha256sig1 = 374,
 551     rv_op_sha256sum0 = 375,
 552     rv_op_sha256sum1 = 376,
 553     rv_op_sha512sig0 = 377,
 554     rv_op_sha512sig1 = 378,
 555     rv_op_sha512sum0 = 379,
 556     rv_op_sha512sum1 = 380,
 557     rv_op_sha512sum0r = 381,
 558     rv_op_sha512sum1r = 382,
 559     rv_op_sha512sig0l = 383,
 560     rv_op_sha512sig0h = 384,
 561     rv_op_sha512sig1l = 385,
 562     rv_op_sha512sig1h = 386,
 563     rv_op_sm3p0 = 387,
 564     rv_op_sm3p1 = 388,
 565     rv_op_sm4ed = 389,
 566     rv_op_sm4ks = 390,
 567     rv_op_brev8 = 391,
 568     rv_op_pack = 392,
 569     rv_op_packh = 393,
 570     rv_op_packw = 394,
 571     rv_op_unzip = 395,
 572     rv_op_zip = 396,
 573     rv_op_xperm4 = 397,
 574     rv_op_xperm8 = 398,
 575     rv_op_vle8_v = 399,
 576     rv_op_vle16_v = 400,
 577     rv_op_vle32_v = 401,
 578     rv_op_vle64_v = 402,
 579     rv_op_vse8_v = 403,
 580     rv_op_vse16_v = 404,
 581     rv_op_vse32_v = 405,
 582     rv_op_vse64_v = 406,
 583     rv_op_vlm_v = 407,
 584     rv_op_vsm_v = 408,
 585     rv_op_vlse8_v = 409,
 586     rv_op_vlse16_v = 410,
 587     rv_op_vlse32_v = 411,
 588     rv_op_vlse64_v = 412,
 589     rv_op_vsse8_v = 413,
 590     rv_op_vsse16_v = 414,
 591     rv_op_vsse32_v = 415,
 592     rv_op_vsse64_v = 416,
 593     rv_op_vluxei8_v = 417,
 594     rv_op_vluxei16_v = 418,
 595     rv_op_vluxei32_v = 419,
 596     rv_op_vluxei64_v = 420,
 597     rv_op_vloxei8_v = 421,
 598     rv_op_vloxei16_v = 422,
 599     rv_op_vloxei32_v = 423,
 600     rv_op_vloxei64_v = 424,
 601     rv_op_vsuxei8_v = 425,
 602     rv_op_vsuxei16_v = 426,
 603     rv_op_vsuxei32_v = 427,
 604     rv_op_vsuxei64_v = 428,
 605     rv_op_vsoxei8_v = 429,
 606     rv_op_vsoxei16_v = 430,
 607     rv_op_vsoxei32_v = 431,
 608     rv_op_vsoxei64_v = 432,
 609     rv_op_vle8ff_v = 433,
 610     rv_op_vle16ff_v = 434,
 611     rv_op_vle32ff_v = 435,
 612     rv_op_vle64ff_v = 436,
 613     rv_op_vl1re8_v = 437,
 614     rv_op_vl1re16_v = 438,
 615     rv_op_vl1re32_v = 439,
 616     rv_op_vl1re64_v = 440,
 617     rv_op_vl2re8_v = 441,
 618     rv_op_vl2re16_v = 442,
 619     rv_op_vl2re32_v = 443,
 620     rv_op_vl2re64_v = 444,
 621     rv_op_vl4re8_v = 445,
 622     rv_op_vl4re16_v = 446,
 623     rv_op_vl4re32_v = 447,
 624     rv_op_vl4re64_v = 448,
 625     rv_op_vl8re8_v = 449,
 626     rv_op_vl8re16_v = 450,
 627     rv_op_vl8re32_v = 451,
 628     rv_op_vl8re64_v = 452,
 629     rv_op_vs1r_v = 453,
 630     rv_op_vs2r_v = 454,
 631     rv_op_vs4r_v = 455,
 632     rv_op_vs8r_v = 456,
 633     rv_op_vadd_vv = 457,
 634     rv_op_vadd_vx = 458,
 635     rv_op_vadd_vi = 459,
 636     rv_op_vsub_vv = 460,
 637     rv_op_vsub_vx = 461,
 638     rv_op_vrsub_vx = 462,
 639     rv_op_vrsub_vi = 463,
 640     rv_op_vwaddu_vv = 464,
 641     rv_op_vwaddu_vx = 465,
 642     rv_op_vwadd_vv = 466,
 643     rv_op_vwadd_vx = 467,
 644     rv_op_vwsubu_vv = 468,
 645     rv_op_vwsubu_vx = 469,
 646     rv_op_vwsub_vv = 470,
 647     rv_op_vwsub_vx = 471,
 648     rv_op_vwaddu_wv = 472,
 649     rv_op_vwaddu_wx = 473,
 650     rv_op_vwadd_wv = 474,
 651     rv_op_vwadd_wx = 475,
 652     rv_op_vwsubu_wv = 476,
 653     rv_op_vwsubu_wx = 477,
 654     rv_op_vwsub_wv = 478,
 655     rv_op_vwsub_wx = 479,
 656     rv_op_vadc_vvm = 480,
 657     rv_op_vadc_vxm = 481,
 658     rv_op_vadc_vim = 482,
 659     rv_op_vmadc_vvm = 483,
 660     rv_op_vmadc_vxm = 484,
 661     rv_op_vmadc_vim = 485,
 662     rv_op_vsbc_vvm = 486,
 663     rv_op_vsbc_vxm = 487,
 664     rv_op_vmsbc_vvm = 488,
 665     rv_op_vmsbc_vxm = 489,
 666     rv_op_vand_vv = 490,
 667     rv_op_vand_vx = 491,
 668     rv_op_vand_vi = 492,
 669     rv_op_vor_vv = 493,
 670     rv_op_vor_vx = 494,
 671     rv_op_vor_vi = 495,
 672     rv_op_vxor_vv = 496,
 673     rv_op_vxor_vx = 497,
 674     rv_op_vxor_vi = 498,
 675     rv_op_vsll_vv = 499,
 676     rv_op_vsll_vx = 500,
 677     rv_op_vsll_vi = 501,
 678     rv_op_vsrl_vv = 502,
 679     rv_op_vsrl_vx = 503,
 680     rv_op_vsrl_vi = 504,
 681     rv_op_vsra_vv = 505,
 682     rv_op_vsra_vx = 506,
 683     rv_op_vsra_vi = 507,
 684     rv_op_vnsrl_wv = 508,
 685     rv_op_vnsrl_wx = 509,
 686     rv_op_vnsrl_wi = 510,
 687     rv_op_vnsra_wv = 511,
 688     rv_op_vnsra_wx = 512,
 689     rv_op_vnsra_wi = 513,
 690     rv_op_vmseq_vv = 514,
 691     rv_op_vmseq_vx = 515,
 692     rv_op_vmseq_vi = 516,
 693     rv_op_vmsne_vv = 517,
 694     rv_op_vmsne_vx = 518,
 695     rv_op_vmsne_vi = 519,
 696     rv_op_vmsltu_vv = 520,
 697     rv_op_vmsltu_vx = 521,
 698     rv_op_vmslt_vv = 522,
 699     rv_op_vmslt_vx = 523,
 700     rv_op_vmsleu_vv = 524,
 701     rv_op_vmsleu_vx = 525,
 702     rv_op_vmsleu_vi = 526,
 703     rv_op_vmsle_vv = 527,
 704     rv_op_vmsle_vx = 528,
 705     rv_op_vmsle_vi = 529,
 706     rv_op_vmsgtu_vx = 530,
 707     rv_op_vmsgtu_vi = 531,
 708     rv_op_vmsgt_vx = 532,
 709     rv_op_vmsgt_vi = 533,
 710     rv_op_vminu_vv = 534,
 711     rv_op_vminu_vx = 535,
 712     rv_op_vmin_vv = 536,
 713     rv_op_vmin_vx = 537,
 714     rv_op_vmaxu_vv = 538,
 715     rv_op_vmaxu_vx = 539,
 716     rv_op_vmax_vv = 540,
 717     rv_op_vmax_vx = 541,
 718     rv_op_vmul_vv = 542,
 719     rv_op_vmul_vx = 543,
 720     rv_op_vmulh_vv = 544,
 721     rv_op_vmulh_vx = 545,
 722     rv_op_vmulhu_vv = 546,
 723     rv_op_vmulhu_vx = 547,
 724     rv_op_vmulhsu_vv = 548,
 725     rv_op_vmulhsu_vx = 549,
 726     rv_op_vdivu_vv = 550,
 727     rv_op_vdivu_vx = 551,
 728     rv_op_vdiv_vv = 552,
 729     rv_op_vdiv_vx = 553,
 730     rv_op_vremu_vv = 554,
 731     rv_op_vremu_vx = 555,
 732     rv_op_vrem_vv = 556,
 733     rv_op_vrem_vx = 557,
 734     rv_op_vwmulu_vv = 558,
 735     rv_op_vwmulu_vx = 559,
 736     rv_op_vwmulsu_vv = 560,
 737     rv_op_vwmulsu_vx = 561,
 738     rv_op_vwmul_vv = 562,
 739     rv_op_vwmul_vx = 563,
 740     rv_op_vmacc_vv = 564,
 741     rv_op_vmacc_vx = 565,
 742     rv_op_vnmsac_vv = 566,
 743     rv_op_vnmsac_vx = 567,
 744     rv_op_vmadd_vv = 568,
 745     rv_op_vmadd_vx = 569,
 746     rv_op_vnmsub_vv = 570,
 747     rv_op_vnmsub_vx = 571,
 748     rv_op_vwmaccu_vv = 572,
 749     rv_op_vwmaccu_vx = 573,
 750     rv_op_vwmacc_vv = 574,
 751     rv_op_vwmacc_vx = 575,
 752     rv_op_vwmaccsu_vv = 576,
 753     rv_op_vwmaccsu_vx = 577,
 754     rv_op_vwmaccus_vx = 578,
 755     rv_op_vmv_v_v = 579,
 756     rv_op_vmv_v_x = 580,
 757     rv_op_vmv_v_i = 581,
 758     rv_op_vmerge_vvm = 582,
 759     rv_op_vmerge_vxm = 583,
 760     rv_op_vmerge_vim = 584,
 761     rv_op_vsaddu_vv = 585,
 762     rv_op_vsaddu_vx = 586,
 763     rv_op_vsaddu_vi = 587,
 764     rv_op_vsadd_vv = 588,
 765     rv_op_vsadd_vx = 589,
 766     rv_op_vsadd_vi = 590,
 767     rv_op_vssubu_vv = 591,
 768     rv_op_vssubu_vx = 592,
 769     rv_op_vssub_vv = 593,
 770     rv_op_vssub_vx = 594,
 771     rv_op_vaadd_vv = 595,
 772     rv_op_vaadd_vx = 596,
 773     rv_op_vaaddu_vv = 597,
 774     rv_op_vaaddu_vx = 598,
 775     rv_op_vasub_vv = 599,
 776     rv_op_vasub_vx = 600,
 777     rv_op_vasubu_vv = 601,
 778     rv_op_vasubu_vx = 602,
 779     rv_op_vsmul_vv = 603,
 780     rv_op_vsmul_vx = 604,
 781     rv_op_vssrl_vv = 605,
 782     rv_op_vssrl_vx = 606,
 783     rv_op_vssrl_vi = 607,
 784     rv_op_vssra_vv = 608,
 785     rv_op_vssra_vx = 609,
 786     rv_op_vssra_vi = 610,
 787     rv_op_vnclipu_wv = 611,
 788     rv_op_vnclipu_wx = 612,
 789     rv_op_vnclipu_wi = 613,
 790     rv_op_vnclip_wv = 614,
 791     rv_op_vnclip_wx = 615,
 792     rv_op_vnclip_wi = 616,
 793     rv_op_vfadd_vv = 617,
 794     rv_op_vfadd_vf = 618,
 795     rv_op_vfsub_vv = 619,
 796     rv_op_vfsub_vf = 620,
 797     rv_op_vfrsub_vf = 621,
 798     rv_op_vfwadd_vv = 622,
 799     rv_op_vfwadd_vf = 623,
 800     rv_op_vfwadd_wv = 624,
 801     rv_op_vfwadd_wf = 625,
 802     rv_op_vfwsub_vv = 626,
 803     rv_op_vfwsub_vf = 627,
 804     rv_op_vfwsub_wv = 628,
 805     rv_op_vfwsub_wf = 629,
 806     rv_op_vfmul_vv = 630,
 807     rv_op_vfmul_vf = 631,
 808     rv_op_vfdiv_vv = 632,
 809     rv_op_vfdiv_vf = 633,
 810     rv_op_vfrdiv_vf = 634,
 811     rv_op_vfwmul_vv = 635,
 812     rv_op_vfwmul_vf = 636,
 813     rv_op_vfmacc_vv = 637,
 814     rv_op_vfmacc_vf = 638,
 815     rv_op_vfnmacc_vv = 639,
 816     rv_op_vfnmacc_vf = 640,
 817     rv_op_vfmsac_vv = 641,
 818     rv_op_vfmsac_vf = 642,
 819     rv_op_vfnmsac_vv = 643,
 820     rv_op_vfnmsac_vf = 644,
 821     rv_op_vfmadd_vv = 645,
 822     rv_op_vfmadd_vf = 646,
 823     rv_op_vfnmadd_vv = 647,
 824     rv_op_vfnmadd_vf = 648,
 825     rv_op_vfmsub_vv = 649,
 826     rv_op_vfmsub_vf = 650,
 827     rv_op_vfnmsub_vv = 651,
 828     rv_op_vfnmsub_vf = 652,
 829     rv_op_vfwmacc_vv = 653,
 830     rv_op_vfwmacc_vf = 654,
 831     rv_op_vfwnmacc_vv = 655,
 832     rv_op_vfwnmacc_vf = 656,
 833     rv_op_vfwmsac_vv = 657,
 834     rv_op_vfwmsac_vf = 658,
 835     rv_op_vfwnmsac_vv = 659,
 836     rv_op_vfwnmsac_vf = 660,
 837     rv_op_vfsqrt_v = 661,
 838     rv_op_vfrsqrt7_v = 662,
 839     rv_op_vfrec7_v = 663,
 840     rv_op_vfmin_vv = 664,
 841     rv_op_vfmin_vf = 665,
 842     rv_op_vfmax_vv = 666,
 843     rv_op_vfmax_vf = 667,
 844     rv_op_vfsgnj_vv = 668,
 845     rv_op_vfsgnj_vf = 669,
 846     rv_op_vfsgnjn_vv = 670,
 847     rv_op_vfsgnjn_vf = 671,
 848     rv_op_vfsgnjx_vv = 672,
 849     rv_op_vfsgnjx_vf = 673,
 850     rv_op_vfslide1up_vf = 674,
 851     rv_op_vfslide1down_vf = 675,
 852     rv_op_vmfeq_vv = 676,
 853     rv_op_vmfeq_vf = 677,
 854     rv_op_vmfne_vv = 678,
 855     rv_op_vmfne_vf = 679,
 856     rv_op_vmflt_vv = 680,
 857     rv_op_vmflt_vf = 681,
 858     rv_op_vmfle_vv = 682,
 859     rv_op_vmfle_vf = 683,
 860     rv_op_vmfgt_vf = 684,
 861     rv_op_vmfge_vf = 685,
 862     rv_op_vfclass_v = 686,
 863     rv_op_vfmerge_vfm = 687,
 864     rv_op_vfmv_v_f = 688,
 865     rv_op_vfcvt_xu_f_v = 689,
 866     rv_op_vfcvt_x_f_v = 690,
 867     rv_op_vfcvt_f_xu_v = 691,
 868     rv_op_vfcvt_f_x_v = 692,
 869     rv_op_vfcvt_rtz_xu_f_v = 693,
 870     rv_op_vfcvt_rtz_x_f_v = 694,
 871     rv_op_vfwcvt_xu_f_v = 695,
 872     rv_op_vfwcvt_x_f_v = 696,
 873     rv_op_vfwcvt_f_xu_v = 697,
 874     rv_op_vfwcvt_f_x_v = 698,
 875     rv_op_vfwcvt_f_f_v = 699,
 876     rv_op_vfwcvt_rtz_xu_f_v = 700,
 877     rv_op_vfwcvt_rtz_x_f_v = 701,
 878     rv_op_vfncvt_xu_f_w = 702,
 879     rv_op_vfncvt_x_f_w = 703,
 880     rv_op_vfncvt_f_xu_w = 704,
 881     rv_op_vfncvt_f_x_w = 705,
 882     rv_op_vfncvt_f_f_w = 706,
 883     rv_op_vfncvt_rod_f_f_w = 707,
 884     rv_op_vfncvt_rtz_xu_f_w = 708,
 885     rv_op_vfncvt_rtz_x_f_w = 709,
 886     rv_op_vredsum_vs = 710,
 887     rv_op_vredand_vs = 711,
 888     rv_op_vredor_vs = 712,
 889     rv_op_vredxor_vs = 713,
 890     rv_op_vredminu_vs = 714,
 891     rv_op_vredmin_vs = 715,
 892     rv_op_vredmaxu_vs = 716,
 893     rv_op_vredmax_vs = 717,
 894     rv_op_vwredsumu_vs = 718,
 895     rv_op_vwredsum_vs = 719,
 896     rv_op_vfredusum_vs = 720,
 897     rv_op_vfredosum_vs = 721,
 898     rv_op_vfredmin_vs = 722,
 899     rv_op_vfredmax_vs = 723,
 900     rv_op_vfwredusum_vs = 724,
 901     rv_op_vfwredosum_vs = 725,
 902     rv_op_vmand_mm = 726,
 903     rv_op_vmnand_mm = 727,
 904     rv_op_vmandn_mm = 728,
 905     rv_op_vmxor_mm = 729,
 906     rv_op_vmor_mm = 730,
 907     rv_op_vmnor_mm = 731,
 908     rv_op_vmorn_mm = 732,
 909     rv_op_vmxnor_mm = 733,
 910     rv_op_vcpop_m = 734,
 911     rv_op_vfirst_m = 735,
 912     rv_op_vmsbf_m = 736,
 913     rv_op_vmsif_m = 737,
 914     rv_op_vmsof_m = 738,
 915     rv_op_viota_m = 739,
 916     rv_op_vid_v = 740,
 917     rv_op_vmv_x_s = 741,
 918     rv_op_vmv_s_x = 742,
 919     rv_op_vfmv_f_s = 743,
 920     rv_op_vfmv_s_f = 744,
 921     rv_op_vslideup_vx = 745,
 922     rv_op_vslideup_vi = 746,
 923     rv_op_vslide1up_vx = 747,
 924     rv_op_vslidedown_vx = 748,
 925     rv_op_vslidedown_vi = 749,
 926     rv_op_vslide1down_vx = 750,
 927     rv_op_vrgather_vv = 751,
 928     rv_op_vrgatherei16_vv = 752,
 929     rv_op_vrgather_vx = 753,
 930     rv_op_vrgather_vi = 754,
 931     rv_op_vcompress_vm = 755,
 932     rv_op_vmv1r_v = 756,
 933     rv_op_vmv2r_v = 757,
 934     rv_op_vmv4r_v = 758,
 935     rv_op_vmv8r_v = 759,
 936     rv_op_vzext_vf2 = 760,
 937     rv_op_vzext_vf4 = 761,
 938     rv_op_vzext_vf8 = 762,
 939     rv_op_vsext_vf2 = 763,
 940     rv_op_vsext_vf4 = 764,
 941     rv_op_vsext_vf8 = 765,
 942     rv_op_vsetvli = 766,
 943     rv_op_vsetivli = 767,
 944     rv_op_vsetvl = 768,
 945     rv_op_c_zext_b = 769,
 946     rv_op_c_sext_b = 770,
 947     rv_op_c_zext_h = 771,
 948     rv_op_c_sext_h = 772,
 949     rv_op_c_zext_w = 773,
 950     rv_op_c_not = 774,
 951     rv_op_c_mul = 775,
 952     rv_op_c_lbu = 776,
 953     rv_op_c_lhu = 777,
 954     rv_op_c_lh = 778,
 955     rv_op_c_sb = 779,
 956     rv_op_c_sh = 780,
 957     rv_op_cm_push = 781,
 958     rv_op_cm_pop = 782,
 959     rv_op_cm_popret = 783,
 960     rv_op_cm_popretz = 784,
 961     rv_op_cm_mva01s = 785,
 962     rv_op_cm_mvsa01 = 786,
 963     rv_op_cm_jt = 787,
 964     rv_op_cm_jalt = 788,
 965     rv_op_czero_eqz = 789,
 966     rv_op_czero_nez = 790,
 967 } rv_op;
 968
 969 /* structures */
 970
 971 typedef struct {
 972     uint64_t  pc;
 973     uint64_t  inst;
 974     int32_t   imm;
 975     uint16_t  op;
 976     uint8_t   codec;
 977     uint8_t   rd;
 978     uint8_t   rs1;
 979     uint8_t   rs2;
 980     uint8_t   rs3;
 981     uint8_t   rm;
 982     uint8_t   pred;
 983     uint8_t   succ;
 984     uint8_t   aq;
 985     uint8_t   rl;
 986     uint8_t   bs;
 987     uint8_t   rnum;
 988     uint8_t   vm;
 989     uint32_t  vzimm;
 990     uint8_t   rlist;
 991 } rv_decode;
 992
 993 typedef struct {
 994     const int op;
 995     const rvc_constraint *constraints;
 996 } rv_comp_data;
 997
 998 enum {
 999     rvcd_imm_nz = 0x1
1000 };
1001
1002 typedef struct {
1003     const char * const name;
1004     const rv_codec codec;
1005     const char * const format;
1006     const rv_comp_data *pseudo;
1007     const short decomp_rv32;
1008     const short decomp_rv64;
1009     const short decomp_rv128;
1010     const short decomp_data;
1011 } rv_opcode_data;
1012
1013 /* register names */
1014
1015 static const char rv_ireg_name_sym[32][5] = {
1016     "zero", "ra",   "sp",   "gp",   "tp",   "t0",   "t1",   "t2",
1017     "s0",   "s1",   "a0",   "a1",   "a2",   "a3",   "a4",   "a5",
1018     "a6",   "a7",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
1019     "s8",   "s9",   "s10",  "s11",  "t3",   "t4",   "t5",   "t6",
1020 };
1021
1022 static const char rv_freg_name_sym[32][5] = {
1023     "ft0",  "ft1",  "ft2",  "ft3",  "ft4",  "ft5",  "ft6",  "ft7",
1024     "fs0",  "fs1",  "fa0",  "fa1",  "fa2",  "fa3",  "fa4",  "fa5",
1025     "fa6",  "fa7",  "fs2",  "fs3",  "fs4",  "fs5",  "fs6",  "fs7",
1026     "fs8",  "fs9",  "fs10", "fs11", "ft8",  "ft9",  "ft10", "ft11",
1027 };
1028
1029 static const char rv_vreg_name_sym[32][4] = {
1030     "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",
1031     "v8",  "v9",  "v10", "v11", "v12", "v13", "v14", "v15",
1032     "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1033     "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
1034 };
1035
1036 /* instruction formats */
1037
1038 #define rv_fmt_none                   "O\t"
1039 #define rv_fmt_rs1                    "O\t1"
1040 #define rv_fmt_offset                 "O\to"
1041 #define rv_fmt_pred_succ              "O\tp,s"
1042 #define rv_fmt_rs1_rs2                "O\t1,2"
1043 #define rv_fmt_rd_imm                 "O\t0,i"
1044 #define rv_fmt_rd_offset              "O\t0,o"
1045 #define rv_fmt_rd_rs1_rs2             "O\t0,1,2"
1046 #define rv_fmt_frd_rs1                "O\t3,1"
1047 #define rv_fmt_frd_frs1               "O\t3,4"
1048 #define rv_fmt_rd_frs1                "O\t0,4"
1049 #define rv_fmt_rd_frs1_frs2           "O\t0,4,5"
1050 #define rv_fmt_frd_frs1_frs2          "O\t3,4,5"
1051 #define rv_fmt_rm_frd_frs1            "O\tr,3,4"
1052 #define rv_fmt_rm_frd_rs1             "O\tr,3,1"
1053 #define rv_fmt_rm_rd_frs1             "O\tr,0,4"
1054 #define rv_fmt_rm_frd_frs1_frs2       "O\tr,3,4,5"
1055 #define rv_fmt_rm_frd_frs1_frs2_frs3  "O\tr,3,4,5,6"
1056 #define rv_fmt_rd_rs1_imm             "O\t0,1,i"
1057 #define rv_fmt_rd_rs1_offset          "O\t0,1,i"
1058 #define rv_fmt_rd_offset_rs1          "O\t0,i(1)"
1059 #define rv_fmt_frd_offset_rs1         "O\t3,i(1)"
1060 #define rv_fmt_rd_csr_rs1             "O\t0,c,1"
1061 #define rv_fmt_rd_csr_zimm            "O\t0,c,7"
1062 #define rv_fmt_rs2_offset_rs1         "O\t2,i(1)"
1063 #define rv_fmt_frs2_offset_rs1        "O\t5,i(1)"
1064 #define rv_fmt_rs1_rs2_offset         "O\t1,2,o"
1065 #define rv_fmt_rs2_rs1_offset         "O\t2,1,o"
1066 #define rv_fmt_aqrl_rd_rs2_rs1        "OAR\t0,2,(1)"
1067 #define rv_fmt_aqrl_rd_rs1            "OAR\t0,(1)"
1068 #define rv_fmt_rd                     "O\t0"
1069 #define rv_fmt_rd_zimm                "O\t0,7"
1070 #define rv_fmt_rd_rs1                 "O\t0,1"
1071 #define rv_fmt_rd_rs2                 "O\t0,2"
1072 #define rv_fmt_rs1_offset             "O\t1,o"
1073 #define rv_fmt_rs2_offset             "O\t2,o"
1074 #define rv_fmt_rs1_rs2_bs             "O\t1,2,b"
1075 #define rv_fmt_rd_rs1_rnum            "O\t0,1,n"
1076 #define rv_fmt_ldst_vd_rs1_vm         "O\tD,(1)m"
1077 #define rv_fmt_ldst_vd_rs1_rs2_vm     "O\tD,(1),2m"
1078 #define rv_fmt_ldst_vd_rs1_vs2_vm     "O\tD,(1),Fm"
1079 #define rv_fmt_vd_vs2_vs1             "O\tD,F,E"
1080 #define rv_fmt_vd_vs2_vs1_vl          "O\tD,F,El"
1081 #define rv_fmt_vd_vs2_vs1_vm          "O\tD,F,Em"
1082 #define rv_fmt_vd_vs2_rs1_vl          "O\tD,F,1l"
1083 #define rv_fmt_vd_vs2_fs1_vl          "O\tD,F,4l"
1084 #define rv_fmt_vd_vs2_rs1_vm          "O\tD,F,1m"
1085 #define rv_fmt_vd_vs2_fs1_vm          "O\tD,F,4m"
1086 #define rv_fmt_vd_vs2_imm_vl          "O\tD,F,il"
1087 #define rv_fmt_vd_vs2_imm_vm          "O\tD,F,im"
1088 #define rv_fmt_vd_vs2_uimm_vm         "O\tD,F,um"
1089 #define rv_fmt_vd_vs1_vs2_vm          "O\tD,E,Fm"
1090 #define rv_fmt_vd_rs1_vs2_vm          "O\tD,1,Fm"
1091 #define rv_fmt_vd_fs1_vs2_vm          "O\tD,4,Fm"
1092 #define rv_fmt_vd_vs1                 "O\tD,E"
1093 #define rv_fmt_vd_rs1                 "O\tD,1"
1094 #define rv_fmt_vd_fs1                 "O\tD,4"
1095 #define rv_fmt_vd_imm                 "O\tD,i"
1096 #define rv_fmt_vd_vs2                 "O\tD,F"
1097 #define rv_fmt_vd_vs2_vm              "O\tD,Fm"
1098 #define rv_fmt_rd_vs2_vm              "O\t0,Fm"
1099 #define rv_fmt_rd_vs2                 "O\t0,F"
1100 #define rv_fmt_fd_vs2                 "O\t3,F"
1101 #define rv_fmt_vd_vm                  "O\tDm"
1102 #define rv_fmt_vsetvli                "O\t0,1,v"
1103 #define rv_fmt_vsetivli               "O\t0,u,v"
1104 #define rv_fmt_rs1_rs2_zce_ldst       "O\t2,i(1)"
1105 #define rv_fmt_push_rlist             "O\tx,-i"
1106 #define rv_fmt_pop_rlist              "O\tx,i"
1107 #define rv_fmt_zcmt_index             "O\ti"
1108
1109 /* pseudo-instruction constraints */
1110
1111 static const rvc_constraint rvcc_jal[] = { rvc_rd_eq_ra, rvc_end };
1112 static const rvc_constraint rvcc_jalr[] = { rvc_rd_eq_ra, rvc_imm_eq_zero, rvc_end };
1113 static const rvc_constraint rvcc_nop[] = { rvc_rd_eq_x0, rvc_rs1_eq_x0, rvc_imm_eq_zero, rvc_end };
1114 static const rvc_constraint rvcc_mv[] = { rvc_imm_eq_zero, rvc_end };
1115 static const rvc_constraint rvcc_not[] = { rvc_imm_eq_n1, rvc_end };
1116 static const rvc_constraint rvcc_neg[] = { rvc_rs1_eq_x0, rvc_end };
1117 static const rvc_constraint rvcc_negw[] = { rvc_rs1_eq_x0, rvc_end };
1118 static const rvc_constraint rvcc_sext_w[] = { rvc_imm_eq_zero, rvc_end };
1119 static const rvc_constraint rvcc_seqz[] = { rvc_imm_eq_p1, rvc_end };
1120 static const rvc_constraint rvcc_snez[] = { rvc_rs1_eq_x0, rvc_end };
1121 static const rvc_constraint rvcc_sltz[] = { rvc_rs2_eq_x0, rvc_end };
1122 static const rvc_constraint rvcc_sgtz[] = { rvc_rs1_eq_x0, rvc_end };
1123 static const rvc_constraint rvcc_fmv_s[] = { rvc_rs2_eq_rs1, rvc_end };
1124 static const rvc_constraint rvcc_fabs_s[] = { rvc_rs2_eq_rs1, rvc_end };
1125 static const rvc_constraint rvcc_fneg_s[] = { rvc_rs2_eq_rs1, rvc_end };
1126 static const rvc_constraint rvcc_fmv_d[] = { rvc_rs2_eq_rs1, rvc_end };
1127 static const rvc_constraint rvcc_fabs_d[] = { rvc_rs2_eq_rs1, rvc_end };
1128 static const rvc_constraint rvcc_fneg_d[] = { rvc_rs2_eq_rs1, rvc_end };
1129 static const rvc_constraint rvcc_fmv_q[] = { rvc_rs2_eq_rs1, rvc_end };
1130 static const rvc_constraint rvcc_fabs_q[] = { rvc_rs2_eq_rs1, rvc_end };
1131 static const rvc_constraint rvcc_fneg_q[] = { rvc_rs2_eq_rs1, rvc_end };
1132 static const rvc_constraint rvcc_beqz[] = { rvc_rs2_eq_x0, rvc_end };
1133 static const rvc_constraint rvcc_bnez[] = { rvc_rs2_eq_x0, rvc_end };
1134 static const rvc_constraint rvcc_blez[] = { rvc_rs1_eq_x0, rvc_end };
1135 static const rvc_constraint rvcc_bgez[] = { rvc_rs2_eq_x0, rvc_end };
1136 static const rvc_constraint rvcc_bltz[] = { rvc_rs2_eq_x0, rvc_end };
1137 static const rvc_constraint rvcc_bgtz[] = { rvc_rs1_eq_x0, rvc_end };
1138 static const rvc_constraint rvcc_ble[] = { rvc_end };
1139 static const rvc_constraint rvcc_bleu[] = { rvc_end };
1140 static const rvc_constraint rvcc_bgt[] = { rvc_end };
1141 static const rvc_constraint rvcc_bgtu[] = { rvc_end };
1142 static const rvc_constraint rvcc_j[] = { rvc_rd_eq_x0, rvc_end };
1143 static const rvc_constraint rvcc_ret[] = { rvc_rd_eq_x0, rvc_rs1_eq_ra, rvc_end };
1144 static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0, rvc_imm_eq_zero, rvc_end };
1145 static const rvc_constraint rvcc_rdcycle[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc00, rvc_end };
1146 static const rvc_constraint rvcc_rdtime[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc01, rvc_end };
1147 static const rvc_constraint rvcc_rdinstret[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc02, rvc_end };
1148 static const rvc_constraint rvcc_rdcycleh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc80, rvc_end };
1149 static const rvc_constraint rvcc_rdtimeh[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc81, rvc_end };
1150 static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0,
1151                                                   rvc_csr_eq_0xc82, rvc_end };
1152 static const rvc_constraint rvcc_frcsr[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x003, rvc_end };
1153 static const rvc_constraint rvcc_frrm[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x002, rvc_end };
1154 static const rvc_constraint rvcc_frflags[] = { rvc_rs1_eq_x0, rvc_csr_eq_0x001, rvc_end };
1155 static const rvc_constraint rvcc_fscsr[] = { rvc_csr_eq_0x003, rvc_end };
1156 static const rvc_constraint rvcc_fsrm[] = { rvc_csr_eq_0x002, rvc_end };
1157 static const rvc_constraint rvcc_fsflags[] = { rvc_csr_eq_0x001, rvc_end };
1158 static const rvc_constraint rvcc_fsrmi[] = { rvc_csr_eq_0x002, rvc_end };
1159 static const rvc_constraint rvcc_fsflagsi[] = { rvc_csr_eq_0x001, rvc_end };
1160
1161 /* pseudo-instruction metadata */
1162
1163 static const rv_comp_data rvcp_jal[] = {
1164     { rv_op_j, rvcc_j },
1165     { rv_op_jal, rvcc_jal },
1166     { rv_op_illegal, NULL }
1167 };
1168
1169 static const rv_comp_data rvcp_jalr[] = {
1170     { rv_op_ret, rvcc_ret },
1171     { rv_op_jr, rvcc_jr },
1172     { rv_op_jalr, rvcc_jalr },
1173     { rv_op_illegal, NULL }
1174 };
1175
1176 static const rv_comp_data rvcp_beq[] = {
1177     { rv_op_beqz, rvcc_beqz },
1178     { rv_op_illegal, NULL }
1179 };
1180
1181 static const rv_comp_data rvcp_bne[] = {
1182     { rv_op_bnez, rvcc_bnez },
1183     { rv_op_illegal, NULL }
1184 };
1185
1186 static const rv_comp_data rvcp_blt[] = {
1187     { rv_op_bltz, rvcc_bltz },
1188     { rv_op_bgtz, rvcc_bgtz },
1189     { rv_op_bgt, rvcc_bgt },
1190     { rv_op_illegal, NULL }
1191 };
1192
1193 static const rv_comp_data rvcp_bge[] = {
1194     { rv_op_blez, rvcc_blez },
1195     { rv_op_bgez, rvcc_bgez },
1196     { rv_op_ble, rvcc_ble },
1197     { rv_op_illegal, NULL }
1198 };
1199
1200 static const rv_comp_data rvcp_bltu[] = {
1201     { rv_op_bgtu, rvcc_bgtu },
1202     { rv_op_illegal, NULL }
1203 };
1204
1205 static const rv_comp_data rvcp_bgeu[] = {
1206     { rv_op_bleu, rvcc_bleu },
1207     { rv_op_illegal, NULL }
1208 };
1209
1210 static const rv_comp_data rvcp_addi[] = {
1211     { rv_op_nop, rvcc_nop },
1212     { rv_op_mv, rvcc_mv },
1213     { rv_op_illegal, NULL }
1214 };
1215
1216 static const rv_comp_data rvcp_sltiu[] = {
1217     { rv_op_seqz, rvcc_seqz },
1218     { rv_op_illegal, NULL }
1219 };
1220
1221 static const rv_comp_data rvcp_xori[] = {
1222     { rv_op_not, rvcc_not },
1223     { rv_op_illegal, NULL }
1224 };
1225
1226 static const rv_comp_data rvcp_sub[] = {
1227     { rv_op_neg, rvcc_neg },
1228     { rv_op_illegal, NULL }
1229 };
1230
1231 static const rv_comp_data rvcp_slt[] = {
1232     { rv_op_sltz, rvcc_sltz },
1233     { rv_op_sgtz, rvcc_sgtz },
1234     { rv_op_illegal, NULL }
1235 };
1236
1237 static const rv_comp_data rvcp_sltu[] = {
1238     { rv_op_snez, rvcc_snez },
1239     { rv_op_illegal, NULL }
1240 };
1241
1242 static const rv_comp_data rvcp_addiw[] = {
1243     { rv_op_sext_w, rvcc_sext_w },
1244     { rv_op_illegal, NULL }
1245 };
1246
1247 static const rv_comp_data rvcp_subw[] = {
1248     { rv_op_negw, rvcc_negw },
1249     { rv_op_illegal, NULL }
1250 };
1251
1252 static const rv_comp_data rvcp_csrrw[] = {
1253     { rv_op_fscsr, rvcc_fscsr },
1254     { rv_op_fsrm, rvcc_fsrm },
1255     { rv_op_fsflags, rvcc_fsflags },
1256     { rv_op_illegal, NULL }
1257 };
1258
1259
1260 static const rv_comp_data rvcp_csrrs[] = {
1261     { rv_op_rdcycle, rvcc_rdcycle },
1262     { rv_op_rdtime, rvcc_rdtime },
1263     { rv_op_rdinstret, rvcc_rdinstret },
1264     { rv_op_rdcycleh, rvcc_rdcycleh },
1265     { rv_op_rdtimeh, rvcc_rdtimeh },
1266     { rv_op_rdinstreth, rvcc_rdinstreth },
1267     { rv_op_frcsr, rvcc_frcsr },
1268     { rv_op_frrm, rvcc_frrm },
1269     { rv_op_frflags, rvcc_frflags },
1270     { rv_op_illegal, NULL }
1271 };
1272
1273 static const rv_comp_data rvcp_csrrwi[] = {
1274     { rv_op_fsrmi, rvcc_fsrmi },
1275     { rv_op_fsflagsi, rvcc_fsflagsi },
1276     { rv_op_illegal, NULL }
1277 };
1278
1279 static const rv_comp_data rvcp_fsgnj_s[] = {
1280     { rv_op_fmv_s, rvcc_fmv_s },
1281     { rv_op_illegal, NULL }
1282 };
1283
1284 static const rv_comp_data rvcp_fsgnjn_s[] = {
1285     { rv_op_fneg_s, rvcc_fneg_s },
1286     { rv_op_illegal, NULL }
1287 };
1288
1289 static const rv_comp_data rvcp_fsgnjx_s[] = {
1290     { rv_op_fabs_s, rvcc_fabs_s },
1291     { rv_op_illegal, NULL }
1292 };
1293
1294 static const rv_comp_data rvcp_fsgnj_d[] = {
1295     { rv_op_fmv_d, rvcc_fmv_d },
1296     { rv_op_illegal, NULL }
1297 };
1298
1299 static const rv_comp_data rvcp_fsgnjn_d[] = {
1300     { rv_op_fneg_d, rvcc_fneg_d },
1301     { rv_op_illegal, NULL }
1302 };
1303
1304 static const rv_comp_data rvcp_fsgnjx_d[] = {
1305     { rv_op_fabs_d, rvcc_fabs_d },
1306     { rv_op_illegal, NULL }
1307 };
1308
1309 static const rv_comp_data rvcp_fsgnj_q[] = {
1310     { rv_op_fmv_q, rvcc_fmv_q },
1311     { rv_op_illegal, NULL }
1312 };
1313
1314 static const rv_comp_data rvcp_fsgnjn_q[] = {
1315     { rv_op_fneg_q, rvcc_fneg_q },
1316     { rv_op_illegal, NULL }
1317 };
1318
1319 static const rv_comp_data rvcp_fsgnjx_q[] = {
1320     { rv_op_fabs_q, rvcc_fabs_q },
1321     { rv_op_illegal, NULL }
1322 };
1323
1324 /* instruction metadata */
1325
1326 const rv_opcode_data opcode_data[] = {
1327     { "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
1328     { "lui", rv_codec_u, rv_fmt_rd_imm, NULL, 0, 0, 0 },
1329     { "auipc", rv_codec_u, rv_fmt_rd_offset, NULL, 0, 0, 0 },
1330     { "jal", rv_codec_uj, rv_fmt_rd_offset, rvcp_jal, 0, 0, 0 },
1331     { "jalr", rv_codec_i, rv_fmt_rd_rs1_offset, rvcp_jalr, 0, 0, 0 },
1332     { "beq", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_beq, 0, 0, 0 },
1333     { "bne", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bne, 0, 0, 0 },
1334     { "blt", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_blt, 0, 0, 0 },
1335     { "bge", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bge, 0, 0, 0 },
1336     { "bltu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bltu, 0, 0, 0 },
1337     { "bgeu", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_bgeu, 0, 0, 0 },
1338     { "lb", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1339     { "lh", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1340     { "lw", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1341     { "lbu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1342     { "lhu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1343     { "sb", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
1344     { "sh", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
1345     { "sw", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
1346     { "addi", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addi, 0, 0, 0 },
1347     { "slti", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1348     { "sltiu", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_sltiu, 0, 0, 0 },
1349     { "xori", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_xori, 0, 0, 0 },
1350     { "ori", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1351     { "andi", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1352     { "slli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1353     { "srli", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1354     { "srai", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1355     { "add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1356     { "sub", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sub, 0, 0, 0 },
1357     { "sll", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1358     { "slt", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_slt, 0, 0, 0 },
1359     { "sltu", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_sltu, 0, 0, 0 },
1360     { "xor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1361     { "srl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1362     { "sra", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1363     { "or", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1364     { "and", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1365     { "fence", rv_codec_r_f, rv_fmt_pred_succ, NULL, 0, 0, 0 },
1366     { "fence.i", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1367     { "lwu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1368     { "ld", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1369     { "sd", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
1370     { "addiw", rv_codec_i, rv_fmt_rd_rs1_imm, rvcp_addiw, 0, 0, 0 },
1371     { "slliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1372     { "srliw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1373     { "sraiw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1374     { "addw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1375     { "subw", rv_codec_r, rv_fmt_rd_rs1_rs2, rvcp_subw, 0, 0, 0 },
1376     { "sllw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1377     { "srlw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1378     { "sraw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1379     { "ldu", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1380     { "lq", rv_codec_i, rv_fmt_rd_offset_rs1, NULL, 0, 0, 0 },
1381     { "sq", rv_codec_s, rv_fmt_rs2_offset_rs1, NULL, 0, 0, 0 },
1382     { "addid", rv_codec_i, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1383     { "sllid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1384     { "srlid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1385     { "sraid", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1386     { "addd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1387     { "subd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1388     { "slld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1389     { "srld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1390     { "srad", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1391     { "mul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1392     { "mulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1393     { "mulhsu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1394     { "mulhu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1395     { "div", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1396     { "divu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1397     { "rem", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1398     { "remu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1399     { "mulw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1400     { "divw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1401     { "divuw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1402     { "remw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1403     { "remuw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1404     { "muld", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1405     { "divd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1406     { "divud", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1407     { "remd", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1408     { "remud", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1409     { "lr.w", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 },
1410     { "sc.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1411     { "amoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1412     { "amoadd.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1413     { "amoxor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1414     { "amoor.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1415     { "amoand.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1416     { "amomin.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1417     { "amomax.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1418     { "amominu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1419     { "amomaxu.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1420     { "lr.d", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 },
1421     { "sc.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1422     { "amoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1423     { "amoadd.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1424     { "amoxor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1425     { "amoor.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1426     { "amoand.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1427     { "amomin.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1428     { "amomax.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1429     { "amominu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1430     { "amomaxu.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1431     { "lr.q", rv_codec_r_l, rv_fmt_aqrl_rd_rs1, NULL, 0, 0, 0 },
1432     { "sc.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1433     { "amoswap.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1434     { "amoadd.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1435     { "amoxor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1436     { "amoor.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1437     { "amoand.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1438     { "amomin.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1439     { "amomax.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1440     { "amominu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1441     { "amomaxu.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
1442     { "ecall", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1443     { "ebreak", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1444     { "uret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1445     { "sret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1446     { "hret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1447     { "mret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1448     { "dret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1449     { "sfence.vm", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
1450     { "sfence.vma", rv_codec_r, rv_fmt_rs1_rs2, NULL, 0, 0, 0 },
1451     { "wfi", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
1452     { "csrrw", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrw, 0, 0, 0 },
1453     { "csrrs", rv_codec_i_csr, rv_fmt_rd_csr_rs1, rvcp_csrrs, 0, 0, 0 },
1454     { "csrrc", rv_codec_i_csr, rv_fmt_rd_csr_rs1, NULL, 0, 0, 0 },
1455     { "csrrwi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, rvcp_csrrwi, 0, 0, 0 },
1456     { "csrrsi", rv_codec_i_csr, rv_fmt_rd_csr_zimm, NULL, 0, 0, 0 },
1457     { "csrrci", rv_codec_i_csr, rv_fmt_rd_csr_zimm, NULL, 0, 0, 0 },
1458     { "flw", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 },
1459     { "fsw", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 },
1460     { "fmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1461     { "fmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1462     { "fnmsub.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1463     { "fnmadd.s", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1464     { "fadd.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1465     { "fsub.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1466     { "fmul.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1467     { "fdiv.s", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1468     { "fsgnj.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_s, 0, 0, 0 },
1469     { "fsgnjn.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_s, 0, 0, 0 },
1470     { "fsgnjx.s", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_s, 0, 0, 0 },
1471     { "fmin.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
1472     { "fmax.s", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
1473     { "fsqrt.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1474     { "fle.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1475     { "flt.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1476     { "feq.s", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1477     { "fcvt.w.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1478     { "fcvt.wu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1479     { "fcvt.s.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1480     { "fcvt.s.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1481     { "fmv.x.s", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
1482     { "fclass.s", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
1483     { "fmv.s.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },
1484     { "fcvt.l.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1485     { "fcvt.lu.s", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1486     { "fcvt.s.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1487     { "fcvt.s.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1488     { "fld", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 },
1489     { "fsd", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 },
1490     { "fmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1491     { "fmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1492     { "fnmsub.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1493     { "fnmadd.d", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1494     { "fadd.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1495     { "fsub.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1496     { "fmul.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1497     { "fdiv.d", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1498     { "fsgnj.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_d, 0, 0, 0 },
1499     { "fsgnjn.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_d, 0, 0, 0 },
1500     { "fsgnjx.d", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_d, 0, 0, 0 },
1501     { "fmin.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
1502     { "fmax.d", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
1503     { "fcvt.s.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1504     { "fcvt.d.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1505     { "fsqrt.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1506     { "fle.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1507     { "flt.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1508     { "feq.d", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1509     { "fcvt.w.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1510     { "fcvt.wu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1511     { "fcvt.d.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1512     { "fcvt.d.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1513     { "fclass.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
1514     { "fcvt.l.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1515     { "fcvt.lu.d", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1516     { "fmv.x.d", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
1517     { "fcvt.d.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1518     { "fcvt.d.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1519     { "fmv.d.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },
1520     { "flq", rv_codec_i, rv_fmt_frd_offset_rs1, NULL, 0, 0, 0 },
1521     { "fsq", rv_codec_s, rv_fmt_frs2_offset_rs1, NULL, 0, 0, 0 },
1522     { "fmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1523     { "fmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1524     { "fnmsub.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1525     { "fnmadd.q", rv_codec_r4_m, rv_fmt_rm_frd_frs1_frs2_frs3, NULL, 0, 0, 0 },
1526     { "fadd.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1527     { "fsub.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1528     { "fmul.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1529     { "fdiv.q", rv_codec_r_m, rv_fmt_rm_frd_frs1_frs2, NULL, 0, 0, 0 },
1530     { "fsgnj.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnj_q, 0, 0, 0 },
1531     { "fsgnjn.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjn_q, 0, 0, 0 },
1532     { "fsgnjx.q", rv_codec_r, rv_fmt_frd_frs1_frs2, rvcp_fsgnjx_q, 0, 0, 0 },
1533     { "fmin.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
1534     { "fmax.q", rv_codec_r, rv_fmt_frd_frs1_frs2, NULL, 0, 0, 0 },
1535     { "fcvt.s.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1536     { "fcvt.q.s", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1537     { "fcvt.d.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1538     { "fcvt.q.d", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1539     { "fsqrt.q", rv_codec_r_m, rv_fmt_rm_frd_frs1, NULL, 0, 0, 0 },
1540     { "fle.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1541     { "flt.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1542     { "feq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 },
1543     { "fcvt.w.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1544     { "fcvt.wu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1545     { "fcvt.q.w", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1546     { "fcvt.q.wu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1547     { "fclass.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
1548     { "fcvt.l.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1549     { "fcvt.lu.q", rv_codec_r_m, rv_fmt_rm_rd_frs1, NULL, 0, 0, 0 },
1550     { "fcvt.q.l", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1551     { "fcvt.q.lu", rv_codec_r_m, rv_fmt_rm_frd_rs1, NULL, 0, 0, 0 },
1552     { "fmv.x.q", rv_codec_r, rv_fmt_rd_frs1, NULL, 0, 0, 0 },
1553     { "fmv.q.x", rv_codec_r, rv_fmt_frd_rs1, NULL, 0, 0, 0 },
1554     { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
1555       rv_op_addi, rv_op_addi, rvcd_imm_nz },
1556     { "c.fld", rv_codec_cl_ld, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, rv_op_fld, 0 },
1557     { "c.lw", rv_codec_cl_lw, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw, rv_op_lw },
1558     { "c.flw", rv_codec_cl_lw, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 },
1559     { "c.fsd", rv_codec_cs_sd, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, rv_op_fsd, 0 },
1560     { "c.sw", rv_codec_cs_sw, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw, rv_op_sw },
1561     { "c.fsw", rv_codec_cs_sw, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 },
1562     { "c.nop", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_addi, rv_op_addi, rv_op_addi },
1563     { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi,
1564       rv_op_addi, rvcd_imm_nz },
1565     { "c.jal", rv_codec_cj_jal, rv_fmt_rd_offset, NULL, rv_op_jal, 0, 0 },
1566     { "c.li", rv_codec_ci_li, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi },
1567     { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
1568       rv_op_addi, rv_op_addi, rvcd_imm_nz },
1569     { "c.lui", rv_codec_ci_lui, rv_fmt_rd_imm, NULL, rv_op_lui, rv_op_lui,
1570       rv_op_lui, rvcd_imm_nz },
1571     { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srli,
1572       rv_op_srli, rv_op_srli, rvcd_imm_nz },
1573     { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srai,
1574       rv_op_srai, rv_op_srai, rvcd_imm_nz },
1575     { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi,
1576       rv_op_andi, rv_op_andi },
1577     { "c.sub", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_sub, rv_op_sub, rv_op_sub },
1578     { "c.xor", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_xor, rv_op_xor, rv_op_xor },
1579     { "c.or", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_or, rv_op_or, rv_op_or },
1580     { "c.and", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_and, rv_op_and, rv_op_and },
1581     { "c.subw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_subw, rv_op_subw, rv_op_subw },
1582     { "c.addw", rv_codec_cs, rv_fmt_rd_rs1_rs2, NULL, rv_op_addw, rv_op_addw, rv_op_addw },
1583     { "c.j", rv_codec_cj, rv_fmt_rd_offset, NULL, rv_op_jal, rv_op_jal, rv_op_jal },
1584     { "c.beqz", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_beq, rv_op_beq, rv_op_beq },
1585     { "c.bnez", rv_codec_cb, rv_fmt_rs1_rs2_offset, NULL, rv_op_bne, rv_op_bne, rv_op_bne },
1586     { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_slli,
1587       rv_op_slli, rv_op_slli, rvcd_imm_nz },
1588     { "c.fldsp", rv_codec_ci_ldsp, rv_fmt_frd_offset_rs1, NULL, rv_op_fld, rv_op_fld, rv_op_fld },
1589     { "c.lwsp", rv_codec_ci_lwsp, rv_fmt_rd_offset_rs1, NULL, rv_op_lw, rv_op_lw, rv_op_lw },
1590     { "c.flwsp", rv_codec_ci_lwsp, rv_fmt_frd_offset_rs1, NULL, rv_op_flw, 0, 0 },
1591     { "c.jr", rv_codec_cr_jr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, rv_op_jalr, rv_op_jalr },
1592     { "c.mv", rv_codec_cr_mv, rv_fmt_rd_rs1_rs2, NULL, rv_op_addi, rv_op_addi, rv_op_addi },
1593     { "c.ebreak", rv_codec_ci_none, rv_fmt_none, NULL, rv_op_ebreak, rv_op_ebreak, rv_op_ebreak },
1594     { "c.jalr", rv_codec_cr_jalr, rv_fmt_rd_rs1_offset, NULL, rv_op_jalr, rv_op_jalr, rv_op_jalr },
1595     { "c.add", rv_codec_cr, rv_fmt_rd_rs1_rs2, NULL, rv_op_add, rv_op_add, rv_op_add },
1596     { "c.fsdsp", rv_codec_css_sdsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsd, rv_op_fsd, rv_op_fsd },
1597     { "c.swsp", rv_codec_css_swsp, rv_fmt_rs2_offset_rs1, NULL, rv_op_sw, rv_op_sw, rv_op_sw },
1598     { "c.fswsp", rv_codec_css_swsp, rv_fmt_frs2_offset_rs1, NULL, rv_op_fsw, 0, 0 },
1599     { "c.ld", rv_codec_cl_ld, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, rv_op_ld },
1600     { "c.sd", rv_codec_cs_sd, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, rv_op_sd },
1601     { "c.addiw", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, 0, rv_op_addiw, rv_op_addiw },
1602     { "c.ldsp", rv_codec_ci_ldsp, rv_fmt_rd_offset_rs1, NULL, 0, rv_op_ld, rv_op_ld },
1603     { "c.sdsp", rv_codec_css_sdsp, rv_fmt_rs2_offset_rs1, NULL, 0, rv_op_sd, rv_op_sd },
1604     { "c.lq", rv_codec_cl_lq, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq },
1605     { "c.sq", rv_codec_cs_sq, rv_fmt_rs2_offset_rs1, NULL, 0, 0, rv_op_sq },
1606     { "c.lqsp", rv_codec_ci_lqsp, rv_fmt_rd_offset_rs1, NULL, 0, 0, rv_op_lq },
1607     { "c.sqsp", rv_codec_css_sqsp, rv_fmt_rs2_offset_rs1, NULL, 0, 0, rv_op_sq },
1608     { "nop", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 },
1609     { "mv", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1610     { "not", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1611     { "neg", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
1612     { "negw", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
1613     { "sext.w", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1614     { "seqz", rv_codec_i, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1615     { "snez", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
1616     { "sltz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1617     { "sgtz", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
1618     { "fmv.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1619     { "fabs.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1620     { "fneg.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1621     { "fmv.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1622     { "fabs.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1623     { "fneg.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1624     { "fmv.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1625     { "fabs.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1626     { "fneg.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
1627     { "beqz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
1628     { "bnez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
1629     { "blez", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 },
1630     { "bgez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
1631     { "bltz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
1632     { "bgtz", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 },
1633     { "ble", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 },
1634     { "bleu", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 },
1635     { "bgt", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 },
1636     { "bgtu", rv_codec_sb, rv_fmt_rs2_rs1_offset, NULL, 0, 0, 0 },
1637     { "j", rv_codec_uj, rv_fmt_offset, NULL, 0, 0, 0 },
1638     { "ret", rv_codec_i, rv_fmt_none, NULL, 0, 0, 0 },
1639     { "jr", rv_codec_i, rv_fmt_rs1, NULL, 0, 0, 0 },
1640     { "rdcycle", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1641     { "rdtime", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1642     { "rdinstret", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1643     { "rdcycleh", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1644     { "rdtimeh", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1645     { "rdinstreth", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1646     { "frcsr", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1647     { "frrm", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1648     { "frflags", rv_codec_i_csr, rv_fmt_rd, NULL, 0, 0, 0 },
1649     { "fscsr", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1650     { "fsrm", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1651     { "fsflags", rv_codec_i_csr, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1652     { "fsrmi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 },
1653     { "fsflagsi", rv_codec_i_csr, rv_fmt_rd_zimm, NULL, 0, 0, 0 },
1654     { "bseti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1655     { "bclri", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1656     { "binvi", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1657     { "bexti", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1658     { "rori", rv_codec_i_sh7, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1659     { "clz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1660     { "ctz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1661     { "cpop", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1662     { "sext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1663     { "sext.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1664     { "xnor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1665     { "orn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1666     { "andn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1667     { "rol", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1668     { "ror", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1669     { "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1670     { "sh2add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1671     { "sh3add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1672     { "sh1add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1673     { "sh2add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1674     { "sh3add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1675     { "clmul", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1676     { "clmulr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1677     { "clmulh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1678     { "min", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1679     { "minu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1680     { "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1681     { "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1682     { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1683     { "ctzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1684     { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1685     { "slli.uw", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1686     { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1687     { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1688     { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1689     { "rev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1690     { "zext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1691     { "roriw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
1692     { "orc.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1693     { "bset", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1694     { "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1695     { "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1696     { "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1697     { "aes32esmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
1698     { "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
1699     { "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
1700     { "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
1701     { "aes64ks1i", rv_codec_k_rnum,  rv_fmt_rd_rs1_rnum, NULL, 0, 0, 0 },
1702     { "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1703     { "aes64im", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1704     { "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1705     { "aes64es", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1706     { "aes64dsm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1707     { "aes64ds", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1708     { "sha256sig0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1709     { "sha256sig1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1710     { "sha256sum0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1711     { "sha256sum1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1712     { "sha512sig0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1713     { "sha512sig1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1714     { "sha512sum0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1715     { "sha512sum1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1716     { "sha512sum0r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1717     { "sha512sum1r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1718     { "sha512sig0l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1719     { "sha512sig0h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1720     { "sha512sig1l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1721     { "sha512sig1h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1722     { "sm3p0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1723     { "sm3p1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
1724     { "sm4ed", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
1725     { "sm4ks", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
1726     { "brev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1727     { "pack", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1728     { "packh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1729     { "packw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1730     { "unzip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1731     { "zip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1732     { "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
1733     { "xperm8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
1734     { "vle8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle8_v, rv_op_vle8_v, 0 },
1735     { "vle16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle16_v, rv_op_vle16_v, 0 },
1736     { "vle32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle32_v, rv_op_vle32_v, 0 },
1737     { "vle64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle64_v, rv_op_vle64_v, 0 },
1738     { "vse8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vse8_v, rv_op_vse8_v, 0 },
1739     { "vse16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vse16_v, rv_op_vse16_v, 0 },
1740     { "vse32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vse32_v, rv_op_vse32_v, 0 },
1741     { "vse64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vse64_v, rv_op_vse64_v, 0 },
1742     { "vlm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vlm_v, rv_op_vlm_v, 0 },
1743     { "vsm.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vsm_v, rv_op_vsm_v, 0 },
1744     { "vlse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vlse8_v, rv_op_vlse8_v, 0 },
1745     { "vlse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vlse16_v, rv_op_vlse16_v, 0 },
1746     { "vlse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vlse32_v, rv_op_vlse32_v, 0 },
1747     { "vlse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vlse64_v, rv_op_vlse64_v, 0 },
1748     { "vsse8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vsse8_v, rv_op_vsse8_v, 0 },
1749     { "vsse16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vsse16_v, rv_op_vsse16_v, 0 },
1750     { "vsse32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vsse32_v, rv_op_vsse32_v, 0 },
1751     { "vsse64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_rs2_vm, NULL, rv_op_vsse64_v, rv_op_vsse64_v, 0 },
1752     { "vluxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vluxei8_v, rv_op_vluxei8_v, 0 },
1753     { "vluxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vluxei16_v, rv_op_vluxei16_v, 0 },
1754     { "vluxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vluxei32_v, rv_op_vluxei32_v, 0 },
1755     { "vluxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vluxei64_v, rv_op_vluxei64_v, 0 },
1756     { "vloxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vloxei8_v, rv_op_vloxei8_v, 0 },
1757     { "vloxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vloxei16_v, rv_op_vloxei16_v, 0 },
1758     { "vloxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vloxei32_v, rv_op_vloxei32_v, 0 },
1759     { "vloxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vloxei64_v, rv_op_vloxei64_v, 0 },
1760     { "vsuxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsuxei8_v, rv_op_vsuxei8_v, 0 },
1761     { "vsuxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsuxei16_v, rv_op_vsuxei16_v, 0 },
1762     { "vsuxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsuxei32_v, rv_op_vsuxei32_v, 0 },
1763     { "vsuxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsuxei64_v, rv_op_vsuxei64_v, 0 },
1764     { "vsoxei8.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsoxei8_v, rv_op_vsoxei8_v, 0 },
1765     { "vsoxei16.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsoxei16_v, rv_op_vsoxei16_v, 0 },
1766     { "vsoxei32.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsoxei32_v, rv_op_vsoxei32_v, 0 },
1767     { "vsoxei64.v", rv_codec_v_r, rv_fmt_ldst_vd_rs1_vs2_vm, NULL, rv_op_vsoxei64_v, rv_op_vsoxei64_v, 0 },
1768     { "vle8ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle8ff_v, rv_op_vle8ff_v, 0 },
1769     { "vle16ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle16ff_v, rv_op_vle16ff_v, 0 },
1770     { "vle32ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle32ff_v, rv_op_vle32ff_v, 0 },
1771     { "vle64ff.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vle64ff_v, rv_op_vle64ff_v, 0 },
1772     { "vl1re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl1re8_v, rv_op_vl1re8_v, 0 },
1773     { "vl1re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl1re16_v, rv_op_vl1re16_v, 0 },
1774     { "vl1re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl1re32_v, rv_op_vl1re32_v, 0 },
1775     { "vl1re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl1re64_v, rv_op_vl1re64_v, 0 },
1776     { "vl2re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl2re8_v, rv_op_vl2re8_v, 0 },
1777     { "vl2re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl2re16_v, rv_op_vl2re16_v, 0 },
1778     { "vl2re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl2re32_v, rv_op_vl2re32_v, 0 },
1779     { "vl2re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl2re64_v, rv_op_vl2re64_v, 0 },
1780     { "vl4re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl4re8_v, rv_op_vl4re8_v, 0 },
1781     { "vl4re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl4re16_v, rv_op_vl4re16_v, 0 },
1782     { "vl4re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl4re32_v, rv_op_vl4re32_v, 0 },
1783     { "vl4re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl4re64_v, rv_op_vl4re64_v, 0 },
1784     { "vl8re8.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl8re8_v, rv_op_vl8re8_v, 0 },
1785     { "vl8re16.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl8re16_v, rv_op_vl8re16_v, 0 },
1786     { "vl8re32.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl8re32_v, rv_op_vl8re32_v, 0 },
1787     { "vl8re64.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vl8re64_v, rv_op_vl8re64_v, 0 },
1788     { "vs1r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vs1r_v, rv_op_vs1r_v, 0 },
1789     { "vs2r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vs2r_v, rv_op_vs2r_v, 0 },
1790     { "vs4r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vs4r_v, rv_op_vs4r_v, 0 },
1791     { "vs8r.v", rv_codec_v_ldst, rv_fmt_ldst_vd_rs1_vm, NULL, rv_op_vs8r_v, rv_op_vs8r_v, 0 },
1792     { "vadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vadd_vv, rv_op_vadd_vv, 0 },
1793     { "vadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vadd_vx, rv_op_vadd_vx, 0 },
1794     { "vadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vadd_vi, rv_op_vadd_vi, 0 },
1795     { "vsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsub_vv, rv_op_vsub_vv, 0 },
1796     { "vsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsub_vx, rv_op_vsub_vx, 0 },
1797     { "vrsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vrsub_vx, rv_op_vrsub_vx, 0 },
1798     { "vrsub.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vrsub_vi, rv_op_vrsub_vi, 0 },
1799     { "vwaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwaddu_vv, rv_op_vwaddu_vv, 0 },
1800     { "vwaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwaddu_vx, rv_op_vwaddu_vx, 0 },
1801     { "vwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwadd_vv, rv_op_vwadd_vv, 0 },
1802     { "vwadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwadd_vx, rv_op_vwadd_vx, 0 },
1803     { "vwsubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwsubu_vv, rv_op_vwsubu_vv, 0 },
1804     { "vwsubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwsubu_vx, rv_op_vwsubu_vx, 0 },
1805     { "vwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwsub_vv, rv_op_vwsub_vv, 0 },
1806     { "vwsub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwsub_vx, rv_op_vwsub_vx, 0 },
1807     { "vwaddu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwaddu_wv, rv_op_vwaddu_wv, 0 },
1808     { "vwaddu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwaddu_wx, rv_op_vwaddu_wx, 0 },
1809     { "vwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwadd_wv, rv_op_vwadd_wv, 0 },
1810     { "vwadd.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwadd_wx, rv_op_vwadd_wx, 0 },
1811     { "vwsubu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwsubu_wv, rv_op_vwsubu_wv, 0 },
1812     { "vwsubu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwsubu_wx, rv_op_vwsubu_wx, 0 },
1813     { "vwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwsub_wv, rv_op_vwsub_wv, 0 },
1814     { "vwsub.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwsub_wx, rv_op_vwsub_wx, 0 },
1815     { "vadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vadc_vvm, rv_op_vadc_vvm, 0 },
1816     { "vadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vadc_vxm, rv_op_vadc_vxm, 0 },
1817     { "vadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, rv_op_vadc_vim, rv_op_vadc_vim, 0 },
1818     { "vmadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vmadc_vvm, rv_op_vmadc_vvm, 0 },
1819     { "vmadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vmadc_vxm, rv_op_vmadc_vxm, 0 },
1820     { "vmadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, rv_op_vmadc_vim, rv_op_vmadc_vim, 0 },
1821     { "vsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vsbc_vvm, rv_op_vsbc_vvm, 0 },
1822     { "vsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vsbc_vxm, rv_op_vsbc_vxm, 0 },
1823     { "vmsbc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vmsbc_vvm, rv_op_vmsbc_vvm, 0 },
1824     { "vmsbc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vmsbc_vxm, rv_op_vmsbc_vxm, 0 },
1825     { "vand.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vand_vv, rv_op_vand_vv, 0 },
1826     { "vand.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vand_vx, rv_op_vand_vx, 0 },
1827     { "vand.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vand_vi, rv_op_vand_vi, 0 },
1828     { "vor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vor_vv, rv_op_vor_vv, 0 },
1829     { "vor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vor_vx, rv_op_vor_vx, 0 },
1830     { "vor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vor_vi, rv_op_vor_vi, 0 },
1831     { "vxor.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vxor_vv, rv_op_vxor_vv, 0 },
1832     { "vxor.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vxor_vx, rv_op_vxor_vx, 0 },
1833     { "vxor.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vxor_vi, rv_op_vxor_vi, 0 },
1834     { "vsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsll_vv, rv_op_vsll_vv, 0 },
1835     { "vsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsll_vx, rv_op_vsll_vx, 0 },
1836     { "vsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vsll_vi, rv_op_vsll_vi, 0 },
1837     { "vsrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsrl_vv, rv_op_vsrl_vv, 0 },
1838     { "vsrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsrl_vx, rv_op_vsrl_vx, 0 },
1839     { "vsrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vsrl_vi, rv_op_vsrl_vi, 0 },
1840     { "vsra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsra_vv, rv_op_vsra_vv, 0 },
1841     { "vsra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsra_vx, rv_op_vsra_vx, 0 },
1842     { "vsra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vsra_vi, rv_op_vsra_vi, 0 },
1843     { "vnsrl.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vnsrl_wv, rv_op_vnsrl_wv, 0 },
1844     { "vnsrl.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vnsrl_wx, rv_op_vnsrl_wx, 0 },
1845     { "vnsrl.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vnsrl_wi, rv_op_vnsrl_wi, 0 },
1846     { "vnsra.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vnsra_wv, rv_op_vnsra_wv, 0 },
1847     { "vnsra.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vnsra_wx, rv_op_vnsra_wx, 0 },
1848     { "vnsra.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vnsra_wi, rv_op_vnsra_wi, 0 },
1849     { "vmseq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmseq_vv, rv_op_vmseq_vv, 0 },
1850     { "vmseq.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmseq_vx, rv_op_vmseq_vx, 0 },
1851     { "vmseq.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmseq_vi, rv_op_vmseq_vi, 0 },
1852     { "vmsne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmsne_vv, rv_op_vmsne_vv, 0 },
1853     { "vmsne.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsne_vx, rv_op_vmsne_vx, 0 },
1854     { "vmsne.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsne_vi, rv_op_vmsne_vi, 0 },
1855     { "vmsltu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmsltu_vv, rv_op_vmsltu_vv, 0 },
1856     { "vmsltu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsltu_vx, rv_op_vmsltu_vx, 0 },
1857     { "vmslt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmslt_vv, rv_op_vmslt_vv, 0 },
1858     { "vmslt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmslt_vx, rv_op_vmslt_vx, 0 },
1859     { "vmsleu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmsleu_vv, rv_op_vmsleu_vv, 0 },
1860     { "vmsleu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsleu_vx, rv_op_vmsleu_vx, 0 },
1861     { "vmsleu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsleu_vi, rv_op_vmsleu_vi, 0 },
1862     { "vmsle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmsle_vv, rv_op_vmsle_vv, 0 },
1863     { "vmsle.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsle_vx, rv_op_vmsle_vx, 0 },
1864     { "vmsle.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsle_vi, rv_op_vmsle_vi, 0 },
1865     { "vmsgtu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsgtu_vx, rv_op_vmsgtu_vx, 0 },
1866     { "vmsgtu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsgtu_vi, rv_op_vmsgtu_vi, 0 },
1867     { "vmsgt.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmsgt_vx, rv_op_vmsgt_vx, 0 },
1868     { "vmsgt.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vmsgt_vi, rv_op_vmsgt_vi, 0 },
1869     { "vminu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vminu_vv, rv_op_vminu_vv, 0 },
1870     { "vminu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vminu_vx, rv_op_vminu_vx, 0 },
1871     { "vmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmin_vv, rv_op_vmin_vv, 0 },
1872     { "vmin.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmin_vx, rv_op_vmin_vx, 0 },
1873     { "vmaxu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmaxu_vv, rv_op_vmaxu_vv, 0 },
1874     { "vmaxu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmaxu_vx, rv_op_vmaxu_vx, 0 },
1875     { "vmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmax_vv, rv_op_vmax_vv, 0 },
1876     { "vmax.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmax_vx, rv_op_vmax_vx, 0 },
1877     { "vmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmul_vv, rv_op_vmul_vv, 0 },
1878     { "vmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmul_vx, rv_op_vmul_vx, 0 },
1879     { "vmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmulh_vv, rv_op_vmulh_vv, 0 },
1880     { "vmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmulh_vx, rv_op_vmulh_vx, 0 },
1881     { "vmulhu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmulhu_vv, rv_op_vmulhu_vv, 0 },
1882     { "vmulhu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmulhu_vx, rv_op_vmulhu_vx, 0 },
1883     { "vmulhsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmulhsu_vv, rv_op_vmulhsu_vv, 0 },
1884     { "vmulhsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vmulhsu_vx, rv_op_vmulhsu_vx, 0 },
1885     { "vdivu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vdivu_vv, rv_op_vdivu_vv, 0 },
1886     { "vdivu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vdivu_vx, rv_op_vdivu_vx, 0 },
1887     { "vdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vdiv_vv, rv_op_vdiv_vv, 0 },
1888     { "vdiv.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vdiv_vx, rv_op_vdiv_vx, 0 },
1889     { "vremu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vremu_vv, rv_op_vremu_vv, 0 },
1890     { "vremu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vremu_vx, rv_op_vremu_vx, 0 },
1891     { "vrem.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vrem_vv, rv_op_vrem_vv, 0 },
1892     { "vrem.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vrem_vx, rv_op_vrem_vx, 0 },
1893     { "vwmulu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwmulu_vv, rv_op_vwmulu_vv, 0 },
1894     { "vwmulu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwmulu_vx, rv_op_vwmulu_vx, 0 },
1895     { "vwmulsu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwmulsu_vv, rv_op_vwmulsu_vv, 0 },
1896     { "vwmulsu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwmulsu_vx, rv_op_vwmulsu_vx, 0 },
1897     { "vwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwmul_vv, rv_op_vwmul_vv, 0 },
1898     { "vwmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vwmul_vx, rv_op_vwmul_vx, 0 },
1899     { "vmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vmacc_vv, rv_op_vmacc_vv, 0 },
1900     { "vmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vmacc_vx, rv_op_vmacc_vx, 0 },
1901     { "vnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vnmsac_vv, rv_op_vnmsac_vv, 0 },
1902     { "vnmsac.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vnmsac_vx, rv_op_vnmsac_vx, 0 },
1903     { "vmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vmadd_vv, rv_op_vmadd_vv, 0 },
1904     { "vmadd.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vmadd_vx, rv_op_vmadd_vx, 0 },
1905     { "vnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vnmsub_vv, rv_op_vnmsub_vv, 0 },
1906     { "vnmsub.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vnmsub_vx, rv_op_vnmsub_vx, 0 },
1907     { "vwmaccu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vwmaccu_vv, rv_op_vwmaccu_vv, 0 },
1908     { "vwmaccu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vwmaccu_vx, rv_op_vwmaccu_vx, 0 },
1909     { "vwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vwmacc_vv, rv_op_vwmacc_vv, 0 },
1910     { "vwmacc.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vwmacc_vx, rv_op_vwmacc_vx, 0 },
1911     { "vwmaccsu.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vwmaccsu_vv, rv_op_vwmaccsu_vv, 0 },
1912     { "vwmaccsu.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vwmaccsu_vx, rv_op_vwmaccsu_vx, 0 },
1913     { "vwmaccus.vx", rv_codec_v_r, rv_fmt_vd_rs1_vs2_vm, NULL, rv_op_vwmaccus_vx, rv_op_vwmaccus_vx, 0 },
1914     { "vmv.v.v", rv_codec_v_r, rv_fmt_vd_vs1, NULL, rv_op_vmv_v_v, rv_op_vmv_v_v, 0 },
1915     { "vmv.v.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, rv_op_vmv_v_x, rv_op_vmv_v_x, 0 },
1916     { "vmv.v.i", rv_codec_v_i, rv_fmt_vd_imm, NULL, rv_op_vmv_v_i, rv_op_vmv_v_i, 0 },
1917     { "vmerge.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl, NULL, rv_op_vmerge_vvm, rv_op_vmerge_vvm, 0 },
1918     { "vmerge.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl, NULL, rv_op_vmerge_vxm, rv_op_vmerge_vxm, 0 },
1919     { "vmerge.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl, NULL, rv_op_vmerge_vim, rv_op_vmerge_vim, 0 },
1920     { "vsaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsaddu_vv, rv_op_vsaddu_vv, 0 },
1921     { "vsaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsaddu_vx, rv_op_vsaddu_vx, 0 },
1922     { "vsaddu.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vsaddu_vi, rv_op_vsaddu_vi, 0 },
1923     { "vsadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsadd_vv, rv_op_vsadd_vv, 0 },
1924     { "vsadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsadd_vx, rv_op_vsadd_vx, 0 },
1925     { "vsadd.vi", rv_codec_v_i, rv_fmt_vd_vs2_imm_vm, NULL, rv_op_vsadd_vi, rv_op_vsadd_vi, 0 },
1926     { "vssubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vssubu_vv, rv_op_vssubu_vv, 0 },
1927     { "vssubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vssubu_vx, rv_op_vssubu_vx, 0 },
1928     { "vssub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vssub_vv, rv_op_vssub_vv, 0 },
1929     { "vssub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vssub_vx, rv_op_vssub_vx, 0 },
1930     { "vaadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vaadd_vv, rv_op_vaadd_vv, 0 },
1931     { "vaadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vaadd_vx, rv_op_vaadd_vx, 0 },
1932     { "vaaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vaaddu_vv, rv_op_vaaddu_vv, 0 },
1933     { "vaaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vaaddu_vx, rv_op_vaaddu_vx, 0 },
1934     { "vasub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vasub_vv, rv_op_vasub_vv, 0 },
1935     { "vasub.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vasub_vx, rv_op_vasub_vx, 0 },
1936     { "vasubu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vasubu_vv, rv_op_vasubu_vv, 0 },
1937     { "vasubu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vasubu_vx, rv_op_vasubu_vx, 0 },
1938     { "vsmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vsmul_vv, rv_op_vsmul_vv, 0 },
1939     { "vsmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vsmul_vx, rv_op_vsmul_vx, 0 },
1940     { "vssrl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vssrl_vv, rv_op_vssrl_vv, 0 },
1941     { "vssrl.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vssrl_vx, rv_op_vssrl_vx, 0 },
1942     { "vssrl.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vssrl_vi, rv_op_vssrl_vi, 0 },
1943     { "vssra.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vssra_vv, rv_op_vssra_vv, 0 },
1944     { "vssra.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vssra_vx, rv_op_vssra_vx, 0 },
1945     { "vssra.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vssra_vi, rv_op_vssra_vi, 0 },
1946     { "vnclipu.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vnclipu_wv, rv_op_vnclipu_wv, 0 },
1947     { "vnclipu.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vnclipu_wx, rv_op_vnclipu_wx, 0 },
1948     { "vnclipu.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vnclipu_wi, rv_op_vnclipu_wi, 0 },
1949     { "vnclip.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vnclip_wv, rv_op_vnclip_wv, 0 },
1950     { "vnclip.wx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vnclip_wx, rv_op_vnclip_wx, 0 },
1951     { "vnclip.wi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vnclip_wi, rv_op_vnclip_wi, 0 },
1952     { "vfadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfadd_vv, rv_op_vfadd_vv, 0 },
1953     { "vfadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfadd_vf, rv_op_vfadd_vf, 0 },
1954     { "vfsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfsub_vv, rv_op_vfsub_vv, 0 },
1955     { "vfsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfsub_vf, rv_op_vfsub_vf, 0 },
1956     { "vfrsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfrsub_vf, rv_op_vfrsub_vf, 0 },
1957     { "vfwadd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwadd_vv, rv_op_vfwadd_vv, 0 },
1958     { "vfwadd.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwadd_vf, rv_op_vfwadd_vf, 0 },
1959     { "vfwadd.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwadd_wv, rv_op_vfwadd_wv, 0 },
1960     { "vfwadd.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwadd_wf, rv_op_vfwadd_wf, 0 },
1961     { "vfwsub.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwsub_vv, rv_op_vfwsub_vv, 0 },
1962     { "vfwsub.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwsub_vf, rv_op_vfwsub_vf, 0 },
1963     { "vfwsub.wv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwsub_wv, rv_op_vfwsub_wv, 0 },
1964     { "vfwsub.wf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwsub_wf, rv_op_vfwsub_wf, 0 },
1965     { "vfmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfmul_vv, rv_op_vfmul_vv, 0 },
1966     { "vfmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfmul_vf, rv_op_vfmul_vf, 0 },
1967     { "vfdiv.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfdiv_vv, rv_op_vfdiv_vv, 0 },
1968     { "vfdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfdiv_vf, rv_op_vfdiv_vf, 0 },
1969     { "vfrdiv.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfrdiv_vf, rv_op_vfrdiv_vf, 0 },
1970     { "vfwmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwmul_vv, rv_op_vfwmul_vv, 0 },
1971     { "vfwmul.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfwmul_vf, rv_op_vfwmul_vf, 0 },
1972     { "vfmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfmacc_vv, rv_op_vfmacc_vv, 0 },
1973     { "vfmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfmacc_vf, rv_op_vfmacc_vf, 0 },
1974     { "vfnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfnmacc_vv, rv_op_vfnmacc_vv, 0 },
1975     { "vfnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfnmacc_vf, rv_op_vfnmacc_vf, 0 },
1976     { "vfmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfmsac_vv, rv_op_vfmsac_vv, 0 },
1977     { "vfmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfmsac_vf, rv_op_vfmsac_vf, 0 },
1978     { "vfnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfnmsac_vv, rv_op_vfnmsac_vv, 0 },
1979     { "vfnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfnmsac_vf, rv_op_vfnmsac_vf, 0 },
1980     { "vfmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfmadd_vv, rv_op_vfmadd_vv, 0 },
1981     { "vfmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfmadd_vf, rv_op_vfmadd_vf, 0 },
1982     { "vfnmadd.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfnmadd_vv, rv_op_vfnmadd_vv, 0 },
1983     { "vfnmadd.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfnmadd_vf, rv_op_vfnmadd_vf, 0 },
1984     { "vfmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfmsub_vv, rv_op_vfmsub_vv, 0 },
1985     { "vfmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfmsub_vf, rv_op_vfmsub_vf, 0 },
1986     { "vfnmsub.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfnmsub_vv, rv_op_vfnmsub_vv, 0 },
1987     { "vfnmsub.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfnmsub_vf, rv_op_vfnmsub_vf, 0 },
1988     { "vfwmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfwmacc_vv, rv_op_vfwmacc_vv, 0 },
1989     { "vfwmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfwmacc_vf, rv_op_vfwmacc_vf, 0 },
1990     { "vfwnmacc.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfwnmacc_vv, rv_op_vfwnmacc_vv, 0 },
1991     { "vfwnmacc.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfwnmacc_vf, rv_op_vfwnmacc_vf, 0 },
1992     { "vfwmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfwmsac_vv, rv_op_vfwmsac_vv, 0 },
1993     { "vfwmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfwmsac_vf, rv_op_vfwmsac_vf, 0 },
1994     { "vfwnmsac.vv", rv_codec_v_r, rv_fmt_vd_vs1_vs2_vm, NULL, rv_op_vfwnmsac_vv, rv_op_vfwnmsac_vv, 0 },
1995     { "vfwnmsac.vf", rv_codec_v_r, rv_fmt_vd_fs1_vs2_vm, NULL, rv_op_vfwnmsac_vf, rv_op_vfwnmsac_vf, 0 },
1996     { "vfsqrt.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vfsqrt_v, rv_op_vfsqrt_v, 0 },
1997     { "vfrsqrt7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vfrsqrt7_v, rv_op_vfrsqrt7_v, 0 },
1998     { "vfrec7.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vfrec7_v, rv_op_vfrec7_v, 0 },
1999     { "vfmin.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfmin_vv, rv_op_vfmin_vv, 0 },
2000     { "vfmin.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfmin_vf, rv_op_vfmin_vf, 0 },
2001     { "vfmax.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfmax_vv, rv_op_vfmax_vv, 0 },
2002     { "vfmax.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfmax_vf, rv_op_vfmax_vf, 0 },
2003     { "vfsgnj.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfsgnj_vv, rv_op_vfsgnj_vv, 0 },
2004     { "vfsgnj.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfsgnj_vf, rv_op_vfsgnj_vf, 0 },
2005     { "vfsgnjn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfsgnjn_vv, rv_op_vfsgnjn_vv, 0 },
2006     { "vfsgnjn.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfsgnjn_vf, rv_op_vfsgnjn_vf, 0 },
2007     { "vfsgnjx.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfsgnjx_vv, rv_op_vfsgnjx_vv, 0 },
2008     { "vfsgnjx.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfsgnjx_vf, rv_op_vfsgnjx_vf, 0 },
2009     { "vfslide1up.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfslide1up_vf, rv_op_vfslide1up_vf, 0 },
2010     { "vfslide1down.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vfslide1down_vf, rv_op_vfslide1down_vf, 0 },
2011     { "vmfeq.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmfeq_vv, rv_op_vmfeq_vv, 0 },
2012     { "vmfeq.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfeq_vf, rv_op_vmfeq_vf, 0 },
2013     { "vmfne.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmfne_vv, rv_op_vmfne_vv, 0 },
2014     { "vmfne.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfne_vf, rv_op_vmfne_vf, 0 },
2015     { "vmflt.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmflt_vv, rv_op_vmflt_vv, 0 },
2016     { "vmflt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmflt_vf, rv_op_vmflt_vf, 0 },
2017     { "vmfle.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmfle_vv, rv_op_vmfle_vv, 0 },
2018     { "vmfle.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfle_vf, rv_op_vmfle_vf, 0 },
2019     { "vmfgt.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfgt_vf, rv_op_vmfgt_vf, 0 },
2020     { "vmfge.vf", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vm, NULL, rv_op_vmfge_vf, rv_op_vmfge_vf, 0 },
2021     { "vfclass.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfclass_v, rv_op_vfclass_v, 0 },
2022     { "vfmerge.vfm", rv_codec_v_r, rv_fmt_vd_vs2_fs1_vl, NULL, rv_op_vfmerge_vfm, rv_op_vfmerge_vfm, 0 },
2023     { "vfmv.v.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, rv_op_vfmv_v_f, rv_op_vfmv_v_f, 0 },
2024     { "vfcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_xu_f_v, rv_op_vfcvt_xu_f_v, 0 },
2025     { "vfcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_x_f_v, rv_op_vfcvt_x_f_v, 0 },
2026     { "vfcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_f_xu_v, rv_op_vfcvt_f_xu_v, 0 },
2027     { "vfcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_f_x_v, rv_op_vfcvt_f_x_v, 0 },
2028     { "vfcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_rtz_xu_f_v, rv_op_vfcvt_rtz_xu_f_v, 0 },
2029     { "vfcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfcvt_rtz_x_f_v, rv_op_vfcvt_rtz_x_f_v, 0 },
2030     { "vfwcvt.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_xu_f_v, rv_op_vfwcvt_xu_f_v, 0 },
2031     { "vfwcvt.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_x_f_v, rv_op_vfwcvt_x_f_v, 0 },
2032     { "vfwcvt.f.xu.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_f_xu_v, rv_op_vfwcvt_f_xu_v, 0 },
2033     { "vfwcvt.f.x.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_f_x_v, rv_op_vfwcvt_f_x_v, 0 },
2034     { "vfwcvt.f.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_f_f_v, rv_op_vfwcvt_f_f_v, 0 },
2035     { "vfwcvt.rtz.xu.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_rtz_xu_f_v, rv_op_vfwcvt_rtz_xu_f_v, 0 },
2036     { "vfwcvt.rtz.x.f.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfwcvt_rtz_x_f_v, rv_op_vfwcvt_rtz_x_f_v, 0 },
2037     { "vfncvt.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_xu_f_w, rv_op_vfncvt_xu_f_w, 0 },
2038     { "vfncvt.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_x_f_w, rv_op_vfncvt_x_f_w, 0 },
2039     { "vfncvt.f.xu.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_f_xu_w, rv_op_vfncvt_f_xu_w, 0 },
2040     { "vfncvt.f.x.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_f_x_w, rv_op_vfncvt_f_x_w, 0 },
2041     { "vfncvt.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_f_f_w, rv_op_vfncvt_f_f_w, 0 },
2042     { "vfncvt.rod.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_rod_f_f_w, rv_op_vfncvt_rod_f_f_w, 0 },
2043     { "vfncvt.rtz.xu.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_rtz_xu_f_w, rv_op_vfncvt_rtz_xu_f_w, 0 },
2044     { "vfncvt.rtz.x.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vfncvt_rtz_x_f_w, rv_op_vfncvt_rtz_x_f_w, 0 },
2045     { "vredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredsum_vs, rv_op_vredsum_vs, 0 },
2046     { "vredand.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredand_vs, rv_op_vredand_vs, 0 },
2047     { "vredor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredor_vs, rv_op_vredor_vs, 0 },
2048     { "vredxor.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredxor_vs, rv_op_vredxor_vs, 0 },
2049     { "vredminu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredminu_vs, rv_op_vredminu_vs, 0 },
2050     { "vredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredmin_vs, rv_op_vredmin_vs, 0 },
2051     { "vredmaxu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredmaxu_vs, rv_op_vredmaxu_vs, 0 },
2052     { "vredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vredmax_vs, rv_op_vredmax_vs, 0 },
2053     { "vwredsumu.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwredsumu_vs, rv_op_vwredsumu_vs, 0 },
2054     { "vwredsum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vwredsum_vs, rv_op_vwredsum_vs, 0 },
2055     { "vfredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfredusum_vs, rv_op_vfredusum_vs, 0 },
2056     { "vfredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfredosum_vs, rv_op_vfredosum_vs, 0 },
2057     { "vfredmin.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfredmin_vs, rv_op_vfredmin_vs, 0 },
2058     { "vfredmax.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfredmax_vs, rv_op_vfredmax_vs, 0 },
2059     { "vfwredusum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwredusum_vs, rv_op_vfwredusum_vs, 0 },
2060     { "vfwredosum.vs", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vfwredosum_vs, rv_op_vfwredosum_vs, 0 },
2061     { "vmand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmand_mm, rv_op_vmand_mm, 0 },
2062     { "vmnand.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmnand_mm, rv_op_vmnand_mm, 0 },
2063     { "vmandn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmandn_mm, rv_op_vmandn_mm, 0 },
2064     { "vmxor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmxor_mm, rv_op_vmxor_mm, 0 },
2065     { "vmor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmor_mm, rv_op_vmor_mm, 0 },
2066     { "vmnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmnor_mm, rv_op_vmnor_mm, 0 },
2067     { "vmorn.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmorn_mm, rv_op_vmorn_mm, 0 },
2068     { "vmxnor.mm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vmxnor_mm, rv_op_vmxnor_mm, 0 },
2069     { "vcpop.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, rv_op_vcpop_m, rv_op_vcpop_m, 0 },
2070     { "vfirst.m", rv_codec_v_r, rv_fmt_rd_vs2_vm, NULL, rv_op_vfirst_m, rv_op_vfirst_m, 0 },
2071     { "vmsbf.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vmsbf_m, rv_op_vmsbf_m, 0 },
2072     { "vmsif.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vmsif_m, rv_op_vmsif_m, 0 },
2073     { "vmsof.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vmsof_m, rv_op_vmsof_m, 0 },
2074     { "viota.m", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_viota_m, rv_op_viota_m, 0 },
2075     { "vid.v", rv_codec_v_r, rv_fmt_vd_vm, NULL, rv_op_vid_v, rv_op_vid_v, 0 },
2076     { "vmv.x.s", rv_codec_v_r, rv_fmt_rd_vs2, NULL, rv_op_vmv_x_s, rv_op_vmv_x_s, 0 },
2077     { "vmv.s.x", rv_codec_v_r, rv_fmt_vd_rs1, NULL, rv_op_vmv_s_x, rv_op_vmv_s_x, 0 },
2078     { "vfmv.f.s", rv_codec_v_r, rv_fmt_fd_vs2, NULL, rv_op_vfmv_f_s, rv_op_vfmv_f_s, 0 },
2079     { "vfmv.s.f", rv_codec_v_r, rv_fmt_vd_fs1, NULL, rv_op_vfmv_s_f, rv_op_vfmv_s_f, 0 },
2080     { "vslideup.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vslideup_vx, rv_op_vslideup_vx, 0 },
2081     { "vslideup.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vslideup_vi, rv_op_vslideup_vi, 0 },
2082     { "vslide1up.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vslide1up_vx, rv_op_vslide1up_vx, 0 },
2083     { "vslidedown.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vslidedown_vx, rv_op_vslidedown_vx, 0 },
2084     { "vslidedown.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vslidedown_vi, rv_op_vslidedown_vi, 0 },
2085     { "vslide1down.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vslide1down_vx, rv_op_vslide1down_vx, 0 },
2086     { "vrgather.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vrgather_vv, rv_op_vrgather_vv, 0 },
2087     { "vrgatherei16.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, rv_op_vrgatherei16_vv, rv_op_vrgatherei16_vv, 0 },
2088     { "vrgather.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, rv_op_vrgather_vx, rv_op_vrgather_vx, 0 },
2089     { "vrgather.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, rv_op_vrgather_vi, rv_op_vrgather_vi, 0 },
2090     { "vcompress.vm", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, rv_op_vcompress_vm, rv_op_vcompress_vm, 0 },
2091     { "vmv1r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vmv1r_v, rv_op_vmv1r_v, 0 },
2092     { "vmv2r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vmv2r_v, rv_op_vmv2r_v, 0 },
2093     { "vmv4r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vmv4r_v, rv_op_vmv4r_v, 0 },
2094     { "vmv8r.v", rv_codec_v_r, rv_fmt_vd_vs2, NULL, rv_op_vmv8r_v, rv_op_vmv8r_v, 0 },
2095     { "vzext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vzext_vf2, rv_op_vzext_vf2, 0 },
2096     { "vzext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vzext_vf4, rv_op_vzext_vf4, 0 },
2097     { "vzext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vzext_vf8, rv_op_vzext_vf8, 0 },
2098     { "vsext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vsext_vf2, rv_op_vsext_vf2, 0 },
2099     { "vsext.vf4", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vsext_vf4, rv_op_vsext_vf4, 0 },
2100     { "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vsext_vf8, rv_op_vsext_vf8, 0 },
2101     { "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli, NULL, rv_op_vsetvli, rv_op_vsetvli, 0 },
2102     { "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli, NULL, rv_op_vsetivli, rv_op_vsetivli, 0 },
2103     { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, rv_op_vsetvl, rv_op_vsetvl, 0 },
2104     { "c.zext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
2105     { "c.sext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
2106     { "c.zext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
2107     { "c.sext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
2108     { "c.zext.w", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
2109     { "c.not", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 },
2110     { "c.mul", rv_codec_zcb_mul, rv_fmt_rd_rs2, NULL, 0, 0 },
2111     { "c.lbu", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
2112     { "c.lhu", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
2113     { "c.lh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
2114     { "c.sb", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
2115     { "c.sh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 },
2116     { "cm.push", rv_codec_zcmp_cm_pushpop, rv_fmt_push_rlist, NULL, 0, 0 },
2117     { "cm.pop", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 },
2118     { "cm.popret", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0, 0 },
2119     { "cm.popretz", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 },
2120     { "cm.mva01s", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
2121     { "cm.mvsa01", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
2122     { "cm.jt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 },
2123     { "cm.jalt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 },
2124     { "czero.eqz", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
2125     { "czero.nez", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
2126 };
2127
2128 /* CSR names */
2129
2130 static const char *csr_name(int csrno)
2131 {
2132     switch (csrno) {
2133     case 0x0000: return "ustatus";
2134     case 0x0001: return "fflags";
2135     case 0x0002: return "frm";
2136     case 0x0003: return "fcsr";
2137     case 0x0004: return "uie";
2138     case 0x0005: return "utvec";
2139     case 0x0008: return "vstart";
2140     case 0x0009: return "vxsat";
2141     case 0x000a: return "vxrm";
2142     case 0x000f: return "vcsr";
2143     case 0x0015: return "seed";
2144     case 0x0017: return "jvt";
2145     case 0x0040: return "uscratch";
2146     case 0x0041: return "uepc";
2147     case 0x0042: return "ucause";
2148     case 0x0043: return "utval";
2149     case 0x0044: return "uip";
2150     case 0x0100: return "sstatus";
2151     case 0x0104: return "sie";
2152     case 0x0105: return "stvec";
2153     case 0x0106: return "scounteren";
2154     case 0x0140: return "sscratch";
2155     case 0x0141: return "sepc";
2156     case 0x0142: return "scause";
2157     case 0x0143: return "stval";
2158     case 0x0144: return "sip";
2159     case 0x0180: return "satp";
2160     case 0x0200: return "hstatus";
2161     case 0x0202: return "hedeleg";
2162     case 0x0203: return "hideleg";
2163     case 0x0204: return "hie";
2164     case 0x0205: return "htvec";
2165     case 0x0240: return "hscratch";
2166     case 0x0241: return "hepc";
2167     case 0x0242: return "hcause";
2168     case 0x0243: return "hbadaddr";
2169     case 0x0244: return "hip";
2170     case 0x0300: return "mstatus";
2171     case 0x0301: return "misa";
2172     case 0x0302: return "medeleg";
2173     case 0x0303: return "mideleg";
2174     case 0x0304: return "mie";
2175     case 0x0305: return "mtvec";
2176     case 0x0306: return "mcounteren";
2177     case 0x0320: return "mucounteren";
2178     case 0x0321: return "mscounteren";
2179     case 0x0322: return "mhcounteren";
2180     case 0x0323: return "mhpmevent3";
2181     case 0x0324: return "mhpmevent4";
2182     case 0x0325: return "mhpmevent5";
2183     case 0x0326: return "mhpmevent6";
2184     case 0x0327: return "mhpmevent7";
2185     case 0x0328: return "mhpmevent8";
2186     case 0x0329: return "mhpmevent9";
2187     case 0x032a: return "mhpmevent10";
2188     case 0x032b: return "mhpmevent11";
2189     case 0x032c: return "mhpmevent12";
2190     case 0x032d: return "mhpmevent13";
2191     case 0x032e: return "mhpmevent14";
2192     case 0x032f: return "mhpmevent15";
2193     case 0x0330: return "mhpmevent16";
2194     case 0x0331: return "mhpmevent17";
2195     case 0x0332: return "mhpmevent18";
2196     case 0x0333: return "mhpmevent19";
2197     case 0x0334: return "mhpmevent20";
2198     case 0x0335: return "mhpmevent21";
2199     case 0x0336: return "mhpmevent22";
2200     case 0x0337: return "mhpmevent23";
2201     case 0x0338: return "mhpmevent24";
2202     case 0x0339: return "mhpmevent25";
2203     case 0x033a: return "mhpmevent26";
2204     case 0x033b: return "mhpmevent27";
2205     case 0x033c: return "mhpmevent28";
2206     case 0x033d: return "mhpmevent29";
2207     case 0x033e: return "mhpmevent30";
2208     case 0x033f: return "mhpmevent31";
2209     case 0x0340: return "mscratch";
2210     case 0x0341: return "mepc";
2211     case 0x0342: return "mcause";
2212     case 0x0343: return "mtval";
2213     case 0x0344: return "mip";
2214     case 0x0380: return "mbase";
2215     case 0x0381: return "mbound";
2216     case 0x0382: return "mibase";
2217     case 0x0383: return "mibound";
2218     case 0x0384: return "mdbase";
2219     case 0x0385: return "mdbound";
2220     case 0x03a0: return "pmpcfg3";
2221     case 0x03b0: return "pmpaddr0";
2222     case 0x03b1: return "pmpaddr1";
2223     case 0x03b2: return "pmpaddr2";
2224     case 0x03b3: return "pmpaddr3";
2225     case 0x03b4: return "pmpaddr4";
2226     case 0x03b5: return "pmpaddr5";
2227     case 0x03b6: return "pmpaddr6";
2228     case 0x03b7: return "pmpaddr7";
2229     case 0x03b8: return "pmpaddr8";
2230     case 0x03b9: return "pmpaddr9";
2231     case 0x03ba: return "pmpaddr10";
2232     case 0x03bb: return "pmpaddr11";
2233     case 0x03bc: return "pmpaddr12";
2234     case 0x03bd: return "pmpaddr14";
2235     case 0x03be: return "pmpaddr13";
2236     case 0x03bf: return "pmpaddr15";
2237     case 0x0780: return "mtohost";
2238     case 0x0781: return "mfromhost";
2239     case 0x0782: return "mreset";
2240     case 0x0783: return "mipi";
2241     case 0x0784: return "miobase";
2242     case 0x07a0: return "tselect";
2243     case 0x07a1: return "tdata1";
2244     case 0x07a2: return "tdata2";
2245     case 0x07a3: return "tdata3";
2246     case 0x07b0: return "dcsr";
2247     case 0x07b1: return "dpc";
2248     case 0x07b2: return "dscratch";
2249     case 0x0b00: return "mcycle";
2250     case 0x0b01: return "mtime";
2251     case 0x0b02: return "minstret";
2252     case 0x0b03: return "mhpmcounter3";
2253     case 0x0b04: return "mhpmcounter4";
2254     case 0x0b05: return "mhpmcounter5";
2255     case 0x0b06: return "mhpmcounter6";
2256     case 0x0b07: return "mhpmcounter7";
2257     case 0x0b08: return "mhpmcounter8";
2258     case 0x0b09: return "mhpmcounter9";
2259     case 0x0b0a: return "mhpmcounter10";
2260     case 0x0b0b: return "mhpmcounter11";
2261     case 0x0b0c: return "mhpmcounter12";
2262     case 0x0b0d: return "mhpmcounter13";
2263     case 0x0b0e: return "mhpmcounter14";
2264     case 0x0b0f: return "mhpmcounter15";
2265     case 0x0b10: return "mhpmcounter16";
2266     case 0x0b11: return "mhpmcounter17";
2267     case 0x0b12: return "mhpmcounter18";
2268     case 0x0b13: return "mhpmcounter19";
2269     case 0x0b14: return "mhpmcounter20";
2270     case 0x0b15: return "mhpmcounter21";
2271     case 0x0b16: return "mhpmcounter22";
2272     case 0x0b17: return "mhpmcounter23";
2273     case 0x0b18: return "mhpmcounter24";
2274     case 0x0b19: return "mhpmcounter25";
2275     case 0x0b1a: return "mhpmcounter26";
2276     case 0x0b1b: return "mhpmcounter27";
2277     case 0x0b1c: return "mhpmcounter28";
2278     case 0x0b1d: return "mhpmcounter29";
2279     case 0x0b1e: return "mhpmcounter30";
2280     case 0x0b1f: return "mhpmcounter31";
2281     case 0x0b80: return "mcycleh";
2282     case 0x0b81: return "mtimeh";
2283     case 0x0b82: return "minstreth";
2284     case 0x0b83: return "mhpmcounter3h";
2285     case 0x0b84: return "mhpmcounter4h";
2286     case 0x0b85: return "mhpmcounter5h";
2287     case 0x0b86: return "mhpmcounter6h";
2288     case 0x0b87: return "mhpmcounter7h";
2289     case 0x0b88: return "mhpmcounter8h";
2290     case 0x0b89: return "mhpmcounter9h";
2291     case 0x0b8a: return "mhpmcounter10h";
2292     case 0x0b8b: return "mhpmcounter11h";
2293     case 0x0b8c: return "mhpmcounter12h";
2294     case 0x0b8d: return "mhpmcounter13h";
2295     case 0x0b8e: return "mhpmcounter14h";
2296     case 0x0b8f: return "mhpmcounter15h";
2297     case 0x0b90: return "mhpmcounter16h";
2298     case 0x0b91: return "mhpmcounter17h";
2299     case 0x0b92: return "mhpmcounter18h";
2300     case 0x0b93: return "mhpmcounter19h";
2301     case 0x0b94: return "mhpmcounter20h";
2302     case 0x0b95: return "mhpmcounter21h";
2303     case 0x0b96: return "mhpmcounter22h";
2304     case 0x0b97: return "mhpmcounter23h";
2305     case 0x0b98: return "mhpmcounter24h";
2306     case 0x0b99: return "mhpmcounter25h";
2307     case 0x0b9a: return "mhpmcounter26h";
2308     case 0x0b9b: return "mhpmcounter27h";
2309     case 0x0b9c: return "mhpmcounter28h";
2310     case 0x0b9d: return "mhpmcounter29h";
2311     case 0x0b9e: return "mhpmcounter30h";
2312     case 0x0b9f: return "mhpmcounter31h";
2313     case 0x0c00: return "cycle";
2314     case 0x0c01: return "time";
2315     case 0x0c02: return "instret";
2316     case 0x0c20: return "vl";
2317     case 0x0c21: return "vtype";
2318     case 0x0c22: return "vlenb";
2319     case 0x0c80: return "cycleh";
2320     case 0x0c81: return "timeh";
2321     case 0x0c82: return "instreth";
2322     case 0x0d00: return "scycle";
2323     case 0x0d01: return "stime";
2324     case 0x0d02: return "sinstret";
2325     case 0x0d80: return "scycleh";
2326     case 0x0d81: return "stimeh";
2327     case 0x0d82: return "sinstreth";
2328     case 0x0e00: return "hcycle";
2329     case 0x0e01: return "htime";
2330     case 0x0e02: return "hinstret";
2331     case 0x0e80: return "hcycleh";
2332     case 0x0e81: return "htimeh";
2333     case 0x0e82: return "hinstreth";
2334     case 0x0f11: return "mvendorid";
2335     case 0x0f12: return "marchid";
2336     case 0x0f13: return "mimpid";
2337     case 0x0f14: return "mhartid";
2338     default: return NULL;
2339     }
2340 }
2341
2342 /* decode opcode */
2343
2344 static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
2345 {
2346     rv_inst inst = dec->inst;
2347     rv_opcode op = rv_op_illegal;
2348     switch (((inst >> 0) & 0b11)) {
2349     case 0:
2350         switch (((inst >> 13) & 0b111)) {
2351         case 0: op = rv_op_c_addi4spn; break;
2352         case 1:
2353             if (isa == rv128) {
2354                 op = rv_op_c_lq;
2355             } else {
2356                 op = rv_op_c_fld;
2357             }
2358             break;
2359         case 2: op = rv_op_c_lw; break;
2360         case 3:
2361             if (isa == rv32) {
2362                 op = rv_op_c_flw;
2363             } else {
2364                 op = rv_op_c_ld;
2365             }
2366             break;
2367         case 4:
2368             switch ((inst >> 10) & 0b111) {
2369             case 0: op = rv_op_c_lbu; break;
2370             case 1:
2371                 if (((inst >> 6) & 1) == 0) {
2372                     op = rv_op_c_lhu;
2373                 } else {
2374                     op = rv_op_c_lh;
2375                 }
2376                 break;
2377             case 2: op = rv_op_c_sb; break;
2378             case 3:
2379                 if (((inst >> 6) & 1) == 0) {
2380                     op = rv_op_c_sh;
2381                 }
2382                 break;
2383             }
2384             break;
2385         case 5:
2386             if (isa == rv128) {
2387                 op = rv_op_c_sq;
2388             } else {
2389                 op = rv_op_c_fsd;
2390             }
2391             break;
2392         case 6: op = rv_op_c_sw; break;
2393         case 7:
2394             if (isa == rv32) {
2395                 op = rv_op_c_fsw;
2396             } else {
2397                 op = rv_op_c_sd;
2398             }
2399             break;
2400         }
2401         break;
2402     case 1:
2403         switch (((inst >> 13) & 0b111)) {
2404         case 0:
2405             switch (((inst >> 2) & 0b11111111111)) {
2406             case 0: op = rv_op_c_nop; break;
2407             default: op = rv_op_c_addi; break;
2408             }
2409             break;
2410         case 1:
2411             if (isa == rv32) {
2412                 op = rv_op_c_jal;
2413             } else {
2414                 op = rv_op_c_addiw;
2415             }
2416             break;
2417         case 2: op = rv_op_c_li; break;
2418         case 3:
2419             switch (((inst >> 7) & 0b11111)) {
2420             case 2: op = rv_op_c_addi16sp; break;
2421             default: op = rv_op_c_lui; break;
2422             }
2423             break;
2424         case 4:
2425             switch (((inst >> 10) & 0b11)) {
2426             case 0:
2427                 op = rv_op_c_srli;
2428                 break;
2429             case 1:
2430                 op = rv_op_c_srai;
2431                 break;
2432             case 2: op = rv_op_c_andi; break;
2433             case 3:
2434                 switch (((inst >> 10) & 0b100) | ((inst >> 5) & 0b011)) {
2435                 case 0: op = rv_op_c_sub; break;
2436                 case 1: op = rv_op_c_xor; break;
2437                 case 2: op = rv_op_c_or; break;
2438                 case 3: op = rv_op_c_and; break;
2439                 case 4: op = rv_op_c_subw; break;
2440                 case 5: op = rv_op_c_addw; break;
2441                 case 6: op = rv_op_c_mul; break;
2442                 case 7:
2443                     switch ((inst >> 2) & 0b111) {
2444                     case 0: op = rv_op_c_zext_b; break;
2445                     case 1: op = rv_op_c_sext_b; break;
2446                     case 2: op = rv_op_c_zext_h; break;
2447                     case 3: op = rv_op_c_sext_h; break;
2448                     case 4: op = rv_op_c_zext_w; break;
2449                     case 5: op = rv_op_c_not; break;
2450                     }
2451                     break;
2452                 }
2453                 break;
2454             }
2455             break;
2456         case 5: op = rv_op_c_j; break;
2457         case 6: op = rv_op_c_beqz; break;
2458         case 7: op = rv_op_c_bnez; break;
2459         }
2460         break;
2461     case 2:
2462         switch (((inst >> 13) & 0b111)) {
2463         case 0:
2464             op = rv_op_c_slli;
2465             break;
2466         case 1:
2467             if (isa == rv128) {
2468                 op = rv_op_c_lqsp;
2469             } else {
2470                 op = rv_op_c_fldsp;
2471             }
2472             break;
2473         case 2: op = rv_op_c_lwsp; break;
2474         case 3:
2475             if (isa == rv32) {
2476                 op = rv_op_c_flwsp;
2477             } else {
2478                 op = rv_op_c_ldsp;
2479             }
2480             break;
2481         case 4:
2482             switch (((inst >> 12) & 0b1)) {
2483             case 0:
2484                 switch (((inst >> 2) & 0b11111)) {
2485                 case 0: op = rv_op_c_jr; break;
2486                 default: op = rv_op_c_mv; break;
2487                 }
2488                 break;
2489             case 1:
2490                 switch (((inst >> 2) & 0b11111)) {
2491                 case 0:
2492                     switch (((inst >> 7) & 0b11111)) {
2493                     case 0: op = rv_op_c_ebreak; break;
2494                     default: op = rv_op_c_jalr; break;
2495                     }
2496                     break;
2497                 default: op = rv_op_c_add; break;
2498                 }
2499                 break;
2500             }
2501             break;
2502         case 5:
2503             if (isa == rv128) {
2504                 op = rv_op_c_sqsp;
2505             } else {
2506                 op = rv_op_c_fsdsp;
2507                 if (((inst >> 12) & 0b01)) {
2508                     switch ((inst >> 8) & 0b01111) {
2509                     case 8:
2510                         if (((inst >> 4) & 0b01111) >= 4) {
2511                             op = rv_op_cm_push;
2512                         }
2513                         break;
2514                     case 10:
2515                         if (((inst >> 4) & 0b01111) >= 4) {
2516                             op = rv_op_cm_pop;
2517                         }
2518                         break;
2519                     case 12:
2520                         if (((inst >> 4) & 0b01111) >= 4) {
2521                             op = rv_op_cm_popretz;
2522                         }
2523                         break;
2524                     case 14:
2525                         if (((inst >> 4) & 0b01111) >= 4) {
2526                             op = rv_op_cm_popret;
2527                         }
2528                         break;
2529                     }
2530                 } else {
2531                     switch ((inst >> 10) & 0b011) {
2532                     case 0:
2533                         if (((inst >> 2) & 0xFF) >= 32) {
2534                             op = rv_op_cm_jalt;
2535                         } else {
2536                             op = rv_op_cm_jt;
2537                         }
2538                         break;
2539                     case 3:
2540                         switch ((inst >> 5) & 0b011) {
2541                         case 1: op = rv_op_cm_mvsa01; break;
2542                         case 3: op = rv_op_cm_mva01s; break;
2543                         }
2544                         break;
2545                     }
2546                 }
2547             }
2548             break;
2549         case 6: op = rv_op_c_swsp; break;
2550         case 7:
2551             if (isa == rv32) {
2552                 op = rv_op_c_fswsp;
2553             } else {
2554                 op = rv_op_c_sdsp;
2555             }
2556             break;
2557         }
2558         break;
2559     case 3:
2560         switch (((inst >> 2) & 0b11111)) {
2561         case 0:
2562             switch (((inst >> 12) & 0b111)) {
2563             case 0: op = rv_op_lb; break;
2564             case 1: op = rv_op_lh; break;
2565             case 2: op = rv_op_lw; break;
2566             case 3: op = rv_op_ld; break;
2567             case 4: op = rv_op_lbu; break;
2568             case 5: op = rv_op_lhu; break;
2569             case 6: op = rv_op_lwu; break;
2570             case 7: op = rv_op_ldu; break;
2571             }
2572             break;
2573         case 1:
2574             switch (((inst >> 12) & 0b111)) {
2575             case 0:
2576                 switch (((inst >> 20) & 0b111111111111)) {
2577                 case 40: op = rv_op_vl1re8_v; break;
2578                 case 552: op = rv_op_vl2re8_v; break;
2579                 case 1576: op = rv_op_vl4re8_v; break;
2580                 case 3624: op = rv_op_vl8re8_v; break;
2581                 }
2582                 switch (((inst >> 26) & 0b111)) {
2583                 case 0:
2584                     switch (((inst >> 20) & 0b11111)) {
2585                     case 0: op = rv_op_vle8_v; break;
2586                     case 11: op = rv_op_vlm_v; break;
2587                     case 16: op = rv_op_vle8ff_v; break;
2588                     }
2589                     break;
2590                 case 1: op = rv_op_vluxei8_v; break;
2591                 case 2: op = rv_op_vlse8_v; break;
2592                 case 3: op = rv_op_vloxei8_v; break;
2593                 }
2594                 break;
2595             case 2: op = rv_op_flw; break;
2596             case 3: op = rv_op_fld; break;
2597             case 4: op = rv_op_flq; break;
2598             case 5:
2599                 switch (((inst >> 20) & 0b111111111111)) {
2600                 case 40: op = rv_op_vl1re16_v; break;
2601                 case 552: op = rv_op_vl2re16_v; break;
2602                 case 1576: op = rv_op_vl4re16_v; break;
2603                 case 3624: op = rv_op_vl8re16_v; break;
2604                 }
2605                 switch (((inst >> 26) & 0b111)) {
2606                 case 0:
2607                     switch (((inst >> 20) & 0b11111)) {
2608                     case 0: op = rv_op_vle16_v; break;
2609                     case 16: op = rv_op_vle16ff_v; break;
2610                     }
2611                     break;
2612                 case 1: op = rv_op_vluxei16_v; break;
2613                 case 2: op = rv_op_vlse16_v; break;
2614                 case 3: op = rv_op_vloxei16_v; break;
2615                 }
2616                 break;
2617             case 6:
2618                 switch (((inst >> 20) & 0b111111111111)) {
2619                 case 40: op = rv_op_vl1re32_v; break;
2620                 case 552: op = rv_op_vl2re32_v; break;
2621                 case 1576: op = rv_op_vl4re32_v; break;
2622                 case 3624: op = rv_op_vl8re32_v; break;
2623                 }
2624                 switch (((inst >> 26) & 0b111)) {
2625                 case 0:
2626                     switch (((inst >> 20) & 0b11111)) {
2627                     case 0: op = rv_op_vle32_v; break;
2628                     case 16: op = rv_op_vle32ff_v; break;
2629                     }
2630                     break;
2631                 case 1: op = rv_op_vluxei32_v; break;
2632                 case 2: op = rv_op_vlse32_v; break;
2633                 case 3: op = rv_op_vloxei32_v; break;
2634                 }
2635                 break;
2636             case 7:
2637                 switch (((inst >> 20) & 0b111111111111)) {
2638                 case 40: op = rv_op_vl1re64_v; break;
2639                 case 552: op = rv_op_vl2re64_v; break;
2640                 case 1576: op = rv_op_vl4re64_v; break;
2641                 case 3624: op = rv_op_vl8re64_v; break;
2642                 }
2643                 switch (((inst >> 26) & 0b111)) {
2644                 case 0:
2645                     switch (((inst >> 20) & 0b11111)) {
2646                     case 0: op = rv_op_vle64_v; break;
2647                     case 16: op = rv_op_vle64ff_v; break;
2648                     }
2649                     break;
2650                 case 1: op = rv_op_vluxei64_v; break;
2651                 case 2: op = rv_op_vlse64_v; break;
2652                 case 3: op = rv_op_vloxei64_v; break;
2653                 }
2654                 break;
2655             }
2656             break;
2657         case 3:
2658             switch (((inst >> 12) & 0b111)) {
2659             case 0: op = rv_op_fence; break;
2660             case 1: op = rv_op_fence_i; break;
2661             case 2: op = rv_op_lq; break;
2662             }
2663             break;
2664         case 4:
2665             switch (((inst >> 12) & 0b111)) {
2666             case 0: op = rv_op_addi; break;
2667             case 1:
2668                 switch (((inst >> 27) & 0b11111)) {
2669                 case 0b00000: op = rv_op_slli; break;
2670                 case 0b00001:
2671                     switch (((inst >> 20) & 0b1111111)) {
2672                     case 0b0001111: op = rv_op_zip; break;
2673                     }
2674                     break;
2675                 case 0b00010:
2676                     switch (((inst >> 20) & 0b1111111)) {
2677                     case 0b0000000: op = rv_op_sha256sum0; break;
2678                     case 0b0000001: op = rv_op_sha256sum1; break;
2679                     case 0b0000010: op = rv_op_sha256sig0; break;
2680                     case 0b0000011: op = rv_op_sha256sig1; break;
2681                     case 0b0000100: op = rv_op_sha512sum0; break;
2682                     case 0b0000101: op = rv_op_sha512sum1; break;
2683                     case 0b0000110: op = rv_op_sha512sig0; break;
2684                     case 0b0000111: op = rv_op_sha512sig1; break;
2685                     case 0b0001000: op = rv_op_sm3p0; break;
2686                     case 0b0001001: op = rv_op_sm3p1; break;
2687                     }
2688                     break;
2689                 case 0b00101: op = rv_op_bseti; break;
2690                 case 0b00110:
2691                     switch (((inst >> 20) & 0b1111111)) {
2692                     case 0b0000000: op = rv_op_aes64im; break;
2693                     default:
2694                         if (((inst >> 24) & 0b0111) == 0b001) {
2695                             op = rv_op_aes64ks1i;
2696                         }
2697                         break;
2698                      }
2699                      break;
2700                 case 0b01001: op = rv_op_bclri; break;
2701                 case 0b01101: op = rv_op_binvi; break;
2702                 case 0b01100:
2703                     switch (((inst >> 20) & 0b1111111)) {
2704                     case 0b0000000: op = rv_op_clz; break;
2705                     case 0b0000001: op = rv_op_ctz; break;
2706                     case 0b0000010: op = rv_op_cpop; break;
2707                       /* 0b0000011 */
2708                     case 0b0000100: op = rv_op_sext_b; break;
2709                     case 0b0000101: op = rv_op_sext_h; break;
2710                     }
2711                     break;
2712                 }
2713                 break;
2714             case 2: op = rv_op_slti; break;
2715             case 3: op = rv_op_sltiu; break;
2716             case 4: op = rv_op_xori; break;
2717             case 5:
2718                 switch (((inst >> 27) & 0b11111)) {
2719                 case 0b00000: op = rv_op_srli; break;
2720                 case 0b00001:
2721                     switch (((inst >> 20) & 0b1111111)) {
2722                     case 0b0001111: op = rv_op_unzip; break;
2723                     }
2724                     break;
2725                 case 0b00101: op = rv_op_orc_b; break;
2726                 case 0b01000: op = rv_op_srai; break;
2727                 case 0b01001: op = rv_op_bexti; break;
2728                 case 0b01100: op = rv_op_rori; break;
2729                 case 0b01101:
2730                     switch ((inst >> 20) & 0b1111111) {
2731                     case 0b0011000: op = rv_op_rev8; break;
2732                     case 0b0111000: op = rv_op_rev8; break;
2733                     case 0b0000111: op = rv_op_brev8; break;
2734                     }
2735                     break;
2736                 }
2737                 break;
2738             case 6: op = rv_op_ori; break;
2739             case 7: op = rv_op_andi; break;
2740             }
2741             break;
2742         case 5: op = rv_op_auipc; break;
2743         case 6:
2744             switch (((inst >> 12) & 0b111)) {
2745             case 0: op = rv_op_addiw; break;
2746             case 1:
2747                 switch (((inst >> 26) & 0b111111)) {
2748                 case 0: op = rv_op_slliw; break;
2749                 case 2: op = rv_op_slli_uw; break;
2750                 case 24:
2751                     switch ((inst >> 20) & 0b11111) {
2752                     case 0b00000: op = rv_op_clzw; break;
2753                     case 0b00001: op = rv_op_ctzw; break;
2754                     case 0b00010: op = rv_op_cpopw; break;
2755                     }
2756                     break;
2757                 }
2758                 break;
2759             case 5:
2760                 switch (((inst >> 25) & 0b1111111)) {
2761                 case 0: op = rv_op_srliw; break;
2762                 case 32: op = rv_op_sraiw; break;
2763                 case 48: op = rv_op_roriw; break;
2764                 }
2765                 break;
2766             }
2767             break;
2768         case 8:
2769             switch (((inst >> 12) & 0b111)) {
2770             case 0: op = rv_op_sb; break;
2771             case 1: op = rv_op_sh; break;
2772             case 2: op = rv_op_sw; break;
2773             case 3: op = rv_op_sd; break;
2774             case 4: op = rv_op_sq; break;
2775             }
2776             break;
2777         case 9:
2778             switch (((inst >> 12) & 0b111)) {
2779             case 0:
2780                 switch (((inst >> 20) & 0b111111111111)) {
2781                 case 40: op = rv_op_vs1r_v; break;
2782                 case 552: op = rv_op_vs2r_v; break;
2783                 case 1576: op = rv_op_vs4r_v; break;
2784                 case 3624: op = rv_op_vs8r_v; break;
2785                 }
2786                 switch (((inst >> 26) & 0b111)) {
2787                 case 0:
2788                     switch (((inst >> 20) & 0b11111)) {
2789                     case 0: op = rv_op_vse8_v; break;
2790                     case 11: op = rv_op_vsm_v; break;
2791                     }
2792                     break;
2793                 case 1: op = rv_op_vsuxei8_v; break;
2794                 case 2: op = rv_op_vsse8_v; break;
2795                 case 3: op = rv_op_vsoxei8_v; break;
2796                 }
2797                 break;
2798             case 2: op = rv_op_fsw; break;
2799             case 3: op = rv_op_fsd; break;
2800             case 4: op = rv_op_fsq; break;
2801             case 5:
2802                 switch (((inst >> 26) & 0b111)) {
2803                 case 0:
2804                     switch (((inst >> 20) & 0b11111)) {
2805                     case 0: op = rv_op_vse16_v; break;
2806                     }
2807                     break;
2808                 case 1: op = rv_op_vsuxei16_v; break;
2809                 case 2: op = rv_op_vsse16_v; break;
2810                 case 3: op = rv_op_vsoxei16_v; break;
2811                 }
2812                 break;
2813             case 6:
2814                 switch (((inst >> 26) & 0b111)) {
2815                 case 0:
2816                     switch (((inst >> 20) & 0b11111)) {
2817                     case 0: op = rv_op_vse32_v; break;
2818                     }
2819                     break;
2820                 case 1: op = rv_op_vsuxei32_v; break;
2821                 case 2: op = rv_op_vsse32_v; break;
2822                 case 3: op = rv_op_vsoxei32_v; break;
2823                 }
2824                 break;
2825             case 7:
2826                 switch (((inst >> 26) & 0b111)) {
2827                 case 0:
2828                     switch (((inst >> 20) & 0b11111)) {
2829                     case 0: op = rv_op_vse64_v; break;
2830                     }
2831                     break;
2832                 case 1: op = rv_op_vsuxei64_v; break;
2833                 case 2: op = rv_op_vsse64_v; break;
2834                 case 3: op = rv_op_vsoxei64_v; break;
2835                 }
2836                 break;
2837             }
2838             break;
2839         case 11:
2840             switch (((inst >> 24) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
2841             case 2: op = rv_op_amoadd_w; break;
2842             case 3: op = rv_op_amoadd_d; break;
2843             case 4: op = rv_op_amoadd_q; break;
2844             case 10: op = rv_op_amoswap_w; break;
2845             case 11: op = rv_op_amoswap_d; break;
2846             case 12: op = rv_op_amoswap_q; break;
2847             case 18:
2848                 switch (((inst >> 20) & 0b11111)) {
2849                 case 0: op = rv_op_lr_w; break;
2850                 }
2851                 break;
2852             case 19:
2853                 switch (((inst >> 20) & 0b11111)) {
2854                 case 0: op = rv_op_lr_d; break;
2855                 }
2856                 break;
2857             case 20:
2858                 switch (((inst >> 20) & 0b11111)) {
2859                 case 0: op = rv_op_lr_q; break;
2860                 }
2861                 break;
2862             case 26: op = rv_op_sc_w; break;
2863             case 27: op = rv_op_sc_d; break;
2864             case 28: op = rv_op_sc_q; break;
2865             case 34: op = rv_op_amoxor_w; break;
2866             case 35: op = rv_op_amoxor_d; break;
2867             case 36: op = rv_op_amoxor_q; break;
2868             case 66: op = rv_op_amoor_w; break;
2869             case 67: op = rv_op_amoor_d; break;
2870             case 68: op = rv_op_amoor_q; break;
2871             case 98: op = rv_op_amoand_w; break;
2872             case 99: op = rv_op_amoand_d; break;
2873             case 100: op = rv_op_amoand_q; break;
2874             case 130: op = rv_op_amomin_w; break;
2875             case 131: op = rv_op_amomin_d; break;
2876             case 132: op = rv_op_amomin_q; break;
2877             case 162: op = rv_op_amomax_w; break;
2878             case 163: op = rv_op_amomax_d; break;
2879             case 164: op = rv_op_amomax_q; break;
2880             case 194: op = rv_op_amominu_w; break;
2881             case 195: op = rv_op_amominu_d; break;
2882             case 196: op = rv_op_amominu_q; break;
2883             case 226: op = rv_op_amomaxu_w; break;
2884             case 227: op = rv_op_amomaxu_d; break;
2885             case 228: op = rv_op_amomaxu_q; break;
2886             }
2887             break;
2888         case 12:
2889             switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {
2890             case 0: op = rv_op_add; break;
2891             case 1: op = rv_op_sll; break;
2892             case 2: op = rv_op_slt; break;
2893             case 3: op = rv_op_sltu; break;
2894             case 4: op = rv_op_xor; break;
2895             case 5: op = rv_op_srl; break;
2896             case 6: op = rv_op_or; break;
2897             case 7: op = rv_op_and; break;
2898             case 8: op = rv_op_mul; break;
2899             case 9: op = rv_op_mulh; break;
2900             case 10: op = rv_op_mulhsu; break;
2901             case 11: op = rv_op_mulhu; break;
2902             case 12: op = rv_op_div; break;
2903             case 13: op = rv_op_divu; break;
2904             case 14: op = rv_op_rem; break;
2905             case 15: op = rv_op_remu; break;
2906             case 36:
2907                 switch ((inst >> 20) & 0b11111) {
2908                 case 0: op = rv_op_zext_h; break;
2909                 default: op = rv_op_pack; break;
2910                 }
2911                 break;
2912             case 39: op = rv_op_packh; break;
2913
2914             case 41: op = rv_op_clmul; break;
2915             case 42: op = rv_op_clmulr; break;
2916             case 43: op = rv_op_clmulh; break;
2917             case 44: op = rv_op_min; break;
2918             case 45: op = rv_op_minu; break;
2919             case 46: op = rv_op_max; break;
2920             case 47: op = rv_op_maxu; break;
2921             case 075: op = rv_op_czero_eqz; break;
2922             case 077: op = rv_op_czero_nez; break;
2923             case 130: op = rv_op_sh1add; break;
2924             case 132: op = rv_op_sh2add; break;
2925             case 134: op = rv_op_sh3add; break;
2926             case 161: op = rv_op_bset; break;
2927             case 162: op = rv_op_xperm4; break;
2928             case 164: op = rv_op_xperm8; break;
2929             case 200: op = rv_op_aes64es; break;
2930             case 216: op = rv_op_aes64esm; break;
2931             case 232: op = rv_op_aes64ds; break;
2932             case 248: op = rv_op_aes64dsm; break;
2933             case 256: op = rv_op_sub; break;
2934             case 260: op = rv_op_xnor; break;
2935             case 261: op = rv_op_sra; break;
2936             case 262: op = rv_op_orn; break;
2937             case 263: op = rv_op_andn; break;
2938             case 289: op = rv_op_bclr; break;
2939             case 293: op = rv_op_bext; break;
2940             case 320: op = rv_op_sha512sum0r; break;
2941             case 328: op = rv_op_sha512sum1r; break;
2942             case 336: op = rv_op_sha512sig0l; break;
2943             case 344: op = rv_op_sha512sig1l; break;
2944             case 368: op = rv_op_sha512sig0h; break;
2945             case 376: op = rv_op_sha512sig1h; break;
2946             case 385: op = rv_op_rol; break;
2947             case 389: op = rv_op_ror; break;
2948             case 417: op = rv_op_binv; break;
2949             case 504: op = rv_op_aes64ks2; break;
2950             }
2951             switch ((inst >> 25) & 0b0011111) {
2952             case 17: op = rv_op_aes32esi; break;
2953             case 19: op = rv_op_aes32esmi; break;
2954             case 21: op = rv_op_aes32dsi; break;
2955             case 23: op = rv_op_aes32dsmi; break;
2956             case 24: op = rv_op_sm4ed; break;
2957             case 26: op = rv_op_sm4ks; break;
2958             }
2959             break;
2960         case 13: op = rv_op_lui; break;
2961         case 14:
2962             switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {
2963             case 0: op = rv_op_addw; break;
2964             case 1: op = rv_op_sllw; break;
2965             case 5: op = rv_op_srlw; break;
2966             case 8: op = rv_op_mulw; break;
2967             case 12: op = rv_op_divw; break;
2968             case 13: op = rv_op_divuw; break;
2969             case 14: op = rv_op_remw; break;
2970             case 15: op = rv_op_remuw; break;
2971             case 32: op = rv_op_add_uw; break;
2972             case 36:
2973                 switch ((inst >> 20) & 0b11111) {
2974                 case 0: op = rv_op_zext_h; break;
2975                 default: op = rv_op_packw; break;
2976                 }
2977                 break;
2978             case 130: op = rv_op_sh1add_uw; break;
2979             case 132: op = rv_op_sh2add_uw; break;
2980             case 134: op = rv_op_sh3add_uw; break;
2981             case 256: op = rv_op_subw; break;
2982             case 261: op = rv_op_sraw; break;
2983             case 385: op = rv_op_rolw; break;
2984             case 389: op = rv_op_rorw; break;
2985             }
2986             break;
2987         case 16:
2988             switch (((inst >> 25) & 0b11)) {
2989             case 0: op = rv_op_fmadd_s; break;
2990             case 1: op = rv_op_fmadd_d; break;
2991             case 3: op = rv_op_fmadd_q; break;
2992             }
2993             break;
2994         case 17:
2995             switch (((inst >> 25) & 0b11)) {
2996             case 0: op = rv_op_fmsub_s; break;
2997             case 1: op = rv_op_fmsub_d; break;
2998             case 3: op = rv_op_fmsub_q; break;
2999             }
3000             break;
3001         case 18:
3002             switch (((inst >> 25) & 0b11)) {
3003             case 0: op = rv_op_fnmsub_s; break;
3004             case 1: op = rv_op_fnmsub_d; break;
3005             case 3: op = rv_op_fnmsub_q; break;
3006             }
3007             break;
3008         case 19:
3009             switch (((inst >> 25) & 0b11)) {
3010             case 0: op = rv_op_fnmadd_s; break;
3011             case 1: op = rv_op_fnmadd_d; break;
3012             case 3: op = rv_op_fnmadd_q; break;
3013             }
3014             break;
3015         case 20:
3016             switch (((inst >> 25) & 0b1111111)) {
3017             case 0: op = rv_op_fadd_s; break;
3018             case 1: op = rv_op_fadd_d; break;
3019             case 3: op = rv_op_fadd_q; break;
3020             case 4: op = rv_op_fsub_s; break;
3021             case 5: op = rv_op_fsub_d; break;
3022             case 7: op = rv_op_fsub_q; break;
3023             case 8: op = rv_op_fmul_s; break;
3024             case 9: op = rv_op_fmul_d; break;
3025             case 11: op = rv_op_fmul_q; break;
3026             case 12: op = rv_op_fdiv_s; break;
3027             case 13: op = rv_op_fdiv_d; break;
3028             case 15: op = rv_op_fdiv_q; break;
3029             case 16:
3030                 switch (((inst >> 12) & 0b111)) {
3031                 case 0: op = rv_op_fsgnj_s; break;
3032                 case 1: op = rv_op_fsgnjn_s; break;
3033                 case 2: op = rv_op_fsgnjx_s; break;
3034                 }
3035                 break;
3036             case 17:
3037                 switch (((inst >> 12) & 0b111)) {
3038                 case 0: op = rv_op_fsgnj_d; break;
3039                 case 1: op = rv_op_fsgnjn_d; break;
3040                 case 2: op = rv_op_fsgnjx_d; break;
3041                 }
3042                 break;
3043             case 19:
3044                 switch (((inst >> 12) & 0b111)) {
3045                 case 0: op = rv_op_fsgnj_q; break;
3046                 case 1: op = rv_op_fsgnjn_q; break;
3047                 case 2: op = rv_op_fsgnjx_q; break;
3048                 }
3049                 break;
3050             case 20:
3051                 switch (((inst >> 12) & 0b111)) {
3052                 case 0: op = rv_op_fmin_s; break;
3053                 case 1: op = rv_op_fmax_s; break;
3054                 }
3055                 break;
3056             case 21:
3057                 switch (((inst >> 12) & 0b111)) {
3058                 case 0: op = rv_op_fmin_d; break;
3059                 case 1: op = rv_op_fmax_d; break;
3060                 }
3061                 break;
3062             case 23:
3063                 switch (((inst >> 12) & 0b111)) {
3064                 case 0: op = rv_op_fmin_q; break;
3065                 case 1: op = rv_op_fmax_q; break;
3066                 }
3067                 break;
3068             case 32:
3069                 switch (((inst >> 20) & 0b11111)) {
3070                 case 1: op = rv_op_fcvt_s_d; break;
3071                 case 3: op = rv_op_fcvt_s_q; break;
3072                 }
3073                 break;
3074             case 33:
3075                 switch (((inst >> 20) & 0b11111)) {
3076                 case 0: op = rv_op_fcvt_d_s; break;
3077                 case 3: op = rv_op_fcvt_d_q; break;
3078                 }
3079                 break;
3080             case 35:
3081                 switch (((inst >> 20) & 0b11111)) {
3082                 case 0: op = rv_op_fcvt_q_s; break;
3083                 case 1: op = rv_op_fcvt_q_d; break;
3084                 }
3085                 break;
3086             case 44:
3087                 switch (((inst >> 20) & 0b11111)) {
3088                 case 0: op = rv_op_fsqrt_s; break;
3089                 }
3090                 break;
3091             case 45:
3092                 switch (((inst >> 20) & 0b11111)) {
3093                 case 0: op = rv_op_fsqrt_d; break;
3094                 }
3095                 break;
3096             case 47:
3097                 switch (((inst >> 20) & 0b11111)) {
3098                 case 0: op = rv_op_fsqrt_q; break;
3099                 }
3100                 break;
3101             case 80:
3102                 switch (((inst >> 12) & 0b111)) {
3103                 case 0: op = rv_op_fle_s; break;
3104                 case 1: op = rv_op_flt_s; break;
3105                 case 2: op = rv_op_feq_s; break;
3106                 }
3107                 break;
3108             case 81:
3109                 switch (((inst >> 12) & 0b111)) {
3110                 case 0: op = rv_op_fle_d; break;
3111                 case 1: op = rv_op_flt_d; break;
3112                 case 2: op = rv_op_feq_d; break;
3113                 }
3114                 break;
3115             case 83:
3116                 switch (((inst >> 12) & 0b111)) {
3117                 case 0: op = rv_op_fle_q; break;
3118                 case 1: op = rv_op_flt_q; break;
3119                 case 2: op = rv_op_feq_q; break;
3120                 }
3121                 break;
3122             case 96:
3123                 switch (((inst >> 20) & 0b11111)) {
3124                 case 0: op = rv_op_fcvt_w_s; break;
3125                 case 1: op = rv_op_fcvt_wu_s; break;
3126                 case 2: op = rv_op_fcvt_l_s; break;
3127                 case 3: op = rv_op_fcvt_lu_s; break;
3128                 }
3129                 break;
3130             case 97:
3131                 switch (((inst >> 20) & 0b11111)) {
3132                 case 0: op = rv_op_fcvt_w_d; break;
3133                 case 1: op = rv_op_fcvt_wu_d; break;
3134                 case 2: op = rv_op_fcvt_l_d; break;
3135                 case 3: op = rv_op_fcvt_lu_d; break;
3136                 }
3137                 break;
3138             case 99:
3139                 switch (((inst >> 20) & 0b11111)) {
3140                 case 0: op = rv_op_fcvt_w_q; break;
3141                 case 1: op = rv_op_fcvt_wu_q; break;
3142                 case 2: op = rv_op_fcvt_l_q; break;
3143                 case 3: op = rv_op_fcvt_lu_q; break;
3144                 }
3145                 break;
3146             case 104:
3147                 switch (((inst >> 20) & 0b11111)) {
3148                 case 0: op = rv_op_fcvt_s_w; break;
3149                 case 1: op = rv_op_fcvt_s_wu; break;
3150                 case 2: op = rv_op_fcvt_s_l; break;
3151                 case 3: op = rv_op_fcvt_s_lu; break;
3152                 }
3153                 break;
3154             case 105:
3155                 switch (((inst >> 20) & 0b11111)) {
3156                 case 0: op = rv_op_fcvt_d_w; break;
3157                 case 1: op = rv_op_fcvt_d_wu; break;
3158                 case 2: op = rv_op_fcvt_d_l; break;
3159                 case 3: op = rv_op_fcvt_d_lu; break;
3160                 }
3161                 break;
3162             case 107:
3163                 switch (((inst >> 20) & 0b11111)) {
3164                 case 0: op = rv_op_fcvt_q_w; break;
3165                 case 1: op = rv_op_fcvt_q_wu; break;
3166                 case 2: op = rv_op_fcvt_q_l; break;
3167                 case 3: op = rv_op_fcvt_q_lu; break;
3168                 }
3169                 break;
3170             case 112:
3171                 switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
3172                 case 0: op = rv_op_fmv_x_s; break;
3173                 case 1: op = rv_op_fclass_s; break;
3174                 }
3175                 break;
3176             case 113:
3177                 switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
3178                 case 0: op = rv_op_fmv_x_d; break;
3179                 case 1: op = rv_op_fclass_d; break;
3180                 }
3181                 break;
3182             case 115:
3183                 switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
3184                 case 0: op = rv_op_fmv_x_q; break;
3185                 case 1: op = rv_op_fclass_q; break;
3186                 }
3187                 break;
3188             case 120:
3189                 switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
3190                 case 0: op = rv_op_fmv_s_x; break;
3191                 }
3192                 break;
3193             case 121:
3194                 switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
3195                 case 0: op = rv_op_fmv_d_x; break;
3196                 }
3197                 break;
3198             case 123:
3199                 switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
3200                 case 0: op = rv_op_fmv_q_x; break;
3201                 }
3202                 break;
3203             }
3204             break;
3205         case 21:
3206             switch (((inst >> 12) & 0b111)) {
3207             case 0:
3208                 switch (((inst >> 26) & 0b111111)) {
3209                 case 0: op = rv_op_vadd_vv; break;
3210                 case 2: op = rv_op_vsub_vv; break;
3211                 case 4: op = rv_op_vminu_vv; break;
3212                 case 5: op = rv_op_vmin_vv; break;
3213                 case 6: op = rv_op_vmaxu_vv; break;
3214                 case 7: op = rv_op_vmax_vv; break;
3215                 case 9: op = rv_op_vand_vv; break;
3216                 case 10: op = rv_op_vor_vv; break;
3217                 case 11: op = rv_op_vxor_vv; break;
3218                 case 12: op = rv_op_vrgather_vv; break;
3219                 case 14: op = rv_op_vrgatherei16_vv; break;
3220                 case 16: if (((inst >> 25) & 1) == 0) op = rv_op_vadc_vvm; break;
3221                 case 17: op = rv_op_vmadc_vvm; break;
3222                 case 18: if (((inst >> 25) & 1) == 0) op = rv_op_vsbc_vvm; break;
3223                 case 19: op = rv_op_vmsbc_vvm; break;
3224                 case 23:
3225                     if (((inst >> 20) & 0b111111) == 32)
3226                         op = rv_op_vmv_v_v;
3227                     else if (((inst >> 25) & 1) == 0)
3228                         op = rv_op_vmerge_vvm;
3229                     break;
3230                 case 24: op = rv_op_vmseq_vv; break;
3231                 case 25: op = rv_op_vmsne_vv; break;
3232                 case 26: op = rv_op_vmsltu_vv; break;
3233                 case 27: op = rv_op_vmslt_vv; break;
3234                 case 28: op = rv_op_vmsleu_vv; break;
3235                 case 29: op = rv_op_vmsle_vv; break;
3236                 case 32: op = rv_op_vsaddu_vv; break;
3237                 case 33: op = rv_op_vsadd_vv; break;
3238                 case 34: op = rv_op_vssubu_vv; break;
3239                 case 35: op = rv_op_vssub_vv; break;
3240                 case 37: op = rv_op_vsll_vv; break;
3241                 case 39: op = rv_op_vsmul_vv; break;
3242                 case 40: op = rv_op_vsrl_vv; break;
3243                 case 41: op = rv_op_vsra_vv; break;
3244                 case 42: op = rv_op_vssrl_vv; break;
3245                 case 43: op = rv_op_vssra_vv; break;
3246                 case 44: op = rv_op_vnsrl_wv; break;
3247                 case 45: op = rv_op_vnsra_wv; break;
3248                 case 46: op = rv_op_vnclipu_wv; break;
3249                 case 47: op = rv_op_vnclip_wv; break;
3250                 case 48: op = rv_op_vwredsumu_vs; break;
3251                 case 49: op = rv_op_vwredsum_vs; break;
3252                 }
3253                 break;
3254             case 1:
3255                 switch (((inst >> 26) & 0b111111)) {
3256                 case 0: op = rv_op_vfadd_vv; break;
3257                 case 1: op = rv_op_vfredusum_vs; break;
3258                 case 2: op = rv_op_vfsub_vv; break;
3259                 case 3: op = rv_op_vfredosum_vs; break;
3260                 case 4: op = rv_op_vfmin_vv; break;
3261                 case 5: op = rv_op_vfredmin_vs; break;
3262                 case 6: op = rv_op_vfmax_vv; break;
3263                 case 7: op = rv_op_vfredmax_vs; break;
3264                 case 8: op = rv_op_vfsgnj_vv; break;
3265                 case 9: op = rv_op_vfsgnjn_vv; break;
3266                 case 10: op = rv_op_vfsgnjx_vv; break;
3267                 case 16:
3268                     switch (((inst >> 15) & 0b11111)) {
3269                     case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_f_s; break;
3270                     }
3271                     break;
3272                 case 18:
3273                     switch (((inst >> 15) & 0b11111)) {
3274                     case 0: op = rv_op_vfcvt_xu_f_v; break;
3275                     case 1: op = rv_op_vfcvt_x_f_v; break;
3276                     case 2: op = rv_op_vfcvt_f_xu_v; break;
3277                     case 3: op = rv_op_vfcvt_f_x_v; break;
3278                     case 6: op = rv_op_vfcvt_rtz_xu_f_v; break;
3279                     case 7: op = rv_op_vfcvt_rtz_x_f_v; break;
3280                     case 8: op = rv_op_vfwcvt_xu_f_v; break;
3281                     case 9: op = rv_op_vfwcvt_x_f_v; break;
3282                     case 10: op = rv_op_vfwcvt_f_xu_v; break;
3283                     case 11: op = rv_op_vfwcvt_f_x_v; break;
3284                     case 12: op = rv_op_vfwcvt_f_f_v; break;
3285                     case 14: op = rv_op_vfwcvt_rtz_xu_f_v; break;
3286                     case 15: op = rv_op_vfwcvt_rtz_x_f_v; break;
3287                     case 16: op = rv_op_vfncvt_xu_f_w; break;
3288                     case 17: op = rv_op_vfncvt_x_f_w; break;
3289                     case 18: op = rv_op_vfncvt_f_xu_w; break;
3290                     case 19: op = rv_op_vfncvt_f_x_w; break;
3291                     case 20: op = rv_op_vfncvt_f_f_w; break;
3292                     case 21: op = rv_op_vfncvt_rod_f_f_w; break;
3293                     case 22: op = rv_op_vfncvt_rtz_xu_f_w; break;
3294                     case 23: op = rv_op_vfncvt_rtz_x_f_w; break;
3295                     }
3296                     break;
3297                 case 19:
3298                     switch (((inst >> 15) & 0b11111)) {
3299                     case 0: op = rv_op_vfsqrt_v; break;
3300                     case 4: op = rv_op_vfrsqrt7_v; break;
3301                     case 5: op = rv_op_vfrec7_v; break;
3302                     case 16: op = rv_op_vfclass_v; break;
3303                     }
3304                     break;
3305                 case 24: op = rv_op_vmfeq_vv; break;
3306                 case 25: op = rv_op_vmfle_vv; break;
3307                 case 27: op = rv_op_vmflt_vv; break;
3308                 case 28: op = rv_op_vmfne_vv; break;
3309                 case 32: op = rv_op_vfdiv_vv; break;
3310                 case 36: op = rv_op_vfmul_vv; break;
3311                 case 40: op = rv_op_vfmadd_vv; break;
3312                 case 41: op = rv_op_vfnmadd_vv; break;
3313                 case 42: op = rv_op_vfmsub_vv; break;
3314                 case 43: op = rv_op_vfnmsub_vv; break;
3315                 case 44: op = rv_op_vfmacc_vv; break;
3316                 case 45: op = rv_op_vfnmacc_vv; break;
3317                 case 46: op = rv_op_vfmsac_vv; break;
3318                 case 47: op = rv_op_vfnmsac_vv; break;
3319                 case 48: op = rv_op_vfwadd_vv; break;
3320                 case 49: op = rv_op_vfwredusum_vs; break;
3321                 case 50: op = rv_op_vfwsub_vv; break;
3322                 case 51: op = rv_op_vfwredosum_vs; break;
3323                 case 52: op = rv_op_vfwadd_wv; break;
3324                 case 54: op = rv_op_vfwsub_wv; break;
3325                 case 56: op = rv_op_vfwmul_vv; break;
3326                 case 60: op = rv_op_vfwmacc_vv; break;
3327                 case 61: op = rv_op_vfwnmacc_vv; break;
3328                 case 62: op = rv_op_vfwmsac_vv; break;
3329                 case 63: op = rv_op_vfwnmsac_vv; break;
3330                 }
3331                 break;
3332             case 2:
3333                 switch (((inst >> 26) & 0b111111)) {
3334                 case 0: op = rv_op_vredsum_vs; break;
3335                 case 1: op = rv_op_vredand_vs; break;
3336                 case 2: op = rv_op_vredor_vs; break;
3337                 case 3: op = rv_op_vredxor_vs; break;
3338                 case 4: op = rv_op_vredminu_vs; break;
3339                 case 5: op = rv_op_vredmin_vs; break;
3340                 case 6: op = rv_op_vredmaxu_vs; break;
3341                 case 7: op = rv_op_vredmax_vs; break;
3342                 case 8: op = rv_op_vaaddu_vv; break;
3343                 case 9: op = rv_op_vaadd_vv; break;
3344                 case 10: op = rv_op_vasubu_vv; break;
3345                 case 11: op = rv_op_vasub_vv; break;
3346                 case 16:
3347                     switch (((inst >> 15) & 0b11111)) {
3348                     case 0: if ((inst >> 25) & 1) op = rv_op_vmv_x_s; break;
3349                     case 16: op = rv_op_vcpop_m; break;
3350                     case 17: op = rv_op_vfirst_m; break;
3351                     }
3352                     break;
3353                 case 18:
3354                     switch (((inst >> 15) & 0b11111)) {
3355                     case 2: op = rv_op_vzext_vf8; break;
3356                     case 3: op = rv_op_vsext_vf8; break;
3357                     case 4: op = rv_op_vzext_vf4; break;
3358                     case 5: op = rv_op_vsext_vf4; break;
3359                     case 6: op = rv_op_vzext_vf2; break;
3360                     case 7: op = rv_op_vsext_vf2; break;
3361                     }
3362                     break;
3363                 case 20:
3364                     switch (((inst >> 15) & 0b11111)) {
3365                     case 1: op = rv_op_vmsbf_m;  break;
3366                     case 2: op = rv_op_vmsof_m; break;
3367                     case 3: op = rv_op_vmsif_m; break;
3368                     case 16: op = rv_op_viota_m; break;
3369                     case 17: if (((inst >> 20) & 0b11111) == 0) op = rv_op_vid_v; break;
3370                     }
3371                     break;
3372                 case 23: if ((inst >> 25) & 1) op = rv_op_vcompress_vm; break;
3373                 case 24: if ((inst >> 25) & 1) op = rv_op_vmandn_mm; break;
3374                 case 25: if ((inst >> 25) & 1) op = rv_op_vmand_mm; break;
3375                 case 26: if ((inst >> 25) & 1) op = rv_op_vmor_mm; break;
3376                 case 27: if ((inst >> 25) & 1) op = rv_op_vmxor_mm; break;
3377                 case 28: if ((inst >> 25) & 1) op = rv_op_vmorn_mm; break;
3378                 case 29: if ((inst >> 25) & 1) op = rv_op_vmnand_mm; break;
3379                 case 30: if ((inst >> 25) & 1) op = rv_op_vmnor_mm; break;
3380                 case 31: if ((inst >> 25) & 1) op = rv_op_vmxnor_mm; break;
3381                 case 32: op = rv_op_vdivu_vv; break;
3382                 case 33: op = rv_op_vdiv_vv; break;
3383                 case 34: op = rv_op_vremu_vv; break;
3384                 case 35: op = rv_op_vrem_vv; break;
3385                 case 36: op = rv_op_vmulhu_vv; break;
3386                 case 37: op = rv_op_vmul_vv; break;
3387                 case 38: op = rv_op_vmulhsu_vv; break;
3388                 case 39: op = rv_op_vmulh_vv; break;
3389                 case 41: op = rv_op_vmadd_vv; break;
3390                 case 43: op = rv_op_vnmsub_vv; break;
3391                 case 45: op = rv_op_vmacc_vv; break;
3392                 case 47: op = rv_op_vnmsac_vv; break;
3393                 case 48: op = rv_op_vwaddu_vv; break;
3394                 case 49: op = rv_op_vwadd_vv; break;
3395                 case 50: op = rv_op_vwsubu_vv; break;
3396                 case 51: op = rv_op_vwsub_vv; break;
3397                 case 52: op = rv_op_vwaddu_wv; break;
3398                 case 53: op = rv_op_vwadd_wv; break;
3399                 case 54: op = rv_op_vwsubu_wv; break;
3400                 case 55: op = rv_op_vwsub_wv; break;
3401                 case 56: op = rv_op_vwmulu_vv; break;
3402                 case 58: op = rv_op_vwmulsu_vv; break;
3403                 case 59: op = rv_op_vwmul_vv; break;
3404                 case 60: op = rv_op_vwmaccu_vv; break;
3405                 case 61: op = rv_op_vwmacc_vv; break;
3406                 case 63: op = rv_op_vwmaccsu_vv; break;
3407                 }
3408                 break;
3409             case 3:
3410                 switch (((inst >> 26) & 0b111111)) {
3411                 case 0: op = rv_op_vadd_vi; break;
3412                 case 3: op = rv_op_vrsub_vi; break;
3413                 case 9: op = rv_op_vand_vi; break;
3414                 case 10: op = rv_op_vor_vi; break;
3415                 case 11: op = rv_op_vxor_vi; break;
3416                 case 12: op = rv_op_vrgather_vi; break;
3417                 case 14: op = rv_op_vslideup_vi; break;
3418                 case 15: op = rv_op_vslidedown_vi; break;
3419                 case 16: if (((inst >> 25) & 1) == 0) op = rv_op_vadc_vim; break;
3420                 case 17: op = rv_op_vmadc_vim; break;
3421                 case 23:
3422                     if (((inst >> 20) & 0b111111) == 32)
3423                         op = rv_op_vmv_v_i;
3424                     else if (((inst >> 25) & 1) == 0)
3425                         op = rv_op_vmerge_vim;
3426                     break;
3427                 case 24: op = rv_op_vmseq_vi; break;
3428                 case 25: op = rv_op_vmsne_vi; break;
3429                 case 28: op = rv_op_vmsleu_vi; break;
3430                 case 29: op = rv_op_vmsle_vi; break;
3431                 case 30: op = rv_op_vmsgtu_vi; break;
3432                 case 31: op = rv_op_vmsgt_vi; break;
3433                 case 32: op = rv_op_vsaddu_vi; break;
3434                 case 33: op = rv_op_vsadd_vi; break;
3435                 case 37: op = rv_op_vsll_vi; break;
3436                 case 39:
3437                     switch (((inst >> 15) & 0b11111)) {
3438                     case 0: op = rv_op_vmv1r_v; break;
3439                     case 1: op = rv_op_vmv2r_v; break;
3440                     case 3: op = rv_op_vmv4r_v; break;
3441                     case 7: op = rv_op_vmv8r_v; break;
3442                     }
3443                     break;
3444                 case 40: op = rv_op_vsrl_vi; break;
3445                 case 41: op = rv_op_vsra_vi; break;
3446                 case 42: op = rv_op_vssrl_vi; break;
3447                 case 43: op = rv_op_vssra_vi; break;
3448                 case 44: op = rv_op_vnsrl_wi; break;
3449                 case 45: op = rv_op_vnsra_wi; break;
3450                 case 46: op = rv_op_vnclipu_wi; break;
3451                 case 47: op = rv_op_vnclip_wi; break;
3452                 }
3453                 break;
3454             case 4:
3455                 switch (((inst >> 26) & 0b111111)) {
3456                 case 0: op = rv_op_vadd_vx; break;
3457                 case 2: op = rv_op_vsub_vx; break;
3458                 case 3: op = rv_op_vrsub_vx; break;
3459                 case 4: op = rv_op_vminu_vx; break;
3460                 case 5: op = rv_op_vmin_vx; break;
3461                 case 6: op = rv_op_vmaxu_vx; break;
3462                 case 7: op = rv_op_vmax_vx; break;
3463                 case 9: op = rv_op_vand_vx; break;
3464                 case 10: op = rv_op_vor_vx; break;
3465                 case 11: op = rv_op_vxor_vx; break;
3466                 case 12: op = rv_op_vrgather_vx; break;
3467                 case 14: op = rv_op_vslideup_vx; break;
3468                 case 15: op = rv_op_vslidedown_vx; break;
3469                 case 16: if (((inst >> 25) & 1) == 0) op = rv_op_vadc_vxm; break;
3470                 case 17: op = rv_op_vmadc_vxm; break;
3471                 case 18: if (((inst >> 25) & 1) == 0) op = rv_op_vsbc_vxm; break;
3472                 case 19: op = rv_op_vmsbc_vxm; break;
3473                 case 23:
3474                     if (((inst >> 20) & 0b111111) == 32)
3475                         op = rv_op_vmv_v_x;
3476                     else if (((inst >> 25) & 1) == 0)
3477                         op = rv_op_vmerge_vxm;
3478                     break;
3479                 case 24: op = rv_op_vmseq_vx; break;
3480                 case 25: op = rv_op_vmsne_vx; break;
3481                 case 26: op = rv_op_vmsltu_vx; break;
3482                 case 27: op = rv_op_vmslt_vx; break;
3483                 case 28: op = rv_op_vmsleu_vx; break;
3484                 case 29: op = rv_op_vmsle_vx; break;
3485                 case 30: op = rv_op_vmsgtu_vx; break;
3486                 case 31: op = rv_op_vmsgt_vx; break;
3487                 case 32: op = rv_op_vsaddu_vx; break;
3488                 case 33: op = rv_op_vsadd_vx; break;
3489                 case 34: op = rv_op_vssubu_vx; break;
3490                 case 35: op = rv_op_vssub_vx; break;
3491                 case 37: op = rv_op_vsll_vx; break;
3492                 case 39: op = rv_op_vsmul_vx; break;
3493                 case 40: op = rv_op_vsrl_vx; break;
3494                 case 41: op = rv_op_vsra_vx; break;
3495                 case 42: op = rv_op_vssrl_vx; break;
3496                 case 43: op = rv_op_vssra_vx; break;
3497                 case 44: op = rv_op_vnsrl_wx; break;
3498                 case 45: op = rv_op_vnsra_wx; break;
3499                 case 46: op = rv_op_vnclipu_wx; break;
3500                 case 47: op = rv_op_vnclip_wx; break;
3501                 }
3502                 break;
3503             case 5:
3504                 switch (((inst >> 26) & 0b111111)) {
3505                 case 0: op = rv_op_vfadd_vf; break;
3506                 case 2: op = rv_op_vfsub_vf; break;
3507                 case 4: op = rv_op_vfmin_vf; break;
3508                 case 6: op = rv_op_vfmax_vf; break;
3509                 case 8: op = rv_op_vfsgnj_vf; break;
3510                 case 9: op = rv_op_vfsgnjn_vf; break;
3511                 case 10: op = rv_op_vfsgnjx_vf; break;
3512                 case 14: op = rv_op_vfslide1up_vf; break;
3513                 case 15: op = rv_op_vfslide1down_vf; break;
3514                 case 16:
3515                     switch (((inst >> 20) & 0b11111)) {
3516                     case 0: if ((inst >> 25) & 1) op = rv_op_vfmv_s_f; break;
3517                     }
3518                     break;
3519                 case 23:
3520                     if (((inst >> 25) & 1) == 0)
3521                         op = rv_op_vfmerge_vfm;
3522                     else if (((inst >> 20) & 0b111111) == 32)
3523                         op = rv_op_vfmv_v_f;
3524                     break;
3525                 case 24: op = rv_op_vmfeq_vf; break;
3526                 case 25: op = rv_op_vmfle_vf; break;
3527                 case 27: op = rv_op_vmflt_vf; break;
3528                 case 28: op = rv_op_vmfne_vf; break;
3529                 case 29: op = rv_op_vmfgt_vf; break;
3530                 case 31: op = rv_op_vmfge_vf; break;
3531                 case 32: op = rv_op_vfdiv_vf; break;
3532                 case 33: op = rv_op_vfrdiv_vf; break;
3533                 case 36: op = rv_op_vfmul_vf; break;
3534                 case 39: op = rv_op_vfrsub_vf; break;
3535                 case 40: op = rv_op_vfmadd_vf; break;
3536                 case 41: op = rv_op_vfnmadd_vf; break;
3537                 case 42: op = rv_op_vfmsub_vf; break;
3538                 case 43: op = rv_op_vfnmsub_vf; break;
3539                 case 44: op = rv_op_vfmacc_vf; break;
3540                 case 45: op = rv_op_vfnmacc_vf; break;
3541                 case 46: op = rv_op_vfmsac_vf; break;
3542                 case 47: op = rv_op_vfnmsac_vf; break;
3543                 case 48: op = rv_op_vfwadd_vf; break;
3544                 case 50: op = rv_op_vfwsub_vf; break;
3545                 case 52: op = rv_op_vfwadd_wf; break;
3546                 case 54: op = rv_op_vfwsub_wf; break;
3547                 case 56: op = rv_op_vfwmul_vf; break;
3548                 case 60: op = rv_op_vfwmacc_vf; break;
3549                 case 61: op = rv_op_vfwnmacc_vf; break;
3550                 case 62: op = rv_op_vfwmsac_vf; break;
3551                 case 63: op = rv_op_vfwnmsac_vf; break;
3552                 }
3553                 break;
3554             case 6:
3555                 switch (((inst >> 26) & 0b111111)) {
3556                 case 8: op = rv_op_vaaddu_vx; break;
3557                 case 9: op = rv_op_vaadd_vx; break;
3558                 case 10: op = rv_op_vasubu_vx; break;
3559                 case 11: op = rv_op_vasub_vx; break;
3560                 case 14: op = rv_op_vslide1up_vx; break;
3561                 case 15: op = rv_op_vslide1down_vx; break;
3562                 case 16:
3563                     switch (((inst >> 20) & 0b11111)) {
3564                     case 0: if ((inst >> 25) & 1) op = rv_op_vmv_s_x; break;
3565                     }
3566                     break;
3567                 case 32: op = rv_op_vdivu_vx; break;
3568                 case 33: op = rv_op_vdiv_vx; break;
3569                 case 34: op = rv_op_vremu_vx; break;
3570                 case 35: op = rv_op_vrem_vx; break;
3571                 case 36: op = rv_op_vmulhu_vx; break;
3572                 case 37: op = rv_op_vmul_vx; break;
3573                 case 38: op = rv_op_vmulhsu_vx; break;
3574                 case 39: op = rv_op_vmulh_vx; break;
3575                 case 41: op = rv_op_vmadd_vx; break;
3576                 case 43: op = rv_op_vnmsub_vx; break;
3577                 case 45: op = rv_op_vmacc_vx; break;
3578                 case 47: op = rv_op_vnmsac_vx; break;
3579                 case 48: op = rv_op_vwaddu_vx; break;
3580                 case 49: op = rv_op_vwadd_vx; break;
3581                 case 50: op = rv_op_vwsubu_vx; break;
3582                 case 51: op = rv_op_vwsub_vx; break;
3583                 case 52: op = rv_op_vwaddu_wx; break;
3584                 case 53: op = rv_op_vwadd_wx; break;
3585                 case 54: op = rv_op_vwsubu_wx; break;
3586                 case 55: op = rv_op_vwsub_wx; break;
3587                 case 56: op = rv_op_vwmulu_vx; break;
3588                 case 58: op = rv_op_vwmulsu_vx; break;
3589                 case 59: op = rv_op_vwmul_vx; break;
3590                 case 60: op = rv_op_vwmaccu_vx; break;
3591                 case 61: op = rv_op_vwmacc_vx; break;
3592                 case 62: op = rv_op_vwmaccus_vx; break;
3593                 case 63: op = rv_op_vwmaccsu_vx; break;
3594                 }
3595                 break;
3596             case 7:
3597                 if (((inst >> 31) & 1) == 0) {
3598                     op = rv_op_vsetvli;
3599                 } else if ((inst >> 30) & 1) {
3600                     op = rv_op_vsetivli;
3601                 } else if (((inst >> 25) & 0b11111) == 0) {
3602                     op = rv_op_vsetvl;
3603                 }
3604                 break;
3605             }
3606             break;
3607         case 22:
3608             switch (((inst >> 12) & 0b111)) {
3609             case 0: op = rv_op_addid; break;
3610             case 1:
3611                 switch (((inst >> 26) & 0b111111)) {
3612                 case 0: op = rv_op_sllid; break;
3613                 }
3614                 break;
3615             case 5:
3616                 switch (((inst >> 26) & 0b111111)) {
3617                 case 0: op = rv_op_srlid; break;
3618                 case 16: op = rv_op_sraid; break;
3619                 }
3620                 break;
3621             }
3622             break;
3623         case 24:
3624             switch (((inst >> 12) & 0b111)) {
3625             case 0: op = rv_op_beq; break;
3626             case 1: op = rv_op_bne; break;
3627             case 4: op = rv_op_blt; break;
3628             case 5: op = rv_op_bge; break;
3629             case 6: op = rv_op_bltu; break;
3630             case 7: op = rv_op_bgeu; break;
3631             }
3632             break;
3633         case 25:
3634             switch (((inst >> 12) & 0b111)) {
3635             case 0: op = rv_op_jalr; break;
3636             }
3637             break;
3638         case 27: op = rv_op_jal; break;
3639         case 28:
3640             switch (((inst >> 12) & 0b111)) {
3641             case 0:
3642                 switch (((inst >> 20) & 0b111111100000) | ((inst >> 7) & 0b000000011111)) {
3643                 case 0:
3644                     switch (((inst >> 15) & 0b1111111111)) {
3645                     case 0: op = rv_op_ecall; break;
3646                     case 32: op = rv_op_ebreak; break;
3647                     case 64: op = rv_op_uret; break;
3648                     }
3649                     break;
3650                 case 256:
3651                     switch (((inst >> 20) & 0b11111)) {
3652                     case 2:
3653                         switch (((inst >> 15) & 0b11111)) {
3654                         case 0: op = rv_op_sret; break;
3655                         }
3656                         break;
3657                     case 4: op = rv_op_sfence_vm; break;
3658                     case 5:
3659                         switch (((inst >> 15) & 0b11111)) {
3660                         case 0: op = rv_op_wfi; break;
3661                         }
3662                         break;
3663                     }
3664                     break;
3665                 case 288: op = rv_op_sfence_vma; break;
3666                 case 512:
3667                     switch (((inst >> 15) & 0b1111111111)) {
3668                     case 64: op = rv_op_hret; break;
3669                     }
3670                     break;
3671                 case 768:
3672                     switch (((inst >> 15) & 0b1111111111)) {
3673                     case 64: op = rv_op_mret; break;
3674                     }
3675                     break;
3676                 case 1952:
3677                     switch (((inst >> 15) & 0b1111111111)) {
3678                     case 576: op = rv_op_dret; break;
3679                     }
3680                     break;
3681                 }
3682                 break;
3683             case 1: op = rv_op_csrrw; break;
3684             case 2: op = rv_op_csrrs; break;
3685             case 3: op = rv_op_csrrc; break;
3686             case 5: op = rv_op_csrrwi; break;
3687             case 6: op = rv_op_csrrsi; break;
3688             case 7: op = rv_op_csrrci; break;
3689             }
3690             break;
3691         case 30:
3692             switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {
3693             case 0: op = rv_op_addd; break;
3694             case 1: op = rv_op_slld; break;
3695             case 5: op = rv_op_srld; break;
3696             case 8: op = rv_op_muld; break;
3697             case 12: op = rv_op_divd; break;
3698             case 13: op = rv_op_divud; break;
3699             case 14: op = rv_op_remd; break;
3700             case 15: op = rv_op_remud; break;
3701             case 256: op = rv_op_subd; break;
3702             case 261: op = rv_op_srad; break;
3703             }
3704             break;
3705         }
3706         break;
3707     }
3708     dec->op = op;
3709 }
3710
3711 /* operand extractors */
3712
3713 static uint32_t operand_rd(rv_inst inst)
3714 {
3715     return (inst << 52) >> 59;
3716 }
3717
3718 static uint32_t operand_rs1(rv_inst inst)
3719 {
3720     return (inst << 44) >> 59;
3721 }
3722
3723 static uint32_t operand_rs2(rv_inst inst)
3724 {
3725     return (inst << 39) >> 59;
3726 }
3727
3728 static uint32_t operand_rs3(rv_inst inst)
3729 {
3730     return (inst << 32) >> 59;
3731 }
3732
3733 static uint32_t operand_aq(rv_inst inst)
3734 {
3735     return (inst << 37) >> 63;
3736 }
3737
3738 static uint32_t operand_rl(rv_inst inst)
3739 {
3740     return (inst << 38) >> 63;
3741 }
3742
3743 static uint32_t operand_pred(rv_inst inst)
3744 {
3745     return (inst << 36) >> 60;
3746 }
3747
3748 static uint32_t operand_succ(rv_inst inst)
3749 {
3750     return (inst << 40) >> 60;
3751 }
3752
3753 static uint32_t operand_rm(rv_inst inst)
3754 {
3755     return (inst << 49) >> 61;
3756 }
3757
3758 static uint32_t operand_shamt5(rv_inst inst)
3759 {
3760     return (inst << 39) >> 59;
3761 }
3762
3763 static uint32_t operand_shamt6(rv_inst inst)
3764 {
3765     return (inst << 38) >> 58;
3766 }
3767
3768 static uint32_t operand_shamt7(rv_inst inst)
3769 {
3770     return (inst << 37) >> 57;
3771 }
3772
3773 static uint32_t operand_crdq(rv_inst inst)
3774 {
3775     return (inst << 59) >> 61;
3776 }
3777
3778 static uint32_t operand_crs1q(rv_inst inst)
3779 {
3780     return (inst << 54) >> 61;
3781 }
3782
3783 static uint32_t operand_crs1rdq(rv_inst inst)
3784 {
3785     return (inst << 54) >> 61;
3786 }
3787
3788 static uint32_t operand_crs2q(rv_inst inst)
3789 {
3790     return (inst << 59) >> 61;
3791 }
3792
3793 static uint32_t calculate_xreg(uint32_t sreg)
3794 {
3795     return sreg < 2 ? sreg + 8 : sreg + 16;
3796 }
3797
3798 static uint32_t operand_sreg1(rv_inst inst)
3799 {
3800     return calculate_xreg((inst << 54) >> 61);
3801 }
3802
3803 static uint32_t operand_sreg2(rv_inst inst)
3804 {
3805     return calculate_xreg((inst << 59) >> 61);
3806 }
3807
3808 static uint32_t operand_crd(rv_inst inst)
3809 {
3810     return (inst << 52) >> 59;
3811 }
3812
3813 static uint32_t operand_crs1(rv_inst inst)
3814 {
3815     return (inst << 52) >> 59;
3816 }
3817
3818 static uint32_t operand_crs1rd(rv_inst inst)
3819 {
3820     return (inst << 52) >> 59;
3821 }
3822
3823 static uint32_t operand_crs2(rv_inst inst)
3824 {
3825     return (inst << 57) >> 59;
3826 }
3827
3828 static uint32_t operand_cimmsh5(rv_inst inst)
3829 {
3830     return (inst << 57) >> 59;
3831 }
3832
3833 static uint32_t operand_csr12(rv_inst inst)
3834 {
3835     return (inst << 32) >> 52;
3836 }
3837
3838 static int32_t operand_imm12(rv_inst inst)
3839 {
3840     return ((int64_t)inst << 32) >> 52;
3841 }
3842
3843 static int32_t operand_imm20(rv_inst inst)
3844 {
3845     return (((int64_t)inst << 32) >> 44) << 12;
3846 }
3847
3848 static int32_t operand_jimm20(rv_inst inst)
3849 {
3850     return (((int64_t)inst << 32) >> 63) << 20 |
3851         ((inst << 33) >> 54) << 1 |
3852         ((inst << 43) >> 63) << 11 |
3853         ((inst << 44) >> 56) << 12;
3854 }
3855
3856 static int32_t operand_simm12(rv_inst inst)
3857 {
3858     return (((int64_t)inst << 32) >> 57) << 5 |
3859         (inst << 52) >> 59;
3860 }
3861
3862 static int32_t operand_sbimm12(rv_inst inst)
3863 {
3864     return (((int64_t)inst << 32) >> 63) << 12 |
3865         ((inst << 33) >> 58) << 5 |
3866         ((inst << 52) >> 60) << 1 |
3867         ((inst << 56) >> 63) << 11;
3868 }
3869
3870 static uint32_t operand_cimmshl6(rv_inst inst, rv_isa isa)
3871 {
3872     int imm = ((inst << 51) >> 63) << 5 |
3873         (inst << 57) >> 59;
3874     if (isa == rv128) {
3875         imm = imm ? imm : 64;
3876     }
3877     return imm;
3878 }
3879
3880 static uint32_t operand_cimmshr6(rv_inst inst, rv_isa isa)
3881 {
3882     int imm = ((inst << 51) >> 63) << 5 |
3883         (inst << 57) >> 59;
3884     if (isa == rv128) {
3885         imm = imm | (imm & 32) << 1;
3886         imm = imm ? imm : 64;
3887     }
3888     return imm;
3889 }
3890
3891 static int32_t operand_cimmi(rv_inst inst)
3892 {
3893     return (((int64_t)inst << 51) >> 63) << 5 |
3894         (inst << 57) >> 59;
3895 }
3896
3897 static int32_t operand_cimmui(rv_inst inst)
3898 {
3899     return (((int64_t)inst << 51) >> 63) << 17 |
3900         ((inst << 57) >> 59) << 12;
3901 }
3902
3903 static uint32_t operand_cimmlwsp(rv_inst inst)
3904 {
3905     return ((inst << 51) >> 63) << 5 |
3906         ((inst << 57) >> 61) << 2 |
3907         ((inst << 60) >> 62) << 6;
3908 }
3909
3910 static uint32_t operand_cimmldsp(rv_inst inst)
3911 {
3912     return ((inst << 51) >> 63) << 5 |
3913         ((inst << 57) >> 62) << 3 |
3914         ((inst << 59) >> 61) << 6;
3915 }
3916
3917 static uint32_t operand_cimmlqsp(rv_inst inst)
3918 {
3919     return ((inst << 51) >> 63) << 5 |
3920         ((inst << 57) >> 63) << 4 |
3921         ((inst << 58) >> 60) << 6;
3922 }
3923
3924 static int32_t operand_cimm16sp(rv_inst inst)
3925 {
3926     return (((int64_t)inst << 51) >> 63) << 9 |
3927         ((inst << 57) >> 63) << 4 |
3928         ((inst << 58) >> 63) << 6 |
3929         ((inst << 59) >> 62) << 7 |
3930         ((inst << 61) >> 63) << 5;
3931 }
3932
3933 static int32_t operand_cimmj(rv_inst inst)
3934 {
3935     return (((int64_t)inst << 51) >> 63) << 11 |
3936         ((inst << 52) >> 63) << 4 |
3937         ((inst << 53) >> 62) << 8 |
3938         ((inst << 55) >> 63) << 10 |
3939         ((inst << 56) >> 63) << 6 |
3940         ((inst << 57) >> 63) << 7 |
3941         ((inst << 58) >> 61) << 1 |
3942         ((inst << 61) >> 63) << 5;
3943 }
3944
3945 static int32_t operand_cimmb(rv_inst inst)
3946 {
3947     return (((int64_t)inst << 51) >> 63) << 8 |
3948         ((inst << 52) >> 62) << 3 |
3949         ((inst << 57) >> 62) << 6 |
3950         ((inst << 59) >> 62) << 1 |
3951         ((inst << 61) >> 63) << 5;
3952 }
3953
3954 static uint32_t operand_cimmswsp(rv_inst inst)
3955 {
3956     return ((inst << 51) >> 60) << 2 |
3957         ((inst << 55) >> 62) << 6;
3958 }
3959
3960 static uint32_t operand_cimmsdsp(rv_inst inst)
3961 {
3962     return ((inst << 51) >> 61) << 3 |
3963         ((inst << 54) >> 61) << 6;
3964 }
3965
3966 static uint32_t operand_cimmsqsp(rv_inst inst)
3967 {
3968     return ((inst << 51) >> 62) << 4 |
3969         ((inst << 53) >> 60) << 6;
3970 }
3971
3972 static uint32_t operand_cimm4spn(rv_inst inst)
3973 {
3974     return ((inst << 51) >> 62) << 4 |
3975         ((inst << 53) >> 60) << 6 |
3976         ((inst << 57) >> 63) << 2 |
3977         ((inst << 58) >> 63) << 3;
3978 }
3979
3980 static uint32_t operand_cimmw(rv_inst inst)
3981 {
3982     return ((inst << 51) >> 61) << 3 |
3983         ((inst << 57) >> 63) << 2 |
3984         ((inst << 58) >> 63) << 6;
3985 }
3986
3987 static uint32_t operand_cimmd(rv_inst inst)
3988 {
3989     return ((inst << 51) >> 61) << 3 |
3990         ((inst << 57) >> 62) << 6;
3991 }
3992
3993 static uint32_t operand_cimmq(rv_inst inst)
3994 {
3995     return ((inst << 51) >> 62) << 4 |
3996         ((inst << 53) >> 63) << 8 |
3997         ((inst << 57) >> 62) << 6;
3998 }
3999
4000 static uint32_t operand_vimm(rv_inst inst)
4001 {
4002     return (int64_t)(inst << 44) >> 59;
4003 }
4004
4005 static uint32_t operand_vzimm11(rv_inst inst)
4006 {
4007     return (inst << 33) >> 53;
4008 }
4009
4010 static uint32_t operand_vzimm10(rv_inst inst)
4011 {
4012     return (inst << 34) >> 54;
4013 }
4014
4015 static uint32_t operand_bs(rv_inst inst)
4016 {
4017     return (inst << 32) >> 62;
4018 }
4019
4020 static uint32_t operand_rnum(rv_inst inst)
4021 {
4022     return (inst << 40) >> 60;
4023 }
4024
4025 static uint32_t operand_vm(rv_inst inst)
4026 {
4027     return (inst << 38) >> 63;
4028 }
4029
4030 static uint32_t operand_uimm_c_lb(rv_inst inst)
4031 {
4032     return (((inst << 58) >> 63) << 1) |
4033         ((inst << 57) >> 63);
4034 }
4035
4036 static uint32_t operand_uimm_c_lh(rv_inst inst)
4037 {
4038     return (((inst << 58) >> 63) << 1);
4039 }
4040
4041 static uint32_t operand_zcmp_spimm(rv_inst inst)
4042 {
4043     return ((inst << 60) >> 62) << 4;
4044 }
4045
4046 static uint32_t operand_zcmp_rlist(rv_inst inst)
4047 {
4048     return ((inst << 56) >> 60);
4049 }
4050
4051 static uint32_t calculate_stack_adj(rv_isa isa, uint32_t rlist, uint32_t spimm)
4052 {
4053     int xlen_bytes_log2 = isa == rv64 ? 3 : 2;
4054     int regs = rlist == 15 ? 13 : rlist - 3;
4055     uint32_t stack_adj_base = ROUND_UP(regs << xlen_bytes_log2, 16);
4056     return stack_adj_base + spimm;
4057 }
4058
4059 static uint32_t operand_zcmp_stack_adj(rv_inst inst, rv_isa isa)
4060 {
4061     return calculate_stack_adj(isa, operand_zcmp_rlist(inst),
4062                                operand_zcmp_spimm(inst));
4063 }
4064
4065 static uint32_t operand_tbl_index(rv_inst inst)
4066 {
4067     return ((inst << 54) >> 56);
4068 }
4069
4070 /* decode operands */
4071
4072 static void decode_inst_operands(rv_decode *dec, rv_isa isa)
4073 {
4074     rv_inst inst = dec->inst;
4075     dec->codec = opcode_data[dec->op].codec;
4076     switch (dec->codec) {
4077     case rv_codec_none:
4078         dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero;
4079         dec->imm = 0;
4080         break;
4081     case rv_codec_u:
4082         dec->rd = operand_rd(inst);
4083         dec->rs1 = dec->rs2 = rv_ireg_zero;
4084         dec->imm = operand_imm20(inst);
4085         break;
4086     case rv_codec_uj:
4087         dec->rd = operand_rd(inst);
4088         dec->rs1 = dec->rs2 = rv_ireg_zero;
4089         dec->imm = operand_jimm20(inst);
4090         break;
4091     case rv_codec_i:
4092         dec->rd = operand_rd(inst);
4093         dec->rs1 = operand_rs1(inst);
4094         dec->rs2 = rv_ireg_zero;
4095         dec->imm = operand_imm12(inst);
4096         break;
4097     case rv_codec_i_sh5:
4098         dec->rd = operand_rd(inst);
4099         dec->rs1 = operand_rs1(inst);
4100         dec->rs2 = rv_ireg_zero;
4101         dec->imm = operand_shamt5(inst);
4102         break;
4103     case rv_codec_i_sh6:
4104         dec->rd = operand_rd(inst);
4105         dec->rs1 = operand_rs1(inst);
4106         dec->rs2 = rv_ireg_zero;
4107         dec->imm = operand_shamt6(inst);
4108         break;
4109     case rv_codec_i_sh7:
4110         dec->rd = operand_rd(inst);
4111         dec->rs1 = operand_rs1(inst);
4112         dec->rs2 = rv_ireg_zero;
4113         dec->imm = operand_shamt7(inst);
4114         break;
4115     case rv_codec_i_csr:
4116         dec->rd = operand_rd(inst);
4117         dec->rs1 = operand_rs1(inst);
4118         dec->rs2 = rv_ireg_zero;
4119         dec->imm = operand_csr12(inst);
4120         break;
4121     case rv_codec_s:
4122         dec->rd = rv_ireg_zero;
4123         dec->rs1 = operand_rs1(inst);
4124         dec->rs2 = operand_rs2(inst);
4125         dec->imm = operand_simm12(inst);
4126         break;
4127     case rv_codec_sb:
4128         dec->rd = rv_ireg_zero;
4129         dec->rs1 = operand_rs1(inst);
4130         dec->rs2 = operand_rs2(inst);
4131         dec->imm = operand_sbimm12(inst);
4132         break;
4133     case rv_codec_r:
4134         dec->rd = operand_rd(inst);
4135         dec->rs1 = operand_rs1(inst);
4136         dec->rs2 = operand_rs2(inst);
4137         dec->imm = 0;
4138         break;
4139     case rv_codec_r_m:
4140         dec->rd = operand_rd(inst);
4141         dec->rs1 = operand_rs1(inst);
4142         dec->rs2 = operand_rs2(inst);
4143         dec->imm = 0;
4144         dec->rm = operand_rm(inst);
4145         break;
4146     case rv_codec_r4_m:
4147         dec->rd = operand_rd(inst);
4148         dec->rs1 = operand_rs1(inst);
4149         dec->rs2 = operand_rs2(inst);
4150         dec->rs3 = operand_rs3(inst);
4151         dec->imm = 0;
4152         dec->rm = operand_rm(inst);
4153         break;
4154     case rv_codec_r_a:
4155         dec->rd = operand_rd(inst);
4156         dec->rs1 = operand_rs1(inst);
4157         dec->rs2 = operand_rs2(inst);
4158         dec->imm = 0;
4159         dec->aq = operand_aq(inst);
4160         dec->rl = operand_rl(inst);
4161         break;
4162     case rv_codec_r_l:
4163         dec->rd = operand_rd(inst);
4164         dec->rs1 = operand_rs1(inst);
4165         dec->rs2 = rv_ireg_zero;
4166         dec->imm = 0;
4167         dec->aq = operand_aq(inst);
4168         dec->rl = operand_rl(inst);
4169         break;
4170     case rv_codec_r_f:
4171         dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero;
4172         dec->pred = operand_pred(inst);
4173         dec->succ = operand_succ(inst);
4174         dec->imm = 0;
4175         break;
4176     case rv_codec_cb:
4177         dec->rd = rv_ireg_zero;
4178         dec->rs1 = operand_crs1q(inst) + 8;
4179         dec->rs2 = rv_ireg_zero;
4180         dec->imm = operand_cimmb(inst);
4181         break;
4182     case rv_codec_cb_imm:
4183         dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8;
4184         dec->rs2 = rv_ireg_zero;
4185         dec->imm = operand_cimmi(inst);
4186         break;
4187     case rv_codec_cb_sh5:
4188         dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8;
4189         dec->rs2 = rv_ireg_zero;
4190         dec->imm = operand_cimmsh5(inst);
4191         break;
4192     case rv_codec_cb_sh6:
4193         dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8;
4194         dec->rs2 = rv_ireg_zero;
4195         dec->imm = operand_cimmshr6(inst, isa);
4196         break;
4197     case rv_codec_ci:
4198         dec->rd = dec->rs1 = operand_crs1rd(inst);
4199         dec->rs2 = rv_ireg_zero;
4200         dec->imm = operand_cimmi(inst);
4201         break;
4202     case rv_codec_ci_sh5:
4203         dec->rd = dec->rs1 = operand_crs1rd(inst);
4204         dec->rs2 = rv_ireg_zero;
4205         dec->imm = operand_cimmsh5(inst);
4206         break;
4207     case rv_codec_ci_sh6:
4208         dec->rd = dec->rs1 = operand_crs1rd(inst);
4209         dec->rs2 = rv_ireg_zero;
4210         dec->imm = operand_cimmshl6(inst, isa);
4211         break;
4212     case rv_codec_ci_16sp:
4213         dec->rd = rv_ireg_sp;
4214         dec->rs1 = rv_ireg_sp;
4215         dec->rs2 = rv_ireg_zero;
4216         dec->imm = operand_cimm16sp(inst);
4217         break;
4218     case rv_codec_ci_lwsp:
4219         dec->rd = operand_crd(inst);
4220         dec->rs1 = rv_ireg_sp;
4221         dec->rs2 = rv_ireg_zero;
4222         dec->imm = operand_cimmlwsp(inst);
4223         break;
4224     case rv_codec_ci_ldsp:
4225         dec->rd = operand_crd(inst);
4226         dec->rs1 = rv_ireg_sp;
4227         dec->rs2 = rv_ireg_zero;
4228         dec->imm = operand_cimmldsp(inst);
4229         break;
4230     case rv_codec_ci_lqsp:
4231         dec->rd = operand_crd(inst);
4232         dec->rs1 = rv_ireg_sp;
4233         dec->rs2 = rv_ireg_zero;
4234         dec->imm = operand_cimmlqsp(inst);
4235         break;
4236     case rv_codec_ci_li:
4237         dec->rd = operand_crd(inst);
4238         dec->rs1 = rv_ireg_zero;
4239         dec->rs2 = rv_ireg_zero;
4240         dec->imm = operand_cimmi(inst);
4241         break;
4242     case rv_codec_ci_lui:
4243         dec->rd = operand_crd(inst);
4244         dec->rs1 = rv_ireg_zero;
4245         dec->rs2 = rv_ireg_zero;
4246         dec->imm = operand_cimmui(inst);
4247         break;
4248     case rv_codec_ci_none:
4249         dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero;
4250         dec->imm = 0;
4251         break;
4252     case rv_codec_ciw_4spn:
4253         dec->rd = operand_crdq(inst) + 8;
4254         dec->rs1 = rv_ireg_sp;
4255         dec->rs2 = rv_ireg_zero;
4256         dec->imm = operand_cimm4spn(inst);
4257         break;
4258     case rv_codec_cj:
4259         dec->rd = dec->rs1 = dec->rs2 = rv_ireg_zero;
4260         dec->imm = operand_cimmj(inst);
4261         break;
4262     case rv_codec_cj_jal:
4263         dec->rd = rv_ireg_ra;
4264         dec->rs1 = dec->rs2 = rv_ireg_zero;
4265         dec->imm = operand_cimmj(inst);
4266         break;
4267     case rv_codec_cl_lw:
4268         dec->rd = operand_crdq(inst) + 8;
4269         dec->rs1 = operand_crs1q(inst) + 8;
4270         dec->rs2 = rv_ireg_zero;
4271         dec->imm = operand_cimmw(inst);
4272         break;
4273     case rv_codec_cl_ld:
4274         dec->rd = operand_crdq(inst) + 8;
4275         dec->rs1 = operand_crs1q(inst) + 8;
4276         dec->rs2 = rv_ireg_zero;
4277         dec->imm = operand_cimmd(inst);
4278         break;
4279     case rv_codec_cl_lq:
4280         dec->rd = operand_crdq(inst) + 8;
4281         dec->rs1 = operand_crs1q(inst) + 8;
4282         dec->rs2 = rv_ireg_zero;
4283         dec->imm = operand_cimmq(inst);
4284         break;
4285     case rv_codec_cr:
4286         dec->rd = dec->rs1 = operand_crs1rd(inst);
4287         dec->rs2 = operand_crs2(inst);
4288         dec->imm = 0;
4289         break;
4290     case rv_codec_cr_mv:
4291         dec->rd = operand_crd(inst);
4292         dec->rs1 = operand_crs2(inst);
4293         dec->rs2 = rv_ireg_zero;
4294         dec->imm = 0;
4295         break;
4296     case rv_codec_cr_jalr:
4297         dec->rd = rv_ireg_ra;
4298         dec->rs1 = operand_crs1(inst);
4299         dec->rs2 = rv_ireg_zero;
4300         dec->imm = 0;
4301         break;
4302     case rv_codec_cr_jr:
4303         dec->rd = rv_ireg_zero;
4304         dec->rs1 = operand_crs1(inst);
4305         dec->rs2 = rv_ireg_zero;
4306         dec->imm = 0;
4307         break;
4308     case rv_codec_cs:
4309         dec->rd = dec->rs1 = operand_crs1rdq(inst) + 8;
4310         dec->rs2 = operand_crs2q(inst) + 8;
4311         dec->imm = 0;
4312         break;
4313     case rv_codec_cs_sw:
4314         dec->rd = rv_ireg_zero;
4315         dec->rs1 = operand_crs1q(inst) + 8;
4316         dec->rs2 = operand_crs2q(inst) + 8;
4317         dec->imm = operand_cimmw(inst);
4318         break;
4319     case rv_codec_cs_sd:
4320         dec->rd = rv_ireg_zero;
4321         dec->rs1 = operand_crs1q(inst) + 8;
4322         dec->rs2 = operand_crs2q(inst) + 8;
4323         dec->imm = operand_cimmd(inst);
4324         break;
4325     case rv_codec_cs_sq:
4326         dec->rd = rv_ireg_zero;
4327         dec->rs1 = operand_crs1q(inst) + 8;
4328         dec->rs2 = operand_crs2q(inst) + 8;
4329         dec->imm = operand_cimmq(inst);
4330         break;
4331     case rv_codec_css_swsp:
4332         dec->rd = rv_ireg_zero;
4333         dec->rs1 = rv_ireg_sp;
4334         dec->rs2 = operand_crs2(inst);
4335         dec->imm = operand_cimmswsp(inst);
4336         break;
4337     case rv_codec_css_sdsp:
4338         dec->rd = rv_ireg_zero;
4339         dec->rs1 = rv_ireg_sp;
4340         dec->rs2 = operand_crs2(inst);
4341         dec->imm = operand_cimmsdsp(inst);
4342         break;
4343     case rv_codec_css_sqsp:
4344         dec->rd = rv_ireg_zero;
4345         dec->rs1 = rv_ireg_sp;
4346         dec->rs2 = operand_crs2(inst);
4347         dec->imm = operand_cimmsqsp(inst);
4348         break;
4349     case rv_codec_k_bs:
4350         dec->rs1 = operand_rs1(inst);
4351         dec->rs2 = operand_rs2(inst);
4352         dec->bs = operand_bs(inst);
4353         break;
4354     case rv_codec_k_rnum:
4355         dec->rd = operand_rd(inst);
4356         dec->rs1 = operand_rs1(inst);
4357         dec->rnum = operand_rnum(inst);
4358         break;
4359     case rv_codec_v_r:
4360         dec->rd = operand_rd(inst);
4361         dec->rs1 = operand_rs1(inst);
4362         dec->rs2 = operand_rs2(inst);
4363         dec->vm = operand_vm(inst);
4364         break;
4365     case rv_codec_v_ldst:
4366         dec->rd = operand_rd(inst);
4367         dec->rs1 = operand_rs1(inst);
4368         dec->vm = operand_vm(inst);
4369         break;
4370     case rv_codec_v_i:
4371         dec->rd = operand_rd(inst);
4372         dec->rs2 = operand_rs2(inst);
4373         dec->imm = operand_vimm(inst);
4374         dec->vm = operand_vm(inst);
4375         break;
4376     case rv_codec_vsetvli:
4377         dec->rd = operand_rd(inst);
4378         dec->rs1 = operand_rs1(inst);
4379         dec->vzimm = operand_vzimm11(inst);
4380         break;
4381     case rv_codec_vsetivli:
4382         dec->rd = operand_rd(inst);
4383         dec->imm = operand_vimm(inst);
4384         dec->vzimm = operand_vzimm10(inst);
4385         break;
4386     case rv_codec_zcb_lb:
4387         dec->rs1 = operand_crs1q(inst) + 8;
4388         dec->rs2 = operand_crs2q(inst) + 8;
4389         dec->imm = operand_uimm_c_lb(inst);
4390         break;
4391     case rv_codec_zcb_lh:
4392         dec->rs1 = operand_crs1q(inst) + 8;
4393         dec->rs2 = operand_crs2q(inst) + 8;
4394         dec->imm = operand_uimm_c_lh(inst);
4395         break;
4396     case rv_codec_zcb_ext:
4397         dec->rd = operand_crs1q(inst) + 8;
4398         break;
4399     case rv_codec_zcb_mul:
4400         dec->rd = operand_crs1rdq(inst) + 8;
4401         dec->rs2 = operand_crs2q(inst) + 8;
4402         break;
4403     case rv_codec_zcmp_cm_pushpop:
4404         dec->imm = operand_zcmp_stack_adj(inst, isa);
4405         dec->rlist = operand_zcmp_rlist(inst);
4406         break;
4407     case rv_codec_zcmp_cm_mv:
4408         dec->rd = operand_sreg1(inst);
4409         dec->rs2 = operand_sreg2(inst);
4410         break;
4411     case rv_codec_zcmt_jt:
4412         dec->imm = operand_tbl_index(inst);
4413         break;
4414     };
4415 }
4416
4417 /* check constraint */
4418
4419 static bool check_constraints(rv_decode *dec, const rvc_constraint *c)
4420 {
4421     int32_t imm = dec->imm;
4422     uint8_t rd = dec->rd, rs1 = dec->rs1, rs2 = dec->rs2;
4423     while (*c != rvc_end) {
4424         switch (*c) {
4425         case rvc_rd_eq_ra:
4426             if (!(rd == 1)) {
4427                 return false;
4428             }
4429             break;
4430         case rvc_rd_eq_x0:
4431             if (!(rd == 0)) {
4432                 return false;
4433             }
4434             break;
4435         case rvc_rs1_eq_x0:
4436             if (!(rs1 == 0)) {
4437                 return false;
4438             }
4439             break;
4440         case rvc_rs2_eq_x0:
4441             if (!(rs2 == 0)) {
4442                 return false;
4443             }
4444             break;
4445         case rvc_rs2_eq_rs1:
4446             if (!(rs2 == rs1)) {
4447                 return false;
4448             }
4449             break;
4450         case rvc_rs1_eq_ra:
4451             if (!(rs1 == 1)) {
4452                 return false;
4453             }
4454             break;
4455         case rvc_imm_eq_zero:
4456             if (!(imm == 0)) {
4457                 return false;
4458             }
4459             break;
4460         case rvc_imm_eq_n1:
4461             if (!(imm == -1)) {
4462                 return false;
4463             }
4464             break;
4465         case rvc_imm_eq_p1:
4466             if (!(imm == 1)) {
4467                 return false;
4468             }
4469             break;
4470         case rvc_csr_eq_0x001:
4471             if (!(imm == 0x001)) {
4472                 return false;
4473             }
4474             break;
4475         case rvc_csr_eq_0x002:
4476             if (!(imm == 0x002)) {
4477                 return false;
4478             }
4479             break;
4480         case rvc_csr_eq_0x003:
4481             if (!(imm == 0x003)) {
4482                 return false;
4483             }
4484             break;
4485         case rvc_csr_eq_0xc00:
4486             if (!(imm == 0xc00)) {
4487                 return false;
4488             }
4489             break;
4490         case rvc_csr_eq_0xc01:
4491             if (!(imm == 0xc01)) {
4492                 return false;
4493             }
4494             break;
4495         case rvc_csr_eq_0xc02:
4496             if (!(imm == 0xc02)) {
4497                 return false;
4498             }
4499             break;
4500         case rvc_csr_eq_0xc80:
4501             if (!(imm == 0xc80)) {
4502                 return false;
4503             }
4504             break;
4505         case rvc_csr_eq_0xc81:
4506             if (!(imm == 0xc81)) {
4507                 return false;
4508             }
4509             break;
4510         case rvc_csr_eq_0xc82:
4511             if (!(imm == 0xc82)) {
4512                 return false;
4513             }
4514             break;
4515         default: break;
4516         }
4517         c++;
4518     }
4519     return true;
4520 }
4521
4522 /* instruction length */
4523
4524 static size_t inst_length(rv_inst inst)
4525 {
4526     /* NOTE: supports maximum instruction size of 64-bits */
4527
4528     /* instruction length coding
4529      *
4530      *      aa - 16 bit aa != 11
4531      *   bbb11 - 32 bit bbb != 111
4532      *  011111 - 48 bit
4533      * 0111111 - 64 bit
4534      */
4535
4536     return (inst &      0b11) != 0b11      ? 2
4537          : (inst &   0b11100) != 0b11100   ? 4
4538          : (inst &  0b111111) == 0b011111  ? 6
4539          : (inst & 0b1111111) == 0b0111111 ? 8
4540          : 0;
4541 }
4542
4543 /* format instruction */
4544
4545 static void append(char *s1, const char *s2, size_t n)
4546 {
4547     size_t l1 = strlen(s1);
4548     if (n - l1 - 1 > 0) {
4549         strncat(s1, s2, n - l1);
4550     }
4551 }
4552
4553 static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec)
4554 {
4555     char tmp[64];
4556     const char *fmt;
4557
4558     fmt = opcode_data[dec->op].format;
4559     while (*fmt) {
4560         switch (*fmt) {
4561         case 'O':
4562             append(buf, opcode_data[dec->op].name, buflen);
4563             break;
4564         case '(':
4565             append(buf, "(", buflen);
4566             break;
4567         case ',':
4568             append(buf, ",", buflen);
4569             break;
4570         case ')':
4571             append(buf, ")", buflen);
4572             break;
4573         case '-':
4574             append(buf, "-", buflen);
4575             break;
4576         case 'b':
4577             snprintf(tmp, sizeof(tmp), "%d", dec->bs);
4578             append(buf, tmp, buflen);
4579             break;
4580         case 'n':
4581             snprintf(tmp, sizeof(tmp), "%d", dec->rnum);
4582             append(buf, tmp, buflen);
4583             break;
4584         case '0':
4585             append(buf, rv_ireg_name_sym[dec->rd], buflen);
4586             break;
4587         case '1':
4588             append(buf, rv_ireg_name_sym[dec->rs1], buflen);
4589             break;
4590         case '2':
4591             append(buf, rv_ireg_name_sym[dec->rs2], buflen);
4592             break;
4593         case '3':
4594             append(buf, rv_freg_name_sym[dec->rd], buflen);
4595             break;
4596         case '4':
4597             append(buf, rv_freg_name_sym[dec->rs1], buflen);
4598             break;
4599         case '5':
4600             append(buf, rv_freg_name_sym[dec->rs2], buflen);
4601             break;
4602         case '6':
4603             append(buf, rv_freg_name_sym[dec->rs3], buflen);
4604             break;
4605         case '7':
4606             snprintf(tmp, sizeof(tmp), "%d", dec->rs1);
4607             append(buf, tmp, buflen);
4608             break;
4609         case 'i':
4610             snprintf(tmp, sizeof(tmp), "%d", dec->imm);
4611             append(buf, tmp, buflen);
4612             break;
4613         case 'u':
4614             snprintf(tmp, sizeof(tmp), "%u", ((uint32_t)dec->imm & 0b11111));
4615             append(buf, tmp, buflen);
4616             break;
4617         case 'o':
4618             snprintf(tmp, sizeof(tmp), "%d", dec->imm);
4619             append(buf, tmp, buflen);
4620             while (strlen(buf) < tab * 2) {
4621                 append(buf, " ", buflen);
4622             }
4623             snprintf(tmp, sizeof(tmp), "# 0x%" PRIx64,
4624                 dec->pc + dec->imm);
4625             append(buf, tmp, buflen);
4626             break;
4627         case 'c': {
4628             const char *name = csr_name(dec->imm & 0xfff);
4629             if (name) {
4630                 append(buf, name, buflen);
4631             } else {
4632                 snprintf(tmp, sizeof(tmp), "0x%03x", dec->imm & 0xfff);
4633                 append(buf, tmp, buflen);
4634             }
4635             break;
4636         }
4637         case 'r':
4638             switch (dec->rm) {
4639             case rv_rm_rne:
4640                 append(buf, "rne", buflen);
4641                 break;
4642             case rv_rm_rtz:
4643                 append(buf, "rtz", buflen);
4644                 break;
4645             case rv_rm_rdn:
4646                 append(buf, "rdn", buflen);
4647                 break;
4648             case rv_rm_rup:
4649                 append(buf, "rup", buflen);
4650                 break;
4651             case rv_rm_rmm:
4652                 append(buf, "rmm", buflen);
4653                 break;
4654             case rv_rm_dyn:
4655                 append(buf, "dyn", buflen);
4656                 break;
4657             default:
4658                 append(buf, "inv", buflen);
4659                 break;
4660             }
4661             break;
4662         case 'p':
4663             if (dec->pred & rv_fence_i) {
4664                 append(buf, "i", buflen);
4665             }
4666             if (dec->pred & rv_fence_o) {
4667                 append(buf, "o", buflen);
4668             }
4669             if (dec->pred & rv_fence_r) {
4670                 append(buf, "r", buflen);
4671             }
4672             if (dec->pred & rv_fence_w) {
4673                 append(buf, "w", buflen);
4674             }
4675             break;
4676         case 's':
4677             if (dec->succ & rv_fence_i) {
4678                 append(buf, "i", buflen);
4679             }
4680             if (dec->succ & rv_fence_o) {
4681                 append(buf, "o", buflen);
4682             }
4683             if (dec->succ & rv_fence_r) {
4684                 append(buf, "r", buflen);
4685             }
4686             if (dec->succ & rv_fence_w) {
4687                 append(buf, "w", buflen);
4688             }
4689             break;
4690         case '\t':
4691             while (strlen(buf) < tab) {
4692                 append(buf, " ", buflen);
4693             }
4694             break;
4695         case 'A':
4696             if (dec->aq) {
4697                 append(buf, ".aq", buflen);
4698             }
4699             break;
4700         case 'R':
4701             if (dec->rl) {
4702                 append(buf, ".rl", buflen);
4703             }
4704             break;
4705         case 'l':
4706             append(buf, ",v0", buflen);
4707             break;
4708         case 'm':
4709             if (dec->vm == 0) {
4710                 append(buf, ",v0.t", buflen);
4711             }
4712             break;
4713         case 'D':
4714             append(buf, rv_vreg_name_sym[dec->rd], buflen);
4715             break;
4716         case 'E':
4717             append(buf, rv_vreg_name_sym[dec->rs1], buflen);
4718             break;
4719         case 'F':
4720             append(buf, rv_vreg_name_sym[dec->rs2], buflen);
4721             break;
4722         case 'G':
4723             append(buf, rv_vreg_name_sym[dec->rs3], buflen);
4724             break;
4725         case 'v': {
4726             char nbuf[32] = {0};
4727             const int sew = 1 << (((dec->vzimm >> 3) & 0b111) + 3);
4728             sprintf(nbuf, "%d", sew);
4729             const int lmul = dec->vzimm & 0b11;
4730             const int flmul = (dec->vzimm >> 2) & 1;
4731             const char *vta = (dec->vzimm >> 6) & 1 ? "ta" : "tu";
4732             const char *vma = (dec->vzimm >> 7) & 1 ? "ma" : "mu";
4733             append(buf, "e", buflen);
4734             append(buf, nbuf, buflen);
4735             append(buf, ",m", buflen);
4736             if (flmul) {
4737                 switch (lmul) {
4738                 case 3:
4739                     sprintf(nbuf, "f2");
4740                     break;
4741                 case 2:
4742                     sprintf(nbuf, "f4");
4743                     break;
4744                 case 1:
4745                     sprintf(nbuf, "f8");
4746                 break;
4747                 }
4748                 append(buf, nbuf, buflen);
4749             } else {
4750                 sprintf(nbuf, "%d", 1 << lmul);
4751                 append(buf, nbuf, buflen);
4752             }
4753             append(buf, ",", buflen);
4754             append(buf, vta, buflen);
4755             append(buf, ",", buflen);
4756             append(buf, vma, buflen);
4757             break;
4758         }
4759         case 'x': {
4760             switch (dec->rlist) {
4761             case 4:
4762                 snprintf(tmp, sizeof(tmp), "{ra}");
4763                 break;
4764             case 5:
4765                 snprintf(tmp, sizeof(tmp), "{ra, s0}");
4766                 break;
4767             case 15:
4768                 snprintf(tmp, sizeof(tmp), "{ra, s0-s11}");
4769                 break;
4770             default:
4771                 snprintf(tmp, sizeof(tmp), "{ra, s0-s%d}", dec->rlist - 5);
4772                 break;
4773             }
4774             append(buf, tmp, buflen);
4775             break;
4776         }
4777         default:
4778             break;
4779         }
4780         fmt++;
4781     }
4782 }
4783
4784 /* lift instruction to pseudo-instruction */
4785
4786 static void decode_inst_lift_pseudo(rv_decode *dec)
4787 {
4788     const rv_comp_data *comp_data = opcode_data[dec->op].pseudo;
4789     if (!comp_data) {
4790         return;
4791     }
4792     while (comp_data->constraints) {
4793         if (check_constraints(dec, comp_data->constraints)) {
4794             dec->op = comp_data->op;
4795             dec->codec = opcode_data[dec->op].codec;
4796             return;
4797         }
4798         comp_data++;
4799     }
4800 }
4801
4802 /* decompress instruction */
4803
4804 static void decode_inst_decompress_rv32(rv_decode *dec)
4805 {
4806     int decomp_op = opcode_data[dec->op].decomp_rv32;
4807     if (decomp_op != rv_op_illegal) {
4808         if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz)
4809             && dec->imm == 0) {
4810             dec->op = rv_op_illegal;
4811         } else {
4812             dec->op = decomp_op;
4813             dec->codec = opcode_data[decomp_op].codec;
4814         }
4815     }
4816 }
4817
4818 static void decode_inst_decompress_rv64(rv_decode *dec)
4819 {
4820     int decomp_op = opcode_data[dec->op].decomp_rv64;
4821     if (decomp_op != rv_op_illegal) {
4822         if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz)
4823             && dec->imm == 0) {
4824             dec->op = rv_op_illegal;
4825         } else {
4826             dec->op = decomp_op;
4827             dec->codec = opcode_data[decomp_op].codec;
4828         }
4829     }
4830 }
4831
4832 static void decode_inst_decompress_rv128(rv_decode *dec)
4833 {
4834     int decomp_op = opcode_data[dec->op].decomp_rv128;
4835     if (decomp_op != rv_op_illegal) {
4836         if ((opcode_data[dec->op].decomp_data & rvcd_imm_nz)
4837             && dec->imm == 0) {
4838             dec->op = rv_op_illegal;
4839         } else {
4840             dec->op = decomp_op;
4841             dec->codec = opcode_data[decomp_op].codec;
4842         }
4843     }
4844 }
4845
4846 static void decode_inst_decompress(rv_decode *dec, rv_isa isa)
4847 {
4848     switch (isa) {
4849     case rv32:
4850         decode_inst_decompress_rv32(dec);
4851         break;
4852     case rv64:
4853         decode_inst_decompress_rv64(dec);
4854         break;
4855     case rv128:
4856         decode_inst_decompress_rv128(dec);
4857         break;
4858     }
4859 }
4860
4861 /* disassemble instruction */
4862
4863 static void
4864 disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst)
4865 {
4866     rv_decode dec = { 0 };
4867     dec.pc = pc;
4868     dec.inst = inst;
4869     decode_inst_opcode(&dec, isa);
4870     decode_inst_operands(&dec, isa);
4871     decode_inst_decompress(&dec, isa);
4872     decode_inst_lift_pseudo(&dec);
4873     format_inst(buf, buflen, 24, &dec);
4874 }
4875
4876 #define INST_FMT_2 "%04" PRIx64 "              "
4877 #define INST_FMT_4 "%08" PRIx64 "          "
4878 #define INST_FMT_6 "%012" PRIx64 "      "
4879 #define INST_FMT_8 "%016" PRIx64 "  "
4880
4881 static int
4882 print_insn_riscv(bfd_vma memaddr, struct disassemble_info *info, rv_isa isa)
4883 {
4884     char buf[128] = { 0 };
4885     bfd_byte packet[2];
4886     rv_inst inst = 0;
4887     size_t len = 2;
4888     bfd_vma n;
4889     int status;
4890
4891     /* Instructions are made of 2-byte packets in little-endian order */
4892     for (n = 0; n < len; n += 2) {
4893         status = (*info->read_memory_func)(memaddr + n, packet, 2, info);
4894         if (status != 0) {
4895             /* Don't fail just because we fell off the end.  */
4896             if (n > 0) {
4897                 break;
4898             }
4899             (*info->memory_error_func)(status, memaddr, info);
4900             return status;
4901         }
4902         inst |= ((rv_inst) bfd_getl16(packet)) << (8 * n);
4903         if (n == 0) {
4904             len = inst_length(inst);
4905         }
4906     }
4907
4908     switch (len) {
4909     case 2:
4910         (*info->fprintf_func)(info->stream, INST_FMT_2, inst);
4911         break;
4912     case 4:
4913         (*info->fprintf_func)(info->stream, INST_FMT_4, inst);
4914         break;
4915     case 6:
4916         (*info->fprintf_func)(info->stream, INST_FMT_6, inst);
4917         break;
4918     default:
4919         (*info->fprintf_func)(info->stream, INST_FMT_8, inst);
4920         break;
4921     }
4922
4923     disasm_inst(buf, sizeof(buf), isa, memaddr, inst);
4924     (*info->fprintf_func)(info->stream, "%s", buf);
4925
4926     return len;
4927 }
4928
4929 int print_insn_riscv32(bfd_vma memaddr, struct disassemble_info *info)
4930 {
4931     return print_insn_riscv(memaddr, info, rv32);
4932 }
4933
4934 int print_insn_riscv64(bfd_vma memaddr, struct disassemble_info *info)
4935 {
4936     return print_insn_riscv(memaddr, info, rv64);
4937 }
4938
4939 int print_insn_riscv128(bfd_vma memaddr, struct disassemble_info *info)
4940 {
4941     return print_insn_riscv(memaddr, info, rv128);
4942 }