hw/dma/sun4m_iommu.c

   1 /*
   2  * QEMU Sun4m iommu emulation
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw/sparc/sun4m.h"
  26 #include "hw/sysbus.h"
  27 #include "exec/address-spaces.h"
  28 #include "trace.h"
  29
  30 /*
  31  * I/O MMU used by Sun4m systems
  32  *
  33  * Chipset docs:
  34  * "Sun-4M System Architecture (revision 2.0) by Chuck Narad", 950-1373-01,
  35  * http://mediacast.sun.com/users/Barton808/media/Sun4M_SystemArchitecture_edited2.pdf
  36  */
  37
  38 #define IOMMU_NREGS         (4*4096/4)
  39 #define IOMMU_CTRL          (0x0000 >> 2)
  40 #define IOMMU_CTRL_IMPL     0xf0000000 /* Implementation */
  41 #define IOMMU_CTRL_VERS     0x0f000000 /* Version */
  42 #define IOMMU_CTRL_RNGE     0x0000001c /* Mapping RANGE */
  43 #define IOMMU_RNGE_16MB     0x00000000 /* 0xff000000 -> 0xffffffff */
  44 #define IOMMU_RNGE_32MB     0x00000004 /* 0xfe000000 -> 0xffffffff */
  45 #define IOMMU_RNGE_64MB     0x00000008 /* 0xfc000000 -> 0xffffffff */
  46 #define IOMMU_RNGE_128MB    0x0000000c /* 0xf8000000 -> 0xffffffff */
  47 #define IOMMU_RNGE_256MB    0x00000010 /* 0xf0000000 -> 0xffffffff */
  48 #define IOMMU_RNGE_512MB    0x00000014 /* 0xe0000000 -> 0xffffffff */
  49 #define IOMMU_RNGE_1GB      0x00000018 /* 0xc0000000 -> 0xffffffff */
  50 #define IOMMU_RNGE_2GB      0x0000001c /* 0x80000000 -> 0xffffffff */
  51 #define IOMMU_CTRL_ENAB     0x00000001 /* IOMMU Enable */
  52 #define IOMMU_CTRL_MASK     0x0000001d
  53
  54 #define IOMMU_BASE          (0x0004 >> 2)
  55 #define IOMMU_BASE_MASK     0x07fffc00
  56
  57 #define IOMMU_TLBFLUSH      (0x0014 >> 2)
  58 #define IOMMU_TLBFLUSH_MASK 0xffffffff
  59
  60 #define IOMMU_PGFLUSH       (0x0018 >> 2)
  61 #define IOMMU_PGFLUSH_MASK  0xffffffff
  62
  63 #define IOMMU_AFSR          (0x1000 >> 2)
  64 #define IOMMU_AFSR_ERR      0x80000000 /* LE, TO, or BE asserted */
  65 #define IOMMU_AFSR_LE       0x40000000 /* SBUS reports error after
  66                                           transaction */
  67 #define IOMMU_AFSR_TO       0x20000000 /* Write access took more than
  68                                           12.8 us. */
  69 #define IOMMU_AFSR_BE       0x10000000 /* Write access received error
  70                                           acknowledge */
  71 #define IOMMU_AFSR_SIZE     0x0e000000 /* Size of transaction causing error */
  72 #define IOMMU_AFSR_S        0x01000000 /* Sparc was in supervisor mode */
  73 #define IOMMU_AFSR_RESV     0x00800000 /* Reserved, forced to 0x8 by
  74                                           hardware */
  75 #define IOMMU_AFSR_ME       0x00080000 /* Multiple errors occurred */
  76 #define IOMMU_AFSR_RD       0x00040000 /* A read operation was in progress */
  77 #define IOMMU_AFSR_FAV      0x00020000 /* IOMMU afar has valid contents */
  78 #define IOMMU_AFSR_MASK     0xff0fffff
  79
  80 #define IOMMU_AFAR          (0x1004 >> 2)
  81
  82 #define IOMMU_AER           (0x1008 >> 2) /* Arbiter Enable Register */
  83 #define IOMMU_AER_EN_P0_ARB 0x00000001    /* MBus master 0x8 (Always 1) */
  84 #define IOMMU_AER_EN_P1_ARB 0x00000002    /* MBus master 0x9 */
  85 #define IOMMU_AER_EN_P2_ARB 0x00000004    /* MBus master 0xa */
  86 #define IOMMU_AER_EN_P3_ARB 0x00000008    /* MBus master 0xb */
  87 #define IOMMU_AER_EN_0      0x00010000    /* SBus slot 0 */
  88 #define IOMMU_AER_EN_1      0x00020000    /* SBus slot 1 */
  89 #define IOMMU_AER_EN_2      0x00040000    /* SBus slot 2 */
  90 #define IOMMU_AER_EN_3      0x00080000    /* SBus slot 3 */
  91 #define IOMMU_AER_EN_F      0x00100000    /* SBus on-board */
  92 #define IOMMU_AER_SBW       0x80000000    /* S-to-M asynchronous writes */
  93 #define IOMMU_AER_MASK      0x801f000f
  94
  95 #define IOMMU_SBCFG0        (0x1010 >> 2) /* SBUS configration per-slot */
  96 #define IOMMU_SBCFG1        (0x1014 >> 2) /* SBUS configration per-slot */
  97 #define IOMMU_SBCFG2        (0x1018 >> 2) /* SBUS configration per-slot */
  98 #define IOMMU_SBCFG3        (0x101c >> 2) /* SBUS configration per-slot */
  99 #define IOMMU_SBCFG_SAB30   0x00010000 /* Phys-address bit 30 when
 100                                           bypass enabled */
 101 #define IOMMU_SBCFG_BA16    0x00000004 /* Slave supports 16 byte bursts */
 102 #define IOMMU_SBCFG_BA8     0x00000002 /* Slave supports 8 byte bursts */
 103 #define IOMMU_SBCFG_BYPASS  0x00000001 /* Bypass IOMMU, treat all addresses
 104                                           produced by this device as pure
 105                                           physical. */
 106 #define IOMMU_SBCFG_MASK    0x00010003
 107
 108 #define IOMMU_ARBEN         (0x2000 >> 2) /* SBUS arbitration enable */
 109 #define IOMMU_ARBEN_MASK    0x001f0000
 110 #define IOMMU_MID           0x00000008
 111
 112 #define IOMMU_MASK_ID       (0x3018 >> 2) /* Mask ID */
 113 #define IOMMU_MASK_ID_MASK  0x00ffffff
 114
 115 #define IOMMU_MSII_MASK     0x26000000 /* microSPARC II mask number */
 116 #define IOMMU_TS_MASK       0x23000000 /* turboSPARC mask number */
 117
 118 /* The format of an iopte in the page tables */
 119 #define IOPTE_PAGE          0xffffff00 /* Physical page number (PA[35:12]) */
 120 #define IOPTE_CACHE         0x00000080 /* Cached (in vme IOCACHE or
 121                                           Viking/MXCC) */
 122 #define IOPTE_WRITE         0x00000004 /* Writable */
 123 #define IOPTE_VALID         0x00000002 /* IOPTE is valid */
 124 #define IOPTE_WAZ           0x00000001 /* Write as zeros */
 125
 126 #define IOMMU_PAGE_SHIFT    12
 127 #define IOMMU_PAGE_SIZE     (1 << IOMMU_PAGE_SHIFT)
 128 #define IOMMU_PAGE_MASK     ~(IOMMU_PAGE_SIZE - 1)
 129
 130 #define TYPE_SUN4M_IOMMU "iommu"
 131 #define SUN4M_IOMMU(obj) OBJECT_CHECK(IOMMUState, (obj), TYPE_SUN4M_IOMMU)
 132
 133 typedef struct IOMMUState {
 134     SysBusDevice parent_obj;
 135
 136     MemoryRegion iomem;
 137     uint32_t regs[IOMMU_NREGS];
 138     hwaddr iostart;
 139     qemu_irq irq;
 140     uint32_t version;
 141 } IOMMUState;
 142
 143 static uint64_t iommu_mem_read(void *opaque, hwaddr addr,
 144                                unsigned size)
 145 {
 146     IOMMUState *s = opaque;
 147     hwaddr saddr;
 148     uint32_t ret;
 149
 150     saddr = addr >> 2;
 151     switch (saddr) {
 152     default:
 153         ret = s->regs[saddr];
 154         break;
 155     case IOMMU_AFAR:
 156     case IOMMU_AFSR:
 157         ret = s->regs[saddr];
 158         qemu_irq_lower(s->irq);
 159         break;
 160     }
 161     trace_sun4m_iommu_mem_readl(saddr, ret);
 162     return ret;
 163 }
 164
 165 static void iommu_mem_write(void *opaque, hwaddr addr,
 166                             uint64_t val, unsigned size)
 167 {
 168     IOMMUState *s = opaque;
 169     hwaddr saddr;
 170
 171     saddr = addr >> 2;
 172     trace_sun4m_iommu_mem_writel(saddr, val);
 173     switch (saddr) {
 174     case IOMMU_CTRL:
 175         switch (val & IOMMU_CTRL_RNGE) {
 176         case IOMMU_RNGE_16MB:
 177             s->iostart = 0xffffffffff000000ULL;
 178             break;
 179         case IOMMU_RNGE_32MB:
 180             s->iostart = 0xfffffffffe000000ULL;
 181             break;
 182         case IOMMU_RNGE_64MB:
 183             s->iostart = 0xfffffffffc000000ULL;
 184             break;
 185         case IOMMU_RNGE_128MB:
 186             s->iostart = 0xfffffffff8000000ULL;
 187             break;
 188         case IOMMU_RNGE_256MB:
 189             s->iostart = 0xfffffffff0000000ULL;
 190             break;
 191         case IOMMU_RNGE_512MB:
 192             s->iostart = 0xffffffffe0000000ULL;
 193             break;
 194         case IOMMU_RNGE_1GB:
 195             s->iostart = 0xffffffffc0000000ULL;
 196             break;
 197         default:
 198         case IOMMU_RNGE_2GB:
 199             s->iostart = 0xffffffff80000000ULL;
 200             break;
 201         }
 202         trace_sun4m_iommu_mem_writel_ctrl(s->iostart);
 203         s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | s->version);
 204         break;
 205     case IOMMU_BASE:
 206         s->regs[saddr] = val & IOMMU_BASE_MASK;
 207         break;
 208     case IOMMU_TLBFLUSH:
 209         trace_sun4m_iommu_mem_writel_tlbflush(val);
 210         s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
 211         break;
 212     case IOMMU_PGFLUSH:
 213         trace_sun4m_iommu_mem_writel_pgflush(val);
 214         s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
 215         break;
 216     case IOMMU_AFAR:
 217         s->regs[saddr] = val;
 218         qemu_irq_lower(s->irq);
 219         break;
 220     case IOMMU_AER:
 221         s->regs[saddr] = (val & IOMMU_AER_MASK) | IOMMU_AER_EN_P0_ARB;
 222         break;
 223     case IOMMU_AFSR:
 224         s->regs[saddr] = (val & IOMMU_AFSR_MASK) | IOMMU_AFSR_RESV;
 225         qemu_irq_lower(s->irq);
 226         break;
 227     case IOMMU_SBCFG0:
 228     case IOMMU_SBCFG1:
 229     case IOMMU_SBCFG2:
 230     case IOMMU_SBCFG3:
 231         s->regs[saddr] = val & IOMMU_SBCFG_MASK;
 232         break;
 233     case IOMMU_ARBEN:
 234         // XXX implement SBus probing: fault when reading unmapped
 235         // addresses, fault cause and address stored to MMU/IOMMU
 236         s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID;
 237         break;
 238     case IOMMU_MASK_ID:
 239         s->regs[saddr] |= val & IOMMU_MASK_ID_MASK;
 240         break;
 241     default:
 242         s->regs[saddr] = val;
 243         break;
 244     }
 245 }
 246
 247 static const MemoryRegionOps iommu_mem_ops = {
 248     .read = iommu_mem_read,
 249     .write = iommu_mem_write,
 250     .endianness = DEVICE_NATIVE_ENDIAN,
 251     .valid = {
 252         .min_access_size = 4,
 253         .max_access_size = 4,
 254     },
 255 };
 256
 257 static uint32_t iommu_page_get_flags(IOMMUState *s, hwaddr addr)
 258 {
 259     uint32_t ret;
 260     hwaddr iopte;
 261     hwaddr pa = addr;
 262
 263     iopte = s->regs[IOMMU_BASE] << 4;
 264     addr &= ~s->iostart;
 265     iopte += (addr >> (IOMMU_PAGE_SHIFT - 2)) & ~3;
 266     ret = ldl_be_phys(&address_space_memory, iopte);
 267     trace_sun4m_iommu_page_get_flags(pa, iopte, ret);
 268     return ret;
 269 }
 270
 271 static hwaddr iommu_translate_pa(hwaddr addr,
 272                                              uint32_t pte)
 273 {
 274     hwaddr pa;
 275
 276     pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK);
 277     trace_sun4m_iommu_translate_pa(addr, pa, pte);
 278     return pa;
 279 }
 280
 281 static void iommu_bad_addr(IOMMUState *s, hwaddr addr,
 282                            int is_write)
 283 {
 284     trace_sun4m_iommu_bad_addr(addr);
 285     s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | IOMMU_AFSR_RESV |
 286         IOMMU_AFSR_FAV;
 287     if (!is_write)
 288         s->regs[IOMMU_AFSR] |= IOMMU_AFSR_RD;
 289     s->regs[IOMMU_AFAR] = addr;
 290     qemu_irq_raise(s->irq);
 291 }
 292
 293 void sparc_iommu_memory_rw(void *opaque, hwaddr addr,
 294                            uint8_t *buf, int len, int is_write)
 295 {
 296     int l;
 297     uint32_t flags;
 298     hwaddr page, phys_addr;
 299
 300     while (len > 0) {
 301         page = addr & IOMMU_PAGE_MASK;
 302         l = (page + IOMMU_PAGE_SIZE) - addr;
 303         if (l > len)
 304             l = len;
 305         flags = iommu_page_get_flags(opaque, page);
 306         if (!(flags & IOPTE_VALID)) {
 307             iommu_bad_addr(opaque, page, is_write);
 308             return;
 309         }
 310         phys_addr = iommu_translate_pa(addr, flags);
 311         if (is_write) {
 312             if (!(flags & IOPTE_WRITE)) {
 313                 iommu_bad_addr(opaque, page, is_write);
 314                 return;
 315             }
 316             cpu_physical_memory_write(phys_addr, buf, l);
 317         } else {
 318             cpu_physical_memory_read(phys_addr, buf, l);
 319         }
 320         len -= l;
 321         buf += l;
 322         addr += l;
 323     }
 324 }
 325
 326 static const VMStateDescription vmstate_iommu = {
 327     .name ="iommu",
 328     .version_id = 2,
 329     .minimum_version_id = 2,
 330     .fields = (VMStateField[]) {
 331         VMSTATE_UINT32_ARRAY(regs, IOMMUState, IOMMU_NREGS),
 332         VMSTATE_UINT64(iostart, IOMMUState),
 333         VMSTATE_END_OF_LIST()
 334     }
 335 };
 336
 337 static void iommu_reset(DeviceState *d)
 338 {
 339     IOMMUState *s = SUN4M_IOMMU(d);
 340
 341     memset(s->regs, 0, IOMMU_NREGS * 4);
 342     s->iostart = 0;
 343     s->regs[IOMMU_CTRL] = s->version;
 344     s->regs[IOMMU_ARBEN] = IOMMU_MID;
 345     s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV;
 346     s->regs[IOMMU_AER] = IOMMU_AER_EN_P0_ARB | IOMMU_AER_EN_P1_ARB;
 347     s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK;
 348 }
 349
 350 static int iommu_init1(SysBusDevice *dev)
 351 {
 352     IOMMUState *s = SUN4M_IOMMU(dev);
 353
 354     sysbus_init_irq(dev, &s->irq);
 355
 356     memory_region_init_io(&s->iomem, OBJECT(s), &iommu_mem_ops, s, "iommu",
 357                           IOMMU_NREGS * sizeof(uint32_t));
 358     sysbus_init_mmio(dev, &s->iomem);
 359
 360     return 0;
 361 }
 362
 363 static Property iommu_properties[] = {
 364     DEFINE_PROP_UINT32("version", IOMMUState, version, 0),
 365     DEFINE_PROP_END_OF_LIST(),
 366 };
 367
 368 static void iommu_class_init(ObjectClass *klass, void *data)
 369 {
 370     DeviceClass *dc = DEVICE_CLASS(klass);
 371     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 372
 373     k->init = iommu_init1;
 374     dc->reset = iommu_reset;
 375     dc->vmsd = &vmstate_iommu;
 376     dc->props = iommu_properties;
 377 }
 378
 379 static const TypeInfo iommu_info = {
 380     .name          = TYPE_SUN4M_IOMMU,
 381     .parent        = TYPE_SYS_BUS_DEVICE,
 382     .instance_size = sizeof(IOMMUState),
 383     .class_init    = iommu_class_init,
 384 };
 385
 386 static void iommu_register_types(void)
 387 {
 388     type_register_static(&iommu_info);
 389 }
 390
 391 type_init(iommu_register_types)