hw/arm/strongarm.c

   1 /*
   2  * StrongARM SA-1100/SA-1110 emulation
   3  *
   4  * Copyright (C) 2011 Dmitry Eremin-Solenikov
   5  *
   6  * Largely based on StrongARM emulation:
   7  * Copyright (c) 2006 Openedhand Ltd.
   8  * Written by Andrzej Zaborowski <balrog@zabor.org>
   9  *
  10  * UART code based on QEMU 16550A UART emulation
  11  * Copyright (c) 2003-2004 Fabrice Bellard
  12  * Copyright (c) 2008 Citrix Systems, Inc.
  13  *
  14  *  This program is free software; you can redistribute it and/or modify
  15  *  it under the terms of the GNU General Public License version 2 as
  16  *  published by the Free Software Foundation.
  17  *
  18  *  This program is distributed in the hope that it will be useful,
  19  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  *  GNU General Public License for more details.
  22  *
  23  *  You should have received a copy of the GNU General Public License along
  24  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  25  *
  26  *  Contributions after 2012-01-13 are licensed under the terms of the
  27  *  GNU GPL, version 2 or (at your option) any later version.
  28  */
  29
  30 #include "qemu/osdep.h"
  31 #include "cpu.h"
  32 #include "hw/boards.h"
  33 #include "hw/sysbus.h"
  34 #include "strongarm.h"
  35 #include "qemu/error-report.h"
  36 #include "hw/arm/arm.h"
  37 #include "sysemu/char.h"
  38 #include "sysemu/sysemu.h"
  39 #include "hw/ssi/ssi.h"
  40 #include "qemu/cutils.h"
  41 #include "qemu/log.h"
  42
  43 //#define DEBUG
  44
  45 /*
  46  TODO
  47  - Implement cp15, c14 ?
  48  - Implement cp15, c15 !!! (idle used in L)
  49  - Implement idle mode handling/DIM
  50  - Implement sleep mode/Wake sources
  51  - Implement reset control
  52  - Implement memory control regs
  53  - PCMCIA handling
  54  - Maybe support MBGNT/MBREQ
  55  - DMA channels
  56  - GPCLK
  57  - IrDA
  58  - MCP
  59  - Enhance UART with modem signals
  60  */
  61
  62 #ifdef DEBUG
  63 # define DPRINTF(format, ...) printf(format , ## __VA_ARGS__)
  64 #else
  65 # define DPRINTF(format, ...) do { } while (0)
  66 #endif
  67
  68 static struct {
  69     hwaddr io_base;
  70     int irq;
  71 } sa_serial[] = {
  72     { 0x80010000, SA_PIC_UART1 },
  73     { 0x80030000, SA_PIC_UART2 },
  74     { 0x80050000, SA_PIC_UART3 },
  75     { 0, 0 }
  76 };
  77
  78 /* Interrupt Controller */
  79
  80 #define TYPE_STRONGARM_PIC "strongarm_pic"
  81 #define STRONGARM_PIC(obj) \
  82     OBJECT_CHECK(StrongARMPICState, (obj), TYPE_STRONGARM_PIC)
  83
  84 typedef struct StrongARMPICState {
  85     SysBusDevice parent_obj;
  86
  87     MemoryRegion iomem;
  88     qemu_irq    irq;
  89     qemu_irq    fiq;
  90
  91     uint32_t pending;
  92     uint32_t enabled;
  93     uint32_t is_fiq;
  94     uint32_t int_idle;
  95 } StrongARMPICState;
  96
  97 #define ICIP    0x00
  98 #define ICMR    0x04
  99 #define ICLR    0x08
 100 #define ICFP    0x10
 101 #define ICPR    0x20
 102 #define ICCR    0x0c
 103
 104 #define SA_PIC_SRCS     32
 105
 106
 107 static void strongarm_pic_update(void *opaque)
 108 {
 109     StrongARMPICState *s = opaque;
 110
 111     /* FIXME: reflect DIM */
 112     qemu_set_irq(s->fiq, s->pending & s->enabled &  s->is_fiq);
 113     qemu_set_irq(s->irq, s->pending & s->enabled & ~s->is_fiq);
 114 }
 115
 116 static void strongarm_pic_set_irq(void *opaque, int irq, int level)
 117 {
 118     StrongARMPICState *s = opaque;
 119
 120     if (level) {
 121         s->pending |= 1 << irq;
 122     } else {
 123         s->pending &= ~(1 << irq);
 124     }
 125
 126     strongarm_pic_update(s);
 127 }
 128
 129 static uint64_t strongarm_pic_mem_read(void *opaque, hwaddr offset,
 130                                        unsigned size)
 131 {
 132     StrongARMPICState *s = opaque;
 133
 134     switch (offset) {
 135     case ICIP:
 136         return s->pending & ~s->is_fiq & s->enabled;
 137     case ICMR:
 138         return s->enabled;
 139     case ICLR:
 140         return s->is_fiq;
 141     case ICCR:
 142         return s->int_idle == 0;
 143     case ICFP:
 144         return s->pending & s->is_fiq & s->enabled;
 145     case ICPR:
 146         return s->pending;
 147     default:
 148         printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n",
 149                         __func__, offset);
 150         return 0;
 151     }
 152 }
 153
 154 static void strongarm_pic_mem_write(void *opaque, hwaddr offset,
 155                                     uint64_t value, unsigned size)
 156 {
 157     StrongARMPICState *s = opaque;
 158
 159     switch (offset) {
 160     case ICMR:
 161         s->enabled = value;
 162         break;
 163     case ICLR:
 164         s->is_fiq = value;
 165         break;
 166     case ICCR:
 167         s->int_idle = (value & 1) ? 0 : ~0;
 168         break;
 169     default:
 170         printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n",
 171                         __func__, offset);
 172         break;
 173     }
 174     strongarm_pic_update(s);
 175 }
 176
 177 static const MemoryRegionOps strongarm_pic_ops = {
 178     .read = strongarm_pic_mem_read,
 179     .write = strongarm_pic_mem_write,
 180     .endianness = DEVICE_NATIVE_ENDIAN,
 181 };
 182
 183 static void strongarm_pic_initfn(Object *obj)
 184 {
 185     DeviceState *dev = DEVICE(obj);
 186     StrongARMPICState *s = STRONGARM_PIC(obj);
 187     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 188
 189     qdev_init_gpio_in(dev, strongarm_pic_set_irq, SA_PIC_SRCS);
 190     memory_region_init_io(&s->iomem, obj, &strongarm_pic_ops, s,
 191                           "pic", 0x1000);
 192     sysbus_init_mmio(sbd, &s->iomem);
 193     sysbus_init_irq(sbd, &s->irq);
 194     sysbus_init_irq(sbd, &s->fiq);
 195 }
 196
 197 static int strongarm_pic_post_load(void *opaque, int version_id)
 198 {
 199     strongarm_pic_update(opaque);
 200     return 0;
 201 }
 202
 203 static VMStateDescription vmstate_strongarm_pic_regs = {
 204     .name = "strongarm_pic",
 205     .version_id = 0,
 206     .minimum_version_id = 0,
 207     .post_load = strongarm_pic_post_load,
 208     .fields = (VMStateField[]) {
 209         VMSTATE_UINT32(pending, StrongARMPICState),
 210         VMSTATE_UINT32(enabled, StrongARMPICState),
 211         VMSTATE_UINT32(is_fiq, StrongARMPICState),
 212         VMSTATE_UINT32(int_idle, StrongARMPICState),
 213         VMSTATE_END_OF_LIST(),
 214     },
 215 };
 216
 217 static void strongarm_pic_class_init(ObjectClass *klass, void *data)
 218 {
 219     DeviceClass *dc = DEVICE_CLASS(klass);
 220
 221     dc->desc = "StrongARM PIC";
 222     dc->vmsd = &vmstate_strongarm_pic_regs;
 223 }
 224
 225 static const TypeInfo strongarm_pic_info = {
 226     .name          = TYPE_STRONGARM_PIC,
 227     .parent        = TYPE_SYS_BUS_DEVICE,
 228     .instance_size = sizeof(StrongARMPICState),
 229     .instance_init = strongarm_pic_initfn,
 230     .class_init    = strongarm_pic_class_init,
 231 };
 232
 233 /* Real-Time Clock */
 234 #define RTAR 0x00 /* RTC Alarm register */
 235 #define RCNR 0x04 /* RTC Counter register */
 236 #define RTTR 0x08 /* RTC Timer Trim register */
 237 #define RTSR 0x10 /* RTC Status register */
 238
 239 #define RTSR_AL (1 << 0) /* RTC Alarm detected */
 240 #define RTSR_HZ (1 << 1) /* RTC 1Hz detected */
 241 #define RTSR_ALE (1 << 2) /* RTC Alarm enable */
 242 #define RTSR_HZE (1 << 3) /* RTC 1Hz enable */
 243
 244 /* 16 LSB of RTTR are clockdiv for internal trim logic,
 245  * trim delete isn't emulated, so
 246  * f = 32 768 / (RTTR_trim + 1) */
 247
 248 #define TYPE_STRONGARM_RTC "strongarm-rtc"
 249 #define STRONGARM_RTC(obj) \
 250     OBJECT_CHECK(StrongARMRTCState, (obj), TYPE_STRONGARM_RTC)
 251
 252 typedef struct StrongARMRTCState {
 253     SysBusDevice parent_obj;
 254
 255     MemoryRegion iomem;
 256     uint32_t rttr;
 257     uint32_t rtsr;
 258     uint32_t rtar;
 259     uint32_t last_rcnr;
 260     int64_t last_hz;
 261     QEMUTimer *rtc_alarm;
 262     QEMUTimer *rtc_hz;
 263     qemu_irq rtc_irq;
 264     qemu_irq rtc_hz_irq;
 265 } StrongARMRTCState;
 266
 267 static inline void strongarm_rtc_int_update(StrongARMRTCState *s)
 268 {
 269     qemu_set_irq(s->rtc_irq, s->rtsr & RTSR_AL);
 270     qemu_set_irq(s->rtc_hz_irq, s->rtsr & RTSR_HZ);
 271 }
 272
 273 static void strongarm_rtc_hzupdate(StrongARMRTCState *s)
 274 {
 275     int64_t rt = qemu_clock_get_ms(rtc_clock);
 276     s->last_rcnr += ((rt - s->last_hz) << 15) /
 277             (1000 * ((s->rttr & 0xffff) + 1));
 278     s->last_hz = rt;
 279 }
 280
 281 static inline void strongarm_rtc_timer_update(StrongARMRTCState *s)
 282 {
 283     if ((s->rtsr & RTSR_HZE) && !(s->rtsr & RTSR_HZ)) {
 284         timer_mod(s->rtc_hz, s->last_hz + 1000);
 285     } else {
 286         timer_del(s->rtc_hz);
 287     }
 288
 289     if ((s->rtsr & RTSR_ALE) && !(s->rtsr & RTSR_AL)) {
 290         timer_mod(s->rtc_alarm, s->last_hz +
 291                 (((s->rtar - s->last_rcnr) * 1000 *
 292                   ((s->rttr & 0xffff) + 1)) >> 15));
 293     } else {
 294         timer_del(s->rtc_alarm);
 295     }
 296 }
 297
 298 static inline void strongarm_rtc_alarm_tick(void *opaque)
 299 {
 300     StrongARMRTCState *s = opaque;
 301     s->rtsr |= RTSR_AL;
 302     strongarm_rtc_timer_update(s);
 303     strongarm_rtc_int_update(s);
 304 }
 305
 306 static inline void strongarm_rtc_hz_tick(void *opaque)
 307 {
 308     StrongARMRTCState *s = opaque;
 309     s->rtsr |= RTSR_HZ;
 310     strongarm_rtc_timer_update(s);
 311     strongarm_rtc_int_update(s);
 312 }
 313
 314 static uint64_t strongarm_rtc_read(void *opaque, hwaddr addr,
 315                                    unsigned size)
 316 {
 317     StrongARMRTCState *s = opaque;
 318
 319     switch (addr) {
 320     case RTTR:
 321         return s->rttr;
 322     case RTSR:
 323         return s->rtsr;
 324     case RTAR:
 325         return s->rtar;
 326     case RCNR:
 327         return s->last_rcnr +
 328                 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) /
 329                 (1000 * ((s->rttr & 0xffff) + 1));
 330     default:
 331         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
 332         return 0;
 333     }
 334 }
 335
 336 static void strongarm_rtc_write(void *opaque, hwaddr addr,
 337                                 uint64_t value, unsigned size)
 338 {
 339     StrongARMRTCState *s = opaque;
 340     uint32_t old_rtsr;
 341
 342     switch (addr) {
 343     case RTTR:
 344         strongarm_rtc_hzupdate(s);
 345         s->rttr = value;
 346         strongarm_rtc_timer_update(s);
 347         break;
 348
 349     case RTSR:
 350         old_rtsr = s->rtsr;
 351         s->rtsr = (value & (RTSR_ALE | RTSR_HZE)) |
 352                   (s->rtsr & ~(value & (RTSR_AL | RTSR_HZ)));
 353
 354         if (s->rtsr != old_rtsr) {
 355             strongarm_rtc_timer_update(s);
 356         }
 357
 358         strongarm_rtc_int_update(s);
 359         break;
 360
 361     case RTAR:
 362         s->rtar = value;
 363         strongarm_rtc_timer_update(s);
 364         break;
 365
 366     case RCNR:
 367         strongarm_rtc_hzupdate(s);
 368         s->last_rcnr = value;
 369         strongarm_rtc_timer_update(s);
 370         break;
 371
 372     default:
 373         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
 374     }
 375 }
 376
 377 static const MemoryRegionOps strongarm_rtc_ops = {
 378     .read = strongarm_rtc_read,
 379     .write = strongarm_rtc_write,
 380     .endianness = DEVICE_NATIVE_ENDIAN,
 381 };
 382
 383 static void strongarm_rtc_init(Object *obj)
 384 {
 385     StrongARMRTCState *s = STRONGARM_RTC(obj);
 386     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 387     struct tm tm;
 388
 389     s->rttr = 0x0;
 390     s->rtsr = 0;
 391
 392     qemu_get_timedate(&tm, 0);
 393
 394     s->last_rcnr = (uint32_t) mktimegm(&tm);
 395     s->last_hz = qemu_clock_get_ms(rtc_clock);
 396
 397     s->rtc_alarm = timer_new_ms(rtc_clock, strongarm_rtc_alarm_tick, s);
 398     s->rtc_hz = timer_new_ms(rtc_clock, strongarm_rtc_hz_tick, s);
 399
 400     sysbus_init_irq(dev, &s->rtc_irq);
 401     sysbus_init_irq(dev, &s->rtc_hz_irq);
 402
 403     memory_region_init_io(&s->iomem, obj, &strongarm_rtc_ops, s,
 404                           "rtc", 0x10000);
 405     sysbus_init_mmio(dev, &s->iomem);
 406 }
 407
 408 static void strongarm_rtc_pre_save(void *opaque)
 409 {
 410     StrongARMRTCState *s = opaque;
 411
 412     strongarm_rtc_hzupdate(s);
 413 }
 414
 415 static int strongarm_rtc_post_load(void *opaque, int version_id)
 416 {
 417     StrongARMRTCState *s = opaque;
 418
 419     strongarm_rtc_timer_update(s);
 420     strongarm_rtc_int_update(s);
 421
 422     return 0;
 423 }
 424
 425 static const VMStateDescription vmstate_strongarm_rtc_regs = {
 426     .name = "strongarm-rtc",
 427     .version_id = 0,
 428     .minimum_version_id = 0,
 429     .pre_save = strongarm_rtc_pre_save,
 430     .post_load = strongarm_rtc_post_load,
 431     .fields = (VMStateField[]) {
 432         VMSTATE_UINT32(rttr, StrongARMRTCState),
 433         VMSTATE_UINT32(rtsr, StrongARMRTCState),
 434         VMSTATE_UINT32(rtar, StrongARMRTCState),
 435         VMSTATE_UINT32(last_rcnr, StrongARMRTCState),
 436         VMSTATE_INT64(last_hz, StrongARMRTCState),
 437         VMSTATE_END_OF_LIST(),
 438     },
 439 };
 440
 441 static void strongarm_rtc_sysbus_class_init(ObjectClass *klass, void *data)
 442 {
 443     DeviceClass *dc = DEVICE_CLASS(klass);
 444
 445     dc->desc = "StrongARM RTC Controller";
 446     dc->vmsd = &vmstate_strongarm_rtc_regs;
 447 }
 448
 449 static const TypeInfo strongarm_rtc_sysbus_info = {
 450     .name          = TYPE_STRONGARM_RTC,
 451     .parent        = TYPE_SYS_BUS_DEVICE,
 452     .instance_size = sizeof(StrongARMRTCState),
 453     .instance_init = strongarm_rtc_init,
 454     .class_init    = strongarm_rtc_sysbus_class_init,
 455 };
 456
 457 /* GPIO */
 458 #define GPLR 0x00
 459 #define GPDR 0x04
 460 #define GPSR 0x08
 461 #define GPCR 0x0c
 462 #define GRER 0x10
 463 #define GFER 0x14
 464 #define GEDR 0x18
 465 #define GAFR 0x1c
 466
 467 #define TYPE_STRONGARM_GPIO "strongarm-gpio"
 468 #define STRONGARM_GPIO(obj) \
 469     OBJECT_CHECK(StrongARMGPIOInfo, (obj), TYPE_STRONGARM_GPIO)
 470
 471 typedef struct StrongARMGPIOInfo StrongARMGPIOInfo;
 472 struct StrongARMGPIOInfo {
 473     SysBusDevice busdev;
 474     MemoryRegion iomem;
 475     qemu_irq handler[28];
 476     qemu_irq irqs[11];
 477     qemu_irq irqX;
 478
 479     uint32_t ilevel;
 480     uint32_t olevel;
 481     uint32_t dir;
 482     uint32_t rising;
 483     uint32_t falling;
 484     uint32_t status;
 485     uint32_t gafr;
 486
 487     uint32_t prev_level;
 488 };
 489
 490
 491 static void strongarm_gpio_irq_update(StrongARMGPIOInfo *s)
 492 {
 493     int i;
 494     for (i = 0; i < 11; i++) {
 495         qemu_set_irq(s->irqs[i], s->status & (1 << i));
 496     }
 497
 498     qemu_set_irq(s->irqX, (s->status & ~0x7ff));
 499 }
 500
 501 static void strongarm_gpio_set(void *opaque, int line, int level)
 502 {
 503     StrongARMGPIOInfo *s = opaque;
 504     uint32_t mask;
 505
 506     mask = 1 << line;
 507
 508     if (level) {
 509         s->status |= s->rising & mask &
 510                 ~s->ilevel & ~s->dir;
 511         s->ilevel |= mask;
 512     } else {
 513         s->status |= s->falling & mask &
 514                 s->ilevel & ~s->dir;
 515         s->ilevel &= ~mask;
 516     }
 517
 518     if (s->status & mask) {
 519         strongarm_gpio_irq_update(s);
 520     }
 521 }
 522
 523 static void strongarm_gpio_handler_update(StrongARMGPIOInfo *s)
 524 {
 525     uint32_t level, diff;
 526     int bit;
 527
 528     level = s->olevel & s->dir;
 529
 530     for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
 531         bit = ctz32(diff);
 532         qemu_set_irq(s->handler[bit], (level >> bit) & 1);
 533     }
 534
 535     s->prev_level = level;
 536 }
 537
 538 static uint64_t strongarm_gpio_read(void *opaque, hwaddr offset,
 539                                     unsigned size)
 540 {
 541     StrongARMGPIOInfo *s = opaque;
 542
 543     switch (offset) {
 544     case GPDR:        /* GPIO Pin-Direction registers */
 545         return s->dir;
 546
 547     case GPSR:        /* GPIO Pin-Output Set registers */
 548         qemu_log_mask(LOG_GUEST_ERROR,
 549                       "strongarm GPIO: read from write only register GPSR\n");
 550         return 0;
 551
 552     case GPCR:        /* GPIO Pin-Output Clear registers */
 553         qemu_log_mask(LOG_GUEST_ERROR,
 554                       "strongarm GPIO: read from write only register GPCR\n");
 555         return 0;
 556
 557     case GRER:        /* GPIO Rising-Edge Detect Enable registers */
 558         return s->rising;
 559
 560     case GFER:        /* GPIO Falling-Edge Detect Enable registers */
 561         return s->falling;
 562
 563     case GAFR:        /* GPIO Alternate Function registers */
 564         return s->gafr;
 565
 566     case GPLR:        /* GPIO Pin-Level registers */
 567         return (s->olevel & s->dir) |
 568                (s->ilevel & ~s->dir);
 569
 570     case GEDR:        /* GPIO Edge Detect Status registers */
 571         return s->status;
 572
 573     default:
 574         printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
 575     }
 576
 577     return 0;
 578 }
 579
 580 static void strongarm_gpio_write(void *opaque, hwaddr offset,
 581                                  uint64_t value, unsigned size)
 582 {
 583     StrongARMGPIOInfo *s = opaque;
 584
 585     switch (offset) {
 586     case GPDR:        /* GPIO Pin-Direction registers */
 587         s->dir = value;
 588         strongarm_gpio_handler_update(s);
 589         break;
 590
 591     case GPSR:        /* GPIO Pin-Output Set registers */
 592         s->olevel |= value;
 593         strongarm_gpio_handler_update(s);
 594         break;
 595
 596     case GPCR:        /* GPIO Pin-Output Clear registers */
 597         s->olevel &= ~value;
 598         strongarm_gpio_handler_update(s);
 599         break;
 600
 601     case GRER:        /* GPIO Rising-Edge Detect Enable registers */
 602         s->rising = value;
 603         break;
 604
 605     case GFER:        /* GPIO Falling-Edge Detect Enable registers */
 606         s->falling = value;
 607         break;
 608
 609     case GAFR:        /* GPIO Alternate Function registers */
 610         s->gafr = value;
 611         break;
 612
 613     case GEDR:        /* GPIO Edge Detect Status registers */
 614         s->status &= ~value;
 615         strongarm_gpio_irq_update(s);
 616         break;
 617
 618     default:
 619         printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
 620     }
 621 }
 622
 623 static const MemoryRegionOps strongarm_gpio_ops = {
 624     .read = strongarm_gpio_read,
 625     .write = strongarm_gpio_write,
 626     .endianness = DEVICE_NATIVE_ENDIAN,
 627 };
 628
 629 static DeviceState *strongarm_gpio_init(hwaddr base,
 630                 DeviceState *pic)
 631 {
 632     DeviceState *dev;
 633     int i;
 634
 635     dev = qdev_create(NULL, TYPE_STRONGARM_GPIO);
 636     qdev_init_nofail(dev);
 637
 638     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
 639     for (i = 0; i < 12; i++)
 640         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
 641                     qdev_get_gpio_in(pic, SA_PIC_GPIO0_EDGE + i));
 642
 643     return dev;
 644 }
 645
 646 static void strongarm_gpio_initfn(Object *obj)
 647 {
 648     DeviceState *dev = DEVICE(obj);
 649     StrongARMGPIOInfo *s = STRONGARM_GPIO(obj);
 650     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 651     int i;
 652
 653     qdev_init_gpio_in(dev, strongarm_gpio_set, 28);
 654     qdev_init_gpio_out(dev, s->handler, 28);
 655
 656     memory_region_init_io(&s->iomem, obj, &strongarm_gpio_ops, s,
 657                           "gpio", 0x1000);
 658
 659     sysbus_init_mmio(sbd, &s->iomem);
 660     for (i = 0; i < 11; i++) {
 661         sysbus_init_irq(sbd, &s->irqs[i]);
 662     }
 663     sysbus_init_irq(sbd, &s->irqX);
 664 }
 665
 666 static const VMStateDescription vmstate_strongarm_gpio_regs = {
 667     .name = "strongarm-gpio",
 668     .version_id = 0,
 669     .minimum_version_id = 0,
 670     .fields = (VMStateField[]) {
 671         VMSTATE_UINT32(ilevel, StrongARMGPIOInfo),
 672         VMSTATE_UINT32(olevel, StrongARMGPIOInfo),
 673         VMSTATE_UINT32(dir, StrongARMGPIOInfo),
 674         VMSTATE_UINT32(rising, StrongARMGPIOInfo),
 675         VMSTATE_UINT32(falling, StrongARMGPIOInfo),
 676         VMSTATE_UINT32(status, StrongARMGPIOInfo),
 677         VMSTATE_UINT32(gafr, StrongARMGPIOInfo),
 678         VMSTATE_UINT32(prev_level, StrongARMGPIOInfo),
 679         VMSTATE_END_OF_LIST(),
 680     },
 681 };
 682
 683 static void strongarm_gpio_class_init(ObjectClass *klass, void *data)
 684 {
 685     DeviceClass *dc = DEVICE_CLASS(klass);
 686
 687     dc->desc = "StrongARM GPIO controller";
 688     dc->vmsd = &vmstate_strongarm_gpio_regs;
 689 }
 690
 691 static const TypeInfo strongarm_gpio_info = {
 692     .name          = TYPE_STRONGARM_GPIO,
 693     .parent        = TYPE_SYS_BUS_DEVICE,
 694     .instance_size = sizeof(StrongARMGPIOInfo),
 695     .instance_init = strongarm_gpio_initfn,
 696     .class_init    = strongarm_gpio_class_init,
 697 };
 698
 699 /* Peripheral Pin Controller */
 700 #define PPDR 0x00
 701 #define PPSR 0x04
 702 #define PPAR 0x08
 703 #define PSDR 0x0c
 704 #define PPFR 0x10
 705
 706 #define TYPE_STRONGARM_PPC "strongarm-ppc"
 707 #define STRONGARM_PPC(obj) \
 708     OBJECT_CHECK(StrongARMPPCInfo, (obj), TYPE_STRONGARM_PPC)
 709
 710 typedef struct StrongARMPPCInfo StrongARMPPCInfo;
 711 struct StrongARMPPCInfo {
 712     SysBusDevice parent_obj;
 713
 714     MemoryRegion iomem;
 715     qemu_irq handler[28];
 716
 717     uint32_t ilevel;
 718     uint32_t olevel;
 719     uint32_t dir;
 720     uint32_t ppar;
 721     uint32_t psdr;
 722     uint32_t ppfr;
 723
 724     uint32_t prev_level;
 725 };
 726
 727 static void strongarm_ppc_set(void *opaque, int line, int level)
 728 {
 729     StrongARMPPCInfo *s = opaque;
 730
 731     if (level) {
 732         s->ilevel |= 1 << line;
 733     } else {
 734         s->ilevel &= ~(1 << line);
 735     }
 736 }
 737
 738 static void strongarm_ppc_handler_update(StrongARMPPCInfo *s)
 739 {
 740     uint32_t level, diff;
 741     int bit;
 742
 743     level = s->olevel & s->dir;
 744
 745     for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
 746         bit = ctz32(diff);
 747         qemu_set_irq(s->handler[bit], (level >> bit) & 1);
 748     }
 749
 750     s->prev_level = level;
 751 }
 752
 753 static uint64_t strongarm_ppc_read(void *opaque, hwaddr offset,
 754                                    unsigned size)
 755 {
 756     StrongARMPPCInfo *s = opaque;
 757
 758     switch (offset) {
 759     case PPDR:        /* PPC Pin Direction registers */
 760         return s->dir | ~0x3fffff;
 761
 762     case PPSR:        /* PPC Pin State registers */
 763         return (s->olevel & s->dir) |
 764                (s->ilevel & ~s->dir) |
 765                ~0x3fffff;
 766
 767     case PPAR:
 768         return s->ppar | ~0x41000;
 769
 770     case PSDR:
 771         return s->psdr;
 772
 773     case PPFR:
 774         return s->ppfr | ~0x7f001;
 775
 776     default:
 777         printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
 778     }
 779
 780     return 0;
 781 }
 782
 783 static void strongarm_ppc_write(void *opaque, hwaddr offset,
 784                                 uint64_t value, unsigned size)
 785 {
 786     StrongARMPPCInfo *s = opaque;
 787
 788     switch (offset) {
 789     case PPDR:        /* PPC Pin Direction registers */
 790         s->dir = value & 0x3fffff;
 791         strongarm_ppc_handler_update(s);
 792         break;
 793
 794     case PPSR:        /* PPC Pin State registers */
 795         s->olevel = value & s->dir & 0x3fffff;
 796         strongarm_ppc_handler_update(s);
 797         break;
 798
 799     case PPAR:
 800         s->ppar = value & 0x41000;
 801         break;
 802
 803     case PSDR:
 804         s->psdr = value & 0x3fffff;
 805         break;
 806
 807     case PPFR:
 808         s->ppfr = value & 0x7f001;
 809         break;
 810
 811     default:
 812         printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
 813     }
 814 }
 815
 816 static const MemoryRegionOps strongarm_ppc_ops = {
 817     .read = strongarm_ppc_read,
 818     .write = strongarm_ppc_write,
 819     .endianness = DEVICE_NATIVE_ENDIAN,
 820 };
 821
 822 static void strongarm_ppc_init(Object *obj)
 823 {
 824     DeviceState *dev = DEVICE(obj);
 825     StrongARMPPCInfo *s = STRONGARM_PPC(obj);
 826     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 827
 828     qdev_init_gpio_in(dev, strongarm_ppc_set, 22);
 829     qdev_init_gpio_out(dev, s->handler, 22);
 830
 831     memory_region_init_io(&s->iomem, obj, &strongarm_ppc_ops, s,
 832                           "ppc", 0x1000);
 833
 834     sysbus_init_mmio(sbd, &s->iomem);
 835 }
 836
 837 static const VMStateDescription vmstate_strongarm_ppc_regs = {
 838     .name = "strongarm-ppc",
 839     .version_id = 0,
 840     .minimum_version_id = 0,
 841     .fields = (VMStateField[]) {
 842         VMSTATE_UINT32(ilevel, StrongARMPPCInfo),
 843         VMSTATE_UINT32(olevel, StrongARMPPCInfo),
 844         VMSTATE_UINT32(dir, StrongARMPPCInfo),
 845         VMSTATE_UINT32(ppar, StrongARMPPCInfo),
 846         VMSTATE_UINT32(psdr, StrongARMPPCInfo),
 847         VMSTATE_UINT32(ppfr, StrongARMPPCInfo),
 848         VMSTATE_UINT32(prev_level, StrongARMPPCInfo),
 849         VMSTATE_END_OF_LIST(),
 850     },
 851 };
 852
 853 static void strongarm_ppc_class_init(ObjectClass *klass, void *data)
 854 {
 855     DeviceClass *dc = DEVICE_CLASS(klass);
 856
 857     dc->desc = "StrongARM PPC controller";
 858     dc->vmsd = &vmstate_strongarm_ppc_regs;
 859 }
 860
 861 static const TypeInfo strongarm_ppc_info = {
 862     .name          = TYPE_STRONGARM_PPC,
 863     .parent        = TYPE_SYS_BUS_DEVICE,
 864     .instance_size = sizeof(StrongARMPPCInfo),
 865     .instance_init = strongarm_ppc_init,
 866     .class_init    = strongarm_ppc_class_init,
 867 };
 868
 869 /* UART Ports */
 870 #define UTCR0 0x00
 871 #define UTCR1 0x04
 872 #define UTCR2 0x08
 873 #define UTCR3 0x0c
 874 #define UTDR  0x14
 875 #define UTSR0 0x1c
 876 #define UTSR1 0x20
 877
 878 #define UTCR0_PE  (1 << 0) /* Parity enable */
 879 #define UTCR0_OES (1 << 1) /* Even parity */
 880 #define UTCR0_SBS (1 << 2) /* 2 stop bits */
 881 #define UTCR0_DSS (1 << 3) /* 8-bit data */
 882
 883 #define UTCR3_RXE (1 << 0) /* Rx enable */
 884 #define UTCR3_TXE (1 << 1) /* Tx enable */
 885 #define UTCR3_BRK (1 << 2) /* Force Break */
 886 #define UTCR3_RIE (1 << 3) /* Rx int enable */
 887 #define UTCR3_TIE (1 << 4) /* Tx int enable */
 888 #define UTCR3_LBM (1 << 5) /* Loopback */
 889
 890 #define UTSR0_TFS (1 << 0) /* Tx FIFO nearly empty */
 891 #define UTSR0_RFS (1 << 1) /* Rx FIFO nearly full */
 892 #define UTSR0_RID (1 << 2) /* Receiver Idle */
 893 #define UTSR0_RBB (1 << 3) /* Receiver begin break */
 894 #define UTSR0_REB (1 << 4) /* Receiver end break */
 895 #define UTSR0_EIF (1 << 5) /* Error in FIFO */
 896
 897 #define UTSR1_RNE (1 << 1) /* Receive FIFO not empty */
 898 #define UTSR1_TNF (1 << 2) /* Transmit FIFO not full */
 899 #define UTSR1_PRE (1 << 3) /* Parity error */
 900 #define UTSR1_FRE (1 << 4) /* Frame error */
 901 #define UTSR1_ROR (1 << 5) /* Receive Over Run */
 902
 903 #define RX_FIFO_PRE (1 << 8)
 904 #define RX_FIFO_FRE (1 << 9)
 905 #define RX_FIFO_ROR (1 << 10)
 906
 907 #define TYPE_STRONGARM_UART "strongarm-uart"
 908 #define STRONGARM_UART(obj) \
 909     OBJECT_CHECK(StrongARMUARTState, (obj), TYPE_STRONGARM_UART)
 910
 911 typedef struct StrongARMUARTState {
 912     SysBusDevice parent_obj;
 913
 914     MemoryRegion iomem;
 915     CharBackend chr;
 916     qemu_irq irq;
 917
 918     uint8_t utcr0;
 919     uint16_t brd;
 920     uint8_t utcr3;
 921     uint8_t utsr0;
 922     uint8_t utsr1;
 923
 924     uint8_t tx_fifo[8];
 925     uint8_t tx_start;
 926     uint8_t tx_len;
 927     uint16_t rx_fifo[12]; /* value + error flags in high bits */
 928     uint8_t rx_start;
 929     uint8_t rx_len;
 930
 931     uint64_t char_transmit_time; /* time to transmit a char in ticks*/
 932     bool wait_break_end;
 933     QEMUTimer *rx_timeout_timer;
 934     QEMUTimer *tx_timer;
 935 } StrongARMUARTState;
 936
 937 static void strongarm_uart_update_status(StrongARMUARTState *s)
 938 {
 939     uint16_t utsr1 = 0;
 940
 941     if (s->tx_len != 8) {
 942         utsr1 |= UTSR1_TNF;
 943     }
 944
 945     if (s->rx_len != 0) {
 946         uint16_t ent = s->rx_fifo[s->rx_start];
 947
 948         utsr1 |= UTSR1_RNE;
 949         if (ent & RX_FIFO_PRE) {
 950             s->utsr1 |= UTSR1_PRE;
 951         }
 952         if (ent & RX_FIFO_FRE) {
 953             s->utsr1 |= UTSR1_FRE;
 954         }
 955         if (ent & RX_FIFO_ROR) {
 956             s->utsr1 |= UTSR1_ROR;
 957         }
 958     }
 959
 960     s->utsr1 = utsr1;
 961 }
 962
 963 static void strongarm_uart_update_int_status(StrongARMUARTState *s)
 964 {
 965     uint16_t utsr0 = s->utsr0 &
 966             (UTSR0_REB | UTSR0_RBB | UTSR0_RID);
 967     int i;
 968
 969     if ((s->utcr3 & UTCR3_TXE) &&
 970                 (s->utcr3 & UTCR3_TIE) &&
 971                 s->tx_len <= 4) {
 972         utsr0 |= UTSR0_TFS;
 973     }
 974
 975     if ((s->utcr3 & UTCR3_RXE) &&
 976                 (s->utcr3 & UTCR3_RIE) &&
 977                 s->rx_len > 4) {
 978         utsr0 |= UTSR0_RFS;
 979     }
 980
 981     for (i = 0; i < s->rx_len && i < 4; i++)
 982         if (s->rx_fifo[(s->rx_start + i) % 12] & ~0xff) {
 983             utsr0 |= UTSR0_EIF;
 984             break;
 985         }
 986
 987     s->utsr0 = utsr0;
 988     qemu_set_irq(s->irq, utsr0);
 989 }
 990
 991 static void strongarm_uart_update_parameters(StrongARMUARTState *s)
 992 {
 993     int speed, parity, data_bits, stop_bits, frame_size;
 994     QEMUSerialSetParams ssp;
 995
 996     /* Start bit. */
 997     frame_size = 1;
 998     if (s->utcr0 & UTCR0_PE) {
 999         /* Parity bit. */
1000         frame_size++;
1001         if (s->utcr0 & UTCR0_OES) {
1002             parity = 'E';
1003         } else {
1004             parity = 'O';
1005         }
1006     } else {
1007             parity = 'N';
1008     }
1009     if (s->utcr0 & UTCR0_SBS) {
1010         stop_bits = 2;
1011     } else {
1012         stop_bits = 1;
1013     }
1014
1015     data_bits = (s->utcr0 & UTCR0_DSS) ? 8 : 7;
1016     frame_size += data_bits + stop_bits;
1017     speed = 3686400 / 16 / (s->brd + 1);
1018     ssp.speed = speed;
1019     ssp.parity = parity;
1020     ssp.data_bits = data_bits;
1021     ssp.stop_bits = stop_bits;
1022     s->char_transmit_time =  (NANOSECONDS_PER_SECOND / speed) * frame_size;
1023     qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
1024
1025     DPRINTF(stderr, "%s speed=%d parity=%c data=%d stop=%d\n", s->chr->label,
1026             speed, parity, data_bits, stop_bits);
1027 }
1028
1029 static void strongarm_uart_rx_to(void *opaque)
1030 {
1031     StrongARMUARTState *s = opaque;
1032
1033     if (s->rx_len) {
1034         s->utsr0 |= UTSR0_RID;
1035         strongarm_uart_update_int_status(s);
1036     }
1037 }
1038
1039 static void strongarm_uart_rx_push(StrongARMUARTState *s, uint16_t c)
1040 {
1041     if ((s->utcr3 & UTCR3_RXE) == 0) {
1042         /* rx disabled */
1043         return;
1044     }
1045
1046     if (s->wait_break_end) {
1047         s->utsr0 |= UTSR0_REB;
1048         s->wait_break_end = false;
1049     }
1050
1051     if (s->rx_len < 12) {
1052         s->rx_fifo[(s->rx_start + s->rx_len) % 12] = c;
1053         s->rx_len++;
1054     } else
1055         s->rx_fifo[(s->rx_start + 11) % 12] |= RX_FIFO_ROR;
1056 }
1057
1058 static int strongarm_uart_can_receive(void *opaque)
1059 {
1060     StrongARMUARTState *s = opaque;
1061
1062     if (s->rx_len == 12) {
1063         return 0;
1064     }
1065     /* It's best not to get more than 2/3 of RX FIFO, so advertise that much */
1066     if (s->rx_len < 8) {
1067         return 8 - s->rx_len;
1068     }
1069     return 1;
1070 }
1071
1072 static void strongarm_uart_receive(void *opaque, const uint8_t *buf, int size)
1073 {
1074     StrongARMUARTState *s = opaque;
1075     int i;
1076
1077     for (i = 0; i < size; i++) {
1078         strongarm_uart_rx_push(s, buf[i]);
1079     }
1080
1081     /* call the timeout receive callback in 3 char transmit time */
1082     timer_mod(s->rx_timeout_timer,
1083                     qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 3);
1084
1085     strongarm_uart_update_status(s);
1086     strongarm_uart_update_int_status(s);
1087 }
1088
1089 static void strongarm_uart_event(void *opaque, int event)
1090 {
1091     StrongARMUARTState *s = opaque;
1092     if (event == CHR_EVENT_BREAK) {
1093         s->utsr0 |= UTSR0_RBB;
1094         strongarm_uart_rx_push(s, RX_FIFO_FRE);
1095         s->wait_break_end = true;
1096         strongarm_uart_update_status(s);
1097         strongarm_uart_update_int_status(s);
1098     }
1099 }
1100
1101 static void strongarm_uart_tx(void *opaque)
1102 {
1103     StrongARMUARTState *s = opaque;
1104     uint64_t new_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1105
1106     if (s->utcr3 & UTCR3_LBM) /* loopback */ {
1107         strongarm_uart_receive(s, &s->tx_fifo[s->tx_start], 1);
1108     } else if (qemu_chr_fe_get_driver(&s->chr)) {
1109         /* XXX this blocks entire thread. Rewrite to use
1110          * qemu_chr_fe_write and background I/O callbacks */
1111         qemu_chr_fe_write_all(&s->chr, &s->tx_fifo[s->tx_start], 1);
1112     }
1113
1114     s->tx_start = (s->tx_start + 1) % 8;
1115     s->tx_len--;
1116     if (s->tx_len) {
1117         timer_mod(s->tx_timer, new_xmit_ts + s->char_transmit_time);
1118     }
1119     strongarm_uart_update_status(s);
1120     strongarm_uart_update_int_status(s);
1121 }
1122
1123 static uint64_t strongarm_uart_read(void *opaque, hwaddr addr,
1124                                     unsigned size)
1125 {
1126     StrongARMUARTState *s = opaque;
1127     uint16_t ret;
1128
1129     switch (addr) {
1130     case UTCR0:
1131         return s->utcr0;
1132
1133     case UTCR1:
1134         return s->brd >> 8;
1135
1136     case UTCR2:
1137         return s->brd & 0xff;
1138
1139     case UTCR3:
1140         return s->utcr3;
1141
1142     case UTDR:
1143         if (s->rx_len != 0) {
1144             ret = s->rx_fifo[s->rx_start];
1145             s->rx_start = (s->rx_start + 1) % 12;
1146             s->rx_len--;
1147             strongarm_uart_update_status(s);
1148             strongarm_uart_update_int_status(s);
1149             return ret;
1150         }
1151         return 0;
1152
1153     case UTSR0:
1154         return s->utsr0;
1155
1156     case UTSR1:
1157         return s->utsr1;
1158
1159     default:
1160         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1161         return 0;
1162     }
1163 }
1164
1165 static void strongarm_uart_write(void *opaque, hwaddr addr,
1166                                  uint64_t value, unsigned size)
1167 {
1168     StrongARMUARTState *s = opaque;
1169
1170     switch (addr) {
1171     case UTCR0:
1172         s->utcr0 = value & 0x7f;
1173         strongarm_uart_update_parameters(s);
1174         break;
1175
1176     case UTCR1:
1177         s->brd = (s->brd & 0xff) | ((value & 0xf) << 8);
1178         strongarm_uart_update_parameters(s);
1179         break;
1180
1181     case UTCR2:
1182         s->brd = (s->brd & 0xf00) | (value & 0xff);
1183         strongarm_uart_update_parameters(s);
1184         break;
1185
1186     case UTCR3:
1187         s->utcr3 = value & 0x3f;
1188         if ((s->utcr3 & UTCR3_RXE) == 0) {
1189             s->rx_len = 0;
1190         }
1191         if ((s->utcr3 & UTCR3_TXE) == 0) {
1192             s->tx_len = 0;
1193         }
1194         strongarm_uart_update_status(s);
1195         strongarm_uart_update_int_status(s);
1196         break;
1197
1198     case UTDR:
1199         if ((s->utcr3 & UTCR3_TXE) && s->tx_len != 8) {
1200             s->tx_fifo[(s->tx_start + s->tx_len) % 8] = value;
1201             s->tx_len++;
1202             strongarm_uart_update_status(s);
1203             strongarm_uart_update_int_status(s);
1204             if (s->tx_len == 1) {
1205                 strongarm_uart_tx(s);
1206             }
1207         }
1208         break;
1209
1210     case UTSR0:
1211         s->utsr0 = s->utsr0 & ~(value &
1212                 (UTSR0_REB | UTSR0_RBB | UTSR0_RID));
1213         strongarm_uart_update_int_status(s);
1214         break;
1215
1216     default:
1217         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1218     }
1219 }
1220
1221 static const MemoryRegionOps strongarm_uart_ops = {
1222     .read = strongarm_uart_read,
1223     .write = strongarm_uart_write,
1224     .endianness = DEVICE_NATIVE_ENDIAN,
1225 };
1226
1227 static void strongarm_uart_init(Object *obj)
1228 {
1229     StrongARMUARTState *s = STRONGARM_UART(obj);
1230     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
1231
1232     memory_region_init_io(&s->iomem, obj, &strongarm_uart_ops, s,
1233                           "uart", 0x10000);
1234     sysbus_init_mmio(dev, &s->iomem);
1235     sysbus_init_irq(dev, &s->irq);
1236
1237     s->rx_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_rx_to, s);
1238     s->tx_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_tx, s);
1239 }
1240
1241 static void strongarm_uart_realize(DeviceState *dev, Error **errp)
1242 {
1243     StrongARMUARTState *s = STRONGARM_UART(dev);
1244
1245     qemu_chr_fe_set_handlers(&s->chr,
1246                              strongarm_uart_can_receive,
1247                              strongarm_uart_receive,
1248                              strongarm_uart_event,
1249                              s, NULL, true);
1250 }
1251
1252 static void strongarm_uart_reset(DeviceState *dev)
1253 {
1254     StrongARMUARTState *s = STRONGARM_UART(dev);
1255
1256     s->utcr0 = UTCR0_DSS; /* 8 data, no parity */
1257     s->brd = 23;    /* 9600 */
1258     /* enable send & recv - this actually violates spec */
1259     s->utcr3 = UTCR3_TXE | UTCR3_RXE;
1260
1261     s->rx_len = s->tx_len = 0;
1262
1263     strongarm_uart_update_parameters(s);
1264     strongarm_uart_update_status(s);
1265     strongarm_uart_update_int_status(s);
1266 }
1267
1268 static int strongarm_uart_post_load(void *opaque, int version_id)
1269 {
1270     StrongARMUARTState *s = opaque;
1271
1272     strongarm_uart_update_parameters(s);
1273     strongarm_uart_update_status(s);
1274     strongarm_uart_update_int_status(s);
1275
1276     /* tx and restart timer */
1277     if (s->tx_len) {
1278         strongarm_uart_tx(s);
1279     }
1280
1281     /* restart rx timeout timer */
1282     if (s->rx_len) {
1283         timer_mod(s->rx_timeout_timer,
1284                 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 3);
1285     }
1286
1287     return 0;
1288 }
1289
1290 static const VMStateDescription vmstate_strongarm_uart_regs = {
1291     .name = "strongarm-uart",
1292     .version_id = 0,
1293     .minimum_version_id = 0,
1294     .post_load = strongarm_uart_post_load,
1295     .fields = (VMStateField[]) {
1296         VMSTATE_UINT8(utcr0, StrongARMUARTState),
1297         VMSTATE_UINT16(brd, StrongARMUARTState),
1298         VMSTATE_UINT8(utcr3, StrongARMUARTState),
1299         VMSTATE_UINT8(utsr0, StrongARMUARTState),
1300         VMSTATE_UINT8_ARRAY(tx_fifo, StrongARMUARTState, 8),
1301         VMSTATE_UINT8(tx_start, StrongARMUARTState),
1302         VMSTATE_UINT8(tx_len, StrongARMUARTState),
1303         VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMUARTState, 12),
1304         VMSTATE_UINT8(rx_start, StrongARMUARTState),
1305         VMSTATE_UINT8(rx_len, StrongARMUARTState),
1306         VMSTATE_BOOL(wait_break_end, StrongARMUARTState),
1307         VMSTATE_END_OF_LIST(),
1308     },
1309 };
1310
1311 static Property strongarm_uart_properties[] = {
1312     DEFINE_PROP_CHR("chardev", StrongARMUARTState, chr),
1313     DEFINE_PROP_END_OF_LIST(),
1314 };
1315
1316 static void strongarm_uart_class_init(ObjectClass *klass, void *data)
1317 {
1318     DeviceClass *dc = DEVICE_CLASS(klass);
1319
1320     dc->desc = "StrongARM UART controller";
1321     dc->reset = strongarm_uart_reset;
1322     dc->vmsd = &vmstate_strongarm_uart_regs;
1323     dc->props = strongarm_uart_properties;
1324     dc->realize = strongarm_uart_realize;
1325 }
1326
1327 static const TypeInfo strongarm_uart_info = {
1328     .name          = TYPE_STRONGARM_UART,
1329     .parent        = TYPE_SYS_BUS_DEVICE,
1330     .instance_size = sizeof(StrongARMUARTState),
1331     .instance_init = strongarm_uart_init,
1332     .class_init    = strongarm_uart_class_init,
1333 };
1334
1335 /* Synchronous Serial Ports */
1336
1337 #define TYPE_STRONGARM_SSP "strongarm-ssp"
1338 #define STRONGARM_SSP(obj) \
1339     OBJECT_CHECK(StrongARMSSPState, (obj), TYPE_STRONGARM_SSP)
1340
1341 typedef struct StrongARMSSPState {
1342     SysBusDevice parent_obj;
1343
1344     MemoryRegion iomem;
1345     qemu_irq irq;
1346     SSIBus *bus;
1347
1348     uint16_t sscr[2];
1349     uint16_t sssr;
1350
1351     uint16_t rx_fifo[8];
1352     uint8_t rx_level;
1353     uint8_t rx_start;
1354 } StrongARMSSPState;
1355
1356 #define SSCR0 0x60 /* SSP Control register 0 */
1357 #define SSCR1 0x64 /* SSP Control register 1 */
1358 #define SSDR  0x6c /* SSP Data register */
1359 #define SSSR  0x74 /* SSP Status register */
1360
1361 /* Bitfields for above registers */
1362 #define SSCR0_SPI(x)    (((x) & 0x30) == 0x00)
1363 #define SSCR0_SSP(x)    (((x) & 0x30) == 0x10)
1364 #define SSCR0_UWIRE(x)  (((x) & 0x30) == 0x20)
1365 #define SSCR0_PSP(x)    (((x) & 0x30) == 0x30)
1366 #define SSCR0_SSE       (1 << 7)
1367 #define SSCR0_DSS(x)    (((x) & 0xf) + 1)
1368 #define SSCR1_RIE       (1 << 0)
1369 #define SSCR1_TIE       (1 << 1)
1370 #define SSCR1_LBM       (1 << 2)
1371 #define SSSR_TNF        (1 << 2)
1372 #define SSSR_RNE        (1 << 3)
1373 #define SSSR_TFS        (1 << 5)
1374 #define SSSR_RFS        (1 << 6)
1375 #define SSSR_ROR        (1 << 7)
1376 #define SSSR_RW         0x0080
1377
1378 static void strongarm_ssp_int_update(StrongARMSSPState *s)
1379 {
1380     int level = 0;
1381
1382     level |= (s->sssr & SSSR_ROR);
1383     level |= (s->sssr & SSSR_RFS)  &&  (s->sscr[1] & SSCR1_RIE);
1384     level |= (s->sssr & SSSR_TFS)  &&  (s->sscr[1] & SSCR1_TIE);
1385     qemu_set_irq(s->irq, level);
1386 }
1387
1388 static void strongarm_ssp_fifo_update(StrongARMSSPState *s)
1389 {
1390     s->sssr &= ~SSSR_TFS;
1391     s->sssr &= ~SSSR_TNF;
1392     if (s->sscr[0] & SSCR0_SSE) {
1393         if (s->rx_level >= 4) {
1394             s->sssr |= SSSR_RFS;
1395         } else {
1396             s->sssr &= ~SSSR_RFS;
1397         }
1398         if (s->rx_level) {
1399             s->sssr |= SSSR_RNE;
1400         } else {
1401             s->sssr &= ~SSSR_RNE;
1402         }
1403         /* TX FIFO is never filled, so it is always in underrun
1404            condition if SSP is enabled */
1405         s->sssr |= SSSR_TFS;
1406         s->sssr |= SSSR_TNF;
1407     }
1408
1409     strongarm_ssp_int_update(s);
1410 }
1411
1412 static uint64_t strongarm_ssp_read(void *opaque, hwaddr addr,
1413                                    unsigned size)
1414 {
1415     StrongARMSSPState *s = opaque;
1416     uint32_t retval;
1417
1418     switch (addr) {
1419     case SSCR0:
1420         return s->sscr[0];
1421     case SSCR1:
1422         return s->sscr[1];
1423     case SSSR:
1424         return s->sssr;
1425     case SSDR:
1426         if (~s->sscr[0] & SSCR0_SSE) {
1427             return 0xffffffff;
1428         }
1429         if (s->rx_level < 1) {
1430             printf("%s: SSP Rx Underrun\n", __func__);
1431             return 0xffffffff;
1432         }
1433         s->rx_level--;
1434         retval = s->rx_fifo[s->rx_start++];
1435         s->rx_start &= 0x7;
1436         strongarm_ssp_fifo_update(s);
1437         return retval;
1438     default:
1439         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1440         break;
1441     }
1442     return 0;
1443 }
1444
1445 static void strongarm_ssp_write(void *opaque, hwaddr addr,
1446                                 uint64_t value, unsigned size)
1447 {
1448     StrongARMSSPState *s = opaque;
1449
1450     switch (addr) {
1451     case SSCR0:
1452         s->sscr[0] = value & 0xffbf;
1453         if ((s->sscr[0] & SSCR0_SSE) && SSCR0_DSS(value) < 4) {
1454             printf("%s: Wrong data size: %i bits\n", __func__,
1455                    (int)SSCR0_DSS(value));
1456         }
1457         if (!(value & SSCR0_SSE)) {
1458             s->sssr = 0;
1459             s->rx_level = 0;
1460         }
1461         strongarm_ssp_fifo_update(s);
1462         break;
1463
1464     case SSCR1:
1465         s->sscr[1] = value & 0x2f;
1466         if (value & SSCR1_LBM) {
1467             printf("%s: Attempt to use SSP LBM mode\n", __func__);
1468         }
1469         strongarm_ssp_fifo_update(s);
1470         break;
1471
1472     case SSSR:
1473         s->sssr &= ~(value & SSSR_RW);
1474         strongarm_ssp_int_update(s);
1475         break;
1476
1477     case SSDR:
1478         if (SSCR0_UWIRE(s->sscr[0])) {
1479             value &= 0xff;
1480         } else
1481             /* Note how 32bits overflow does no harm here */
1482             value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
1483
1484         /* Data goes from here to the Tx FIFO and is shifted out from
1485          * there directly to the slave, no need to buffer it.
1486          */
1487         if (s->sscr[0] & SSCR0_SSE) {
1488             uint32_t readval;
1489             if (s->sscr[1] & SSCR1_LBM) {
1490                 readval = value;
1491             } else {
1492                 readval = ssi_transfer(s->bus, value);
1493             }
1494
1495             if (s->rx_level < 0x08) {
1496                 s->rx_fifo[(s->rx_start + s->rx_level++) & 0x7] = readval;
1497             } else {
1498                 s->sssr |= SSSR_ROR;
1499             }
1500         }
1501         strongarm_ssp_fifo_update(s);
1502         break;
1503
1504     default:
1505         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1506         break;
1507     }
1508 }
1509
1510 static const MemoryRegionOps strongarm_ssp_ops = {
1511     .read = strongarm_ssp_read,
1512     .write = strongarm_ssp_write,
1513     .endianness = DEVICE_NATIVE_ENDIAN,
1514 };
1515
1516 static int strongarm_ssp_post_load(void *opaque, int version_id)
1517 {
1518     StrongARMSSPState *s = opaque;
1519
1520     strongarm_ssp_fifo_update(s);
1521
1522     return 0;
1523 }
1524
1525 static void strongarm_ssp_init(Object *obj)
1526 {
1527     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1528     DeviceState *dev = DEVICE(sbd);
1529     StrongARMSSPState *s = STRONGARM_SSP(dev);
1530
1531     sysbus_init_irq(sbd, &s->irq);
1532
1533     memory_region_init_io(&s->iomem, obj, &strongarm_ssp_ops, s,
1534                           "ssp", 0x1000);
1535     sysbus_init_mmio(sbd, &s->iomem);
1536
1537     s->bus = ssi_create_bus(dev, "ssi");
1538 }
1539
1540 static void strongarm_ssp_reset(DeviceState *dev)
1541 {
1542     StrongARMSSPState *s = STRONGARM_SSP(dev);
1543
1544     s->sssr = 0x03; /* 3 bit data, SPI, disabled */
1545     s->rx_start = 0;
1546     s->rx_level = 0;
1547 }
1548
1549 static const VMStateDescription vmstate_strongarm_ssp_regs = {
1550     .name = "strongarm-ssp",
1551     .version_id = 0,
1552     .minimum_version_id = 0,
1553     .post_load = strongarm_ssp_post_load,
1554     .fields = (VMStateField[]) {
1555         VMSTATE_UINT16_ARRAY(sscr, StrongARMSSPState, 2),
1556         VMSTATE_UINT16(sssr, StrongARMSSPState),
1557         VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMSSPState, 8),
1558         VMSTATE_UINT8(rx_start, StrongARMSSPState),
1559         VMSTATE_UINT8(rx_level, StrongARMSSPState),
1560         VMSTATE_END_OF_LIST(),
1561     },
1562 };
1563
1564 static void strongarm_ssp_class_init(ObjectClass *klass, void *data)
1565 {
1566     DeviceClass *dc = DEVICE_CLASS(klass);
1567
1568     dc->desc = "StrongARM SSP controller";
1569     dc->reset = strongarm_ssp_reset;
1570     dc->vmsd = &vmstate_strongarm_ssp_regs;
1571 }
1572
1573 static const TypeInfo strongarm_ssp_info = {
1574     .name          = TYPE_STRONGARM_SSP,
1575     .parent        = TYPE_SYS_BUS_DEVICE,
1576     .instance_size = sizeof(StrongARMSSPState),
1577     .instance_init = strongarm_ssp_init,
1578     .class_init    = strongarm_ssp_class_init,
1579 };
1580
1581 /* Main CPU functions */
1582 StrongARMState *sa1110_init(MemoryRegion *sysmem,
1583                             unsigned int sdram_size, const char *rev)
1584 {
1585     StrongARMState *s;
1586     int i;
1587
1588     s = g_new0(StrongARMState, 1);
1589
1590     if (!rev) {
1591         rev = "sa1110-b5";
1592     }
1593
1594     if (strncmp(rev, "sa1110", 6)) {
1595         error_report("Machine requires a SA1110 processor.");
1596         exit(1);
1597     }
1598
1599     s->cpu = cpu_arm_init(rev);
1600
1601     if (!s->cpu) {
1602         error_report("Unable to find CPU definition");
1603         exit(1);
1604     }
1605
1606     memory_region_allocate_system_memory(&s->sdram, NULL, "strongarm.sdram",
1607                                          sdram_size);
1608     memory_region_add_subregion(sysmem, SA_SDCS0, &s->sdram);
1609
1610     s->pic = sysbus_create_varargs("strongarm_pic", 0x90050000,
1611                     qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ),
1612                     qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ),
1613                     NULL);
1614
1615     sysbus_create_varargs("pxa25x-timer", 0x90000000,
1616                     qdev_get_gpio_in(s->pic, SA_PIC_OSTC0),
1617                     qdev_get_gpio_in(s->pic, SA_PIC_OSTC1),
1618                     qdev_get_gpio_in(s->pic, SA_PIC_OSTC2),
1619                     qdev_get_gpio_in(s->pic, SA_PIC_OSTC3),
1620                     NULL);
1621
1622     sysbus_create_simple(TYPE_STRONGARM_RTC, 0x90010000,
1623                     qdev_get_gpio_in(s->pic, SA_PIC_RTC_ALARM));
1624
1625     s->gpio = strongarm_gpio_init(0x90040000, s->pic);
1626
1627     s->ppc = sysbus_create_varargs(TYPE_STRONGARM_PPC, 0x90060000, NULL);
1628
1629     for (i = 0; sa_serial[i].io_base; i++) {
1630         DeviceState *dev = qdev_create(NULL, TYPE_STRONGARM_UART);
1631         qdev_prop_set_chr(dev, "chardev", serial_hds[i]);
1632         qdev_init_nofail(dev);
1633         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0,
1634                 sa_serial[i].io_base);
1635         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
1636                 qdev_get_gpio_in(s->pic, sa_serial[i].irq));
1637     }
1638
1639     s->ssp = sysbus_create_varargs(TYPE_STRONGARM_SSP, 0x80070000,
1640                 qdev_get_gpio_in(s->pic, SA_PIC_SSP), NULL);
1641     s->ssp_bus = (SSIBus *)qdev_get_child_bus(s->ssp, "ssi");
1642
1643     return s;
1644 }
1645
1646 static void strongarm_register_types(void)
1647 {
1648     type_register_static(&strongarm_pic_info);
1649     type_register_static(&strongarm_rtc_sysbus_info);
1650     type_register_static(&strongarm_gpio_info);
1651     type_register_static(&strongarm_ppc_info);
1652     type_register_static(&strongarm_uart_info);
1653     type_register_static(&strongarm_ssp_info);
1654 }
1655
1656 type_init(strongarm_register_types)