1 #include "qemu/osdep.h"
5 #include "exec/gdbstub.h"
6 #include "exec/helper-proto.h"
7 #include "qemu/host-utils.h"
8 #include "sysemu/arch_init.h"
9 #include "sysemu/sysemu.h"
10 #include "qemu/bitops.h"
11 #include "qemu/crc32c.h"
12 #include "exec/exec-all.h"
13 #include "exec/cpu_ldst.h"
15 #include <zlib.h> /* For crc32 */
16 #include "exec/semihost.h"
17 #include "sysemu/kvm.h"
19 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
21 #ifndef CONFIG_USER_ONLY
22 static bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
23 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
24 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
25 target_ulong
*page_size
, uint32_t *fsr
,
28 static bool get_phys_addr_lpae(CPUARMState
*env
, target_ulong address
,
29 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
30 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
, int *prot
,
31 target_ulong
*page_size_ptr
, uint32_t *fsr
,
34 /* Definitions for the PMCCNTR and PMCR registers */
40 static int vfp_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
44 /* VFP data registers are always little-endian. */
45 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
47 stfq_le_p(buf
, env
->vfp
.regs
[reg
]);
50 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
51 /* Aliases for Q regs. */
54 stfq_le_p(buf
, env
->vfp
.regs
[(reg
- 32) * 2]);
55 stfq_le_p(buf
+ 8, env
->vfp
.regs
[(reg
- 32) * 2 + 1]);
59 switch (reg
- nregs
) {
60 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
61 case 1: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSCR
]); return 4;
62 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
67 static int vfp_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
71 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
73 env
->vfp
.regs
[reg
] = ldfq_le_p(buf
);
76 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
79 env
->vfp
.regs
[(reg
- 32) * 2] = ldfq_le_p(buf
);
80 env
->vfp
.regs
[(reg
- 32) * 2 + 1] = ldfq_le_p(buf
+ 8);
84 switch (reg
- nregs
) {
85 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
86 case 1: env
->vfp
.xregs
[ARM_VFP_FPSCR
] = ldl_p(buf
); return 4;
87 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
92 static int aarch64_fpu_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
96 /* 128 bit FP register */
97 stfq_le_p(buf
, env
->vfp
.regs
[reg
* 2]);
98 stfq_le_p(buf
+ 8, env
->vfp
.regs
[reg
* 2 + 1]);
102 stl_p(buf
, vfp_get_fpsr(env
));
106 stl_p(buf
, vfp_get_fpcr(env
));
113 static int aarch64_fpu_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
117 /* 128 bit FP register */
118 env
->vfp
.regs
[reg
* 2] = ldfq_le_p(buf
);
119 env
->vfp
.regs
[reg
* 2 + 1] = ldfq_le_p(buf
+ 8);
123 vfp_set_fpsr(env
, ldl_p(buf
));
127 vfp_set_fpcr(env
, ldl_p(buf
));
134 static uint64_t raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
136 assert(ri
->fieldoffset
);
137 if (cpreg_field_is_64bit(ri
)) {
138 return CPREG_FIELD64(env
, ri
);
140 return CPREG_FIELD32(env
, ri
);
144 static void raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
147 assert(ri
->fieldoffset
);
148 if (cpreg_field_is_64bit(ri
)) {
149 CPREG_FIELD64(env
, ri
) = value
;
151 CPREG_FIELD32(env
, ri
) = value
;
155 static void *raw_ptr(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
157 return (char *)env
+ ri
->fieldoffset
;
160 uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
162 /* Raw read of a coprocessor register (as needed for migration, etc). */
163 if (ri
->type
& ARM_CP_CONST
) {
164 return ri
->resetvalue
;
165 } else if (ri
->raw_readfn
) {
166 return ri
->raw_readfn(env
, ri
);
167 } else if (ri
->readfn
) {
168 return ri
->readfn(env
, ri
);
170 return raw_read(env
, ri
);
174 static void write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
177 /* Raw write of a coprocessor register (as needed for migration, etc).
178 * Note that constant registers are treated as write-ignored; the
179 * caller should check for success by whether a readback gives the
182 if (ri
->type
& ARM_CP_CONST
) {
184 } else if (ri
->raw_writefn
) {
185 ri
->raw_writefn(env
, ri
, v
);
186 } else if (ri
->writefn
) {
187 ri
->writefn(env
, ri
, v
);
189 raw_write(env
, ri
, v
);
193 static bool raw_accessors_invalid(const ARMCPRegInfo
*ri
)
195 /* Return true if the regdef would cause an assertion if you called
196 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
197 * program bug for it not to have the NO_RAW flag).
198 * NB that returning false here doesn't necessarily mean that calling
199 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
200 * read/write access functions which are safe for raw use" from "has
201 * read/write access functions which have side effects but has forgotten
202 * to provide raw access functions".
203 * The tests here line up with the conditions in read/write_raw_cp_reg()
204 * and assertions in raw_read()/raw_write().
206 if ((ri
->type
& ARM_CP_CONST
) ||
208 ((ri
->raw_writefn
|| ri
->writefn
) && (ri
->raw_readfn
|| ri
->readfn
))) {
214 bool write_cpustate_to_list(ARMCPU
*cpu
)
216 /* Write the coprocessor state from cpu->env to the (index,value) list. */
220 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
221 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
222 const ARMCPRegInfo
*ri
;
224 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
229 if (ri
->type
& ARM_CP_NO_RAW
) {
232 cpu
->cpreg_values
[i
] = read_raw_cp_reg(&cpu
->env
, ri
);
237 bool write_list_to_cpustate(ARMCPU
*cpu
)
242 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
243 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
244 uint64_t v
= cpu
->cpreg_values
[i
];
245 const ARMCPRegInfo
*ri
;
247 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
252 if (ri
->type
& ARM_CP_NO_RAW
) {
255 /* Write value and confirm it reads back as written
256 * (to catch read-only registers and partially read-only
257 * registers where the incoming migration value doesn't match)
259 write_raw_cp_reg(&cpu
->env
, ri
, v
);
260 if (read_raw_cp_reg(&cpu
->env
, ri
) != v
) {
267 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
269 ARMCPU
*cpu
= opaque
;
271 const ARMCPRegInfo
*ri
;
273 regidx
= *(uint32_t *)key
;
274 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
276 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
277 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
278 /* The value array need not be initialized at this point */
279 cpu
->cpreg_array_len
++;
283 static void count_cpreg(gpointer key
, gpointer opaque
)
285 ARMCPU
*cpu
= opaque
;
287 const ARMCPRegInfo
*ri
;
289 regidx
= *(uint32_t *)key
;
290 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
292 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
293 cpu
->cpreg_array_len
++;
297 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
299 uint64_t aidx
= cpreg_to_kvm_id(*(uint32_t *)a
);
300 uint64_t bidx
= cpreg_to_kvm_id(*(uint32_t *)b
);
311 void init_cpreg_list(ARMCPU
*cpu
)
313 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
314 * Note that we require cpreg_tuples[] to be sorted by key ID.
319 keys
= g_hash_table_get_keys(cpu
->cp_regs
);
320 keys
= g_list_sort(keys
, cpreg_key_compare
);
322 cpu
->cpreg_array_len
= 0;
324 g_list_foreach(keys
, count_cpreg
, cpu
);
326 arraylen
= cpu
->cpreg_array_len
;
327 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
328 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
329 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
330 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
331 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
332 cpu
->cpreg_array_len
= 0;
334 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
336 assert(cpu
->cpreg_array_len
== arraylen
);
342 * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but
343 * they are accessible when EL3 is using AArch64 regardless of EL3.NS.
345 * access_el3_aa32ns: Used to check AArch32 register views.
346 * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views.
348 static CPAccessResult
access_el3_aa32ns(CPUARMState
*env
,
349 const ARMCPRegInfo
*ri
,
352 bool secure
= arm_is_secure_below_el3(env
);
354 assert(!arm_el_is_aa64(env
, 3));
356 return CP_ACCESS_TRAP_UNCATEGORIZED
;
361 static CPAccessResult
access_el3_aa32ns_aa64any(CPUARMState
*env
,
362 const ARMCPRegInfo
*ri
,
365 if (!arm_el_is_aa64(env
, 3)) {
366 return access_el3_aa32ns(env
, ri
, isread
);
371 /* Some secure-only AArch32 registers trap to EL3 if used from
372 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
373 * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
374 * We assume that the .access field is set to PL1_RW.
376 static CPAccessResult
access_trap_aa32s_el1(CPUARMState
*env
,
377 const ARMCPRegInfo
*ri
,
380 if (arm_current_el(env
) == 3) {
383 if (arm_is_secure_below_el3(env
)) {
384 return CP_ACCESS_TRAP_EL3
;
386 /* This will be EL1 NS and EL2 NS, which just UNDEF */
387 return CP_ACCESS_TRAP_UNCATEGORIZED
;
390 /* Check for traps to "powerdown debug" registers, which are controlled
393 static CPAccessResult
access_tdosa(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
396 int el
= arm_current_el(env
);
398 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TDOSA
)
399 && !arm_is_secure_below_el3(env
)) {
400 return CP_ACCESS_TRAP_EL2
;
402 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDOSA
)) {
403 return CP_ACCESS_TRAP_EL3
;
408 /* Check for traps to "debug ROM" registers, which are controlled
409 * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3.
411 static CPAccessResult
access_tdra(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
414 int el
= arm_current_el(env
);
416 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TDRA
)
417 && !arm_is_secure_below_el3(env
)) {
418 return CP_ACCESS_TRAP_EL2
;
420 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDA
)) {
421 return CP_ACCESS_TRAP_EL3
;
426 /* Check for traps to general debug registers, which are controlled
427 * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3.
429 static CPAccessResult
access_tda(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
432 int el
= arm_current_el(env
);
434 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TDA
)
435 && !arm_is_secure_below_el3(env
)) {
436 return CP_ACCESS_TRAP_EL2
;
438 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDA
)) {
439 return CP_ACCESS_TRAP_EL3
;
444 /* Check for traps to performance monitor registers, which are controlled
445 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
447 static CPAccessResult
access_tpm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
450 int el
= arm_current_el(env
);
452 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TPM
)
453 && !arm_is_secure_below_el3(env
)) {
454 return CP_ACCESS_TRAP_EL2
;
456 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
457 return CP_ACCESS_TRAP_EL3
;
462 static void dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
464 ARMCPU
*cpu
= arm_env_get_cpu(env
);
466 raw_write(env
, ri
, value
);
467 tlb_flush(CPU(cpu
)); /* Flush TLB as domain not tracked in TLB */
470 static void fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
472 ARMCPU
*cpu
= arm_env_get_cpu(env
);
474 if (raw_read(env
, ri
) != value
) {
475 /* Unlike real hardware the qemu TLB uses virtual addresses,
476 * not modified virtual addresses, so this causes a TLB flush.
479 raw_write(env
, ri
, value
);
483 static void contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
486 ARMCPU
*cpu
= arm_env_get_cpu(env
);
488 if (raw_read(env
, ri
) != value
&& !arm_feature(env
, ARM_FEATURE_PMSA
)
489 && !extended_addresses_enabled(env
)) {
490 /* For VMSA (when not using the LPAE long descriptor page table
491 * format) this register includes the ASID, so do a TLB flush.
492 * For PMSA it is purely a process ID and no action is needed.
496 raw_write(env
, ri
, value
);
499 static void tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
502 /* Invalidate all (TLBIALL) */
503 ARMCPU
*cpu
= arm_env_get_cpu(env
);
508 static void tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
511 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
512 ARMCPU
*cpu
= arm_env_get_cpu(env
);
514 tlb_flush_page(CPU(cpu
), value
& TARGET_PAGE_MASK
);
517 static void tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
520 /* Invalidate by ASID (TLBIASID) */
521 ARMCPU
*cpu
= arm_env_get_cpu(env
);
526 static void tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
529 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
530 ARMCPU
*cpu
= arm_env_get_cpu(env
);
532 tlb_flush_page(CPU(cpu
), value
& TARGET_PAGE_MASK
);
535 /* IS variants of TLB operations must affect all cores */
536 static void tlbiall_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
539 CPUState
*cs
= ENV_GET_CPU(env
);
541 tlb_flush_all_cpus_synced(cs
);
544 static void tlbiasid_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
547 CPUState
*cs
= ENV_GET_CPU(env
);
549 tlb_flush_all_cpus_synced(cs
);
552 static void tlbimva_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
555 CPUState
*cs
= ENV_GET_CPU(env
);
557 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
560 static void tlbimvaa_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
563 CPUState
*cs
= ENV_GET_CPU(env
);
565 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
568 static void tlbiall_nsnh_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
571 CPUState
*cs
= ENV_GET_CPU(env
);
573 tlb_flush_by_mmuidx(cs
,
574 ARMMMUIdxBit_S12NSE1
|
575 ARMMMUIdxBit_S12NSE0
|
579 static void tlbiall_nsnh_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
582 CPUState
*cs
= ENV_GET_CPU(env
);
584 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
585 ARMMMUIdxBit_S12NSE1
|
586 ARMMMUIdxBit_S12NSE0
|
590 static void tlbiipas2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
593 /* Invalidate by IPA. This has to invalidate any structures that
594 * contain only stage 2 translation information, but does not need
595 * to apply to structures that contain combined stage 1 and stage 2
596 * translation information.
597 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
599 CPUState
*cs
= ENV_GET_CPU(env
);
602 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
606 pageaddr
= sextract64(value
<< 12, 0, 40);
608 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S2NS
);
611 static void tlbiipas2_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
614 CPUState
*cs
= ENV_GET_CPU(env
);
617 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
621 pageaddr
= sextract64(value
<< 12, 0, 40);
623 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
627 static void tlbiall_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
630 CPUState
*cs
= ENV_GET_CPU(env
);
632 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_S1E2
);
635 static void tlbiall_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
638 CPUState
*cs
= ENV_GET_CPU(env
);
640 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_S1E2
);
643 static void tlbimva_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
646 CPUState
*cs
= ENV_GET_CPU(env
);
647 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
649 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S1E2
);
652 static void tlbimva_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
655 CPUState
*cs
= ENV_GET_CPU(env
);
656 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
658 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
662 static const ARMCPRegInfo cp_reginfo
[] = {
663 /* Define the secure and non-secure FCSE identifier CP registers
664 * separately because there is no secure bank in V8 (no _EL3). This allows
665 * the secure register to be properly reset and migrated. There is also no
666 * v8 EL1 version of the register so the non-secure instance stands alone.
668 { .name
= "FCSEIDR(NS)",
669 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
670 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
671 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_ns
),
672 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
673 { .name
= "FCSEIDR(S)",
674 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
675 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
676 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_s
),
677 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
678 /* Define the secure and non-secure context identifier CP registers
679 * separately because there is no secure bank in V8 (no _EL3). This allows
680 * the secure register to be properly reset and migrated. In the
681 * non-secure case, the 32-bit register will have reset and migration
682 * disabled during registration as it is handled by the 64-bit instance.
684 { .name
= "CONTEXTIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
685 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
686 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
687 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[1]),
688 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
689 { .name
= "CONTEXTIDR(S)", .state
= ARM_CP_STATE_AA32
,
690 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
691 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
692 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_s
),
693 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
697 static const ARMCPRegInfo not_v8_cp_reginfo
[] = {
698 /* NB: Some of these registers exist in v8 but with more precise
699 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
701 /* MMU Domain access control / MPU write buffer control */
703 .cp
= 15, .opc1
= CP_ANY
, .crn
= 3, .crm
= CP_ANY
, .opc2
= CP_ANY
,
704 .access
= PL1_RW
, .resetvalue
= 0,
705 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
706 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
707 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
708 /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
709 * For v6 and v5, these mappings are overly broad.
711 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 0,
712 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
713 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 1,
714 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
715 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 4,
716 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
717 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 8,
718 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
719 /* Cache maintenance ops; some of this space may be overridden later. */
720 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
721 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
722 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
726 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
727 /* Not all pre-v6 cores implemented this WFI, so this is slightly
730 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
731 .access
= PL1_W
, .type
= ARM_CP_WFI
},
735 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
736 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
737 * is UNPREDICTABLE; we choose to NOP as most implementations do).
739 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
740 .access
= PL1_W
, .type
= ARM_CP_WFI
},
741 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
742 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
743 * OMAPCP will override this space.
745 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
746 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
748 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
749 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
751 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
752 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
753 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
755 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
756 * implementing it as RAZ means the "debug architecture version" bits
757 * will read as a reserved value, which should cause Linux to not try
758 * to use the debug hardware.
760 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
761 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
762 /* MMU TLB control. Note that the wildcarding means we cover not just
763 * the unified TLB ops but also the dside/iside/inner-shareable variants.
765 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
766 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
767 .type
= ARM_CP_NO_RAW
},
768 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
769 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
770 .type
= ARM_CP_NO_RAW
},
771 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
772 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
773 .type
= ARM_CP_NO_RAW
},
774 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
775 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
776 .type
= ARM_CP_NO_RAW
},
777 { .name
= "PRRR", .cp
= 15, .crn
= 10, .crm
= 2,
778 .opc1
= 0, .opc2
= 0, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
779 { .name
= "NMRR", .cp
= 15, .crn
= 10, .crm
= 2,
780 .opc1
= 0, .opc2
= 1, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
784 static void cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
789 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
790 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
791 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
792 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
793 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
795 if (arm_feature(env
, ARM_FEATURE_VFP
)) {
796 /* VFP coprocessor: cp10 & cp11 [23:20] */
797 mask
|= (1 << 31) | (1 << 30) | (0xf << 20);
799 if (!arm_feature(env
, ARM_FEATURE_NEON
)) {
800 /* ASEDIS [31] bit is RAO/WI */
804 /* VFPv3 and upwards with NEON implement 32 double precision
805 * registers (D0-D31).
807 if (!arm_feature(env
, ARM_FEATURE_NEON
) ||
808 !arm_feature(env
, ARM_FEATURE_VFP3
)) {
809 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
815 env
->cp15
.cpacr_el1
= value
;
818 static CPAccessResult
cpacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
821 if (arm_feature(env
, ARM_FEATURE_V8
)) {
822 /* Check if CPACR accesses are to be trapped to EL2 */
823 if (arm_current_el(env
) == 1 &&
824 (env
->cp15
.cptr_el
[2] & CPTR_TCPAC
) && !arm_is_secure(env
)) {
825 return CP_ACCESS_TRAP_EL2
;
826 /* Check if CPACR accesses are to be trapped to EL3 */
827 } else if (arm_current_el(env
) < 3 &&
828 (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
829 return CP_ACCESS_TRAP_EL3
;
836 static CPAccessResult
cptr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
839 /* Check if CPTR accesses are set to trap to EL3 */
840 if (arm_current_el(env
) == 2 && (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
841 return CP_ACCESS_TRAP_EL3
;
847 static const ARMCPRegInfo v6_cp_reginfo
[] = {
848 /* prefetch by MVA in v6, NOP in v7 */
849 { .name
= "MVA_prefetch",
850 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
851 .access
= PL1_W
, .type
= ARM_CP_NOP
},
852 /* We need to break the TB after ISB to execute self-modifying code
853 * correctly and also to take any pending interrupts immediately.
854 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
856 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
857 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
, .writefn
= arm_cp_write_ignore
},
858 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
859 .access
= PL0_W
, .type
= ARM_CP_NOP
},
860 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
861 .access
= PL0_W
, .type
= ARM_CP_NOP
},
862 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
864 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ifar_s
),
865 offsetof(CPUARMState
, cp15
.ifar_ns
) },
867 /* Watchpoint Fault Address Register : should actually only be present
868 * for 1136, 1176, 11MPCore.
870 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
871 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
872 { .name
= "CPACR", .state
= ARM_CP_STATE_BOTH
, .opc0
= 3,
873 .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2, .accessfn
= cpacr_access
,
874 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.cpacr_el1
),
875 .resetvalue
= 0, .writefn
= cpacr_write
},
879 static CPAccessResult
pmreg_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
882 /* Performance monitor registers user accessibility is controlled
883 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
884 * trapping to EL2 or EL3 for other accesses.
886 int el
= arm_current_el(env
);
888 if (el
== 0 && !(env
->cp15
.c9_pmuserenr
& 1)) {
889 return CP_ACCESS_TRAP
;
891 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TPM
)
892 && !arm_is_secure_below_el3(env
)) {
893 return CP_ACCESS_TRAP_EL2
;
895 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
896 return CP_ACCESS_TRAP_EL3
;
902 static CPAccessResult
pmreg_access_xevcntr(CPUARMState
*env
,
903 const ARMCPRegInfo
*ri
,
906 /* ER: event counter read trap control */
907 if (arm_feature(env
, ARM_FEATURE_V8
)
908 && arm_current_el(env
) == 0
909 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0
914 return pmreg_access(env
, ri
, isread
);
917 static CPAccessResult
pmreg_access_swinc(CPUARMState
*env
,
918 const ARMCPRegInfo
*ri
,
921 /* SW: software increment write trap control */
922 if (arm_feature(env
, ARM_FEATURE_V8
)
923 && arm_current_el(env
) == 0
924 && (env
->cp15
.c9_pmuserenr
& (1 << 1)) != 0
929 return pmreg_access(env
, ri
, isread
);
932 #ifndef CONFIG_USER_ONLY
934 static CPAccessResult
pmreg_access_selr(CPUARMState
*env
,
935 const ARMCPRegInfo
*ri
,
938 /* ER: event counter read trap control */
939 if (arm_feature(env
, ARM_FEATURE_V8
)
940 && arm_current_el(env
) == 0
941 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0) {
945 return pmreg_access(env
, ri
, isread
);
948 static CPAccessResult
pmreg_access_ccntr(CPUARMState
*env
,
949 const ARMCPRegInfo
*ri
,
952 /* CR: cycle counter read trap control */
953 if (arm_feature(env
, ARM_FEATURE_V8
)
954 && arm_current_el(env
) == 0
955 && (env
->cp15
.c9_pmuserenr
& (1 << 2)) != 0
960 return pmreg_access(env
, ri
, isread
);
963 static inline bool arm_ccnt_enabled(CPUARMState
*env
)
965 /* This does not support checking PMCCFILTR_EL0 register */
967 if (!(env
->cp15
.c9_pmcr
& PMCRE
)) {
974 void pmccntr_sync(CPUARMState
*env
)
978 temp_ticks
= muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
979 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
981 if (env
->cp15
.c9_pmcr
& PMCRD
) {
982 /* Increment once every 64 processor clock cycles */
986 if (arm_ccnt_enabled(env
)) {
987 env
->cp15
.c15_ccnt
= temp_ticks
- env
->cp15
.c15_ccnt
;
991 static void pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
997 /* The counter has been reset */
998 env
->cp15
.c15_ccnt
= 0;
1001 /* only the DP, X, D and E bits are writable */
1002 env
->cp15
.c9_pmcr
&= ~0x39;
1003 env
->cp15
.c9_pmcr
|= (value
& 0x39);
1008 static uint64_t pmccntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1010 uint64_t total_ticks
;
1012 if (!arm_ccnt_enabled(env
)) {
1013 /* Counter is disabled, do not change value */
1014 return env
->cp15
.c15_ccnt
;
1017 total_ticks
= muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1018 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
1020 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1021 /* Increment once every 64 processor clock cycles */
1024 return total_ticks
- env
->cp15
.c15_ccnt
;
1027 static void pmselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1030 /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
1031 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
1032 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
1035 env
->cp15
.c9_pmselr
= value
& 0x1f;
1038 static void pmccntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1041 uint64_t total_ticks
;
1043 if (!arm_ccnt_enabled(env
)) {
1044 /* Counter is disabled, set the absolute value */
1045 env
->cp15
.c15_ccnt
= value
;
1049 total_ticks
= muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1050 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
1052 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1053 /* Increment once every 64 processor clock cycles */
1056 env
->cp15
.c15_ccnt
= total_ticks
- value
;
1059 static void pmccntr_write32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1062 uint64_t cur_val
= pmccntr_read(env
, NULL
);
1064 pmccntr_write(env
, ri
, deposit64(cur_val
, 0, 32, value
));
1067 #else /* CONFIG_USER_ONLY */
1069 void pmccntr_sync(CPUARMState
*env
)
1075 static void pmccfiltr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1079 env
->cp15
.pmccfiltr_el0
= value
& 0x7E000000;
1083 static void pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1087 env
->cp15
.c9_pmcnten
|= value
;
1090 static void pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1094 env
->cp15
.c9_pmcnten
&= ~value
;
1097 static void pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1100 env
->cp15
.c9_pmovsr
&= ~value
;
1103 static void pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1106 /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
1107 * PMSELR value is equal to or greater than the number of implemented
1108 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
1110 if (env
->cp15
.c9_pmselr
== 0x1f) {
1111 pmccfiltr_write(env
, ri
, value
);
1115 static uint64_t pmxevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1117 /* We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
1118 * are CONSTRAINED UNPREDICTABLE. See comments in pmxevtyper_write().
1120 if (env
->cp15
.c9_pmselr
== 0x1f) {
1121 return env
->cp15
.pmccfiltr_el0
;
1127 static void pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1130 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1131 env
->cp15
.c9_pmuserenr
= value
& 0xf;
1133 env
->cp15
.c9_pmuserenr
= value
& 1;
1137 static void pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1140 /* We have no event counters so only the C bit can be changed */
1142 env
->cp15
.c9_pminten
|= value
;
1145 static void pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1149 env
->cp15
.c9_pminten
&= ~value
;
1152 static void vbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1155 /* Note that even though the AArch64 view of this register has bits
1156 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
1157 * architectural requirements for bits which are RES0 only in some
1158 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
1159 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
1161 raw_write(env
, ri
, value
& ~0x1FULL
);
1164 static void scr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1166 /* We only mask off bits that are RES0 both for AArch64 and AArch32.
1167 * For bits that vary between AArch32/64, code needs to check the
1168 * current execution mode before directly using the feature bit.
1170 uint32_t valid_mask
= SCR_AARCH64_MASK
| SCR_AARCH32_MASK
;
1172 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1173 valid_mask
&= ~SCR_HCE
;
1175 /* On ARMv7, SMD (or SCD as it is called in v7) is only
1176 * supported if EL2 exists. The bit is UNK/SBZP when
1177 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
1178 * when EL2 is unavailable.
1179 * On ARMv8, this bit is always available.
1181 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1182 !arm_feature(env
, ARM_FEATURE_V8
)) {
1183 valid_mask
&= ~SCR_SMD
;
1187 /* Clear all-context RES0 bits. */
1188 value
&= valid_mask
;
1189 raw_write(env
, ri
, value
);
1192 static uint64_t ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1194 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1196 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
1199 uint32_t index
= A32_BANKED_REG_GET(env
, csselr
,
1200 ri
->secure
& ARM_CP_SECSTATE_S
);
1202 return cpu
->ccsidr
[index
];
1205 static void csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1208 raw_write(env
, ri
, value
& 0xf);
1211 static uint64_t isr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1213 CPUState
*cs
= ENV_GET_CPU(env
);
1216 if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
1219 if (cs
->interrupt_request
& CPU_INTERRUPT_FIQ
) {
1222 /* External aborts are not possible in QEMU so A bit is always clear */
1226 static const ARMCPRegInfo v7_cp_reginfo
[] = {
1227 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
1228 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
1229 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1230 /* Performance monitors are implementation defined in v7,
1231 * but with an ARM recommended set of registers, which we
1232 * follow (although we don't actually implement any counters)
1234 * Performance registers fall into three categories:
1235 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
1236 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
1237 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
1238 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
1239 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
1241 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
1242 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
1243 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
1244 .writefn
= pmcntenset_write
,
1245 .accessfn
= pmreg_access
,
1246 .raw_writefn
= raw_write
},
1247 { .name
= "PMCNTENSET_EL0", .state
= ARM_CP_STATE_AA64
,
1248 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 1,
1249 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1250 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
), .resetvalue
= 0,
1251 .writefn
= pmcntenset_write
, .raw_writefn
= raw_write
},
1252 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
1254 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
1255 .accessfn
= pmreg_access
,
1256 .writefn
= pmcntenclr_write
,
1257 .type
= ARM_CP_ALIAS
},
1258 { .name
= "PMCNTENCLR_EL0", .state
= ARM_CP_STATE_AA64
,
1259 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 2,
1260 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1261 .type
= ARM_CP_ALIAS
,
1262 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
1263 .writefn
= pmcntenclr_write
},
1264 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
1265 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
1266 .accessfn
= pmreg_access
,
1267 .writefn
= pmovsr_write
,
1268 .raw_writefn
= raw_write
},
1269 { .name
= "PMOVSCLR_EL0", .state
= ARM_CP_STATE_AA64
,
1270 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 3,
1271 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1272 .type
= ARM_CP_ALIAS
,
1273 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
1274 .writefn
= pmovsr_write
,
1275 .raw_writefn
= raw_write
},
1276 /* Unimplemented so WI. */
1277 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
1278 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
, .type
= ARM_CP_NOP
},
1279 #ifndef CONFIG_USER_ONLY
1280 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
1281 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
1282 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmselr
),
1283 .accessfn
= pmreg_access_selr
, .writefn
= pmselr_write
,
1284 .raw_writefn
= raw_write
},
1285 { .name
= "PMSELR_EL0", .state
= ARM_CP_STATE_AA64
,
1286 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 5,
1287 .access
= PL0_RW
, .accessfn
= pmreg_access_selr
,
1288 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmselr
),
1289 .writefn
= pmselr_write
, .raw_writefn
= raw_write
, },
1290 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
1291 .access
= PL0_RW
, .resetvalue
= 0, .type
= ARM_CP_IO
,
1292 .readfn
= pmccntr_read
, .writefn
= pmccntr_write32
,
1293 .accessfn
= pmreg_access_ccntr
},
1294 { .name
= "PMCCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
1295 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 0,
1296 .access
= PL0_RW
, .accessfn
= pmreg_access_ccntr
,
1298 .readfn
= pmccntr_read
, .writefn
= pmccntr_write
, },
1300 { .name
= "PMCCFILTR_EL0", .state
= ARM_CP_STATE_AA64
,
1301 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 15, .opc2
= 7,
1302 .writefn
= pmccfiltr_write
,
1303 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1305 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmccfiltr_el0
),
1307 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
1308 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
, .accessfn
= pmreg_access
,
1309 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
1310 { .name
= "PMXEVTYPER_EL0", .state
= ARM_CP_STATE_AA64
,
1311 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 1,
1312 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
, .accessfn
= pmreg_access
,
1313 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
1314 /* Unimplemented, RAZ/WI. */
1315 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
1316 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0,
1317 .accessfn
= pmreg_access_xevcntr
},
1318 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
1319 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
,
1320 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
1322 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
1323 { .name
= "PMUSERENR_EL0", .state
= ARM_CP_STATE_AA64
,
1324 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 0,
1325 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
1326 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
1328 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
1329 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
1330 .access
= PL1_RW
, .accessfn
= access_tpm
,
1331 .type
= ARM_CP_ALIAS
,
1332 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pminten
),
1334 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
1335 { .name
= "PMINTENSET_EL1", .state
= ARM_CP_STATE_AA64
,
1336 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 1,
1337 .access
= PL1_RW
, .accessfn
= access_tpm
,
1339 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
1340 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
,
1341 .resetvalue
= 0x0 },
1342 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
1343 .access
= PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
1344 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
1345 .writefn
= pmintenclr_write
, },
1346 { .name
= "PMINTENCLR_EL1", .state
= ARM_CP_STATE_AA64
,
1347 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 2,
1348 .access
= PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
1349 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
1350 .writefn
= pmintenclr_write
},
1351 { .name
= "CCSIDR", .state
= ARM_CP_STATE_BOTH
,
1352 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
1353 .access
= PL1_R
, .readfn
= ccsidr_read
, .type
= ARM_CP_NO_RAW
},
1354 { .name
= "CSSELR", .state
= ARM_CP_STATE_BOTH
,
1355 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
1356 .access
= PL1_RW
, .writefn
= csselr_write
, .resetvalue
= 0,
1357 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.csselr_s
),
1358 offsetof(CPUARMState
, cp15
.csselr_ns
) } },
1359 /* Auxiliary ID register: this actually has an IMPDEF value but for now
1360 * just RAZ for all cores:
1362 { .name
= "AIDR", .state
= ARM_CP_STATE_BOTH
,
1363 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 7,
1364 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1365 /* Auxiliary fault status registers: these also are IMPDEF, and we
1366 * choose to RAZ/WI for all cores.
1368 { .name
= "AFSR0_EL1", .state
= ARM_CP_STATE_BOTH
,
1369 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 0,
1370 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1371 { .name
= "AFSR1_EL1", .state
= ARM_CP_STATE_BOTH
,
1372 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 1,
1373 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1374 /* MAIR can just read-as-written because we don't implement caches
1375 * and so don't need to care about memory attributes.
1377 { .name
= "MAIR_EL1", .state
= ARM_CP_STATE_AA64
,
1378 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
1379 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[1]),
1381 { .name
= "MAIR_EL3", .state
= ARM_CP_STATE_AA64
,
1382 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 2, .opc2
= 0,
1383 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[3]),
1385 /* For non-long-descriptor page tables these are PRRR and NMRR;
1386 * regardless they still act as reads-as-written for QEMU.
1388 /* MAIR0/1 are defined separately from their 64-bit counterpart which
1389 * allows them to assign the correct fieldoffset based on the endianness
1390 * handled in the field definitions.
1392 { .name
= "MAIR0", .state
= ARM_CP_STATE_AA32
,
1393 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0, .access
= PL1_RW
,
1394 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair0_s
),
1395 offsetof(CPUARMState
, cp15
.mair0_ns
) },
1396 .resetfn
= arm_cp_reset_ignore
},
1397 { .name
= "MAIR1", .state
= ARM_CP_STATE_AA32
,
1398 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 1, .access
= PL1_RW
,
1399 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair1_s
),
1400 offsetof(CPUARMState
, cp15
.mair1_ns
) },
1401 .resetfn
= arm_cp_reset_ignore
},
1402 { .name
= "ISR_EL1", .state
= ARM_CP_STATE_BOTH
,
1403 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 0,
1404 .type
= ARM_CP_NO_RAW
, .access
= PL1_R
, .readfn
= isr_read
},
1405 /* 32 bit ITLB invalidates */
1406 { .name
= "ITLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 0,
1407 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
1408 { .name
= "ITLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
1409 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
1410 { .name
= "ITLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 2,
1411 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
1412 /* 32 bit DTLB invalidates */
1413 { .name
= "DTLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 0,
1414 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
1415 { .name
= "DTLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
1416 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
1417 { .name
= "DTLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 2,
1418 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
1419 /* 32 bit TLB invalidates */
1420 { .name
= "TLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
1421 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
1422 { .name
= "TLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
1423 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
1424 { .name
= "TLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
1425 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
1426 { .name
= "TLBIMVAA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
1427 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimvaa_write
},
1431 static const ARMCPRegInfo v7mp_cp_reginfo
[] = {
1432 /* 32 bit TLB invalidates, Inner Shareable */
1433 { .name
= "TLBIALLIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
1434 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_is_write
},
1435 { .name
= "TLBIMVAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
1436 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_is_write
},
1437 { .name
= "TLBIASIDIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
1438 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
1439 .writefn
= tlbiasid_is_write
},
1440 { .name
= "TLBIMVAAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
1441 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
1442 .writefn
= tlbimvaa_is_write
},
1446 static void teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1453 static CPAccessResult
teehbr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1456 if (arm_current_el(env
) == 0 && (env
->teecr
& 1)) {
1457 return CP_ACCESS_TRAP
;
1459 return CP_ACCESS_OK
;
1462 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
1463 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
1464 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
1466 .writefn
= teecr_write
},
1467 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
1468 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
1469 .accessfn
= teehbr_access
, .resetvalue
= 0 },
1473 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
1474 { .name
= "TPIDR_EL0", .state
= ARM_CP_STATE_AA64
,
1475 .opc0
= 3, .opc1
= 3, .opc2
= 2, .crn
= 13, .crm
= 0,
1477 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[0]), .resetvalue
= 0 },
1478 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
1480 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrurw_s
),
1481 offsetoflow32(CPUARMState
, cp15
.tpidrurw_ns
) },
1482 .resetfn
= arm_cp_reset_ignore
},
1483 { .name
= "TPIDRRO_EL0", .state
= ARM_CP_STATE_AA64
,
1484 .opc0
= 3, .opc1
= 3, .opc2
= 3, .crn
= 13, .crm
= 0,
1485 .access
= PL0_R
|PL1_W
,
1486 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidrro_el
[0]),
1488 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
1489 .access
= PL0_R
|PL1_W
,
1490 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidruro_s
),
1491 offsetoflow32(CPUARMState
, cp15
.tpidruro_ns
) },
1492 .resetfn
= arm_cp_reset_ignore
},
1493 { .name
= "TPIDR_EL1", .state
= ARM_CP_STATE_AA64
,
1494 .opc0
= 3, .opc1
= 0, .opc2
= 4, .crn
= 13, .crm
= 0,
1496 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[1]), .resetvalue
= 0 },
1497 { .name
= "TPIDRPRW", .opc1
= 0, .cp
= 15, .crn
= 13, .crm
= 0, .opc2
= 4,
1499 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrprw_s
),
1500 offsetoflow32(CPUARMState
, cp15
.tpidrprw_ns
) },
1505 #ifndef CONFIG_USER_ONLY
1507 static CPAccessResult
gt_cntfrq_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1510 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
1511 * Writable only at the highest implemented exception level.
1513 int el
= arm_current_el(env
);
1517 if (!extract32(env
->cp15
.c14_cntkctl
, 0, 2)) {
1518 return CP_ACCESS_TRAP
;
1522 if (!isread
&& ri
->state
== ARM_CP_STATE_AA32
&&
1523 arm_is_secure_below_el3(env
)) {
1524 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
1525 return CP_ACCESS_TRAP_UNCATEGORIZED
;
1533 if (!isread
&& el
< arm_highest_el(env
)) {
1534 return CP_ACCESS_TRAP_UNCATEGORIZED
;
1537 return CP_ACCESS_OK
;
1540 static CPAccessResult
gt_counter_access(CPUARMState
*env
, int timeridx
,
1543 unsigned int cur_el
= arm_current_el(env
);
1544 bool secure
= arm_is_secure(env
);
1546 /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
1548 !extract32(env
->cp15
.c14_cntkctl
, timeridx
, 1)) {
1549 return CP_ACCESS_TRAP
;
1552 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
1553 timeridx
== GTIMER_PHYS
&& !secure
&& cur_el
< 2 &&
1554 !extract32(env
->cp15
.cnthctl_el2
, 0, 1)) {
1555 return CP_ACCESS_TRAP_EL2
;
1557 return CP_ACCESS_OK
;
1560 static CPAccessResult
gt_timer_access(CPUARMState
*env
, int timeridx
,
1563 unsigned int cur_el
= arm_current_el(env
);
1564 bool secure
= arm_is_secure(env
);
1566 /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
1567 * EL0[PV]TEN is zero.
1570 !extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
1571 return CP_ACCESS_TRAP
;
1574 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
1575 timeridx
== GTIMER_PHYS
&& !secure
&& cur_el
< 2 &&
1576 !extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
1577 return CP_ACCESS_TRAP_EL2
;
1579 return CP_ACCESS_OK
;
1582 static CPAccessResult
gt_pct_access(CPUARMState
*env
,
1583 const ARMCPRegInfo
*ri
,
1586 return gt_counter_access(env
, GTIMER_PHYS
, isread
);
1589 static CPAccessResult
gt_vct_access(CPUARMState
*env
,
1590 const ARMCPRegInfo
*ri
,
1593 return gt_counter_access(env
, GTIMER_VIRT
, isread
);
1596 static CPAccessResult
gt_ptimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1599 return gt_timer_access(env
, GTIMER_PHYS
, isread
);
1602 static CPAccessResult
gt_vtimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1605 return gt_timer_access(env
, GTIMER_VIRT
, isread
);
1608 static CPAccessResult
gt_stimer_access(CPUARMState
*env
,
1609 const ARMCPRegInfo
*ri
,
1612 /* The AArch64 register view of the secure physical timer is
1613 * always accessible from EL3, and configurably accessible from
1616 switch (arm_current_el(env
)) {
1618 if (!arm_is_secure(env
)) {
1619 return CP_ACCESS_TRAP
;
1621 if (!(env
->cp15
.scr_el3
& SCR_ST
)) {
1622 return CP_ACCESS_TRAP_EL3
;
1624 return CP_ACCESS_OK
;
1627 return CP_ACCESS_TRAP
;
1629 return CP_ACCESS_OK
;
1631 g_assert_not_reached();
1635 static uint64_t gt_get_countervalue(CPUARMState
*env
)
1637 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / GTIMER_SCALE
;
1640 static void gt_recalc_timer(ARMCPU
*cpu
, int timeridx
)
1642 ARMGenericTimer
*gt
= &cpu
->env
.cp15
.c14_timer
[timeridx
];
1645 /* Timer enabled: calculate and set current ISTATUS, irq, and
1646 * reset timer to when ISTATUS next has to change
1648 uint64_t offset
= timeridx
== GTIMER_VIRT
?
1649 cpu
->env
.cp15
.cntvoff_el2
: 0;
1650 uint64_t count
= gt_get_countervalue(&cpu
->env
);
1651 /* Note that this must be unsigned 64 bit arithmetic: */
1652 int istatus
= count
- offset
>= gt
->cval
;
1656 gt
->ctl
= deposit32(gt
->ctl
, 2, 1, istatus
);
1658 irqstate
= (istatus
&& !(gt
->ctl
& 2));
1659 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
1662 /* Next transition is when count rolls back over to zero */
1663 nexttick
= UINT64_MAX
;
1665 /* Next transition is when we hit cval */
1666 nexttick
= gt
->cval
+ offset
;
1668 /* Note that the desired next expiry time might be beyond the
1669 * signed-64-bit range of a QEMUTimer -- in this case we just
1670 * set the timer for as far in the future as possible. When the
1671 * timer expires we will reset the timer for any remaining period.
1673 if (nexttick
> INT64_MAX
/ GTIMER_SCALE
) {
1674 nexttick
= INT64_MAX
/ GTIMER_SCALE
;
1676 timer_mod(cpu
->gt_timer
[timeridx
], nexttick
);
1677 trace_arm_gt_recalc(timeridx
, irqstate
, nexttick
);
1679 /* Timer disabled: ISTATUS and timer output always clear */
1681 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], 0);
1682 timer_del(cpu
->gt_timer
[timeridx
]);
1683 trace_arm_gt_recalc_disabled(timeridx
);
1687 static void gt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1690 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1692 timer_del(cpu
->gt_timer
[timeridx
]);
1695 static uint64_t gt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1697 return gt_get_countervalue(env
);
1700 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1702 return gt_get_countervalue(env
) - env
->cp15
.cntvoff_el2
;
1705 static void gt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1709 trace_arm_gt_cval_write(timeridx
, value
);
1710 env
->cp15
.c14_timer
[timeridx
].cval
= value
;
1711 gt_recalc_timer(arm_env_get_cpu(env
), timeridx
);
1714 static uint64_t gt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1717 uint64_t offset
= timeridx
== GTIMER_VIRT
? env
->cp15
.cntvoff_el2
: 0;
1719 return (uint32_t)(env
->cp15
.c14_timer
[timeridx
].cval
-
1720 (gt_get_countervalue(env
) - offset
));
1723 static void gt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1727 uint64_t offset
= timeridx
== GTIMER_VIRT
? env
->cp15
.cntvoff_el2
: 0;
1729 trace_arm_gt_tval_write(timeridx
, value
);
1730 env
->cp15
.c14_timer
[timeridx
].cval
= gt_get_countervalue(env
) - offset
+
1731 sextract64(value
, 0, 32);
1732 gt_recalc_timer(arm_env_get_cpu(env
), timeridx
);
1735 static void gt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1739 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1740 uint32_t oldval
= env
->cp15
.c14_timer
[timeridx
].ctl
;
1742 trace_arm_gt_ctl_write(timeridx
, value
);
1743 env
->cp15
.c14_timer
[timeridx
].ctl
= deposit64(oldval
, 0, 2, value
);
1744 if ((oldval
^ value
) & 1) {
1745 /* Enable toggled */
1746 gt_recalc_timer(cpu
, timeridx
);
1747 } else if ((oldval
^ value
) & 2) {
1748 /* IMASK toggled: don't need to recalculate,
1749 * just set the interrupt line based on ISTATUS
1751 int irqstate
= (oldval
& 4) && !(value
& 2);
1753 trace_arm_gt_imask_toggle(timeridx
, irqstate
);
1754 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
1758 static void gt_phys_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1760 gt_timer_reset(env
, ri
, GTIMER_PHYS
);
1763 static void gt_phys_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1766 gt_cval_write(env
, ri
, GTIMER_PHYS
, value
);
1769 static uint64_t gt_phys_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1771 return gt_tval_read(env
, ri
, GTIMER_PHYS
);
1774 static void gt_phys_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1777 gt_tval_write(env
, ri
, GTIMER_PHYS
, value
);
1780 static void gt_phys_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1783 gt_ctl_write(env
, ri
, GTIMER_PHYS
, value
);
1786 static void gt_virt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1788 gt_timer_reset(env
, ri
, GTIMER_VIRT
);
1791 static void gt_virt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1794 gt_cval_write(env
, ri
, GTIMER_VIRT
, value
);
1797 static uint64_t gt_virt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1799 return gt_tval_read(env
, ri
, GTIMER_VIRT
);
1802 static void gt_virt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1805 gt_tval_write(env
, ri
, GTIMER_VIRT
, value
);
1808 static void gt_virt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1811 gt_ctl_write(env
, ri
, GTIMER_VIRT
, value
);
1814 static void gt_cntvoff_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1817 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1819 trace_arm_gt_cntvoff_write(value
);
1820 raw_write(env
, ri
, value
);
1821 gt_recalc_timer(cpu
, GTIMER_VIRT
);
1824 static void gt_hyp_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1826 gt_timer_reset(env
, ri
, GTIMER_HYP
);
1829 static void gt_hyp_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1832 gt_cval_write(env
, ri
, GTIMER_HYP
, value
);
1835 static uint64_t gt_hyp_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1837 return gt_tval_read(env
, ri
, GTIMER_HYP
);
1840 static void gt_hyp_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1843 gt_tval_write(env
, ri
, GTIMER_HYP
, value
);
1846 static void gt_hyp_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1849 gt_ctl_write(env
, ri
, GTIMER_HYP
, value
);
1852 static void gt_sec_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1854 gt_timer_reset(env
, ri
, GTIMER_SEC
);
1857 static void gt_sec_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1860 gt_cval_write(env
, ri
, GTIMER_SEC
, value
);
1863 static uint64_t gt_sec_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1865 return gt_tval_read(env
, ri
, GTIMER_SEC
);
1868 static void gt_sec_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1871 gt_tval_write(env
, ri
, GTIMER_SEC
, value
);
1874 static void gt_sec_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1877 gt_ctl_write(env
, ri
, GTIMER_SEC
, value
);
1880 void arm_gt_ptimer_cb(void *opaque
)
1882 ARMCPU
*cpu
= opaque
;
1884 gt_recalc_timer(cpu
, GTIMER_PHYS
);
1887 void arm_gt_vtimer_cb(void *opaque
)
1889 ARMCPU
*cpu
= opaque
;
1891 gt_recalc_timer(cpu
, GTIMER_VIRT
);
1894 void arm_gt_htimer_cb(void *opaque
)
1896 ARMCPU
*cpu
= opaque
;
1898 gt_recalc_timer(cpu
, GTIMER_HYP
);
1901 void arm_gt_stimer_cb(void *opaque
)
1903 ARMCPU
*cpu
= opaque
;
1905 gt_recalc_timer(cpu
, GTIMER_SEC
);
1908 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
1909 /* Note that CNTFRQ is purely reads-as-written for the benefit
1910 * of software; writing it doesn't actually change the timer frequency.
1911 * Our reset value matches the fixed frequency we implement the timer at.
1913 { .name
= "CNTFRQ", .cp
= 15, .crn
= 14, .crm
= 0, .opc1
= 0, .opc2
= 0,
1914 .type
= ARM_CP_ALIAS
,
1915 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
1916 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c14_cntfrq
),
1918 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
1919 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
1920 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
1921 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
1922 .resetvalue
= (1000 * 1000 * 1000) / GTIMER_SCALE
,
1924 /* overall control: mostly access permissions */
1925 { .name
= "CNTKCTL", .state
= ARM_CP_STATE_BOTH
,
1926 .opc0
= 3, .opc1
= 0, .crn
= 14, .crm
= 1, .opc2
= 0,
1928 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntkctl
),
1931 /* per-timer control */
1932 { .name
= "CNTP_CTL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
1933 .secure
= ARM_CP_SECSTATE_NS
,
1934 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL1_RW
| PL0_R
,
1935 .accessfn
= gt_ptimer_access
,
1936 .fieldoffset
= offsetoflow32(CPUARMState
,
1937 cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
1938 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
,
1940 { .name
= "CNTP_CTL(S)",
1941 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
1942 .secure
= ARM_CP_SECSTATE_S
,
1943 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL1_RW
| PL0_R
,
1944 .accessfn
= gt_ptimer_access
,
1945 .fieldoffset
= offsetoflow32(CPUARMState
,
1946 cp15
.c14_timer
[GTIMER_SEC
].ctl
),
1947 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
1949 { .name
= "CNTP_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
1950 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 1,
1951 .type
= ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1952 .accessfn
= gt_ptimer_access
,
1953 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
1955 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
,
1957 { .name
= "CNTV_CTL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 1,
1958 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL1_RW
| PL0_R
,
1959 .accessfn
= gt_vtimer_access
,
1960 .fieldoffset
= offsetoflow32(CPUARMState
,
1961 cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
1962 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
,
1964 { .name
= "CNTV_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
1965 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 1,
1966 .type
= ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1967 .accessfn
= gt_vtimer_access
,
1968 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
1970 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
,
1972 /* TimerValue views: a 32 bit downcounting view of the underlying state */
1973 { .name
= "CNTP_TVAL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
1974 .secure
= ARM_CP_SECSTATE_NS
,
1975 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1976 .accessfn
= gt_ptimer_access
,
1977 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
,
1979 { .name
= "CNTP_TVAL(S)",
1980 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
1981 .secure
= ARM_CP_SECSTATE_S
,
1982 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1983 .accessfn
= gt_ptimer_access
,
1984 .readfn
= gt_sec_tval_read
, .writefn
= gt_sec_tval_write
,
1986 { .name
= "CNTP_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
1987 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 0,
1988 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1989 .accessfn
= gt_ptimer_access
, .resetfn
= gt_phys_timer_reset
,
1990 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
,
1992 { .name
= "CNTV_TVAL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 0,
1993 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1994 .accessfn
= gt_vtimer_access
,
1995 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
,
1997 { .name
= "CNTV_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
1998 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 0,
1999 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
2000 .accessfn
= gt_vtimer_access
, .resetfn
= gt_virt_timer_reset
,
2001 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
,
2003 /* The counter itself */
2004 { .name
= "CNTPCT", .cp
= 15, .crm
= 14, .opc1
= 0,
2005 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
2006 .accessfn
= gt_pct_access
,
2007 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
2009 { .name
= "CNTPCT_EL0", .state
= ARM_CP_STATE_AA64
,
2010 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 1,
2011 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2012 .accessfn
= gt_pct_access
, .readfn
= gt_cnt_read
,
2014 { .name
= "CNTVCT", .cp
= 15, .crm
= 14, .opc1
= 1,
2015 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
2016 .accessfn
= gt_vct_access
,
2017 .readfn
= gt_virt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
2019 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
2020 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
2021 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2022 .accessfn
= gt_vct_access
, .readfn
= gt_virt_cnt_read
,
2024 /* Comparison value, indicating when the timer goes off */
2025 { .name
= "CNTP_CVAL", .cp
= 15, .crm
= 14, .opc1
= 2,
2026 .secure
= ARM_CP_SECSTATE_NS
,
2027 .access
= PL1_RW
| PL0_R
,
2028 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
2029 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
2030 .accessfn
= gt_ptimer_access
,
2031 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
,
2033 { .name
= "CNTP_CVAL(S)", .cp
= 15, .crm
= 14, .opc1
= 2,
2034 .secure
= ARM_CP_SECSTATE_S
,
2035 .access
= PL1_RW
| PL0_R
,
2036 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
2037 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
2038 .accessfn
= gt_ptimer_access
,
2039 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
2041 { .name
= "CNTP_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2042 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 2,
2043 .access
= PL1_RW
| PL0_R
,
2045 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
2046 .resetvalue
= 0, .accessfn
= gt_ptimer_access
,
2047 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
,
2049 { .name
= "CNTV_CVAL", .cp
= 15, .crm
= 14, .opc1
= 3,
2050 .access
= PL1_RW
| PL0_R
,
2051 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
2052 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
2053 .accessfn
= gt_vtimer_access
,
2054 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
,
2056 { .name
= "CNTV_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2057 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 2,
2058 .access
= PL1_RW
| PL0_R
,
2060 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
2061 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
2062 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
,
2064 /* Secure timer -- this is actually restricted to only EL3
2065 * and configurably Secure-EL1 via the accessfn.
2067 { .name
= "CNTPS_TVAL_EL1", .state
= ARM_CP_STATE_AA64
,
2068 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 0,
2069 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
,
2070 .accessfn
= gt_stimer_access
,
2071 .readfn
= gt_sec_tval_read
,
2072 .writefn
= gt_sec_tval_write
,
2073 .resetfn
= gt_sec_timer_reset
,
2075 { .name
= "CNTPS_CTL_EL1", .state
= ARM_CP_STATE_AA64
,
2076 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 1,
2077 .type
= ARM_CP_IO
, .access
= PL1_RW
,
2078 .accessfn
= gt_stimer_access
,
2079 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].ctl
),
2081 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
2083 { .name
= "CNTPS_CVAL_EL1", .state
= ARM_CP_STATE_AA64
,
2084 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 2,
2085 .type
= ARM_CP_IO
, .access
= PL1_RW
,
2086 .accessfn
= gt_stimer_access
,
2087 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
2088 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
2094 /* In user-mode none of the generic timer registers are accessible,
2095 * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
2096 * so instead just don't register any of them.
2098 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
2104 static void par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
2106 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
2107 raw_write(env
, ri
, value
);
2108 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
2109 raw_write(env
, ri
, value
& 0xfffff6ff);
2111 raw_write(env
, ri
, value
& 0xfffff1ff);
2115 #ifndef CONFIG_USER_ONLY
2116 /* get_phys_addr() isn't present for user-mode-only targets */
2118 static CPAccessResult
ats_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2122 /* The ATS12NSO* operations must trap to EL3 if executed in
2123 * Secure EL1 (which can only happen if EL3 is AArch64).
2124 * They are simply UNDEF if executed from NS EL1.
2125 * They function normally from EL2 or EL3.
2127 if (arm_current_el(env
) == 1) {
2128 if (arm_is_secure_below_el3(env
)) {
2129 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3
;
2131 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2134 return CP_ACCESS_OK
;
2137 static uint64_t do_ats_write(CPUARMState
*env
, uint64_t value
,
2138 MMUAccessType access_type
, ARMMMUIdx mmu_idx
)
2141 target_ulong page_size
;
2146 MemTxAttrs attrs
= {};
2147 ARMMMUFaultInfo fi
= {};
2149 ret
= get_phys_addr(env
, value
, access_type
, mmu_idx
,
2150 &phys_addr
, &attrs
, &prot
, &page_size
, &fsr
, &fi
);
2151 if (extended_addresses_enabled(env
)) {
2152 /* fsr is a DFSR/IFSR value for the long descriptor
2153 * translation table format, but with WnR always clear.
2154 * Convert it to a 64-bit PAR.
2156 par64
= (1 << 11); /* LPAE bit always set */
2158 par64
|= phys_addr
& ~0xfffULL
;
2159 if (!attrs
.secure
) {
2160 par64
|= (1 << 9); /* NS */
2162 /* We don't set the ATTR or SH fields in the PAR. */
2165 par64
|= (fsr
& 0x3f) << 1; /* FS */
2166 /* Note that S2WLK and FSTAGE are always zero, because we don't
2167 * implement virtualization and therefore there can't be a stage 2
2172 /* fsr is a DFSR/IFSR value for the short descriptor
2173 * translation table format (with WnR always clear).
2174 * Convert it to a 32-bit PAR.
2177 /* We do not set any attribute bits in the PAR */
2178 if (page_size
== (1 << 24)
2179 && arm_feature(env
, ARM_FEATURE_V7
)) {
2180 par64
= (phys_addr
& 0xff000000) | (1 << 1);
2182 par64
= phys_addr
& 0xfffff000;
2184 if (!attrs
.secure
) {
2185 par64
|= (1 << 9); /* NS */
2188 par64
= ((fsr
& (1 << 10)) >> 5) | ((fsr
& (1 << 12)) >> 6) |
2189 ((fsr
& 0xf) << 1) | 1;
2195 static void ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
2197 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
2200 int el
= arm_current_el(env
);
2201 bool secure
= arm_is_secure_below_el3(env
);
2203 switch (ri
->opc2
& 6) {
2205 /* stage 1 current state PL1: ATS1CPR, ATS1CPW */
2208 mmu_idx
= ARMMMUIdx_S1E3
;
2211 mmu_idx
= ARMMMUIdx_S1NSE1
;
2214 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S1NSE1
;
2217 g_assert_not_reached();
2221 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
2224 mmu_idx
= ARMMMUIdx_S1SE0
;
2227 mmu_idx
= ARMMMUIdx_S1NSE0
;
2230 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S1NSE0
;
2233 g_assert_not_reached();
2237 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
2238 mmu_idx
= ARMMMUIdx_S12NSE1
;
2241 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
2242 mmu_idx
= ARMMMUIdx_S12NSE0
;
2245 g_assert_not_reached();
2248 par64
= do_ats_write(env
, value
, access_type
, mmu_idx
);
2250 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
2253 static void ats1h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2256 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
2259 par64
= do_ats_write(env
, value
, access_type
, ARMMMUIdx_S2NS
);
2261 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
2264 static CPAccessResult
at_s1e2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2267 if (arm_current_el(env
) == 3 && !(env
->cp15
.scr_el3
& SCR_NS
)) {
2268 return CP_ACCESS_TRAP
;
2270 return CP_ACCESS_OK
;
2273 static void ats_write64(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2276 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
2278 int secure
= arm_is_secure_below_el3(env
);
2280 switch (ri
->opc2
& 6) {
2283 case 0: /* AT S1E1R, AT S1E1W */
2284 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S1NSE1
;
2286 case 4: /* AT S1E2R, AT S1E2W */
2287 mmu_idx
= ARMMMUIdx_S1E2
;
2289 case 6: /* AT S1E3R, AT S1E3W */
2290 mmu_idx
= ARMMMUIdx_S1E3
;
2293 g_assert_not_reached();
2296 case 2: /* AT S1E0R, AT S1E0W */
2297 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S1NSE0
;
2299 case 4: /* AT S12E1R, AT S12E1W */
2300 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S12NSE1
;
2302 case 6: /* AT S12E0R, AT S12E0W */
2303 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S12NSE0
;
2306 g_assert_not_reached();
2309 env
->cp15
.par_el
[1] = do_ats_write(env
, value
, access_type
, mmu_idx
);
2313 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
2314 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
2315 .access
= PL1_RW
, .resetvalue
= 0,
2316 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.par_s
),
2317 offsetoflow32(CPUARMState
, cp15
.par_ns
) },
2318 .writefn
= par_write
},
2319 #ifndef CONFIG_USER_ONLY
2320 /* This underdecoding is safe because the reginfo is NO_RAW. */
2321 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
2322 .access
= PL1_W
, .accessfn
= ats_access
,
2323 .writefn
= ats_write
, .type
= ARM_CP_NO_RAW
},
2328 /* Return basic MPU access permission bits. */
2329 static uint32_t simple_mpu_ap_bits(uint32_t val
)
2336 for (i
= 0; i
< 16; i
+= 2) {
2337 ret
|= (val
>> i
) & mask
;
2343 /* Pad basic MPU access permission bits to extended format. */
2344 static uint32_t extended_mpu_ap_bits(uint32_t val
)
2351 for (i
= 0; i
< 16; i
+= 2) {
2352 ret
|= (val
& mask
) << i
;
2358 static void pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2361 env
->cp15
.pmsav5_data_ap
= extended_mpu_ap_bits(value
);
2364 static uint64_t pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2366 return simple_mpu_ap_bits(env
->cp15
.pmsav5_data_ap
);
2369 static void pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2372 env
->cp15
.pmsav5_insn_ap
= extended_mpu_ap_bits(value
);
2375 static uint64_t pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2377 return simple_mpu_ap_bits(env
->cp15
.pmsav5_insn_ap
);
2380 static uint64_t pmsav7_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2382 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
2388 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
2392 static void pmsav7_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2395 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2396 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
2402 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
2403 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
2407 static void pmsav7_rgnr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2410 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2411 uint32_t nrgs
= cpu
->pmsav7_dregion
;
2413 if (value
>= nrgs
) {
2414 qemu_log_mask(LOG_GUEST_ERROR
,
2415 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
2416 " > %" PRIu32
"\n", (uint32_t)value
, nrgs
);
2420 raw_write(env
, ri
, value
);
2423 static const ARMCPRegInfo pmsav7_cp_reginfo
[] = {
2424 /* Reset for all these registers is handled in arm_cpu_reset(),
2425 * because the PMSAv7 is also used by M-profile CPUs, which do
2426 * not register cpregs but still need the state to be reset.
2428 { .name
= "DRBAR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 0,
2429 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
2430 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drbar
),
2431 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
2432 .resetfn
= arm_cp_reset_ignore
},
2433 { .name
= "DRSR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 2,
2434 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
2435 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drsr
),
2436 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
2437 .resetfn
= arm_cp_reset_ignore
},
2438 { .name
= "DRACR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 4,
2439 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
2440 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.dracr
),
2441 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
2442 .resetfn
= arm_cp_reset_ignore
},
2443 { .name
= "RGNR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 2, .opc2
= 0,
2445 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]),
2446 .writefn
= pmsav7_rgnr_write
,
2447 .resetfn
= arm_cp_reset_ignore
},
2451 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
2452 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
2453 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
2454 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
2455 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
2456 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
2457 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
2458 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
2459 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
2460 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
2462 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
2464 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
2466 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
2468 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
2470 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
2471 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
2473 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
2474 /* Protection region base and size registers */
2475 { .name
= "946_PRBS0", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0,
2476 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2477 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[0]) },
2478 { .name
= "946_PRBS1", .cp
= 15, .crn
= 6, .crm
= 1, .opc1
= 0,
2479 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2480 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[1]) },
2481 { .name
= "946_PRBS2", .cp
= 15, .crn
= 6, .crm
= 2, .opc1
= 0,
2482 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2483 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[2]) },
2484 { .name
= "946_PRBS3", .cp
= 15, .crn
= 6, .crm
= 3, .opc1
= 0,
2485 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2486 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[3]) },
2487 { .name
= "946_PRBS4", .cp
= 15, .crn
= 6, .crm
= 4, .opc1
= 0,
2488 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2489 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[4]) },
2490 { .name
= "946_PRBS5", .cp
= 15, .crn
= 6, .crm
= 5, .opc1
= 0,
2491 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2492 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[5]) },
2493 { .name
= "946_PRBS6", .cp
= 15, .crn
= 6, .crm
= 6, .opc1
= 0,
2494 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2495 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[6]) },
2496 { .name
= "946_PRBS7", .cp
= 15, .crn
= 6, .crm
= 7, .opc1
= 0,
2497 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2498 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[7]) },
2502 static void vmsa_ttbcr_raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2505 TCR
*tcr
= raw_ptr(env
, ri
);
2506 int maskshift
= extract32(value
, 0, 3);
2508 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
2509 if (arm_feature(env
, ARM_FEATURE_LPAE
) && (value
& TTBCR_EAE
)) {
2510 /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
2511 * using Long-desciptor translation table format */
2512 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
2513 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
2514 /* In an implementation that includes the Security Extensions
2515 * TTBCR has additional fields PD0 [4] and PD1 [5] for
2516 * Short-descriptor translation table format.
2518 value
&= TTBCR_PD1
| TTBCR_PD0
| TTBCR_N
;
2524 /* Update the masks corresponding to the TCR bank being written
2525 * Note that we always calculate mask and base_mask, but
2526 * they are only used for short-descriptor tables (ie if EAE is 0);
2527 * for long-descriptor tables the TCR fields are used differently
2528 * and the mask and base_mask values are meaningless.
2530 tcr
->raw_tcr
= value
;
2531 tcr
->mask
= ~(((uint32_t)0xffffffffu
) >> maskshift
);
2532 tcr
->base_mask
= ~((uint32_t)0x3fffu
>> maskshift
);
2535 static void vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2538 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2540 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
2541 /* With LPAE the TTBCR could result in a change of ASID
2542 * via the TTBCR.A1 bit, so do a TLB flush.
2544 tlb_flush(CPU(cpu
));
2546 vmsa_ttbcr_raw_write(env
, ri
, value
);
2549 static void vmsa_ttbcr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2551 TCR
*tcr
= raw_ptr(env
, ri
);
2553 /* Reset both the TCR as well as the masks corresponding to the bank of
2554 * the TCR being reset.
2558 tcr
->base_mask
= 0xffffc000u
;
2561 static void vmsa_tcr_el1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2564 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2565 TCR
*tcr
= raw_ptr(env
, ri
);
2567 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
2568 tlb_flush(CPU(cpu
));
2569 tcr
->raw_tcr
= value
;
2572 static void vmsa_ttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2575 /* 64 bit accesses to the TTBRs can change the ASID and so we
2576 * must flush the TLB.
2578 if (cpreg_field_is_64bit(ri
)) {
2579 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2581 tlb_flush(CPU(cpu
));
2583 raw_write(env
, ri
, value
);
2586 static void vttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2589 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2590 CPUState
*cs
= CPU(cpu
);
2592 /* Accesses to VTTBR may change the VMID so we must flush the TLB. */
2593 if (raw_read(env
, ri
) != value
) {
2594 tlb_flush_by_mmuidx(cs
,
2595 ARMMMUIdxBit_S12NSE1
|
2596 ARMMMUIdxBit_S12NSE0
|
2598 raw_write(env
, ri
, value
);
2602 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo
[] = {
2603 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
2604 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
2605 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dfsr_s
),
2606 offsetoflow32(CPUARMState
, cp15
.dfsr_ns
) }, },
2607 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
2608 .access
= PL1_RW
, .resetvalue
= 0,
2609 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.ifsr_s
),
2610 offsetoflow32(CPUARMState
, cp15
.ifsr_ns
) } },
2611 { .name
= "DFAR", .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 0, .opc2
= 0,
2612 .access
= PL1_RW
, .resetvalue
= 0,
2613 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.dfar_s
),
2614 offsetof(CPUARMState
, cp15
.dfar_ns
) } },
2615 { .name
= "FAR_EL1", .state
= ARM_CP_STATE_AA64
,
2616 .opc0
= 3, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
2617 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[1]),
2622 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
2623 { .name
= "ESR_EL1", .state
= ARM_CP_STATE_AA64
,
2624 .opc0
= 3, .crn
= 5, .crm
= 2, .opc1
= 0, .opc2
= 0,
2626 .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[1]), .resetvalue
= 0, },
2627 { .name
= "TTBR0_EL1", .state
= ARM_CP_STATE_BOTH
,
2628 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 0,
2629 .access
= PL1_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
2630 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
2631 offsetof(CPUARMState
, cp15
.ttbr0_ns
) } },
2632 { .name
= "TTBR1_EL1", .state
= ARM_CP_STATE_BOTH
,
2633 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 1,
2634 .access
= PL1_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
2635 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
2636 offsetof(CPUARMState
, cp15
.ttbr1_ns
) } },
2637 { .name
= "TCR_EL1", .state
= ARM_CP_STATE_AA64
,
2638 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
2639 .access
= PL1_RW
, .writefn
= vmsa_tcr_el1_write
,
2640 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= raw_write
,
2641 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[1]) },
2642 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
2643 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
, .writefn
= vmsa_ttbcr_write
,
2644 .raw_writefn
= vmsa_ttbcr_raw_write
,
2645 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tcr_el
[3]),
2646 offsetoflow32(CPUARMState
, cp15
.tcr_el
[1])} },
2650 static void omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2653 env
->cp15
.c15_ticonfig
= value
& 0xe7;
2654 /* The OS_TYPE bit in this register changes the reported CPUID! */
2655 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
2656 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
2659 static void omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2662 env
->cp15
.c15_threadid
= value
& 0xffff;
2665 static void omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2668 /* Wait-for-interrupt (deprecated) */
2669 cpu_interrupt(CPU(arm_env_get_cpu(env
)), CPU_INTERRUPT_HALT
);
2672 static void omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2675 /* On OMAP there are registers indicating the max/min index of dcache lines
2676 * containing a dirty line; cache flush operations have to reset these.
2678 env
->cp15
.c15_i_max
= 0x000;
2679 env
->cp15
.c15_i_min
= 0xff0;
2682 static const ARMCPRegInfo omap_cp_reginfo
[] = {
2683 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
2684 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
2685 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.esr_el
[1]),
2687 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
2688 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
2689 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
2691 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
2692 .writefn
= omap_ticonfig_write
},
2693 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
2695 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
2696 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
2697 .access
= PL1_RW
, .resetvalue
= 0xff0,
2698 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
2699 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
2701 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
2702 .writefn
= omap_threadid_write
},
2703 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
2704 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
2705 .type
= ARM_CP_NO_RAW
,
2706 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
2707 /* TODO: Peripheral port remap register:
2708 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
2709 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
2712 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
2713 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
2714 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
,
2715 .writefn
= omap_cachemaint_write
},
2716 { .name
= "C9", .cp
= 15, .crn
= 9,
2717 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
2718 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
2722 static void xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2725 env
->cp15
.c15_cpar
= value
& 0x3fff;
2728 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
2729 { .name
= "XSCALE_CPAR",
2730 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
2731 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
2732 .writefn
= xscale_cpar_write
, },
2733 { .name
= "XSCALE_AUXCR",
2734 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
2735 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
2737 /* XScale specific cache-lockdown: since we have no cache we NOP these
2738 * and hope the guest does not really rely on cache behaviour.
2740 { .name
= "XSCALE_LOCK_ICACHE_LINE",
2741 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
2742 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2743 { .name
= "XSCALE_UNLOCK_ICACHE",
2744 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
2745 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2746 { .name
= "XSCALE_DCACHE_LOCK",
2747 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 0,
2748 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
2749 { .name
= "XSCALE_UNLOCK_DCACHE",
2750 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 1,
2751 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2755 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
2756 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
2757 * implementation of this implementation-defined space.
2758 * Ideally this should eventually disappear in favour of actually
2759 * implementing the correct behaviour for all cores.
2761 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
2762 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
2764 .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
| ARM_CP_OVERRIDE
,
2769 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
2770 /* Cache status: RAZ because we have no cache so it's always clean */
2771 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
2772 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2777 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
2778 /* We never have a a block transfer operation in progress */
2779 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
2780 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2782 /* The cache ops themselves: these all NOP for QEMU */
2783 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
2784 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2785 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
2786 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2787 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
2788 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2789 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
2790 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2791 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
2792 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2793 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
2794 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2798 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
2799 /* The cache test-and-clean instructions always return (1 << 30)
2800 * to indicate that there are no dirty cache lines.
2802 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
2803 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2804 .resetvalue
= (1 << 30) },
2805 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
2806 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2807 .resetvalue
= (1 << 30) },
2811 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
2812 /* Ignore ReadBuffer accesses */
2813 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
2814 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
2815 .access
= PL1_RW
, .resetvalue
= 0,
2816 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
},
2820 static uint64_t midr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2822 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2823 unsigned int cur_el
= arm_current_el(env
);
2824 bool secure
= arm_is_secure(env
);
2826 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
) && !secure
&& cur_el
== 1) {
2827 return env
->cp15
.vpidr_el2
;
2829 return raw_read(env
, ri
);
2832 static uint64_t mpidr_read_val(CPUARMState
*env
)
2834 ARMCPU
*cpu
= ARM_CPU(arm_env_get_cpu(env
));
2835 uint64_t mpidr
= cpu
->mp_affinity
;
2837 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
2838 mpidr
|= (1U << 31);
2839 /* Cores which are uniprocessor (non-coherent)
2840 * but still implement the MP extensions set
2841 * bit 30. (For instance, Cortex-R5).
2843 if (cpu
->mp_is_up
) {
2844 mpidr
|= (1u << 30);
2850 static uint64_t mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2852 unsigned int cur_el
= arm_current_el(env
);
2853 bool secure
= arm_is_secure(env
);
2855 if (arm_feature(env
, ARM_FEATURE_EL2
) && !secure
&& cur_el
== 1) {
2856 return env
->cp15
.vmpidr_el2
;
2858 return mpidr_read_val(env
);
2861 static const ARMCPRegInfo mpidr_cp_reginfo
[] = {
2862 { .name
= "MPIDR", .state
= ARM_CP_STATE_BOTH
,
2863 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
2864 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_RAW
},
2868 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
2870 { .name
= "AMAIR0", .state
= ARM_CP_STATE_BOTH
,
2871 .opc0
= 3, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
2872 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
2874 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
2875 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
2876 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
2878 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
2879 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .resetvalue
= 0,
2880 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.par_s
),
2881 offsetof(CPUARMState
, cp15
.par_ns
)} },
2882 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
2883 .access
= PL1_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
2884 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
2885 offsetof(CPUARMState
, cp15
.ttbr0_ns
) },
2886 .writefn
= vmsa_ttbr_write
, },
2887 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
2888 .access
= PL1_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
2889 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
2890 offsetof(CPUARMState
, cp15
.ttbr1_ns
) },
2891 .writefn
= vmsa_ttbr_write
, },
2895 static uint64_t aa64_fpcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2897 return vfp_get_fpcr(env
);
2900 static void aa64_fpcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2903 vfp_set_fpcr(env
, value
);
2906 static uint64_t aa64_fpsr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2908 return vfp_get_fpsr(env
);
2911 static void aa64_fpsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2914 vfp_set_fpsr(env
, value
);
2917 static CPAccessResult
aa64_daif_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2920 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UMA
)) {
2921 return CP_ACCESS_TRAP
;
2923 return CP_ACCESS_OK
;
2926 static void aa64_daif_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2929 env
->daif
= value
& PSTATE_DAIF
;
2932 static CPAccessResult
aa64_cacheop_access(CPUARMState
*env
,
2933 const ARMCPRegInfo
*ri
,
2936 /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
2937 * SCTLR_EL1.UCI is set.
2939 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UCI
)) {
2940 return CP_ACCESS_TRAP
;
2942 return CP_ACCESS_OK
;
2945 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
2946 * Page D4-1736 (DDI0487A.b)
2949 static void tlbi_aa64_vmalle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2952 CPUState
*cs
= ENV_GET_CPU(env
);
2954 if (arm_is_secure_below_el3(env
)) {
2955 tlb_flush_by_mmuidx(cs
,
2956 ARMMMUIdxBit_S1SE1
|
2957 ARMMMUIdxBit_S1SE0
);
2959 tlb_flush_by_mmuidx(cs
,
2960 ARMMMUIdxBit_S12NSE1
|
2961 ARMMMUIdxBit_S12NSE0
);
2965 static void tlbi_aa64_vmalle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2968 CPUState
*cs
= ENV_GET_CPU(env
);
2969 bool sec
= arm_is_secure_below_el3(env
);
2972 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
2973 ARMMMUIdxBit_S1SE1
|
2974 ARMMMUIdxBit_S1SE0
);
2976 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
2977 ARMMMUIdxBit_S12NSE1
|
2978 ARMMMUIdxBit_S12NSE0
);
2982 static void tlbi_aa64_alle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2985 /* Note that the 'ALL' scope must invalidate both stage 1 and
2986 * stage 2 translations, whereas most other scopes only invalidate
2987 * stage 1 translations.
2989 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2990 CPUState
*cs
= CPU(cpu
);
2992 if (arm_is_secure_below_el3(env
)) {
2993 tlb_flush_by_mmuidx(cs
,
2994 ARMMMUIdxBit_S1SE1
|
2995 ARMMMUIdxBit_S1SE0
);
2997 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
2998 tlb_flush_by_mmuidx(cs
,
2999 ARMMMUIdxBit_S12NSE1
|
3000 ARMMMUIdxBit_S12NSE0
|
3003 tlb_flush_by_mmuidx(cs
,
3004 ARMMMUIdxBit_S12NSE1
|
3005 ARMMMUIdxBit_S12NSE0
);
3010 static void tlbi_aa64_alle2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3013 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3014 CPUState
*cs
= CPU(cpu
);
3016 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_S1E2
);
3019 static void tlbi_aa64_alle3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3022 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3023 CPUState
*cs
= CPU(cpu
);
3025 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_S1E3
);
3028 static void tlbi_aa64_alle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3031 /* Note that the 'ALL' scope must invalidate both stage 1 and
3032 * stage 2 translations, whereas most other scopes only invalidate
3033 * stage 1 translations.
3035 CPUState
*cs
= ENV_GET_CPU(env
);
3036 bool sec
= arm_is_secure_below_el3(env
);
3037 bool has_el2
= arm_feature(env
, ARM_FEATURE_EL2
);
3040 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3041 ARMMMUIdxBit_S1SE1
|
3042 ARMMMUIdxBit_S1SE0
);
3043 } else if (has_el2
) {
3044 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3045 ARMMMUIdxBit_S12NSE1
|
3046 ARMMMUIdxBit_S12NSE0
|
3049 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3050 ARMMMUIdxBit_S12NSE1
|
3051 ARMMMUIdxBit_S12NSE0
);
3055 static void tlbi_aa64_alle2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3058 CPUState
*cs
= ENV_GET_CPU(env
);
3060 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_S1E2
);
3063 static void tlbi_aa64_alle3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3066 CPUState
*cs
= ENV_GET_CPU(env
);
3068 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_S1E3
);
3071 static void tlbi_aa64_vae1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3074 /* Invalidate by VA, EL1&0 (AArch64 version).
3075 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
3076 * since we don't support flush-for-specific-ASID-only or
3077 * flush-last-level-only.
3079 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3080 CPUState
*cs
= CPU(cpu
);
3081 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3083 if (arm_is_secure_below_el3(env
)) {
3084 tlb_flush_page_by_mmuidx(cs
, pageaddr
,
3085 ARMMMUIdxBit_S1SE1
|
3086 ARMMMUIdxBit_S1SE0
);
3088 tlb_flush_page_by_mmuidx(cs
, pageaddr
,
3089 ARMMMUIdxBit_S12NSE1
|
3090 ARMMMUIdxBit_S12NSE0
);
3094 static void tlbi_aa64_vae2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3097 /* Invalidate by VA, EL2
3098 * Currently handles both VAE2 and VALE2, since we don't support
3099 * flush-last-level-only.
3101 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3102 CPUState
*cs
= CPU(cpu
);
3103 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3105 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S1E2
);
3108 static void tlbi_aa64_vae3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3111 /* Invalidate by VA, EL3
3112 * Currently handles both VAE3 and VALE3, since we don't support
3113 * flush-last-level-only.
3115 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3116 CPUState
*cs
= CPU(cpu
);
3117 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3119 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S1E3
);
3122 static void tlbi_aa64_vae1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3125 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3126 CPUState
*cs
= CPU(cpu
);
3127 bool sec
= arm_is_secure_below_el3(env
);
3128 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3131 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
3132 ARMMMUIdxBit_S1SE1
|
3133 ARMMMUIdxBit_S1SE0
);
3135 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
3136 ARMMMUIdxBit_S12NSE1
|
3137 ARMMMUIdxBit_S12NSE0
);
3141 static void tlbi_aa64_vae2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3144 CPUState
*cs
= ENV_GET_CPU(env
);
3145 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3147 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
3151 static void tlbi_aa64_vae3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3154 CPUState
*cs
= ENV_GET_CPU(env
);
3155 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3157 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
3161 static void tlbi_aa64_ipas2e1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3164 /* Invalidate by IPA. This has to invalidate any structures that
3165 * contain only stage 2 translation information, but does not need
3166 * to apply to structures that contain combined stage 1 and stage 2
3167 * translation information.
3168 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
3170 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3171 CPUState
*cs
= CPU(cpu
);
3174 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
3178 pageaddr
= sextract64(value
<< 12, 0, 48);
3180 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S2NS
);
3183 static void tlbi_aa64_ipas2e1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3186 CPUState
*cs
= ENV_GET_CPU(env
);
3189 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
3193 pageaddr
= sextract64(value
<< 12, 0, 48);
3195 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
3199 static CPAccessResult
aa64_zva_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3202 /* We don't implement EL2, so the only control on DC ZVA is the
3203 * bit in the SCTLR which can prohibit access for EL0.
3205 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_DZE
)) {
3206 return CP_ACCESS_TRAP
;
3208 return CP_ACCESS_OK
;
3211 static uint64_t aa64_dczid_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3213 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3214 int dzp_bit
= 1 << 4;
3216 /* DZP indicates whether DC ZVA access is allowed */
3217 if (aa64_zva_access(env
, NULL
, false) == CP_ACCESS_OK
) {
3220 return cpu
->dcz_blocksize
| dzp_bit
;
3223 static CPAccessResult
sp_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3226 if (!(env
->pstate
& PSTATE_SP
)) {
3227 /* Access to SP_EL0 is undefined if it's being used as
3228 * the stack pointer.
3230 return CP_ACCESS_TRAP_UNCATEGORIZED
;
3232 return CP_ACCESS_OK
;
3235 static uint64_t spsel_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3237 return env
->pstate
& PSTATE_SP
;
3240 static void spsel_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
3242 update_spsel(env
, val
);
3245 static void sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3248 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3250 if (raw_read(env
, ri
) == value
) {
3251 /* Skip the TLB flush if nothing actually changed; Linux likes
3252 * to do a lot of pointless SCTLR writes.
3257 if (arm_feature(env
, ARM_FEATURE_PMSA
) && !cpu
->has_mpu
) {
3258 /* M bit is RAZ/WI for PMSA with no MPU implemented */
3262 raw_write(env
, ri
, value
);
3263 /* ??? Lots of these bits are not implemented. */
3264 /* This may enable/disable the MMU, so do a TLB flush. */
3265 tlb_flush(CPU(cpu
));
3268 static CPAccessResult
fpexc32_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3271 if ((env
->cp15
.cptr_el
[2] & CPTR_TFP
) && arm_current_el(env
) == 2) {
3272 return CP_ACCESS_TRAP_FP_EL2
;
3274 if (env
->cp15
.cptr_el
[3] & CPTR_TFP
) {
3275 return CP_ACCESS_TRAP_FP_EL3
;
3277 return CP_ACCESS_OK
;
3280 static void sdcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3283 env
->cp15
.mdcr_el3
= value
& SDCR_VALID_MASK
;
3286 static const ARMCPRegInfo v8_cp_reginfo
[] = {
3287 /* Minimal set of EL0-visible registers. This will need to be expanded
3288 * significantly for system emulation of AArch64 CPUs.
3290 { .name
= "NZCV", .state
= ARM_CP_STATE_AA64
,
3291 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 2,
3292 .access
= PL0_RW
, .type
= ARM_CP_NZCV
},
3293 { .name
= "DAIF", .state
= ARM_CP_STATE_AA64
,
3294 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 2,
3295 .type
= ARM_CP_NO_RAW
,
3296 .access
= PL0_RW
, .accessfn
= aa64_daif_access
,
3297 .fieldoffset
= offsetof(CPUARMState
, daif
),
3298 .writefn
= aa64_daif_write
, .resetfn
= arm_cp_reset_ignore
},
3299 { .name
= "FPCR", .state
= ARM_CP_STATE_AA64
,
3300 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 4,
3301 .access
= PL0_RW
, .readfn
= aa64_fpcr_read
, .writefn
= aa64_fpcr_write
},
3302 { .name
= "FPSR", .state
= ARM_CP_STATE_AA64
,
3303 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 4,
3304 .access
= PL0_RW
, .readfn
= aa64_fpsr_read
, .writefn
= aa64_fpsr_write
},
3305 { .name
= "DCZID_EL0", .state
= ARM_CP_STATE_AA64
,
3306 .opc0
= 3, .opc1
= 3, .opc2
= 7, .crn
= 0, .crm
= 0,
3307 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
,
3308 .readfn
= aa64_dczid_read
},
3309 { .name
= "DC_ZVA", .state
= ARM_CP_STATE_AA64
,
3310 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 1,
3311 .access
= PL0_W
, .type
= ARM_CP_DC_ZVA
,
3312 #ifndef CONFIG_USER_ONLY
3313 /* Avoid overhead of an access check that always passes in user-mode */
3314 .accessfn
= aa64_zva_access
,
3317 { .name
= "CURRENTEL", .state
= ARM_CP_STATE_AA64
,
3318 .opc0
= 3, .opc1
= 0, .opc2
= 2, .crn
= 4, .crm
= 2,
3319 .access
= PL1_R
, .type
= ARM_CP_CURRENTEL
},
3320 /* Cache ops: all NOPs since we don't emulate caches */
3321 { .name
= "IC_IALLUIS", .state
= ARM_CP_STATE_AA64
,
3322 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
3323 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3324 { .name
= "IC_IALLU", .state
= ARM_CP_STATE_AA64
,
3325 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
3326 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3327 { .name
= "IC_IVAU", .state
= ARM_CP_STATE_AA64
,
3328 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 5, .opc2
= 1,
3329 .access
= PL0_W
, .type
= ARM_CP_NOP
,
3330 .accessfn
= aa64_cacheop_access
},
3331 { .name
= "DC_IVAC", .state
= ARM_CP_STATE_AA64
,
3332 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
3333 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3334 { .name
= "DC_ISW", .state
= ARM_CP_STATE_AA64
,
3335 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
3336 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3337 { .name
= "DC_CVAC", .state
= ARM_CP_STATE_AA64
,
3338 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 1,
3339 .access
= PL0_W
, .type
= ARM_CP_NOP
,
3340 .accessfn
= aa64_cacheop_access
},
3341 { .name
= "DC_CSW", .state
= ARM_CP_STATE_AA64
,
3342 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
3343 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3344 { .name
= "DC_CVAU", .state
= ARM_CP_STATE_AA64
,
3345 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 11, .opc2
= 1,
3346 .access
= PL0_W
, .type
= ARM_CP_NOP
,
3347 .accessfn
= aa64_cacheop_access
},
3348 { .name
= "DC_CIVAC", .state
= ARM_CP_STATE_AA64
,
3349 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 1,
3350 .access
= PL0_W
, .type
= ARM_CP_NOP
,
3351 .accessfn
= aa64_cacheop_access
},
3352 { .name
= "DC_CISW", .state
= ARM_CP_STATE_AA64
,
3353 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
3354 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3355 /* TLBI operations */
3356 { .name
= "TLBI_VMALLE1IS", .state
= ARM_CP_STATE_AA64
,
3357 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
3358 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3359 .writefn
= tlbi_aa64_vmalle1is_write
},
3360 { .name
= "TLBI_VAE1IS", .state
= ARM_CP_STATE_AA64
,
3361 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
3362 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3363 .writefn
= tlbi_aa64_vae1is_write
},
3364 { .name
= "TLBI_ASIDE1IS", .state
= ARM_CP_STATE_AA64
,
3365 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
3366 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3367 .writefn
= tlbi_aa64_vmalle1is_write
},
3368 { .name
= "TLBI_VAAE1IS", .state
= ARM_CP_STATE_AA64
,
3369 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
3370 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3371 .writefn
= tlbi_aa64_vae1is_write
},
3372 { .name
= "TLBI_VALE1IS", .state
= ARM_CP_STATE_AA64
,
3373 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
3374 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3375 .writefn
= tlbi_aa64_vae1is_write
},
3376 { .name
= "TLBI_VAALE1IS", .state
= ARM_CP_STATE_AA64
,
3377 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
3378 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3379 .writefn
= tlbi_aa64_vae1is_write
},
3380 { .name
= "TLBI_VMALLE1", .state
= ARM_CP_STATE_AA64
,
3381 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
3382 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3383 .writefn
= tlbi_aa64_vmalle1_write
},
3384 { .name
= "TLBI_VAE1", .state
= ARM_CP_STATE_AA64
,
3385 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
3386 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3387 .writefn
= tlbi_aa64_vae1_write
},
3388 { .name
= "TLBI_ASIDE1", .state
= ARM_CP_STATE_AA64
,
3389 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
3390 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3391 .writefn
= tlbi_aa64_vmalle1_write
},
3392 { .name
= "TLBI_VAAE1", .state
= ARM_CP_STATE_AA64
,
3393 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
3394 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3395 .writefn
= tlbi_aa64_vae1_write
},
3396 { .name
= "TLBI_VALE1", .state
= ARM_CP_STATE_AA64
,
3397 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
3398 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3399 .writefn
= tlbi_aa64_vae1_write
},
3400 { .name
= "TLBI_VAALE1", .state
= ARM_CP_STATE_AA64
,
3401 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
3402 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3403 .writefn
= tlbi_aa64_vae1_write
},
3404 { .name
= "TLBI_IPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
3405 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
3406 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3407 .writefn
= tlbi_aa64_ipas2e1is_write
},
3408 { .name
= "TLBI_IPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
3409 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
3410 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3411 .writefn
= tlbi_aa64_ipas2e1is_write
},
3412 { .name
= "TLBI_ALLE1IS", .state
= ARM_CP_STATE_AA64
,
3413 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
3414 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3415 .writefn
= tlbi_aa64_alle1is_write
},
3416 { .name
= "TLBI_VMALLS12E1IS", .state
= ARM_CP_STATE_AA64
,
3417 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 6,
3418 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3419 .writefn
= tlbi_aa64_alle1is_write
},
3420 { .name
= "TLBI_IPAS2E1", .state
= ARM_CP_STATE_AA64
,
3421 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
3422 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3423 .writefn
= tlbi_aa64_ipas2e1_write
},
3424 { .name
= "TLBI_IPAS2LE1", .state
= ARM_CP_STATE_AA64
,
3425 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
3426 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3427 .writefn
= tlbi_aa64_ipas2e1_write
},
3428 { .name
= "TLBI_ALLE1", .state
= ARM_CP_STATE_AA64
,
3429 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
3430 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3431 .writefn
= tlbi_aa64_alle1_write
},
3432 { .name
= "TLBI_VMALLS12E1", .state
= ARM_CP_STATE_AA64
,
3433 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 6,
3434 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3435 .writefn
= tlbi_aa64_alle1is_write
},
3436 #ifndef CONFIG_USER_ONLY
3437 /* 64 bit address translation operations */
3438 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
3439 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 0,
3440 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3441 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
3442 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 1,
3443 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3444 { .name
= "AT_S1E0R", .state
= ARM_CP_STATE_AA64
,
3445 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 2,
3446 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3447 { .name
= "AT_S1E0W", .state
= ARM_CP_STATE_AA64
,
3448 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 3,
3449 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3450 { .name
= "AT_S12E1R", .state
= ARM_CP_STATE_AA64
,
3451 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 4,
3452 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3453 { .name
= "AT_S12E1W", .state
= ARM_CP_STATE_AA64
,
3454 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 5,
3455 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3456 { .name
= "AT_S12E0R", .state
= ARM_CP_STATE_AA64
,
3457 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 6,
3458 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3459 { .name
= "AT_S12E0W", .state
= ARM_CP_STATE_AA64
,
3460 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 7,
3461 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3462 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
3463 { .name
= "AT_S1E3R", .state
= ARM_CP_STATE_AA64
,
3464 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 0,
3465 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3466 { .name
= "AT_S1E3W", .state
= ARM_CP_STATE_AA64
,
3467 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 1,
3468 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3469 { .name
= "PAR_EL1", .state
= ARM_CP_STATE_AA64
,
3470 .type
= ARM_CP_ALIAS
,
3471 .opc0
= 3, .opc1
= 0, .crn
= 7, .crm
= 4, .opc2
= 0,
3472 .access
= PL1_RW
, .resetvalue
= 0,
3473 .fieldoffset
= offsetof(CPUARMState
, cp15
.par_el
[1]),
3474 .writefn
= par_write
},
3476 /* TLB invalidate last level of translation table walk */
3477 { .name
= "TLBIMVALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
3478 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_is_write
},
3479 { .name
= "TLBIMVAALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
3480 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
3481 .writefn
= tlbimvaa_is_write
},
3482 { .name
= "TLBIMVAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
3483 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
3484 { .name
= "TLBIMVAAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
3485 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimvaa_write
},
3486 { .name
= "TLBIMVALH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
3487 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3488 .writefn
= tlbimva_hyp_write
},
3489 { .name
= "TLBIMVALHIS",
3490 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
3491 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3492 .writefn
= tlbimva_hyp_is_write
},
3493 { .name
= "TLBIIPAS2",
3494 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
3495 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3496 .writefn
= tlbiipas2_write
},
3497 { .name
= "TLBIIPAS2IS",
3498 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
3499 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3500 .writefn
= tlbiipas2_is_write
},
3501 { .name
= "TLBIIPAS2L",
3502 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
3503 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3504 .writefn
= tlbiipas2_write
},
3505 { .name
= "TLBIIPAS2LIS",
3506 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
3507 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3508 .writefn
= tlbiipas2_is_write
},
3509 /* 32 bit cache operations */
3510 { .name
= "ICIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
3511 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3512 { .name
= "BPIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 6,
3513 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3514 { .name
= "ICIALLU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
3515 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3516 { .name
= "ICIMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 1,
3517 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3518 { .name
= "BPIALL", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 6,
3519 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3520 { .name
= "BPIMVA", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 7,
3521 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3522 { .name
= "DCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
3523 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3524 { .name
= "DCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
3525 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3526 { .name
= "DCCMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 1,
3527 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3528 { .name
= "DCCSW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
3529 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3530 { .name
= "DCCMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 11, .opc2
= 1,
3531 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3532 { .name
= "DCCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 1,
3533 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3534 { .name
= "DCCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
3535 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3536 /* MMU Domain access control / MPU write buffer control */
3537 { .name
= "DACR", .cp
= 15, .opc1
= 0, .crn
= 3, .crm
= 0, .opc2
= 0,
3538 .access
= PL1_RW
, .resetvalue
= 0,
3539 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
3540 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
3541 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
3542 { .name
= "ELR_EL1", .state
= ARM_CP_STATE_AA64
,
3543 .type
= ARM_CP_ALIAS
,
3544 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 1,
3546 .fieldoffset
= offsetof(CPUARMState
, elr_el
[1]) },
3547 { .name
= "SPSR_EL1", .state
= ARM_CP_STATE_AA64
,
3548 .type
= ARM_CP_ALIAS
,
3549 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 0,
3551 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_SVC
]) },
3552 /* We rely on the access checks not allowing the guest to write to the
3553 * state field when SPSel indicates that it's being used as the stack
3556 { .name
= "SP_EL0", .state
= ARM_CP_STATE_AA64
,
3557 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 1, .opc2
= 0,
3558 .access
= PL1_RW
, .accessfn
= sp_el0_access
,
3559 .type
= ARM_CP_ALIAS
,
3560 .fieldoffset
= offsetof(CPUARMState
, sp_el
[0]) },
3561 { .name
= "SP_EL1", .state
= ARM_CP_STATE_AA64
,
3562 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 1, .opc2
= 0,
3563 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
3564 .fieldoffset
= offsetof(CPUARMState
, sp_el
[1]) },
3565 { .name
= "SPSel", .state
= ARM_CP_STATE_AA64
,
3566 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 0,
3567 .type
= ARM_CP_NO_RAW
,
3568 .access
= PL1_RW
, .readfn
= spsel_read
, .writefn
= spsel_write
},
3569 { .name
= "FPEXC32_EL2", .state
= ARM_CP_STATE_AA64
,
3570 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 3, .opc2
= 0,
3571 .type
= ARM_CP_ALIAS
,
3572 .fieldoffset
= offsetof(CPUARMState
, vfp
.xregs
[ARM_VFP_FPEXC
]),
3573 .access
= PL2_RW
, .accessfn
= fpexc32_access
},
3574 { .name
= "DACR32_EL2", .state
= ARM_CP_STATE_AA64
,
3575 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 0, .opc2
= 0,
3576 .access
= PL2_RW
, .resetvalue
= 0,
3577 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
3578 .fieldoffset
= offsetof(CPUARMState
, cp15
.dacr32_el2
) },
3579 { .name
= "IFSR32_EL2", .state
= ARM_CP_STATE_AA64
,
3580 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 0, .opc2
= 1,
3581 .access
= PL2_RW
, .resetvalue
= 0,
3582 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifsr32_el2
) },
3583 { .name
= "SPSR_IRQ", .state
= ARM_CP_STATE_AA64
,
3584 .type
= ARM_CP_ALIAS
,
3585 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 0,
3587 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_IRQ
]) },
3588 { .name
= "SPSR_ABT", .state
= ARM_CP_STATE_AA64
,
3589 .type
= ARM_CP_ALIAS
,
3590 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 1,
3592 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_ABT
]) },
3593 { .name
= "SPSR_UND", .state
= ARM_CP_STATE_AA64
,
3594 .type
= ARM_CP_ALIAS
,
3595 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 2,
3597 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_UND
]) },
3598 { .name
= "SPSR_FIQ", .state
= ARM_CP_STATE_AA64
,
3599 .type
= ARM_CP_ALIAS
,
3600 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 3,
3602 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_FIQ
]) },
3603 { .name
= "MDCR_EL3", .state
= ARM_CP_STATE_AA64
,
3604 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 3, .opc2
= 1,
3606 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el3
) },
3607 { .name
= "SDCR", .type
= ARM_CP_ALIAS
,
3608 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 1,
3609 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
3610 .writefn
= sdcr_write
,
3611 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.mdcr_el3
) },
3615 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
3616 static const ARMCPRegInfo el3_no_el2_cp_reginfo
[] = {
3617 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_AA64
,
3618 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
3620 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
},
3621 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
3622 .type
= ARM_CP_NO_RAW
,
3623 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
3625 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
},
3626 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
3627 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
3628 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3629 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
3630 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
3631 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3633 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
3634 .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
3635 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3636 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
3637 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
3638 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3640 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
3641 .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
3642 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3644 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
3645 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
3646 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3648 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
3649 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
3650 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3652 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
3653 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
3654 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3655 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_BOTH
,
3656 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
3657 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
3658 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3659 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
3660 .cp
= 15, .opc1
= 6, .crm
= 2,
3661 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
3662 .type
= ARM_CP_CONST
| ARM_CP_64BIT
, .resetvalue
= 0 },
3663 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
3664 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
3665 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3666 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
3667 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
3668 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3669 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
3670 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
3671 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3672 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
3673 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
3674 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3675 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
3676 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
3678 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
3679 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
3680 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3681 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
3682 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
3683 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3684 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
3685 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
3687 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
3688 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
3689 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3690 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
3691 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
3693 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
3694 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
3695 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3696 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
3697 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
3698 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3699 { .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
,
3700 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
3701 .access
= PL2_RW
, .accessfn
= access_tda
,
3702 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3703 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_BOTH
,
3704 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
3705 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
3706 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3707 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
3708 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
3709 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3713 static void hcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3715 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3716 uint64_t valid_mask
= HCR_MASK
;
3718 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
3719 valid_mask
&= ~HCR_HCD
;
3721 valid_mask
&= ~HCR_TSC
;
3724 /* Clear RES0 bits. */
3725 value
&= valid_mask
;
3727 /* These bits change the MMU setup:
3728 * HCR_VM enables stage 2 translation
3729 * HCR_PTW forbids certain page-table setups
3730 * HCR_DC Disables stage1 and enables stage2 translation
3732 if ((raw_read(env
, ri
) ^ value
) & (HCR_VM
| HCR_PTW
| HCR_DC
)) {
3733 tlb_flush(CPU(cpu
));
3735 raw_write(env
, ri
, value
);
3738 static const ARMCPRegInfo el2_cp_reginfo
[] = {
3739 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
3740 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
3741 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
3742 .writefn
= hcr_write
},
3743 { .name
= "ELR_EL2", .state
= ARM_CP_STATE_AA64
,
3744 .type
= ARM_CP_ALIAS
,
3745 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 1,
3747 .fieldoffset
= offsetof(CPUARMState
, elr_el
[2]) },
3748 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_AA64
,
3749 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
3750 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[2]) },
3751 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_AA64
,
3752 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
3753 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[2]) },
3754 { .name
= "SPSR_EL2", .state
= ARM_CP_STATE_AA64
,
3755 .type
= ARM_CP_ALIAS
,
3756 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 0,
3758 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_HYP
]) },
3759 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_AA64
,
3760 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
3761 .access
= PL2_RW
, .writefn
= vbar_write
,
3762 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[2]),
3764 { .name
= "SP_EL2", .state
= ARM_CP_STATE_AA64
,
3765 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 1, .opc2
= 0,
3766 .access
= PL3_RW
, .type
= ARM_CP_ALIAS
,
3767 .fieldoffset
= offsetof(CPUARMState
, sp_el
[2]) },
3768 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
3769 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
3770 .access
= PL2_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
3771 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[2]) },
3772 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
3773 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
3774 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[2]),
3776 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
3777 .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
3778 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
3779 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.mair_el
[2]) },
3780 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
3781 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
3782 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3784 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
3785 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
3786 .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
3787 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3789 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
3790 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
3791 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3793 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
3794 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
3795 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3797 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
3798 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
3800 /* no .writefn needed as this can't cause an ASID change;
3801 * no .raw_writefn or .resetfn needed as we never use mask/base_mask
3803 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[2]) },
3804 { .name
= "VTCR", .state
= ARM_CP_STATE_AA32
,
3805 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
3806 .type
= ARM_CP_ALIAS
,
3807 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
3808 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
3809 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_AA64
,
3810 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
3812 /* no .writefn needed as this can't cause an ASID change;
3813 * no .raw_writefn or .resetfn needed as we never use mask/base_mask
3815 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
3816 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
3817 .cp
= 15, .opc1
= 6, .crm
= 2,
3818 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
3819 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
3820 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
),
3821 .writefn
= vttbr_write
},
3822 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
3823 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
3824 .access
= PL2_RW
, .writefn
= vttbr_write
,
3825 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
) },
3826 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
3827 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
3828 .access
= PL2_RW
, .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
3829 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[2]) },
3830 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
3831 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
3832 .access
= PL2_RW
, .resetvalue
= 0,
3833 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[2]) },
3834 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
3835 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
3836 .access
= PL2_RW
, .resetvalue
= 0,
3837 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
3838 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
3839 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
3840 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
3841 { .name
= "TLBIALLNSNH",
3842 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
3843 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3844 .writefn
= tlbiall_nsnh_write
},
3845 { .name
= "TLBIALLNSNHIS",
3846 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
3847 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3848 .writefn
= tlbiall_nsnh_is_write
},
3849 { .name
= "TLBIALLH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
3850 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3851 .writefn
= tlbiall_hyp_write
},
3852 { .name
= "TLBIALLHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
3853 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3854 .writefn
= tlbiall_hyp_is_write
},
3855 { .name
= "TLBIMVAH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
3856 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3857 .writefn
= tlbimva_hyp_write
},
3858 { .name
= "TLBIMVAHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
3859 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3860 .writefn
= tlbimva_hyp_is_write
},
3861 { .name
= "TLBI_ALLE2", .state
= ARM_CP_STATE_AA64
,
3862 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
3863 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3864 .writefn
= tlbi_aa64_alle2_write
},
3865 { .name
= "TLBI_VAE2", .state
= ARM_CP_STATE_AA64
,
3866 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
3867 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3868 .writefn
= tlbi_aa64_vae2_write
},
3869 { .name
= "TLBI_VALE2", .state
= ARM_CP_STATE_AA64
,
3870 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
3871 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3872 .writefn
= tlbi_aa64_vae2_write
},
3873 { .name
= "TLBI_ALLE2IS", .state
= ARM_CP_STATE_AA64
,
3874 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
3875 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3876 .writefn
= tlbi_aa64_alle2is_write
},
3877 { .name
= "TLBI_VAE2IS", .state
= ARM_CP_STATE_AA64
,
3878 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
3879 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3880 .writefn
= tlbi_aa64_vae2is_write
},
3881 { .name
= "TLBI_VALE2IS", .state
= ARM_CP_STATE_AA64
,
3882 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
3883 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3884 .writefn
= tlbi_aa64_vae2is_write
},
3885 #ifndef CONFIG_USER_ONLY
3886 /* Unlike the other EL2-related AT operations, these must
3887 * UNDEF from EL3 if EL2 is not implemented, which is why we
3888 * define them here rather than with the rest of the AT ops.
3890 { .name
= "AT_S1E2R", .state
= ARM_CP_STATE_AA64
,
3891 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
3892 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
3893 .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3894 { .name
= "AT_S1E2W", .state
= ARM_CP_STATE_AA64
,
3895 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
3896 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
3897 .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3898 /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
3899 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
3900 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
3901 * to behave as if SCR.NS was 1.
3903 { .name
= "ATS1HR", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
3905 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
},
3906 { .name
= "ATS1HW", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
3908 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
},
3909 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
3910 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
3911 /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
3912 * reset values as IMPDEF. We choose to reset to 3 to comply with
3913 * both ARMv7 and ARMv8.
3915 .access
= PL2_RW
, .resetvalue
= 3,
3916 .fieldoffset
= offsetof(CPUARMState
, cp15
.cnthctl_el2
) },
3917 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
3918 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
3919 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 0,
3920 .writefn
= gt_cntvoff_write
,
3921 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
3922 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
3923 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
| ARM_CP_IO
,
3924 .writefn
= gt_cntvoff_write
,
3925 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
3926 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
3927 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
3928 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
3929 .type
= ARM_CP_IO
, .access
= PL2_RW
,
3930 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
3931 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
3932 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
3933 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_IO
,
3934 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
3935 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
3936 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
3937 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
3938 .resetfn
= gt_hyp_timer_reset
,
3939 .readfn
= gt_hyp_tval_read
, .writefn
= gt_hyp_tval_write
},
3940 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
3942 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
3944 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].ctl
),
3946 .writefn
= gt_hyp_ctl_write
, .raw_writefn
= raw_write
},
3948 /* The only field of MDCR_EL2 that has a defined architectural reset value
3949 * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we
3950 * don't impelment any PMU event counters, so using zero as a reset
3951 * value for MDCR_EL2 is okay
3953 { .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
,
3954 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
3955 .access
= PL2_RW
, .resetvalue
= 0,
3956 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el2
), },
3957 { .name
= "HPFAR", .state
= ARM_CP_STATE_AA32
,
3958 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
3959 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
3960 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
3961 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_AA64
,
3962 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
3964 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
3965 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
3966 .cp
= 15, .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
3968 .fieldoffset
= offsetof(CPUARMState
, cp15
.hstr_el2
) },
3972 static CPAccessResult
nsacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3975 /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
3976 * At Secure EL1 it traps to EL3.
3978 if (arm_current_el(env
) == 3) {
3979 return CP_ACCESS_OK
;
3981 if (arm_is_secure_below_el3(env
)) {
3982 return CP_ACCESS_TRAP_EL3
;
3984 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
3986 return CP_ACCESS_OK
;
3988 return CP_ACCESS_TRAP_UNCATEGORIZED
;
3991 static const ARMCPRegInfo el3_cp_reginfo
[] = {
3992 { .name
= "SCR_EL3", .state
= ARM_CP_STATE_AA64
,
3993 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 0,
3994 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.scr_el3
),
3995 .resetvalue
= 0, .writefn
= scr_write
},
3996 { .name
= "SCR", .type
= ARM_CP_ALIAS
,
3997 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 0,
3998 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
3999 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.scr_el3
),
4000 .writefn
= scr_write
},
4001 { .name
= "SDER32_EL3", .state
= ARM_CP_STATE_AA64
,
4002 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 1,
4003 .access
= PL3_RW
, .resetvalue
= 0,
4004 .fieldoffset
= offsetof(CPUARMState
, cp15
.sder
) },
4006 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 1,
4007 .access
= PL3_RW
, .resetvalue
= 0,
4008 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.sder
) },
4009 { .name
= "MVBAR", .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
4010 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
4011 .writefn
= vbar_write
, .resetvalue
= 0,
4012 .fieldoffset
= offsetof(CPUARMState
, cp15
.mvbar
) },
4013 { .name
= "TTBR0_EL3", .state
= ARM_CP_STATE_AA64
,
4014 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 0,
4015 .access
= PL3_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
4016 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[3]) },
4017 { .name
= "TCR_EL3", .state
= ARM_CP_STATE_AA64
,
4018 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 2,
4020 /* no .writefn needed as this can't cause an ASID change;
4021 * we must provide a .raw_writefn and .resetfn because we handle
4022 * reset and migration for the AArch32 TTBCR(S), which might be
4023 * using mask and base_mask.
4025 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= vmsa_ttbcr_raw_write
,
4026 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[3]) },
4027 { .name
= "ELR_EL3", .state
= ARM_CP_STATE_AA64
,
4028 .type
= ARM_CP_ALIAS
,
4029 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 1,
4031 .fieldoffset
= offsetof(CPUARMState
, elr_el
[3]) },
4032 { .name
= "ESR_EL3", .state
= ARM_CP_STATE_AA64
,
4033 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 2, .opc2
= 0,
4034 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[3]) },
4035 { .name
= "FAR_EL3", .state
= ARM_CP_STATE_AA64
,
4036 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 0,
4037 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[3]) },
4038 { .name
= "SPSR_EL3", .state
= ARM_CP_STATE_AA64
,
4039 .type
= ARM_CP_ALIAS
,
4040 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 0,
4042 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_MON
]) },
4043 { .name
= "VBAR_EL3", .state
= ARM_CP_STATE_AA64
,
4044 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 0,
4045 .access
= PL3_RW
, .writefn
= vbar_write
,
4046 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[3]),
4048 { .name
= "CPTR_EL3", .state
= ARM_CP_STATE_AA64
,
4049 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 2,
4050 .access
= PL3_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
4051 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[3]) },
4052 { .name
= "TPIDR_EL3", .state
= ARM_CP_STATE_AA64
,
4053 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 2,
4054 .access
= PL3_RW
, .resetvalue
= 0,
4055 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[3]) },
4056 { .name
= "AMAIR_EL3", .state
= ARM_CP_STATE_AA64
,
4057 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 3, .opc2
= 0,
4058 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
4060 { .name
= "AFSR0_EL3", .state
= ARM_CP_STATE_BOTH
,
4061 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 0,
4062 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
4064 { .name
= "AFSR1_EL3", .state
= ARM_CP_STATE_BOTH
,
4065 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 1,
4066 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
4068 { .name
= "TLBI_ALLE3IS", .state
= ARM_CP_STATE_AA64
,
4069 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 0,
4070 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4071 .writefn
= tlbi_aa64_alle3is_write
},
4072 { .name
= "TLBI_VAE3IS", .state
= ARM_CP_STATE_AA64
,
4073 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 1,
4074 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4075 .writefn
= tlbi_aa64_vae3is_write
},
4076 { .name
= "TLBI_VALE3IS", .state
= ARM_CP_STATE_AA64
,
4077 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 5,
4078 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4079 .writefn
= tlbi_aa64_vae3is_write
},
4080 { .name
= "TLBI_ALLE3", .state
= ARM_CP_STATE_AA64
,
4081 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 0,
4082 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4083 .writefn
= tlbi_aa64_alle3_write
},
4084 { .name
= "TLBI_VAE3", .state
= ARM_CP_STATE_AA64
,
4085 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 1,
4086 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4087 .writefn
= tlbi_aa64_vae3_write
},
4088 { .name
= "TLBI_VALE3", .state
= ARM_CP_STATE_AA64
,
4089 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 5,
4090 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4091 .writefn
= tlbi_aa64_vae3_write
},
4095 static CPAccessResult
ctr_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4098 /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
4099 * but the AArch32 CTR has its own reginfo struct)
4101 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UCT
)) {
4102 return CP_ACCESS_TRAP
;
4104 return CP_ACCESS_OK
;
4107 static void oslar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4110 /* Writes to OSLAR_EL1 may update the OS lock status, which can be
4111 * read via a bit in OSLSR_EL1.
4115 if (ri
->state
== ARM_CP_STATE_AA32
) {
4116 oslock
= (value
== 0xC5ACCE55);
4121 env
->cp15
.oslsr_el1
= deposit32(env
->cp15
.oslsr_el1
, 1, 1, oslock
);
4124 static const ARMCPRegInfo debug_cp_reginfo
[] = {
4125 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
4126 * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
4127 * unlike DBGDRAR it is never accessible from EL0.
4128 * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
4131 { .name
= "DBGDRAR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
4132 .access
= PL0_R
, .accessfn
= access_tdra
,
4133 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4134 { .name
= "MDRAR_EL1", .state
= ARM_CP_STATE_AA64
,
4135 .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
4136 .access
= PL1_R
, .accessfn
= access_tdra
,
4137 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4138 { .name
= "DBGDSAR", .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
4139 .access
= PL0_R
, .accessfn
= access_tdra
,
4140 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4141 /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
4142 { .name
= "MDSCR_EL1", .state
= ARM_CP_STATE_BOTH
,
4143 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
4144 .access
= PL1_RW
, .accessfn
= access_tda
,
4145 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
),
4147 /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
4148 * We don't implement the configurable EL0 access.
4150 { .name
= "MDCCSR_EL0", .state
= ARM_CP_STATE_BOTH
,
4151 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
4152 .type
= ARM_CP_ALIAS
,
4153 .access
= PL1_R
, .accessfn
= access_tda
,
4154 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
), },
4155 { .name
= "OSLAR_EL1", .state
= ARM_CP_STATE_BOTH
,
4156 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 4,
4157 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4158 .accessfn
= access_tdosa
,
4159 .writefn
= oslar_write
},
4160 { .name
= "OSLSR_EL1", .state
= ARM_CP_STATE_BOTH
,
4161 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 4,
4162 .access
= PL1_R
, .resetvalue
= 10,
4163 .accessfn
= access_tdosa
,
4164 .fieldoffset
= offsetof(CPUARMState
, cp15
.oslsr_el1
) },
4165 /* Dummy OSDLR_EL1: 32-bit Linux will read this */
4166 { .name
= "OSDLR_EL1", .state
= ARM_CP_STATE_BOTH
,
4167 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 4,
4168 .access
= PL1_RW
, .accessfn
= access_tdosa
,
4169 .type
= ARM_CP_NOP
},
4170 /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
4171 * implement vector catch debug events yet.
4174 .cp
= 14, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
4175 .access
= PL1_RW
, .accessfn
= access_tda
,
4176 .type
= ARM_CP_NOP
},
4177 /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor
4178 * to save and restore a 32-bit guest's DBGVCR)
4180 { .name
= "DBGVCR32_EL2", .state
= ARM_CP_STATE_AA64
,
4181 .opc0
= 2, .opc1
= 4, .crn
= 0, .crm
= 7, .opc2
= 0,
4182 .access
= PL2_RW
, .accessfn
= access_tda
,
4183 .type
= ARM_CP_NOP
},
4184 /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
4185 * Channel but Linux may try to access this register. The 32-bit
4186 * alias is DBGDCCINT.
4188 { .name
= "MDCCINT_EL1", .state
= ARM_CP_STATE_BOTH
,
4189 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
4190 .access
= PL1_RW
, .accessfn
= access_tda
,
4191 .type
= ARM_CP_NOP
},
4195 static const ARMCPRegInfo debug_lpae_cp_reginfo
[] = {
4196 /* 64 bit access versions of the (dummy) debug registers */
4197 { .name
= "DBGDRAR", .cp
= 14, .crm
= 1, .opc1
= 0,
4198 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
4199 { .name
= "DBGDSAR", .cp
= 14, .crm
= 2, .opc1
= 0,
4200 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
4204 void hw_watchpoint_update(ARMCPU
*cpu
, int n
)
4206 CPUARMState
*env
= &cpu
->env
;
4208 vaddr wvr
= env
->cp15
.dbgwvr
[n
];
4209 uint64_t wcr
= env
->cp15
.dbgwcr
[n
];
4211 int flags
= BP_CPU
| BP_STOP_BEFORE_ACCESS
;
4213 if (env
->cpu_watchpoint
[n
]) {
4214 cpu_watchpoint_remove_by_ref(CPU(cpu
), env
->cpu_watchpoint
[n
]);
4215 env
->cpu_watchpoint
[n
] = NULL
;
4218 if (!extract64(wcr
, 0, 1)) {
4219 /* E bit clear : watchpoint disabled */
4223 switch (extract64(wcr
, 3, 2)) {
4225 /* LSC 00 is reserved and must behave as if the wp is disabled */
4228 flags
|= BP_MEM_READ
;
4231 flags
|= BP_MEM_WRITE
;
4234 flags
|= BP_MEM_ACCESS
;
4238 /* Attempts to use both MASK and BAS fields simultaneously are
4239 * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
4240 * thus generating a watchpoint for every byte in the masked region.
4242 mask
= extract64(wcr
, 24, 4);
4243 if (mask
== 1 || mask
== 2) {
4244 /* Reserved values of MASK; we must act as if the mask value was
4245 * some non-reserved value, or as if the watchpoint were disabled.
4246 * We choose the latter.
4250 /* Watchpoint covers an aligned area up to 2GB in size */
4252 /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
4253 * whether the watchpoint fires when the unmasked bits match; we opt
4254 * to generate the exceptions.
4258 /* Watchpoint covers bytes defined by the byte address select bits */
4259 int bas
= extract64(wcr
, 5, 8);
4263 /* This must act as if the watchpoint is disabled */
4267 if (extract64(wvr
, 2, 1)) {
4268 /* Deprecated case of an only 4-aligned address. BAS[7:4] are
4269 * ignored, and BAS[3:0] define which bytes to watch.
4273 /* The BAS bits are supposed to be programmed to indicate a contiguous
4274 * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
4275 * we fire for each byte in the word/doubleword addressed by the WVR.
4276 * We choose to ignore any non-zero bits after the first range of 1s.
4278 basstart
= ctz32(bas
);
4279 len
= cto32(bas
>> basstart
);
4283 cpu_watchpoint_insert(CPU(cpu
), wvr
, len
, flags
,
4284 &env
->cpu_watchpoint
[n
]);
4287 void hw_watchpoint_update_all(ARMCPU
*cpu
)
4290 CPUARMState
*env
= &cpu
->env
;
4292 /* Completely clear out existing QEMU watchpoints and our array, to
4293 * avoid possible stale entries following migration load.
4295 cpu_watchpoint_remove_all(CPU(cpu
), BP_CPU
);
4296 memset(env
->cpu_watchpoint
, 0, sizeof(env
->cpu_watchpoint
));
4298 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_watchpoint
); i
++) {
4299 hw_watchpoint_update(cpu
, i
);
4303 static void dbgwvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4306 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4309 /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
4310 * register reads and behaves as if values written are sign extended.
4311 * Bits [1:0] are RES0.
4313 value
= sextract64(value
, 0, 49) & ~3ULL;
4315 raw_write(env
, ri
, value
);
4316 hw_watchpoint_update(cpu
, i
);
4319 static void dbgwcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4322 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4325 raw_write(env
, ri
, value
);
4326 hw_watchpoint_update(cpu
, i
);
4329 void hw_breakpoint_update(ARMCPU
*cpu
, int n
)
4331 CPUARMState
*env
= &cpu
->env
;
4332 uint64_t bvr
= env
->cp15
.dbgbvr
[n
];
4333 uint64_t bcr
= env
->cp15
.dbgbcr
[n
];
4338 if (env
->cpu_breakpoint
[n
]) {
4339 cpu_breakpoint_remove_by_ref(CPU(cpu
), env
->cpu_breakpoint
[n
]);
4340 env
->cpu_breakpoint
[n
] = NULL
;
4343 if (!extract64(bcr
, 0, 1)) {
4344 /* E bit clear : watchpoint disabled */
4348 bt
= extract64(bcr
, 20, 4);
4351 case 4: /* unlinked address mismatch (reserved if AArch64) */
4352 case 5: /* linked address mismatch (reserved if AArch64) */
4353 qemu_log_mask(LOG_UNIMP
,
4354 "arm: address mismatch breakpoint types not implemented");
4356 case 0: /* unlinked address match */
4357 case 1: /* linked address match */
4359 /* Bits [63:49] are hardwired to the value of bit [48]; that is,
4360 * we behave as if the register was sign extended. Bits [1:0] are
4361 * RES0. The BAS field is used to allow setting breakpoints on 16
4362 * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
4363 * a bp will fire if the addresses covered by the bp and the addresses
4364 * covered by the insn overlap but the insn doesn't start at the
4365 * start of the bp address range. We choose to require the insn and
4366 * the bp to have the same address. The constraints on writing to
4367 * BAS enforced in dbgbcr_write mean we have only four cases:
4368 * 0b0000 => no breakpoint
4369 * 0b0011 => breakpoint on addr
4370 * 0b1100 => breakpoint on addr + 2
4371 * 0b1111 => breakpoint on addr
4372 * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
4374 int bas
= extract64(bcr
, 5, 4);
4375 addr
= sextract64(bvr
, 0, 49) & ~3ULL;
4384 case 2: /* unlinked context ID match */
4385 case 8: /* unlinked VMID match (reserved if no EL2) */
4386 case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
4387 qemu_log_mask(LOG_UNIMP
,
4388 "arm: unlinked context breakpoint types not implemented");
4390 case 9: /* linked VMID match (reserved if no EL2) */
4391 case 11: /* linked context ID and VMID match (reserved if no EL2) */
4392 case 3: /* linked context ID match */
4394 /* We must generate no events for Linked context matches (unless
4395 * they are linked to by some other bp/wp, which is handled in
4396 * updates for the linking bp/wp). We choose to also generate no events
4397 * for reserved values.
4402 cpu_breakpoint_insert(CPU(cpu
), addr
, flags
, &env
->cpu_breakpoint
[n
]);
4405 void hw_breakpoint_update_all(ARMCPU
*cpu
)
4408 CPUARMState
*env
= &cpu
->env
;
4410 /* Completely clear out existing QEMU breakpoints and our array, to
4411 * avoid possible stale entries following migration load.
4413 cpu_breakpoint_remove_all(CPU(cpu
), BP_CPU
);
4414 memset(env
->cpu_breakpoint
, 0, sizeof(env
->cpu_breakpoint
));
4416 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_breakpoint
); i
++) {
4417 hw_breakpoint_update(cpu
, i
);
4421 static void dbgbvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4424 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4427 raw_write(env
, ri
, value
);
4428 hw_breakpoint_update(cpu
, i
);
4431 static void dbgbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4434 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4437 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
4440 value
= deposit64(value
, 6, 1, extract64(value
, 5, 1));
4441 value
= deposit64(value
, 8, 1, extract64(value
, 7, 1));
4443 raw_write(env
, ri
, value
);
4444 hw_breakpoint_update(cpu
, i
);
4447 static void define_debug_regs(ARMCPU
*cpu
)
4449 /* Define v7 and v8 architectural debug registers.
4450 * These are just dummy implementations for now.
4453 int wrps
, brps
, ctx_cmps
;
4454 ARMCPRegInfo dbgdidr
= {
4455 .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
4456 .access
= PL0_R
, .accessfn
= access_tda
,
4457 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->dbgdidr
,
4460 /* Note that all these register fields hold "number of Xs minus 1". */
4461 brps
= extract32(cpu
->dbgdidr
, 24, 4);
4462 wrps
= extract32(cpu
->dbgdidr
, 28, 4);
4463 ctx_cmps
= extract32(cpu
->dbgdidr
, 20, 4);
4465 assert(ctx_cmps
<= brps
);
4467 /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
4468 * of the debug registers such as number of breakpoints;
4469 * check that if they both exist then they agree.
4471 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
4472 assert(extract32(cpu
->id_aa64dfr0
, 12, 4) == brps
);
4473 assert(extract32(cpu
->id_aa64dfr0
, 20, 4) == wrps
);
4474 assert(extract32(cpu
->id_aa64dfr0
, 28, 4) == ctx_cmps
);
4477 define_one_arm_cp_reg(cpu
, &dbgdidr
);
4478 define_arm_cp_regs(cpu
, debug_cp_reginfo
);
4480 if (arm_feature(&cpu
->env
, ARM_FEATURE_LPAE
)) {
4481 define_arm_cp_regs(cpu
, debug_lpae_cp_reginfo
);
4484 for (i
= 0; i
< brps
+ 1; i
++) {
4485 ARMCPRegInfo dbgregs
[] = {
4486 { .name
= "DBGBVR", .state
= ARM_CP_STATE_BOTH
,
4487 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 4,
4488 .access
= PL1_RW
, .accessfn
= access_tda
,
4489 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbvr
[i
]),
4490 .writefn
= dbgbvr_write
, .raw_writefn
= raw_write
4492 { .name
= "DBGBCR", .state
= ARM_CP_STATE_BOTH
,
4493 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 5,
4494 .access
= PL1_RW
, .accessfn
= access_tda
,
4495 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbcr
[i
]),
4496 .writefn
= dbgbcr_write
, .raw_writefn
= raw_write
4500 define_arm_cp_regs(cpu
, dbgregs
);
4503 for (i
= 0; i
< wrps
+ 1; i
++) {
4504 ARMCPRegInfo dbgregs
[] = {
4505 { .name
= "DBGWVR", .state
= ARM_CP_STATE_BOTH
,
4506 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 6,
4507 .access
= PL1_RW
, .accessfn
= access_tda
,
4508 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwvr
[i
]),
4509 .writefn
= dbgwvr_write
, .raw_writefn
= raw_write
4511 { .name
= "DBGWCR", .state
= ARM_CP_STATE_BOTH
,
4512 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 7,
4513 .access
= PL1_RW
, .accessfn
= access_tda
,
4514 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwcr
[i
]),
4515 .writefn
= dbgwcr_write
, .raw_writefn
= raw_write
4519 define_arm_cp_regs(cpu
, dbgregs
);
4523 void register_cp_regs_for_features(ARMCPU
*cpu
)
4525 /* Register all the coprocessor registers based on feature bits */
4526 CPUARMState
*env
= &cpu
->env
;
4527 if (arm_feature(env
, ARM_FEATURE_M
)) {
4528 /* M profile has no coprocessor registers */
4532 define_arm_cp_regs(cpu
, cp_reginfo
);
4533 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
4534 /* Must go early as it is full of wildcards that may be
4535 * overridden by later definitions.
4537 define_arm_cp_regs(cpu
, not_v8_cp_reginfo
);
4540 if (arm_feature(env
, ARM_FEATURE_V6
)) {
4541 /* The ID registers all have impdef reset values */
4542 ARMCPRegInfo v6_idregs
[] = {
4543 { .name
= "ID_PFR0", .state
= ARM_CP_STATE_BOTH
,
4544 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
4545 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4546 .resetvalue
= cpu
->id_pfr0
},
4547 { .name
= "ID_PFR1", .state
= ARM_CP_STATE_BOTH
,
4548 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 1,
4549 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4550 .resetvalue
= cpu
->id_pfr1
},
4551 { .name
= "ID_DFR0", .state
= ARM_CP_STATE_BOTH
,
4552 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 2,
4553 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4554 .resetvalue
= cpu
->id_dfr0
},
4555 { .name
= "ID_AFR0", .state
= ARM_CP_STATE_BOTH
,
4556 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 3,
4557 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4558 .resetvalue
= cpu
->id_afr0
},
4559 { .name
= "ID_MMFR0", .state
= ARM_CP_STATE_BOTH
,
4560 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 4,
4561 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4562 .resetvalue
= cpu
->id_mmfr0
},
4563 { .name
= "ID_MMFR1", .state
= ARM_CP_STATE_BOTH
,
4564 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 5,
4565 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4566 .resetvalue
= cpu
->id_mmfr1
},
4567 { .name
= "ID_MMFR2", .state
= ARM_CP_STATE_BOTH
,
4568 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 6,
4569 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4570 .resetvalue
= cpu
->id_mmfr2
},
4571 { .name
= "ID_MMFR3", .state
= ARM_CP_STATE_BOTH
,
4572 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 7,
4573 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4574 .resetvalue
= cpu
->id_mmfr3
},
4575 { .name
= "ID_ISAR0", .state
= ARM_CP_STATE_BOTH
,
4576 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
4577 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4578 .resetvalue
= cpu
->id_isar0
},
4579 { .name
= "ID_ISAR1", .state
= ARM_CP_STATE_BOTH
,
4580 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 1,
4581 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4582 .resetvalue
= cpu
->id_isar1
},
4583 { .name
= "ID_ISAR2", .state
= ARM_CP_STATE_BOTH
,
4584 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
4585 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4586 .resetvalue
= cpu
->id_isar2
},
4587 { .name
= "ID_ISAR3", .state
= ARM_CP_STATE_BOTH
,
4588 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 3,
4589 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4590 .resetvalue
= cpu
->id_isar3
},
4591 { .name
= "ID_ISAR4", .state
= ARM_CP_STATE_BOTH
,
4592 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 4,
4593 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4594 .resetvalue
= cpu
->id_isar4
},
4595 { .name
= "ID_ISAR5", .state
= ARM_CP_STATE_BOTH
,
4596 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 5,
4597 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4598 .resetvalue
= cpu
->id_isar5
},
4599 { .name
= "ID_MMFR4", .state
= ARM_CP_STATE_BOTH
,
4600 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 6,
4601 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4602 .resetvalue
= cpu
->id_mmfr4
},
4603 /* 7 is as yet unallocated and must RAZ */
4604 { .name
= "ID_ISAR7_RESERVED", .state
= ARM_CP_STATE_BOTH
,
4605 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 7,
4606 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4610 define_arm_cp_regs(cpu
, v6_idregs
);
4611 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
4613 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
4615 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
4616 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
4618 if (arm_feature(env
, ARM_FEATURE_V7MP
) &&
4619 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
4620 define_arm_cp_regs(cpu
, v7mp_cp_reginfo
);
4622 if (arm_feature(env
, ARM_FEATURE_V7
)) {
4623 /* v7 performance monitor control register: same implementor
4624 * field as main ID register, and we implement only the cycle
4627 #ifndef CONFIG_USER_ONLY
4628 ARMCPRegInfo pmcr
= {
4629 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
4631 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
4632 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcr
),
4633 .accessfn
= pmreg_access
, .writefn
= pmcr_write
,
4634 .raw_writefn
= raw_write
,
4636 ARMCPRegInfo pmcr64
= {
4637 .name
= "PMCR_EL0", .state
= ARM_CP_STATE_AA64
,
4638 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 0,
4639 .access
= PL0_RW
, .accessfn
= pmreg_access
,
4641 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
4642 .resetvalue
= cpu
->midr
& 0xff000000,
4643 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
4645 define_one_arm_cp_reg(cpu
, &pmcr
);
4646 define_one_arm_cp_reg(cpu
, &pmcr64
);
4648 ARMCPRegInfo clidr
= {
4649 .name
= "CLIDR", .state
= ARM_CP_STATE_BOTH
,
4650 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
4651 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->clidr
4653 define_one_arm_cp_reg(cpu
, &clidr
);
4654 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
4655 define_debug_regs(cpu
);
4657 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
4659 if (arm_feature(env
, ARM_FEATURE_V8
)) {
4660 /* AArch64 ID registers, which all have impdef reset values.
4661 * Note that within the ID register ranges the unused slots
4662 * must all RAZ, not UNDEF; future architecture versions may
4663 * define new registers here.
4665 ARMCPRegInfo v8_idregs
[] = {
4666 { .name
= "ID_AA64PFR0_EL1", .state
= ARM_CP_STATE_AA64
,
4667 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 0,
4668 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4669 .resetvalue
= cpu
->id_aa64pfr0
},
4670 { .name
= "ID_AA64PFR1_EL1", .state
= ARM_CP_STATE_AA64
,
4671 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 1,
4672 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4673 .resetvalue
= cpu
->id_aa64pfr1
},
4674 { .name
= "ID_AA64PFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4675 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 2,
4676 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4678 { .name
= "ID_AA64PFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4679 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 3,
4680 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4682 { .name
= "ID_AA64PFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4683 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 4,
4684 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4686 { .name
= "ID_AA64PFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4687 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 5,
4688 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4690 { .name
= "ID_AA64PFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4691 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 6,
4692 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4694 { .name
= "ID_AA64PFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4695 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 7,
4696 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4698 { .name
= "ID_AA64DFR0_EL1", .state
= ARM_CP_STATE_AA64
,
4699 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 0,
4700 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4701 .resetvalue
= cpu
->id_aa64dfr0
},
4702 { .name
= "ID_AA64DFR1_EL1", .state
= ARM_CP_STATE_AA64
,
4703 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 1,
4704 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4705 .resetvalue
= cpu
->id_aa64dfr1
},
4706 { .name
= "ID_AA64DFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4707 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 2,
4708 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4710 { .name
= "ID_AA64DFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4711 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 3,
4712 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4714 { .name
= "ID_AA64AFR0_EL1", .state
= ARM_CP_STATE_AA64
,
4715 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 4,
4716 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4717 .resetvalue
= cpu
->id_aa64afr0
},
4718 { .name
= "ID_AA64AFR1_EL1", .state
= ARM_CP_STATE_AA64
,
4719 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 5,
4720 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4721 .resetvalue
= cpu
->id_aa64afr1
},
4722 { .name
= "ID_AA64AFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4723 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 6,
4724 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4726 { .name
= "ID_AA64AFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4727 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 7,
4728 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4730 { .name
= "ID_AA64ISAR0_EL1", .state
= ARM_CP_STATE_AA64
,
4731 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 0,
4732 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4733 .resetvalue
= cpu
->id_aa64isar0
},
4734 { .name
= "ID_AA64ISAR1_EL1", .state
= ARM_CP_STATE_AA64
,
4735 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 1,
4736 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4737 .resetvalue
= cpu
->id_aa64isar1
},
4738 { .name
= "ID_AA64ISAR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4739 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 2,
4740 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4742 { .name
= "ID_AA64ISAR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4743 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 3,
4744 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4746 { .name
= "ID_AA64ISAR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4747 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 4,
4748 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4750 { .name
= "ID_AA64ISAR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4751 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 5,
4752 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4754 { .name
= "ID_AA64ISAR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4755 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 6,
4756 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4758 { .name
= "ID_AA64ISAR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4759 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 7,
4760 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4762 { .name
= "ID_AA64MMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
4763 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
4764 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4765 .resetvalue
= cpu
->id_aa64mmfr0
},
4766 { .name
= "ID_AA64MMFR1_EL1", .state
= ARM_CP_STATE_AA64
,
4767 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 1,
4768 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4769 .resetvalue
= cpu
->id_aa64mmfr1
},
4770 { .name
= "ID_AA64MMFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4771 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 2,
4772 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4774 { .name
= "ID_AA64MMFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4775 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 3,
4776 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4778 { .name
= "ID_AA64MMFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4779 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 4,
4780 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4782 { .name
= "ID_AA64MMFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4783 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 5,
4784 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4786 { .name
= "ID_AA64MMFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4787 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 6,
4788 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4790 { .name
= "ID_AA64MMFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4791 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 7,
4792 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4794 { .name
= "MVFR0_EL1", .state
= ARM_CP_STATE_AA64
,
4795 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
4796 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4797 .resetvalue
= cpu
->mvfr0
},
4798 { .name
= "MVFR1_EL1", .state
= ARM_CP_STATE_AA64
,
4799 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
4800 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4801 .resetvalue
= cpu
->mvfr1
},
4802 { .name
= "MVFR2_EL1", .state
= ARM_CP_STATE_AA64
,
4803 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
4804 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4805 .resetvalue
= cpu
->mvfr2
},
4806 { .name
= "MVFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4807 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 3,
4808 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4810 { .name
= "MVFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4811 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 4,
4812 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4814 { .name
= "MVFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4815 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 5,
4816 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4818 { .name
= "MVFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4819 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 6,
4820 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4822 { .name
= "MVFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4823 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 7,
4824 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4826 { .name
= "PMCEID0", .state
= ARM_CP_STATE_AA32
,
4827 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 6,
4828 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
4829 .resetvalue
= cpu
->pmceid0
},
4830 { .name
= "PMCEID0_EL0", .state
= ARM_CP_STATE_AA64
,
4831 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 6,
4832 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
4833 .resetvalue
= cpu
->pmceid0
},
4834 { .name
= "PMCEID1", .state
= ARM_CP_STATE_AA32
,
4835 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 7,
4836 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
4837 .resetvalue
= cpu
->pmceid1
},
4838 { .name
= "PMCEID1_EL0", .state
= ARM_CP_STATE_AA64
,
4839 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 7,
4840 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
4841 .resetvalue
= cpu
->pmceid1
},
4844 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
4845 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
4846 !arm_feature(env
, ARM_FEATURE_EL2
)) {
4847 ARMCPRegInfo rvbar
= {
4848 .name
= "RVBAR_EL1", .state
= ARM_CP_STATE_AA64
,
4849 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
4850 .type
= ARM_CP_CONST
, .access
= PL1_R
, .resetvalue
= cpu
->rvbar
4852 define_one_arm_cp_reg(cpu
, &rvbar
);
4854 define_arm_cp_regs(cpu
, v8_idregs
);
4855 define_arm_cp_regs(cpu
, v8_cp_reginfo
);
4857 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
4858 uint64_t vmpidr_def
= mpidr_read_val(env
);
4859 ARMCPRegInfo vpidr_regs
[] = {
4860 { .name
= "VPIDR", .state
= ARM_CP_STATE_AA32
,
4861 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
4862 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
4863 .resetvalue
= cpu
->midr
,
4864 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
4865 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
4866 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
4867 .access
= PL2_RW
, .resetvalue
= cpu
->midr
,
4868 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
4869 { .name
= "VMPIDR", .state
= ARM_CP_STATE_AA32
,
4870 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
4871 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
4872 .resetvalue
= vmpidr_def
,
4873 .fieldoffset
= offsetof(CPUARMState
, cp15
.vmpidr_el2
) },
4874 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
4875 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
4877 .resetvalue
= vmpidr_def
,
4878 .fieldoffset
= offsetof(CPUARMState
, cp15
.vmpidr_el2
) },
4881 define_arm_cp_regs(cpu
, vpidr_regs
);
4882 define_arm_cp_regs(cpu
, el2_cp_reginfo
);
4883 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
4884 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
4885 ARMCPRegInfo rvbar
= {
4886 .name
= "RVBAR_EL2", .state
= ARM_CP_STATE_AA64
,
4887 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 1,
4888 .type
= ARM_CP_CONST
, .access
= PL2_R
, .resetvalue
= cpu
->rvbar
4890 define_one_arm_cp_reg(cpu
, &rvbar
);
4893 /* If EL2 is missing but higher ELs are enabled, we need to
4894 * register the no_el2 reginfos.
4896 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
4897 /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
4898 * of MIDR_EL1 and MPIDR_EL1.
4900 ARMCPRegInfo vpidr_regs
[] = {
4901 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
4902 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
4903 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
4904 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->midr
,
4905 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
4906 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
4907 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
4908 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
4909 .type
= ARM_CP_NO_RAW
,
4910 .writefn
= arm_cp_write_ignore
, .readfn
= mpidr_read
},
4913 define_arm_cp_regs(cpu
, vpidr_regs
);
4914 define_arm_cp_regs(cpu
, el3_no_el2_cp_reginfo
);
4917 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
4918 define_arm_cp_regs(cpu
, el3_cp_reginfo
);
4919 ARMCPRegInfo el3_regs
[] = {
4920 { .name
= "RVBAR_EL3", .state
= ARM_CP_STATE_AA64
,
4921 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 1,
4922 .type
= ARM_CP_CONST
, .access
= PL3_R
, .resetvalue
= cpu
->rvbar
},
4923 { .name
= "SCTLR_EL3", .state
= ARM_CP_STATE_AA64
,
4924 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 0,
4926 .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
4927 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[3]),
4928 .resetvalue
= cpu
->reset_sctlr
},
4932 define_arm_cp_regs(cpu
, el3_regs
);
4934 /* The behaviour of NSACR is sufficiently various that we don't
4935 * try to describe it in a single reginfo:
4936 * if EL3 is 64 bit, then trap to EL3 from S EL1,
4937 * reads as constant 0xc00 from NS EL1 and NS EL2
4938 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
4939 * if v7 without EL3, register doesn't exist
4940 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
4942 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
4943 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
4944 ARMCPRegInfo nsacr
= {
4945 .name
= "NSACR", .type
= ARM_CP_CONST
,
4946 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
4947 .access
= PL1_RW
, .accessfn
= nsacr_access
,
4950 define_one_arm_cp_reg(cpu
, &nsacr
);
4952 ARMCPRegInfo nsacr
= {
4954 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
4955 .access
= PL3_RW
| PL1_R
,
4957 .fieldoffset
= offsetof(CPUARMState
, cp15
.nsacr
)
4959 define_one_arm_cp_reg(cpu
, &nsacr
);
4962 if (arm_feature(env
, ARM_FEATURE_V8
)) {
4963 ARMCPRegInfo nsacr
= {
4964 .name
= "NSACR", .type
= ARM_CP_CONST
,
4965 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
4969 define_one_arm_cp_reg(cpu
, &nsacr
);
4973 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
4974 if (arm_feature(env
, ARM_FEATURE_V6
)) {
4975 /* PMSAv6 not implemented */
4976 assert(arm_feature(env
, ARM_FEATURE_V7
));
4977 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
4978 define_arm_cp_regs(cpu
, pmsav7_cp_reginfo
);
4980 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
4983 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
4984 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
4986 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
4987 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
4989 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
4990 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
4992 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
4993 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
4995 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
4996 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
4998 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
4999 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
5001 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
5002 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
5004 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
5005 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
5007 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
5008 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
5010 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
5011 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
5013 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
5014 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
5016 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
5017 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
5019 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
5020 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
5021 * be read-only (ie write causes UNDEF exception).
5024 ARMCPRegInfo id_pre_v8_midr_cp_reginfo
[] = {
5025 /* Pre-v8 MIDR space.
5026 * Note that the MIDR isn't a simple constant register because
5027 * of the TI925 behaviour where writes to another register can
5028 * cause the MIDR value to change.
5030 * Unimplemented registers in the c15 0 0 0 space default to
5031 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
5032 * and friends override accordingly.
5035 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
5036 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
5037 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
5038 .readfn
= midr_read
,
5039 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
5040 .type
= ARM_CP_OVERRIDE
},
5041 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
5043 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
5044 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5046 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
5047 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5049 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
5050 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5052 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
5053 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5055 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
5056 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5059 ARMCPRegInfo id_v8_midr_cp_reginfo
[] = {
5060 { .name
= "MIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
5061 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 0,
5062 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
, .resetvalue
= cpu
->midr
,
5063 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
5064 .readfn
= midr_read
},
5065 /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
5066 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
5067 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
5068 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
5069 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
5070 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 7,
5071 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
5072 { .name
= "REVIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
5073 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 6,
5074 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->revidr
},
5077 ARMCPRegInfo id_cp_reginfo
[] = {
5078 /* These are common to v8 and pre-v8 */
5080 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
5081 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
5082 { .name
= "CTR_EL0", .state
= ARM_CP_STATE_AA64
,
5083 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 0, .crm
= 0,
5084 .access
= PL0_R
, .accessfn
= ctr_el0_access
,
5085 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
5086 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
5088 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
5089 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5092 /* TLBTR is specific to VMSA */
5093 ARMCPRegInfo id_tlbtr_reginfo
= {
5095 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
5096 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0,
5098 /* MPUIR is specific to PMSA V6+ */
5099 ARMCPRegInfo id_mpuir_reginfo
= {
5101 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
5102 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5103 .resetvalue
= cpu
->pmsav7_dregion
<< 8
5105 ARMCPRegInfo crn0_wi_reginfo
= {
5106 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
5107 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
5108 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
5110 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
5111 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
5113 /* Register the blanket "writes ignored" value first to cover the
5114 * whole space. Then update the specific ID registers to allow write
5115 * access, so that they ignore writes rather than causing them to
5118 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
5119 for (r
= id_pre_v8_midr_cp_reginfo
;
5120 r
->type
!= ARM_CP_SENTINEL
; r
++) {
5123 for (r
= id_cp_reginfo
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
5126 id_tlbtr_reginfo
.access
= PL1_RW
;
5127 id_tlbtr_reginfo
.access
= PL1_RW
;
5129 if (arm_feature(env
, ARM_FEATURE_V8
)) {
5130 define_arm_cp_regs(cpu
, id_v8_midr_cp_reginfo
);
5132 define_arm_cp_regs(cpu
, id_pre_v8_midr_cp_reginfo
);
5134 define_arm_cp_regs(cpu
, id_cp_reginfo
);
5135 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
5136 define_one_arm_cp_reg(cpu
, &id_tlbtr_reginfo
);
5137 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
5138 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
5142 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
5143 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
5146 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
5147 ARMCPRegInfo auxcr_reginfo
[] = {
5148 { .name
= "ACTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
5149 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 1,
5150 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
5151 .resetvalue
= cpu
->reset_auxcr
},
5152 { .name
= "ACTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
5153 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 1,
5154 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5156 { .name
= "ACTLR_EL3", .state
= ARM_CP_STATE_AA64
,
5157 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 1,
5158 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5162 define_arm_cp_regs(cpu
, auxcr_reginfo
);
5165 if (arm_feature(env
, ARM_FEATURE_CBAR
)) {
5166 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
5167 /* 32 bit view is [31:18] 0...0 [43:32]. */
5168 uint32_t cbar32
= (extract64(cpu
->reset_cbar
, 18, 14) << 18)
5169 | extract64(cpu
->reset_cbar
, 32, 12);
5170 ARMCPRegInfo cbar_reginfo
[] = {
5172 .type
= ARM_CP_CONST
,
5173 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
5174 .access
= PL1_R
, .resetvalue
= cpu
->reset_cbar
},
5175 { .name
= "CBAR_EL1", .state
= ARM_CP_STATE_AA64
,
5176 .type
= ARM_CP_CONST
,
5177 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 3, .opc2
= 0,
5178 .access
= PL1_R
, .resetvalue
= cbar32
},
5181 /* We don't implement a r/w 64 bit CBAR currently */
5182 assert(arm_feature(env
, ARM_FEATURE_CBAR_RO
));
5183 define_arm_cp_regs(cpu
, cbar_reginfo
);
5185 ARMCPRegInfo cbar
= {
5187 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
5188 .access
= PL1_R
|PL3_W
, .resetvalue
= cpu
->reset_cbar
,
5189 .fieldoffset
= offsetof(CPUARMState
,
5190 cp15
.c15_config_base_address
)
5192 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
5193 cbar
.access
= PL1_R
;
5194 cbar
.fieldoffset
= 0;
5195 cbar
.type
= ARM_CP_CONST
;
5197 define_one_arm_cp_reg(cpu
, &cbar
);
5201 if (arm_feature(env
, ARM_FEATURE_VBAR
)) {
5202 ARMCPRegInfo vbar_cp_reginfo
[] = {
5203 { .name
= "VBAR", .state
= ARM_CP_STATE_BOTH
,
5204 .opc0
= 3, .crn
= 12, .crm
= 0, .opc1
= 0, .opc2
= 0,
5205 .access
= PL1_RW
, .writefn
= vbar_write
,
5206 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.vbar_s
),
5207 offsetof(CPUARMState
, cp15
.vbar_ns
) },
5211 define_arm_cp_regs(cpu
, vbar_cp_reginfo
);
5214 /* Generic registers whose values depend on the implementation */
5216 ARMCPRegInfo sctlr
= {
5217 .name
= "SCTLR", .state
= ARM_CP_STATE_BOTH
,
5218 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
5220 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.sctlr_s
),
5221 offsetof(CPUARMState
, cp15
.sctlr_ns
) },
5222 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
5223 .raw_writefn
= raw_write
,
5225 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
5226 /* Normally we would always end the TB on an SCTLR write, but Linux
5227 * arch/arm/mach-pxa/sleep.S expects two instructions following
5228 * an MMU enable to execute from cache. Imitate this behaviour.
5230 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
5232 define_one_arm_cp_reg(cpu
, &sctlr
);
5236 void arm_cpu_register_gdb_regs_for_features(ARMCPU
*cpu
)
5238 CPUState
*cs
= CPU(cpu
);
5239 CPUARMState
*env
= &cpu
->env
;
5241 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
5242 gdb_register_coprocessor(cs
, aarch64_fpu_gdb_get_reg
,
5243 aarch64_fpu_gdb_set_reg
,
5244 34, "aarch64-fpu.xml", 0);
5245 } else if (arm_feature(env
, ARM_FEATURE_NEON
)) {
5246 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
5247 51, "arm-neon.xml", 0);
5248 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
5249 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
5250 35, "arm-vfp3.xml", 0);
5251 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
5252 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
5253 19, "arm-vfp.xml", 0);
5257 /* Sort alphabetically by type name, except for "any". */
5258 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
5260 ObjectClass
*class_a
= (ObjectClass
*)a
;
5261 ObjectClass
*class_b
= (ObjectClass
*)b
;
5262 const char *name_a
, *name_b
;
5264 name_a
= object_class_get_name(class_a
);
5265 name_b
= object_class_get_name(class_b
);
5266 if (strcmp(name_a
, "any-" TYPE_ARM_CPU
) == 0) {
5268 } else if (strcmp(name_b
, "any-" TYPE_ARM_CPU
) == 0) {
5271 return strcmp(name_a
, name_b
);
5275 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
5277 ObjectClass
*oc
= data
;
5278 CPUListState
*s
= user_data
;
5279 const char *typename
;
5282 typename
= object_class_get_name(oc
);
5283 name
= g_strndup(typename
, strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
5284 (*s
->cpu_fprintf
)(s
->file
, " %s\n",
5289 void arm_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
5293 .cpu_fprintf
= cpu_fprintf
,
5297 list
= object_class_get_list(TYPE_ARM_CPU
, false);
5298 list
= g_slist_sort(list
, arm_cpu_list_compare
);
5299 (*cpu_fprintf
)(f
, "Available CPUs:\n");
5300 g_slist_foreach(list
, arm_cpu_list_entry
, &s
);
5303 /* The 'host' CPU type is dynamically registered only if KVM is
5304 * enabled, so we have to special-case it here:
5306 (*cpu_fprintf
)(f
, " host (only available in KVM mode)\n");
5310 static void arm_cpu_add_definition(gpointer data
, gpointer user_data
)
5312 ObjectClass
*oc
= data
;
5313 CpuDefinitionInfoList
**cpu_list
= user_data
;
5314 CpuDefinitionInfoList
*entry
;
5315 CpuDefinitionInfo
*info
;
5316 const char *typename
;
5318 typename
= object_class_get_name(oc
);
5319 info
= g_malloc0(sizeof(*info
));
5320 info
->name
= g_strndup(typename
,
5321 strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
5322 info
->q_typename
= g_strdup(typename
);
5324 entry
= g_malloc0(sizeof(*entry
));
5325 entry
->value
= info
;
5326 entry
->next
= *cpu_list
;
5330 CpuDefinitionInfoList
*arch_query_cpu_definitions(Error
**errp
)
5332 CpuDefinitionInfoList
*cpu_list
= NULL
;
5335 list
= object_class_get_list(TYPE_ARM_CPU
, false);
5336 g_slist_foreach(list
, arm_cpu_add_definition
, &cpu_list
);
5342 static void add_cpreg_to_hashtable(ARMCPU
*cpu
, const ARMCPRegInfo
*r
,
5343 void *opaque
, int state
, int secstate
,
5344 int crm
, int opc1
, int opc2
)
5346 /* Private utility function for define_one_arm_cp_reg_with_opaque():
5347 * add a single reginfo struct to the hash table.
5349 uint32_t *key
= g_new(uint32_t, 1);
5350 ARMCPRegInfo
*r2
= g_memdup(r
, sizeof(ARMCPRegInfo
));
5351 int is64
= (r
->type
& ARM_CP_64BIT
) ? 1 : 0;
5352 int ns
= (secstate
& ARM_CP_SECSTATE_NS
) ? 1 : 0;
5354 /* Reset the secure state to the specific incoming state. This is
5355 * necessary as the register may have been defined with both states.
5357 r2
->secure
= secstate
;
5359 if (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1]) {
5360 /* Register is banked (using both entries in array).
5361 * Overwriting fieldoffset as the array is only used to define
5362 * banked registers but later only fieldoffset is used.
5364 r2
->fieldoffset
= r
->bank_fieldoffsets
[ns
];
5367 if (state
== ARM_CP_STATE_AA32
) {
5368 if (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1]) {
5369 /* If the register is banked then we don't need to migrate or
5370 * reset the 32-bit instance in certain cases:
5372 * 1) If the register has both 32-bit and 64-bit instances then we
5373 * can count on the 64-bit instance taking care of the
5375 * 2) If ARMv8 is enabled then we can count on a 64-bit version
5376 * taking care of the secure bank. This requires that separate
5377 * 32 and 64-bit definitions are provided.
5379 if ((r
->state
== ARM_CP_STATE_BOTH
&& ns
) ||
5380 (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) && !ns
)) {
5381 r2
->type
|= ARM_CP_ALIAS
;
5383 } else if ((secstate
!= r
->secure
) && !ns
) {
5384 /* The register is not banked so we only want to allow migration of
5385 * the non-secure instance.
5387 r2
->type
|= ARM_CP_ALIAS
;
5390 if (r
->state
== ARM_CP_STATE_BOTH
) {
5391 /* We assume it is a cp15 register if the .cp field is left unset.
5397 #ifdef HOST_WORDS_BIGENDIAN
5398 if (r2
->fieldoffset
) {
5399 r2
->fieldoffset
+= sizeof(uint32_t);
5404 if (state
== ARM_CP_STATE_AA64
) {
5405 /* To allow abbreviation of ARMCPRegInfo
5406 * definitions, we treat cp == 0 as equivalent to
5407 * the value for "standard guest-visible sysreg".
5408 * STATE_BOTH definitions are also always "standard
5409 * sysreg" in their AArch64 view (the .cp value may
5410 * be non-zero for the benefit of the AArch32 view).
5412 if (r
->cp
== 0 || r
->state
== ARM_CP_STATE_BOTH
) {
5413 r2
->cp
= CP_REG_ARM64_SYSREG_CP
;
5415 *key
= ENCODE_AA64_CP_REG(r2
->cp
, r2
->crn
, crm
,
5416 r2
->opc0
, opc1
, opc2
);
5418 *key
= ENCODE_CP_REG(r2
->cp
, is64
, ns
, r2
->crn
, crm
, opc1
, opc2
);
5421 r2
->opaque
= opaque
;
5423 /* reginfo passed to helpers is correct for the actual access,
5424 * and is never ARM_CP_STATE_BOTH:
5427 /* Make sure reginfo passed to helpers for wildcarded regs
5428 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
5433 /* By convention, for wildcarded registers only the first
5434 * entry is used for migration; the others are marked as
5435 * ALIAS so we don't try to transfer the register
5436 * multiple times. Special registers (ie NOP/WFI) are
5437 * never migratable and not even raw-accessible.
5439 if ((r
->type
& ARM_CP_SPECIAL
)) {
5440 r2
->type
|= ARM_CP_NO_RAW
;
5442 if (((r
->crm
== CP_ANY
) && crm
!= 0) ||
5443 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
5444 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
5445 r2
->type
|= ARM_CP_ALIAS
;
5448 /* Check that raw accesses are either forbidden or handled. Note that
5449 * we can't assert this earlier because the setup of fieldoffset for
5450 * banked registers has to be done first.
5452 if (!(r2
->type
& ARM_CP_NO_RAW
)) {
5453 assert(!raw_accessors_invalid(r2
));
5456 /* Overriding of an existing definition must be explicitly
5459 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
5460 ARMCPRegInfo
*oldreg
;
5461 oldreg
= g_hash_table_lookup(cpu
->cp_regs
, key
);
5462 if (oldreg
&& !(oldreg
->type
& ARM_CP_OVERRIDE
)) {
5463 fprintf(stderr
, "Register redefined: cp=%d %d bit "
5464 "crn=%d crm=%d opc1=%d opc2=%d, "
5465 "was %s, now %s\n", r2
->cp
, 32 + 32 * is64
,
5466 r2
->crn
, r2
->crm
, r2
->opc1
, r2
->opc2
,
5467 oldreg
->name
, r2
->name
);
5468 g_assert_not_reached();
5471 g_hash_table_insert(cpu
->cp_regs
, key
, r2
);
5475 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
5476 const ARMCPRegInfo
*r
, void *opaque
)
5478 /* Define implementations of coprocessor registers.
5479 * We store these in a hashtable because typically
5480 * there are less than 150 registers in a space which
5481 * is 16*16*16*8*8 = 262144 in size.
5482 * Wildcarding is supported for the crm, opc1 and opc2 fields.
5483 * If a register is defined twice then the second definition is
5484 * used, so this can be used to define some generic registers and
5485 * then override them with implementation specific variations.
5486 * At least one of the original and the second definition should
5487 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
5488 * against accidental use.
5490 * The state field defines whether the register is to be
5491 * visible in the AArch32 or AArch64 execution state. If the
5492 * state is set to ARM_CP_STATE_BOTH then we synthesise a
5493 * reginfo structure for the AArch32 view, which sees the lower
5494 * 32 bits of the 64 bit register.
5496 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
5497 * be wildcarded. AArch64 registers are always considered to be 64
5498 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
5499 * the register, if any.
5501 int crm
, opc1
, opc2
, state
;
5502 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
5503 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
5504 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
5505 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
5506 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
5507 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
5508 /* 64 bit registers have only CRm and Opc1 fields */
5509 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
5510 /* op0 only exists in the AArch64 encodings */
5511 assert((r
->state
!= ARM_CP_STATE_AA32
) || (r
->opc0
== 0));
5512 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
5513 assert((r
->state
!= ARM_CP_STATE_AA64
) || !(r
->type
& ARM_CP_64BIT
));
5514 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
5515 * encodes a minimum access level for the register. We roll this
5516 * runtime check into our general permission check code, so check
5517 * here that the reginfo's specified permissions are strict enough
5518 * to encompass the generic architectural permission check.
5520 if (r
->state
!= ARM_CP_STATE_AA32
) {
5523 case 0: case 1: case 2:
5536 /* unallocated encoding, so not possible */
5544 /* min_EL EL1, secure mode only (we don't check the latter) */
5548 /* broken reginfo with out-of-range opc1 */
5552 /* assert our permissions are not too lax (stricter is fine) */
5553 assert((r
->access
& ~mask
) == 0);
5556 /* Check that the register definition has enough info to handle
5557 * reads and writes if they are permitted.
5559 if (!(r
->type
& (ARM_CP_SPECIAL
|ARM_CP_CONST
))) {
5560 if (r
->access
& PL3_R
) {
5561 assert((r
->fieldoffset
||
5562 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
5565 if (r
->access
& PL3_W
) {
5566 assert((r
->fieldoffset
||
5567 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
5571 /* Bad type field probably means missing sentinel at end of reg list */
5572 assert(cptype_valid(r
->type
));
5573 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
5574 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
5575 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
5576 for (state
= ARM_CP_STATE_AA32
;
5577 state
<= ARM_CP_STATE_AA64
; state
++) {
5578 if (r
->state
!= state
&& r
->state
!= ARM_CP_STATE_BOTH
) {
5581 if (state
== ARM_CP_STATE_AA32
) {
5582 /* Under AArch32 CP registers can be common
5583 * (same for secure and non-secure world) or banked.
5585 switch (r
->secure
) {
5586 case ARM_CP_SECSTATE_S
:
5587 case ARM_CP_SECSTATE_NS
:
5588 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
5589 r
->secure
, crm
, opc1
, opc2
);
5592 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
5595 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
5601 /* AArch64 registers get mapped to non-secure instance
5603 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
5613 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
5614 const ARMCPRegInfo
*regs
, void *opaque
)
5616 /* Define a whole list of registers */
5617 const ARMCPRegInfo
*r
;
5618 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
5619 define_one_arm_cp_reg_with_opaque(cpu
, r
, opaque
);
5623 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
)
5625 return g_hash_table_lookup(cpregs
, &encoded_cp
);
5628 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5631 /* Helper coprocessor write function for write-ignore registers */
5634 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5636 /* Helper coprocessor write function for read-as-zero registers */
5640 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
5642 /* Helper coprocessor reset function for do-nothing-on-reset registers */
5645 static int bad_mode_switch(CPUARMState
*env
, int mode
, CPSRWriteType write_type
)
5647 /* Return true if it is not valid for us to switch to
5648 * this CPU mode (ie all the UNPREDICTABLE cases in
5649 * the ARM ARM CPSRWriteByInstr pseudocode).
5652 /* Changes to or from Hyp via MSR and CPS are illegal. */
5653 if (write_type
== CPSRWriteByInstr
&&
5654 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_HYP
||
5655 mode
== ARM_CPU_MODE_HYP
)) {
5660 case ARM_CPU_MODE_USR
:
5662 case ARM_CPU_MODE_SYS
:
5663 case ARM_CPU_MODE_SVC
:
5664 case ARM_CPU_MODE_ABT
:
5665 case ARM_CPU_MODE_UND
:
5666 case ARM_CPU_MODE_IRQ
:
5667 case ARM_CPU_MODE_FIQ
:
5668 /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
5669 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
5671 /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
5672 * and CPS are treated as illegal mode changes.
5674 if (write_type
== CPSRWriteByInstr
&&
5675 (env
->cp15
.hcr_el2
& HCR_TGE
) &&
5676 (env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
&&
5677 !arm_is_secure_below_el3(env
)) {
5681 case ARM_CPU_MODE_HYP
:
5682 return !arm_feature(env
, ARM_FEATURE_EL2
)
5683 || arm_current_el(env
) < 2 || arm_is_secure(env
);
5684 case ARM_CPU_MODE_MON
:
5685 return arm_current_el(env
) < 3;
5691 uint32_t cpsr_read(CPUARMState
*env
)
5694 ZF
= (env
->ZF
== 0);
5695 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
5696 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
5697 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
5698 | ((env
->condexec_bits
& 0xfc) << 8)
5699 | (env
->GE
<< 16) | (env
->daif
& CPSR_AIF
);
5702 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
,
5703 CPSRWriteType write_type
)
5705 uint32_t changed_daif
;
5707 if (mask
& CPSR_NZCV
) {
5708 env
->ZF
= (~val
) & CPSR_Z
;
5710 env
->CF
= (val
>> 29) & 1;
5711 env
->VF
= (val
<< 3) & 0x80000000;
5714 env
->QF
= ((val
& CPSR_Q
) != 0);
5716 env
->thumb
= ((val
& CPSR_T
) != 0);
5717 if (mask
& CPSR_IT_0_1
) {
5718 env
->condexec_bits
&= ~3;
5719 env
->condexec_bits
|= (val
>> 25) & 3;
5721 if (mask
& CPSR_IT_2_7
) {
5722 env
->condexec_bits
&= 3;
5723 env
->condexec_bits
|= (val
>> 8) & 0xfc;
5725 if (mask
& CPSR_GE
) {
5726 env
->GE
= (val
>> 16) & 0xf;
5729 /* In a V7 implementation that includes the security extensions but does
5730 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
5731 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
5732 * bits respectively.
5734 * In a V8 implementation, it is permitted for privileged software to
5735 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
5737 if (write_type
!= CPSRWriteRaw
&& !arm_feature(env
, ARM_FEATURE_V8
) &&
5738 arm_feature(env
, ARM_FEATURE_EL3
) &&
5739 !arm_feature(env
, ARM_FEATURE_EL2
) &&
5740 !arm_is_secure(env
)) {
5742 changed_daif
= (env
->daif
^ val
) & mask
;
5744 if (changed_daif
& CPSR_A
) {
5745 /* Check to see if we are allowed to change the masking of async
5746 * abort exceptions from a non-secure state.
5748 if (!(env
->cp15
.scr_el3
& SCR_AW
)) {
5749 qemu_log_mask(LOG_GUEST_ERROR
,
5750 "Ignoring attempt to switch CPSR_A flag from "
5751 "non-secure world with SCR.AW bit clear\n");
5756 if (changed_daif
& CPSR_F
) {
5757 /* Check to see if we are allowed to change the masking of FIQ
5758 * exceptions from a non-secure state.
5760 if (!(env
->cp15
.scr_el3
& SCR_FW
)) {
5761 qemu_log_mask(LOG_GUEST_ERROR
,
5762 "Ignoring attempt to switch CPSR_F flag from "
5763 "non-secure world with SCR.FW bit clear\n");
5767 /* Check whether non-maskable FIQ (NMFI) support is enabled.
5768 * If this bit is set software is not allowed to mask
5769 * FIQs, but is allowed to set CPSR_F to 0.
5771 if ((A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_NMFI
) &&
5773 qemu_log_mask(LOG_GUEST_ERROR
,
5774 "Ignoring attempt to enable CPSR_F flag "
5775 "(non-maskable FIQ [NMFI] support enabled)\n");
5781 env
->daif
&= ~(CPSR_AIF
& mask
);
5782 env
->daif
|= val
& CPSR_AIF
& mask
;
5784 if (write_type
!= CPSRWriteRaw
&&
5785 ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
)) {
5786 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
) {
5787 /* Note that we can only get here in USR mode if this is a
5788 * gdb stub write; for this case we follow the architectural
5789 * behaviour for guest writes in USR mode of ignoring an attempt
5790 * to switch mode. (Those are caught by translate.c for writes
5791 * triggered by guest instructions.)
5794 } else if (bad_mode_switch(env
, val
& CPSR_M
, write_type
)) {
5795 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
5796 * v7, and has defined behaviour in v8:
5797 * + leave CPSR.M untouched
5798 * + allow changes to the other CPSR fields
5800 * For user changes via the GDB stub, we don't set PSTATE.IL,
5801 * as this would be unnecessarily harsh for a user error.
5804 if (write_type
!= CPSRWriteByGDBStub
&&
5805 arm_feature(env
, ARM_FEATURE_V8
)) {
5810 switch_mode(env
, val
& CPSR_M
);
5813 mask
&= ~CACHED_CPSR_BITS
;
5814 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
5817 /* Sign/zero extend */
5818 uint32_t HELPER(sxtb16
)(uint32_t x
)
5821 res
= (uint16_t)(int8_t)x
;
5822 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
5826 uint32_t HELPER(uxtb16
)(uint32_t x
)
5829 res
= (uint16_t)(uint8_t)x
;
5830 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
5834 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
5838 if (num
== INT_MIN
&& den
== -1)
5843 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
5850 uint32_t HELPER(rbit
)(uint32_t x
)
5855 #if defined(CONFIG_USER_ONLY)
5857 /* These should probably raise undefined insn exceptions. */
5858 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
5860 ARMCPU
*cpu
= arm_env_get_cpu(env
);
5862 cpu_abort(CPU(cpu
), "v7m_msr %d\n", reg
);
5865 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
5867 ARMCPU
*cpu
= arm_env_get_cpu(env
);
5869 cpu_abort(CPU(cpu
), "v7m_mrs %d\n", reg
);
5873 void switch_mode(CPUARMState
*env
, int mode
)
5875 ARMCPU
*cpu
= arm_env_get_cpu(env
);
5877 if (mode
!= ARM_CPU_MODE_USR
) {
5878 cpu_abort(CPU(cpu
), "Tried to switch out of user mode\n");
5882 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
5883 uint32_t cur_el
, bool secure
)
5888 void aarch64_sync_64_to_32(CPUARMState
*env
)
5890 g_assert_not_reached();
5895 void switch_mode(CPUARMState
*env
, int mode
)
5900 old_mode
= env
->uncached_cpsr
& CPSR_M
;
5901 if (mode
== old_mode
)
5904 if (old_mode
== ARM_CPU_MODE_FIQ
) {
5905 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
5906 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
5907 } else if (mode
== ARM_CPU_MODE_FIQ
) {
5908 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
5909 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
5912 i
= bank_number(old_mode
);
5913 env
->banked_r13
[i
] = env
->regs
[13];
5914 env
->banked_r14
[i
] = env
->regs
[14];
5915 env
->banked_spsr
[i
] = env
->spsr
;
5917 i
= bank_number(mode
);
5918 env
->regs
[13] = env
->banked_r13
[i
];
5919 env
->regs
[14] = env
->banked_r14
[i
];
5920 env
->spsr
= env
->banked_spsr
[i
];
5923 /* Physical Interrupt Target EL Lookup Table
5925 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
5927 * The below multi-dimensional table is used for looking up the target
5928 * exception level given numerous condition criteria. Specifically, the
5929 * target EL is based on SCR and HCR routing controls as well as the
5930 * currently executing EL and secure state.
5933 * target_el_table[2][2][2][2][2][4]
5934 * | | | | | +--- Current EL
5935 * | | | | +------ Non-secure(0)/Secure(1)
5936 * | | | +--------- HCR mask override
5937 * | | +------------ SCR exec state control
5938 * | +--------------- SCR mask override
5939 * +------------------ 32-bit(0)/64-bit(1) EL3
5941 * The table values are as such:
5945 * The ARM ARM target EL table includes entries indicating that an "exception
5946 * is not taken". The two cases where this is applicable are:
5947 * 1) An exception is taken from EL3 but the SCR does not have the exception
5949 * 2) An exception is taken from EL2 but the HCR does not have the exception
5951 * In these two cases, the below table contain a target of EL1. This value is
5952 * returned as it is expected that the consumer of the table data will check
5953 * for "target EL >= current EL" to ensure the exception is not taken.
5957 * BIT IRQ IMO Non-secure Secure
5958 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
5960 static const int8_t target_el_table
[2][2][2][2][2][4] = {
5961 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
5962 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
5963 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
5964 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
5965 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
5966 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
5967 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
5968 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
5969 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
5970 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},
5971 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },},
5972 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},},
5973 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
5974 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
5975 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
5976 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},},
5980 * Determine the target EL for physical exceptions
5982 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
5983 uint32_t cur_el
, bool secure
)
5985 CPUARMState
*env
= cs
->env_ptr
;
5990 /* Is the highest EL AArch64? */
5991 int is64
= arm_feature(env
, ARM_FEATURE_AARCH64
);
5993 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5994 rw
= ((env
->cp15
.scr_el3
& SCR_RW
) == SCR_RW
);
5996 /* Either EL2 is the highest EL (and so the EL2 register width
5997 * is given by is64); or there is no EL2 or EL3, in which case
5998 * the value of 'rw' does not affect the table lookup anyway.
6005 scr
= ((env
->cp15
.scr_el3
& SCR_IRQ
) == SCR_IRQ
);
6006 hcr
= ((env
->cp15
.hcr_el2
& HCR_IMO
) == HCR_IMO
);
6009 scr
= ((env
->cp15
.scr_el3
& SCR_FIQ
) == SCR_FIQ
);
6010 hcr
= ((env
->cp15
.hcr_el2
& HCR_FMO
) == HCR_FMO
);
6013 scr
= ((env
->cp15
.scr_el3
& SCR_EA
) == SCR_EA
);
6014 hcr
= ((env
->cp15
.hcr_el2
& HCR_AMO
) == HCR_AMO
);
6018 /* If HCR.TGE is set then HCR is treated as being 1 */
6019 hcr
|= ((env
->cp15
.hcr_el2
& HCR_TGE
) == HCR_TGE
);
6021 /* Perform a table-lookup for the target EL given the current state */
6022 target_el
= target_el_table
[is64
][scr
][rw
][hcr
][secure
][cur_el
];
6024 assert(target_el
> 0);
6029 static void v7m_push(CPUARMState
*env
, uint32_t val
)
6031 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
6034 stl_phys(cs
->as
, env
->regs
[13], val
);
6037 static uint32_t v7m_pop(CPUARMState
*env
)
6039 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
6042 val
= ldl_phys(cs
->as
, env
->regs
[13]);
6047 /* Switch to V7M main or process stack pointer. */
6048 static void switch_v7m_sp(CPUARMState
*env
, bool new_spsel
)
6051 uint32_t old_control
= env
->v7m
.control
[env
->v7m
.secure
];
6052 bool old_spsel
= old_control
& R_V7M_CONTROL_SPSEL_MASK
;
6054 if (old_spsel
!= new_spsel
) {
6055 tmp
= env
->v7m
.other_sp
;
6056 env
->v7m
.other_sp
= env
->regs
[13];
6057 env
->regs
[13] = tmp
;
6059 env
->v7m
.control
[env
->v7m
.secure
] = deposit32(old_control
,
6060 R_V7M_CONTROL_SPSEL_SHIFT
,
6061 R_V7M_CONTROL_SPSEL_LENGTH
, new_spsel
);
6065 static uint32_t arm_v7m_load_vector(ARMCPU
*cpu
)
6067 CPUState
*cs
= CPU(cpu
);
6068 CPUARMState
*env
= &cpu
->env
;
6070 hwaddr vec
= env
->v7m
.vecbase
[env
->v7m
.secure
] + env
->v7m
.exception
* 4;
6073 addr
= address_space_ldl(cs
->as
, vec
,
6074 MEMTXATTRS_UNSPECIFIED
, &result
);
6075 if (result
!= MEMTX_OK
) {
6076 /* Architecturally this should cause a HardFault setting HSFR.VECTTBL,
6077 * which would then be immediately followed by our failing to load
6078 * the entry vector for that HardFault, which is a Lockup case.
6079 * Since we don't model Lockup, we just report this guest error
6082 cpu_abort(cs
, "Failed to read from exception vector table "
6083 "entry %08x\n", (unsigned)vec
);
6088 static void v7m_exception_taken(ARMCPU
*cpu
, uint32_t lr
)
6090 /* Do the "take the exception" parts of exception entry,
6091 * but not the pushing of state to the stack. This is
6092 * similar to the pseudocode ExceptionTaken() function.
6094 CPUARMState
*env
= &cpu
->env
;
6097 armv7m_nvic_acknowledge_irq(env
->nvic
);
6098 switch_v7m_sp(env
, 0);
6100 env
->condexec_bits
= 0;
6102 addr
= arm_v7m_load_vector(cpu
);
6103 env
->regs
[15] = addr
& 0xfffffffe;
6104 env
->thumb
= addr
& 1;
6107 static void v7m_push_stack(ARMCPU
*cpu
)
6109 /* Do the "set up stack frame" part of exception entry,
6110 * similar to pseudocode PushStack().
6112 CPUARMState
*env
= &cpu
->env
;
6113 uint32_t xpsr
= xpsr_read(env
);
6115 /* Align stack pointer if the guest wants that */
6116 if ((env
->regs
[13] & 4) &&
6117 (env
->v7m
.ccr
[env
->v7m
.secure
] & R_V7M_CCR_STKALIGN_MASK
)) {
6119 xpsr
|= XPSR_SPREALIGN
;
6121 /* Switch to the handler mode. */
6122 v7m_push(env
, xpsr
);
6123 v7m_push(env
, env
->regs
[15]);
6124 v7m_push(env
, env
->regs
[14]);
6125 v7m_push(env
, env
->regs
[12]);
6126 v7m_push(env
, env
->regs
[3]);
6127 v7m_push(env
, env
->regs
[2]);
6128 v7m_push(env
, env
->regs
[1]);
6129 v7m_push(env
, env
->regs
[0]);
6132 static void do_v7m_exception_exit(ARMCPU
*cpu
)
6134 CPUARMState
*env
= &cpu
->env
;
6137 bool ufault
= false;
6138 bool return_to_sp_process
= false;
6139 bool return_to_handler
= false;
6140 bool rettobase
= false;
6142 /* We can only get here from an EXCP_EXCEPTION_EXIT, and
6143 * gen_bx_excret() enforces the architectural rule
6144 * that jumps to magic addresses don't have magic behaviour unless
6145 * we're in Handler mode (compare pseudocode BXWritePC()).
6147 assert(arm_v7m_is_handler_mode(env
));
6149 /* In the spec pseudocode ExceptionReturn() is called directly
6150 * from BXWritePC() and gets the full target PC value including
6151 * bit zero. In QEMU's implementation we treat it as a normal
6152 * jump-to-register (which is then caught later on), and so split
6153 * the target value up between env->regs[15] and env->thumb in
6154 * gen_bx(). Reconstitute it.
6156 type
= env
->regs
[15];
6161 qemu_log_mask(CPU_LOG_INT
, "Exception return: magic PC %" PRIx32
6162 " previous exception %d\n",
6163 type
, env
->v7m
.exception
);
6165 if (extract32(type
, 5, 23) != extract32(-1, 5, 23)) {
6166 qemu_log_mask(LOG_GUEST_ERROR
, "M profile: zero high bits in exception "
6167 "exit PC value 0x%" PRIx32
" are UNPREDICTABLE\n", type
);
6170 if (env
->v7m
.exception
!= ARMV7M_EXCP_NMI
) {
6171 /* Auto-clear FAULTMASK on return from other than NMI.
6172 * If the security extension is implemented then this only
6173 * happens if the raw execution priority is >= 0; the
6174 * value of the ES bit in the exception return value indicates
6175 * which security state's faultmask to clear. (v8M ARM ARM R_KBNF.)
6177 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
6179 if (armv7m_nvic_raw_execution_priority(env
->nvic
) >= 0) {
6180 env
->v7m
.faultmask
[es
] = 0;
6183 env
->v7m
.faultmask
[M_REG_NS
] = 0;
6187 switch (armv7m_nvic_complete_irq(env
->nvic
, env
->v7m
.exception
)) {
6189 /* attempt to exit an exception that isn't active */
6193 /* still an irq active now */
6196 /* we returned to base exception level, no nesting.
6197 * (In the pseudocode this is written using "NestedActivation != 1"
6198 * where we have 'rettobase == false'.)
6203 g_assert_not_reached();
6206 switch (type
& 0xf) {
6207 case 1: /* Return to Handler */
6208 return_to_handler
= true;
6210 case 13: /* Return to Thread using Process stack */
6211 return_to_sp_process
= true;
6213 case 9: /* Return to Thread using Main stack */
6215 !(env
->v7m
.ccr
[env
->v7m
.secure
] & R_V7M_CCR_NONBASETHRDENA_MASK
)) {
6224 /* Bad exception return: instead of popping the exception
6225 * stack, directly take a usage fault on the current stack.
6227 env
->v7m
.cfsr
|= R_V7M_CFSR_INVPC_MASK
;
6228 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
);
6229 v7m_exception_taken(cpu
, type
| 0xf0000000);
6230 qemu_log_mask(CPU_LOG_INT
, "...taking UsageFault on existing "
6231 "stackframe: failed exception return integrity check\n");
6235 /* Switch to the target stack. */
6236 switch_v7m_sp(env
, return_to_sp_process
);
6237 /* Pop registers. */
6238 env
->regs
[0] = v7m_pop(env
);
6239 env
->regs
[1] = v7m_pop(env
);
6240 env
->regs
[2] = v7m_pop(env
);
6241 env
->regs
[3] = v7m_pop(env
);
6242 env
->regs
[12] = v7m_pop(env
);
6243 env
->regs
[14] = v7m_pop(env
);
6244 env
->regs
[15] = v7m_pop(env
);
6245 if (env
->regs
[15] & 1) {
6246 qemu_log_mask(LOG_GUEST_ERROR
,
6247 "M profile return from interrupt with misaligned "
6248 "PC is UNPREDICTABLE\n");
6249 /* Actual hardware seems to ignore the lsbit, and there are several
6250 * RTOSes out there which incorrectly assume the r15 in the stack
6251 * frame should be a Thumb-style "lsbit indicates ARM/Thumb" value.
6253 env
->regs
[15] &= ~1U;
6255 xpsr
= v7m_pop(env
);
6256 xpsr_write(env
, xpsr
, ~XPSR_SPREALIGN
);
6257 /* Undo stack alignment. */
6258 if (xpsr
& XPSR_SPREALIGN
) {
6262 /* The restored xPSR exception field will be zero if we're
6263 * resuming in Thread mode. If that doesn't match what the
6264 * exception return type specified then this is a UsageFault.
6266 if (return_to_handler
!= arm_v7m_is_handler_mode(env
)) {
6267 /* Take an INVPC UsageFault by pushing the stack again. */
6268 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
);
6269 env
->v7m
.cfsr
|= R_V7M_CFSR_INVPC_MASK
;
6270 v7m_push_stack(cpu
);
6271 v7m_exception_taken(cpu
, type
| 0xf0000000);
6272 qemu_log_mask(CPU_LOG_INT
, "...taking UsageFault on new stackframe: "
6273 "failed exception return integrity check\n");
6277 /* Otherwise, we have a successful exception exit. */
6278 qemu_log_mask(CPU_LOG_INT
, "...successful exception return\n");
6281 static void arm_log_exception(int idx
)
6283 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
6284 const char *exc
= NULL
;
6285 static const char * const excnames
[] = {
6286 [EXCP_UDEF
] = "Undefined Instruction",
6288 [EXCP_PREFETCH_ABORT
] = "Prefetch Abort",
6289 [EXCP_DATA_ABORT
] = "Data Abort",
6292 [EXCP_BKPT
] = "Breakpoint",
6293 [EXCP_EXCEPTION_EXIT
] = "QEMU v7M exception exit",
6294 [EXCP_KERNEL_TRAP
] = "QEMU intercept of kernel commpage",
6295 [EXCP_HVC
] = "Hypervisor Call",
6296 [EXCP_HYP_TRAP
] = "Hypervisor Trap",
6297 [EXCP_SMC
] = "Secure Monitor Call",
6298 [EXCP_VIRQ
] = "Virtual IRQ",
6299 [EXCP_VFIQ
] = "Virtual FIQ",
6300 [EXCP_SEMIHOST
] = "Semihosting call",
6301 [EXCP_NOCP
] = "v7M NOCP UsageFault",
6302 [EXCP_INVSTATE
] = "v7M INVSTATE UsageFault",
6305 if (idx
>= 0 && idx
< ARRAY_SIZE(excnames
)) {
6306 exc
= excnames
[idx
];
6311 qemu_log_mask(CPU_LOG_INT
, "Taking exception %d [%s]\n", idx
, exc
);
6315 void arm_v7m_cpu_do_interrupt(CPUState
*cs
)
6317 ARMCPU
*cpu
= ARM_CPU(cs
);
6318 CPUARMState
*env
= &cpu
->env
;
6321 arm_log_exception(cs
->exception_index
);
6323 /* For exceptions we just mark as pending on the NVIC, and let that
6325 switch (cs
->exception_index
) {
6327 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
);
6328 env
->v7m
.cfsr
|= R_V7M_CFSR_UNDEFINSTR_MASK
;
6331 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
);
6332 env
->v7m
.cfsr
|= R_V7M_CFSR_NOCP_MASK
;
6335 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
);
6336 env
->v7m
.cfsr
|= R_V7M_CFSR_INVSTATE_MASK
;
6339 /* The PC already points to the next instruction. */
6340 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SVC
);
6342 case EXCP_PREFETCH_ABORT
:
6343 case EXCP_DATA_ABORT
:
6344 /* Note that for M profile we don't have a guest facing FSR, but
6345 * the env->exception.fsr will be populated by the code that
6346 * raises the fault, in the A profile short-descriptor format.
6348 switch (env
->exception
.fsr
& 0xf) {
6349 case 0x8: /* External Abort */
6350 switch (cs
->exception_index
) {
6351 case EXCP_PREFETCH_ABORT
:
6352 env
->v7m
.cfsr
|= R_V7M_CFSR_PRECISERR_MASK
;
6353 qemu_log_mask(CPU_LOG_INT
, "...with CFSR.PRECISERR\n");
6355 case EXCP_DATA_ABORT
:
6357 (R_V7M_CFSR_IBUSERR_MASK
| R_V7M_CFSR_BFARVALID_MASK
);
6358 env
->v7m
.bfar
= env
->exception
.vaddress
;
6359 qemu_log_mask(CPU_LOG_INT
,
6360 "...with CFSR.IBUSERR and BFAR 0x%x\n",
6364 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_BUS
);
6367 /* All other FSR values are either MPU faults or "can't happen
6368 * for M profile" cases.
6370 switch (cs
->exception_index
) {
6371 case EXCP_PREFETCH_ABORT
:
6372 env
->v7m
.cfsr
|= R_V7M_CFSR_IACCVIOL_MASK
;
6373 qemu_log_mask(CPU_LOG_INT
, "...with CFSR.IACCVIOL\n");
6375 case EXCP_DATA_ABORT
:
6377 (R_V7M_CFSR_DACCVIOL_MASK
| R_V7M_CFSR_MMARVALID_MASK
);
6378 env
->v7m
.mmfar
= env
->exception
.vaddress
;
6379 qemu_log_mask(CPU_LOG_INT
,
6380 "...with CFSR.DACCVIOL and MMFAR 0x%x\n",
6384 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
);
6389 if (semihosting_enabled()) {
6391 nr
= arm_lduw_code(env
, env
->regs
[15], arm_sctlr_b(env
)) & 0xff;
6394 qemu_log_mask(CPU_LOG_INT
,
6395 "...handling as semihosting call 0x%x\n",
6397 env
->regs
[0] = do_arm_semihosting(env
);
6401 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_DEBUG
);
6405 case EXCP_EXCEPTION_EXIT
:
6406 do_v7m_exception_exit(cpu
);
6409 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
6410 return; /* Never happens. Keep compiler happy. */
6414 if (env
->v7m
.control
[env
->v7m
.secure
] & R_V7M_CONTROL_SPSEL_MASK
) {
6417 if (!arm_v7m_is_handler_mode(env
)) {
6421 v7m_push_stack(cpu
);
6422 v7m_exception_taken(cpu
, lr
);
6423 qemu_log_mask(CPU_LOG_INT
, "... as %d\n", env
->v7m
.exception
);
6426 /* Function used to synchronize QEMU's AArch64 register set with AArch32
6427 * register set. This is necessary when switching between AArch32 and AArch64
6430 void aarch64_sync_32_to_64(CPUARMState
*env
)
6433 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
6435 /* We can blanket copy R[0:7] to X[0:7] */
6436 for (i
= 0; i
< 8; i
++) {
6437 env
->xregs
[i
] = env
->regs
[i
];
6440 /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
6441 * Otherwise, they come from the banked user regs.
6443 if (mode
== ARM_CPU_MODE_FIQ
) {
6444 for (i
= 8; i
< 13; i
++) {
6445 env
->xregs
[i
] = env
->usr_regs
[i
- 8];
6448 for (i
= 8; i
< 13; i
++) {
6449 env
->xregs
[i
] = env
->regs
[i
];
6453 /* Registers x13-x23 are the various mode SP and FP registers. Registers
6454 * r13 and r14 are only copied if we are in that mode, otherwise we copy
6455 * from the mode banked register.
6457 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
6458 env
->xregs
[13] = env
->regs
[13];
6459 env
->xregs
[14] = env
->regs
[14];
6461 env
->xregs
[13] = env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)];
6462 /* HYP is an exception in that it is copied from r14 */
6463 if (mode
== ARM_CPU_MODE_HYP
) {
6464 env
->xregs
[14] = env
->regs
[14];
6466 env
->xregs
[14] = env
->banked_r14
[bank_number(ARM_CPU_MODE_USR
)];
6470 if (mode
== ARM_CPU_MODE_HYP
) {
6471 env
->xregs
[15] = env
->regs
[13];
6473 env
->xregs
[15] = env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)];
6476 if (mode
== ARM_CPU_MODE_IRQ
) {
6477 env
->xregs
[16] = env
->regs
[14];
6478 env
->xregs
[17] = env
->regs
[13];
6480 env
->xregs
[16] = env
->banked_r14
[bank_number(ARM_CPU_MODE_IRQ
)];
6481 env
->xregs
[17] = env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)];
6484 if (mode
== ARM_CPU_MODE_SVC
) {
6485 env
->xregs
[18] = env
->regs
[14];
6486 env
->xregs
[19] = env
->regs
[13];
6488 env
->xregs
[18] = env
->banked_r14
[bank_number(ARM_CPU_MODE_SVC
)];
6489 env
->xregs
[19] = env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)];
6492 if (mode
== ARM_CPU_MODE_ABT
) {
6493 env
->xregs
[20] = env
->regs
[14];
6494 env
->xregs
[21] = env
->regs
[13];
6496 env
->xregs
[20] = env
->banked_r14
[bank_number(ARM_CPU_MODE_ABT
)];
6497 env
->xregs
[21] = env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)];
6500 if (mode
== ARM_CPU_MODE_UND
) {
6501 env
->xregs
[22] = env
->regs
[14];
6502 env
->xregs
[23] = env
->regs
[13];
6504 env
->xregs
[22] = env
->banked_r14
[bank_number(ARM_CPU_MODE_UND
)];
6505 env
->xregs
[23] = env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)];
6508 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
6509 * mode, then we can copy from r8-r14. Otherwise, we copy from the
6510 * FIQ bank for r8-r14.
6512 if (mode
== ARM_CPU_MODE_FIQ
) {
6513 for (i
= 24; i
< 31; i
++) {
6514 env
->xregs
[i
] = env
->regs
[i
- 16]; /* X[24:30] <- R[8:14] */
6517 for (i
= 24; i
< 29; i
++) {
6518 env
->xregs
[i
] = env
->fiq_regs
[i
- 24];
6520 env
->xregs
[29] = env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)];
6521 env
->xregs
[30] = env
->banked_r14
[bank_number(ARM_CPU_MODE_FIQ
)];
6524 env
->pc
= env
->regs
[15];
6527 /* Function used to synchronize QEMU's AArch32 register set with AArch64
6528 * register set. This is necessary when switching between AArch32 and AArch64
6531 void aarch64_sync_64_to_32(CPUARMState
*env
)
6534 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
6536 /* We can blanket copy X[0:7] to R[0:7] */
6537 for (i
= 0; i
< 8; i
++) {
6538 env
->regs
[i
] = env
->xregs
[i
];
6541 /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
6542 * Otherwise, we copy x8-x12 into the banked user regs.
6544 if (mode
== ARM_CPU_MODE_FIQ
) {
6545 for (i
= 8; i
< 13; i
++) {
6546 env
->usr_regs
[i
- 8] = env
->xregs
[i
];
6549 for (i
= 8; i
< 13; i
++) {
6550 env
->regs
[i
] = env
->xregs
[i
];
6554 /* Registers r13 & r14 depend on the current mode.
6555 * If we are in a given mode, we copy the corresponding x registers to r13
6556 * and r14. Otherwise, we copy the x register to the banked r13 and r14
6559 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
6560 env
->regs
[13] = env
->xregs
[13];
6561 env
->regs
[14] = env
->xregs
[14];
6563 env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[13];
6565 /* HYP is an exception in that it does not have its own banked r14 but
6566 * shares the USR r14
6568 if (mode
== ARM_CPU_MODE_HYP
) {
6569 env
->regs
[14] = env
->xregs
[14];
6571 env
->banked_r14
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[14];
6575 if (mode
== ARM_CPU_MODE_HYP
) {
6576 env
->regs
[13] = env
->xregs
[15];
6578 env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)] = env
->xregs
[15];
6581 if (mode
== ARM_CPU_MODE_IRQ
) {
6582 env
->regs
[14] = env
->xregs
[16];
6583 env
->regs
[13] = env
->xregs
[17];
6585 env
->banked_r14
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[16];
6586 env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[17];
6589 if (mode
== ARM_CPU_MODE_SVC
) {
6590 env
->regs
[14] = env
->xregs
[18];
6591 env
->regs
[13] = env
->xregs
[19];
6593 env
->banked_r14
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[18];
6594 env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[19];
6597 if (mode
== ARM_CPU_MODE_ABT
) {
6598 env
->regs
[14] = env
->xregs
[20];
6599 env
->regs
[13] = env
->xregs
[21];
6601 env
->banked_r14
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[20];
6602 env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[21];
6605 if (mode
== ARM_CPU_MODE_UND
) {
6606 env
->regs
[14] = env
->xregs
[22];
6607 env
->regs
[13] = env
->xregs
[23];
6609 env
->banked_r14
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[22];
6610 env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[23];
6613 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
6614 * mode, then we can copy to r8-r14. Otherwise, we copy to the
6615 * FIQ bank for r8-r14.
6617 if (mode
== ARM_CPU_MODE_FIQ
) {
6618 for (i
= 24; i
< 31; i
++) {
6619 env
->regs
[i
- 16] = env
->xregs
[i
]; /* X[24:30] -> R[8:14] */
6622 for (i
= 24; i
< 29; i
++) {
6623 env
->fiq_regs
[i
- 24] = env
->xregs
[i
];
6625 env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[29];
6626 env
->banked_r14
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[30];
6629 env
->regs
[15] = env
->pc
;
6632 static void arm_cpu_do_interrupt_aarch32(CPUState
*cs
)
6634 ARMCPU
*cpu
= ARM_CPU(cs
);
6635 CPUARMState
*env
= &cpu
->env
;
6642 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
6643 switch (env
->exception
.syndrome
>> ARM_EL_EC_SHIFT
) {
6645 case EC_BREAKPOINT_SAME_EL
:
6649 case EC_WATCHPOINT_SAME_EL
:
6655 case EC_VECTORCATCH
:
6664 env
->cp15
.mdscr_el1
= deposit64(env
->cp15
.mdscr_el1
, 2, 4, moe
);
6667 /* TODO: Vectored interrupt controller. */
6668 switch (cs
->exception_index
) {
6670 new_mode
= ARM_CPU_MODE_UND
;
6679 new_mode
= ARM_CPU_MODE_SVC
;
6682 /* The PC already points to the next instruction. */
6686 env
->exception
.fsr
= 2;
6687 /* Fall through to prefetch abort. */
6688 case EXCP_PREFETCH_ABORT
:
6689 A32_BANKED_CURRENT_REG_SET(env
, ifsr
, env
->exception
.fsr
);
6690 A32_BANKED_CURRENT_REG_SET(env
, ifar
, env
->exception
.vaddress
);
6691 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x IFAR 0x%x\n",
6692 env
->exception
.fsr
, (uint32_t)env
->exception
.vaddress
);
6693 new_mode
= ARM_CPU_MODE_ABT
;
6695 mask
= CPSR_A
| CPSR_I
;
6698 case EXCP_DATA_ABORT
:
6699 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
6700 A32_BANKED_CURRENT_REG_SET(env
, dfar
, env
->exception
.vaddress
);
6701 qemu_log_mask(CPU_LOG_INT
, "...with DFSR 0x%x DFAR 0x%x\n",
6703 (uint32_t)env
->exception
.vaddress
);
6704 new_mode
= ARM_CPU_MODE_ABT
;
6706 mask
= CPSR_A
| CPSR_I
;
6710 new_mode
= ARM_CPU_MODE_IRQ
;
6712 /* Disable IRQ and imprecise data aborts. */
6713 mask
= CPSR_A
| CPSR_I
;
6715 if (env
->cp15
.scr_el3
& SCR_IRQ
) {
6716 /* IRQ routed to monitor mode */
6717 new_mode
= ARM_CPU_MODE_MON
;
6722 new_mode
= ARM_CPU_MODE_FIQ
;
6724 /* Disable FIQ, IRQ and imprecise data aborts. */
6725 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
6726 if (env
->cp15
.scr_el3
& SCR_FIQ
) {
6727 /* FIQ routed to monitor mode */
6728 new_mode
= ARM_CPU_MODE_MON
;
6733 new_mode
= ARM_CPU_MODE_IRQ
;
6735 /* Disable IRQ and imprecise data aborts. */
6736 mask
= CPSR_A
| CPSR_I
;
6740 new_mode
= ARM_CPU_MODE_FIQ
;
6742 /* Disable FIQ, IRQ and imprecise data aborts. */
6743 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
6747 new_mode
= ARM_CPU_MODE_MON
;
6749 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
6753 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
6754 return; /* Never happens. Keep compiler happy. */
6757 if (new_mode
== ARM_CPU_MODE_MON
) {
6758 addr
+= env
->cp15
.mvbar
;
6759 } else if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
6760 /* High vectors. When enabled, base address cannot be remapped. */
6763 /* ARM v7 architectures provide a vector base address register to remap
6764 * the interrupt vector table.
6765 * This register is only followed in non-monitor mode, and is banked.
6766 * Note: only bits 31:5 are valid.
6768 addr
+= A32_BANKED_CURRENT_REG_GET(env
, vbar
);
6771 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
6772 env
->cp15
.scr_el3
&= ~SCR_NS
;
6775 switch_mode (env
, new_mode
);
6776 /* For exceptions taken to AArch32 we must clear the SS bit in both
6777 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
6779 env
->uncached_cpsr
&= ~PSTATE_SS
;
6780 env
->spsr
= cpsr_read(env
);
6781 /* Clear IT bits. */
6782 env
->condexec_bits
= 0;
6783 /* Switch to the new mode, and to the correct instruction set. */
6784 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
6785 /* Set new mode endianness */
6786 env
->uncached_cpsr
&= ~CPSR_E
;
6787 if (env
->cp15
.sctlr_el
[arm_current_el(env
)] & SCTLR_EE
) {
6788 env
->uncached_cpsr
|= CPSR_E
;
6791 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
6792 * and we should just guard the thumb mode on V4 */
6793 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
6794 env
->thumb
= (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_TE
) != 0;
6796 env
->regs
[14] = env
->regs
[15] + offset
;
6797 env
->regs
[15] = addr
;
6800 /* Handle exception entry to a target EL which is using AArch64 */
6801 static void arm_cpu_do_interrupt_aarch64(CPUState
*cs
)
6803 ARMCPU
*cpu
= ARM_CPU(cs
);
6804 CPUARMState
*env
= &cpu
->env
;
6805 unsigned int new_el
= env
->exception
.target_el
;
6806 target_ulong addr
= env
->cp15
.vbar_el
[new_el
];
6807 unsigned int new_mode
= aarch64_pstate_mode(new_el
, true);
6809 if (arm_current_el(env
) < new_el
) {
6810 /* Entry vector offset depends on whether the implemented EL
6811 * immediately lower than the target level is using AArch32 or AArch64
6817 is_aa64
= (env
->cp15
.scr_el3
& SCR_RW
) != 0;
6820 is_aa64
= (env
->cp15
.hcr_el2
& HCR_RW
) != 0;
6823 is_aa64
= is_a64(env
);
6826 g_assert_not_reached();
6834 } else if (pstate_read(env
) & PSTATE_SP
) {
6838 switch (cs
->exception_index
) {
6839 case EXCP_PREFETCH_ABORT
:
6840 case EXCP_DATA_ABORT
:
6841 env
->cp15
.far_el
[new_el
] = env
->exception
.vaddress
;
6842 qemu_log_mask(CPU_LOG_INT
, "...with FAR 0x%" PRIx64
"\n",
6843 env
->cp15
.far_el
[new_el
]);
6851 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
6862 qemu_log_mask(CPU_LOG_INT
,
6863 "...handling as semihosting call 0x%" PRIx64
"\n",
6865 env
->xregs
[0] = do_arm_semihosting(env
);
6868 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
6872 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = pstate_read(env
);
6873 aarch64_save_sp(env
, arm_current_el(env
));
6874 env
->elr_el
[new_el
] = env
->pc
;
6876 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = cpsr_read(env
);
6877 env
->elr_el
[new_el
] = env
->regs
[15];
6879 aarch64_sync_32_to_64(env
);
6881 env
->condexec_bits
= 0;
6883 qemu_log_mask(CPU_LOG_INT
, "...with ELR 0x%" PRIx64
"\n",
6884 env
->elr_el
[new_el
]);
6886 pstate_write(env
, PSTATE_DAIF
| new_mode
);
6888 aarch64_restore_sp(env
, new_el
);
6892 qemu_log_mask(CPU_LOG_INT
, "...to EL%d PC 0x%" PRIx64
" PSTATE 0x%x\n",
6893 new_el
, env
->pc
, pstate_read(env
));
6896 static inline bool check_for_semihosting(CPUState
*cs
)
6898 /* Check whether this exception is a semihosting call; if so
6899 * then handle it and return true; otherwise return false.
6901 ARMCPU
*cpu
= ARM_CPU(cs
);
6902 CPUARMState
*env
= &cpu
->env
;
6905 if (cs
->exception_index
== EXCP_SEMIHOST
) {
6906 /* This is always the 64-bit semihosting exception.
6907 * The "is this usermode" and "is semihosting enabled"
6908 * checks have been done at translate time.
6910 qemu_log_mask(CPU_LOG_INT
,
6911 "...handling as semihosting call 0x%" PRIx64
"\n",
6913 env
->xregs
[0] = do_arm_semihosting(env
);
6920 /* Only intercept calls from privileged modes, to provide some
6921 * semblance of security.
6923 if (cs
->exception_index
!= EXCP_SEMIHOST
&&
6924 (!semihosting_enabled() ||
6925 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
))) {
6929 switch (cs
->exception_index
) {
6931 /* This is always a semihosting call; the "is this usermode"
6932 * and "is semihosting enabled" checks have been done at
6937 /* Check for semihosting interrupt. */
6939 imm
= arm_lduw_code(env
, env
->regs
[15] - 2, arm_sctlr_b(env
))
6945 imm
= arm_ldl_code(env
, env
->regs
[15] - 4, arm_sctlr_b(env
))
6947 if (imm
== 0x123456) {
6953 /* See if this is a semihosting syscall. */
6955 imm
= arm_lduw_code(env
, env
->regs
[15], arm_sctlr_b(env
))
6967 qemu_log_mask(CPU_LOG_INT
,
6968 "...handling as semihosting call 0x%x\n",
6970 env
->regs
[0] = do_arm_semihosting(env
);
6975 /* Handle a CPU exception for A and R profile CPUs.
6976 * Do any appropriate logging, handle PSCI calls, and then hand off
6977 * to the AArch64-entry or AArch32-entry function depending on the
6978 * target exception level's register width.
6980 void arm_cpu_do_interrupt(CPUState
*cs
)
6982 ARMCPU
*cpu
= ARM_CPU(cs
);
6983 CPUARMState
*env
= &cpu
->env
;
6984 unsigned int new_el
= env
->exception
.target_el
;
6986 assert(!arm_feature(env
, ARM_FEATURE_M
));
6988 arm_log_exception(cs
->exception_index
);
6989 qemu_log_mask(CPU_LOG_INT
, "...from EL%d to EL%d\n", arm_current_el(env
),
6991 if (qemu_loglevel_mask(CPU_LOG_INT
)
6992 && !excp_is_internal(cs
->exception_index
)) {
6993 qemu_log_mask(CPU_LOG_INT
, "...with ESR 0x%x/0x%" PRIx32
"\n",
6994 env
->exception
.syndrome
>> ARM_EL_EC_SHIFT
,
6995 env
->exception
.syndrome
);
6998 if (arm_is_psci_call(cpu
, cs
->exception_index
)) {
6999 arm_handle_psci_call(cpu
);
7000 qemu_log_mask(CPU_LOG_INT
, "...handled as PSCI call\n");
7004 /* Semihosting semantics depend on the register width of the
7005 * code that caused the exception, not the target exception level,
7006 * so must be handled here.
7008 if (check_for_semihosting(cs
)) {
7012 assert(!excp_is_internal(cs
->exception_index
));
7013 if (arm_el_is_aa64(env
, new_el
)) {
7014 arm_cpu_do_interrupt_aarch64(cs
);
7016 arm_cpu_do_interrupt_aarch32(cs
);
7019 /* Hooks may change global state so BQL should be held, also the
7020 * BQL needs to be held for any modification of
7021 * cs->interrupt_request.
7023 g_assert(qemu_mutex_iothread_locked());
7025 arm_call_el_change_hook(cpu
);
7027 if (!kvm_enabled()) {
7028 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
7032 /* Return the exception level which controls this address translation regime */
7033 static inline uint32_t regime_el(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
7036 case ARMMMUIdx_S2NS
:
7037 case ARMMMUIdx_S1E2
:
7039 case ARMMMUIdx_S1E3
:
7041 case ARMMMUIdx_S1SE0
:
7042 return arm_el_is_aa64(env
, 3) ? 1 : 3;
7043 case ARMMMUIdx_S1SE1
:
7044 case ARMMMUIdx_S1NSE0
:
7045 case ARMMMUIdx_S1NSE1
:
7046 case ARMMMUIdx_MPriv
:
7047 case ARMMMUIdx_MNegPri
:
7048 case ARMMMUIdx_MUser
:
7049 case ARMMMUIdx_MSPriv
:
7050 case ARMMMUIdx_MSNegPri
:
7051 case ARMMMUIdx_MSUser
:
7054 g_assert_not_reached();
7058 /* Return true if this address translation regime is secure */
7059 static inline bool regime_is_secure(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
7062 case ARMMMUIdx_S12NSE0
:
7063 case ARMMMUIdx_S12NSE1
:
7064 case ARMMMUIdx_S1NSE0
:
7065 case ARMMMUIdx_S1NSE1
:
7066 case ARMMMUIdx_S1E2
:
7067 case ARMMMUIdx_S2NS
:
7068 case ARMMMUIdx_MPriv
:
7069 case ARMMMUIdx_MNegPri
:
7070 case ARMMMUIdx_MUser
:
7072 case ARMMMUIdx_S1E3
:
7073 case ARMMMUIdx_S1SE0
:
7074 case ARMMMUIdx_S1SE1
:
7075 case ARMMMUIdx_MSPriv
:
7076 case ARMMMUIdx_MSNegPri
:
7077 case ARMMMUIdx_MSUser
:
7080 g_assert_not_reached();
7084 /* Return the SCTLR value which controls this address translation regime */
7085 static inline uint32_t regime_sctlr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
7087 return env
->cp15
.sctlr_el
[regime_el(env
, mmu_idx
)];
7090 /* Return true if the specified stage of address translation is disabled */
7091 static inline bool regime_translation_disabled(CPUARMState
*env
,
7094 if (arm_feature(env
, ARM_FEATURE_M
)) {
7095 switch (env
->v7m
.mpu_ctrl
[regime_is_secure(env
, mmu_idx
)] &
7096 (R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
)) {
7097 case R_V7M_MPU_CTRL_ENABLE_MASK
:
7098 /* Enabled, but not for HardFault and NMI */
7099 return mmu_idx
== ARMMMUIdx_MNegPri
||
7100 mmu_idx
== ARMMMUIdx_MSNegPri
;
7101 case R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
:
7102 /* Enabled for all cases */
7106 /* HFNMIENA set and ENABLE clear is UNPREDICTABLE, but
7107 * we warned about that in armv7m_nvic.c when the guest set it.
7113 if (mmu_idx
== ARMMMUIdx_S2NS
) {
7114 return (env
->cp15
.hcr_el2
& HCR_VM
) == 0;
7116 return (regime_sctlr(env
, mmu_idx
) & SCTLR_M
) == 0;
7119 static inline bool regime_translation_big_endian(CPUARMState
*env
,
7122 return (regime_sctlr(env
, mmu_idx
) & SCTLR_EE
) != 0;
7125 /* Return the TCR controlling this translation regime */
7126 static inline TCR
*regime_tcr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
7128 if (mmu_idx
== ARMMMUIdx_S2NS
) {
7129 return &env
->cp15
.vtcr_el2
;
7131 return &env
->cp15
.tcr_el
[regime_el(env
, mmu_idx
)];
7134 /* Convert a possible stage1+2 MMU index into the appropriate
7137 static inline ARMMMUIdx
stage_1_mmu_idx(ARMMMUIdx mmu_idx
)
7139 if (mmu_idx
== ARMMMUIdx_S12NSE0
|| mmu_idx
== ARMMMUIdx_S12NSE1
) {
7140 mmu_idx
+= (ARMMMUIdx_S1NSE0
- ARMMMUIdx_S12NSE0
);
7145 /* Returns TBI0 value for current regime el */
7146 uint32_t arm_regime_tbi0(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
7151 /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert
7152 * a stage 1+2 mmu index into the appropriate stage 1 mmu index.
7154 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
7156 tcr
= regime_tcr(env
, mmu_idx
);
7157 el
= regime_el(env
, mmu_idx
);
7160 return extract64(tcr
->raw_tcr
, 20, 1);
7162 return extract64(tcr
->raw_tcr
, 37, 1);
7166 /* Returns TBI1 value for current regime el */
7167 uint32_t arm_regime_tbi1(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
7172 /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert
7173 * a stage 1+2 mmu index into the appropriate stage 1 mmu index.
7175 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
7177 tcr
= regime_tcr(env
, mmu_idx
);
7178 el
= regime_el(env
, mmu_idx
);
7183 return extract64(tcr
->raw_tcr
, 38, 1);
7187 /* Return the TTBR associated with this translation regime */
7188 static inline uint64_t regime_ttbr(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
7191 if (mmu_idx
== ARMMMUIdx_S2NS
) {
7192 return env
->cp15
.vttbr_el2
;
7195 return env
->cp15
.ttbr0_el
[regime_el(env
, mmu_idx
)];
7197 return env
->cp15
.ttbr1_el
[regime_el(env
, mmu_idx
)];
7201 /* Return true if the translation regime is using LPAE format page tables */
7202 static inline bool regime_using_lpae_format(CPUARMState
*env
,
7205 int el
= regime_el(env
, mmu_idx
);
7206 if (el
== 2 || arm_el_is_aa64(env
, el
)) {
7209 if (arm_feature(env
, ARM_FEATURE_LPAE
)
7210 && (regime_tcr(env
, mmu_idx
)->raw_tcr
& TTBCR_EAE
)) {
7216 /* Returns true if the stage 1 translation regime is using LPAE format page
7217 * tables. Used when raising alignment exceptions, whose FSR changes depending
7218 * on whether the long or short descriptor format is in use. */
7219 bool arm_s1_regime_using_lpae_format(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
7221 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
7223 return regime_using_lpae_format(env
, mmu_idx
);
7226 static inline bool regime_is_user(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
7229 case ARMMMUIdx_S1SE0
:
7230 case ARMMMUIdx_S1NSE0
:
7231 case ARMMMUIdx_MUser
:
7235 case ARMMMUIdx_S12NSE0
:
7236 case ARMMMUIdx_S12NSE1
:
7237 g_assert_not_reached();
7241 /* Translate section/page access permissions to page
7242 * R/W protection flags
7245 * @mmu_idx: MMU index indicating required translation regime
7246 * @ap: The 3-bit access permissions (AP[2:0])
7247 * @domain_prot: The 2-bit domain access permissions
7249 static inline int ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
7250 int ap
, int domain_prot
)
7252 bool is_user
= regime_is_user(env
, mmu_idx
);
7254 if (domain_prot
== 3) {
7255 return PAGE_READ
| PAGE_WRITE
;
7260 if (arm_feature(env
, ARM_FEATURE_V7
)) {
7263 switch (regime_sctlr(env
, mmu_idx
) & (SCTLR_S
| SCTLR_R
)) {
7265 return is_user
? 0 : PAGE_READ
;
7272 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
7277 return PAGE_READ
| PAGE_WRITE
;
7280 return PAGE_READ
| PAGE_WRITE
;
7281 case 4: /* Reserved. */
7284 return is_user
? 0 : PAGE_READ
;
7288 if (!arm_feature(env
, ARM_FEATURE_V6K
)) {
7293 g_assert_not_reached();
7297 /* Translate section/page access permissions to page
7298 * R/W protection flags.
7300 * @ap: The 2-bit simple AP (AP[2:1])
7301 * @is_user: TRUE if accessing from PL0
7303 static inline int simple_ap_to_rw_prot_is_user(int ap
, bool is_user
)
7307 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
7309 return PAGE_READ
| PAGE_WRITE
;
7311 return is_user
? 0 : PAGE_READ
;
7315 g_assert_not_reached();
7320 simple_ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, int ap
)
7322 return simple_ap_to_rw_prot_is_user(ap
, regime_is_user(env
, mmu_idx
));
7325 /* Translate S2 section/page access permissions to protection flags
7328 * @s2ap: The 2-bit stage2 access permissions (S2AP)
7329 * @xn: XN (execute-never) bit
7331 static int get_S2prot(CPUARMState
*env
, int s2ap
, int xn
)
7342 if (arm_el_is_aa64(env
, 2) || prot
& PAGE_READ
) {
7349 /* Translate section/page access permissions to protection flags
7352 * @mmu_idx: MMU index indicating required translation regime
7353 * @is_aa64: TRUE if AArch64
7354 * @ap: The 2-bit simple AP (AP[2:1])
7355 * @ns: NS (non-secure) bit
7356 * @xn: XN (execute-never) bit
7357 * @pxn: PXN (privileged execute-never) bit
7359 static int get_S1prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, bool is_aa64
,
7360 int ap
, int ns
, int xn
, int pxn
)
7362 bool is_user
= regime_is_user(env
, mmu_idx
);
7363 int prot_rw
, user_rw
;
7367 assert(mmu_idx
!= ARMMMUIdx_S2NS
);
7369 user_rw
= simple_ap_to_rw_prot_is_user(ap
, true);
7373 prot_rw
= simple_ap_to_rw_prot_is_user(ap
, false);
7376 if (ns
&& arm_is_secure(env
) && (env
->cp15
.scr_el3
& SCR_SIF
)) {
7380 /* TODO have_wxn should be replaced with
7381 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
7382 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
7383 * compatible processors have EL2, which is required for [U]WXN.
7385 have_wxn
= arm_feature(env
, ARM_FEATURE_LPAE
);
7388 wxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_WXN
;
7392 switch (regime_el(env
, mmu_idx
)) {
7395 xn
= pxn
|| (user_rw
& PAGE_WRITE
);
7402 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
7403 switch (regime_el(env
, mmu_idx
)) {
7407 xn
= xn
|| !(user_rw
& PAGE_READ
);
7411 uwxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_UWXN
;
7413 xn
= xn
|| !(prot_rw
& PAGE_READ
) || pxn
||
7414 (uwxn
&& (user_rw
& PAGE_WRITE
));
7424 if (xn
|| (wxn
&& (prot_rw
& PAGE_WRITE
))) {
7427 return prot_rw
| PAGE_EXEC
;
7430 static bool get_level1_table_address(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
7431 uint32_t *table
, uint32_t address
)
7433 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
7434 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
7436 if (address
& tcr
->mask
) {
7437 if (tcr
->raw_tcr
& TTBCR_PD1
) {
7438 /* Translation table walk disabled for TTBR1 */
7441 *table
= regime_ttbr(env
, mmu_idx
, 1) & 0xffffc000;
7443 if (tcr
->raw_tcr
& TTBCR_PD0
) {
7444 /* Translation table walk disabled for TTBR0 */
7447 *table
= regime_ttbr(env
, mmu_idx
, 0) & tcr
->base_mask
;
7449 *table
|= (address
>> 18) & 0x3ffc;
7453 /* Translate a S1 pagetable walk through S2 if needed. */
7454 static hwaddr
S1_ptw_translate(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
7455 hwaddr addr
, MemTxAttrs txattrs
,
7457 ARMMMUFaultInfo
*fi
)
7459 if ((mmu_idx
== ARMMMUIdx_S1NSE0
|| mmu_idx
== ARMMMUIdx_S1NSE1
) &&
7460 !regime_translation_disabled(env
, ARMMMUIdx_S2NS
)) {
7461 target_ulong s2size
;
7466 ret
= get_phys_addr_lpae(env
, addr
, 0, ARMMMUIdx_S2NS
, &s2pa
,
7467 &txattrs
, &s2prot
, &s2size
, fsr
, fi
);
7479 /* All loads done in the course of a page table walk go through here.
7480 * TODO: rather than ignoring errors from physical memory reads (which
7481 * are external aborts in ARM terminology) we should propagate this
7482 * error out so that we can turn it into a Data Abort if this walk
7483 * was being done for a CPU load/store or an address translation instruction
7484 * (but not if it was for a debug access).
7486 static uint32_t arm_ldl_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
,
7487 ARMMMUIdx mmu_idx
, uint32_t *fsr
,
7488 ARMMMUFaultInfo
*fi
)
7490 ARMCPU
*cpu
= ARM_CPU(cs
);
7491 CPUARMState
*env
= &cpu
->env
;
7492 MemTxAttrs attrs
= {};
7495 attrs
.secure
= is_secure
;
7496 as
= arm_addressspace(cs
, attrs
);
7497 addr
= S1_ptw_translate(env
, mmu_idx
, addr
, attrs
, fsr
, fi
);
7501 if (regime_translation_big_endian(env
, mmu_idx
)) {
7502 return address_space_ldl_be(as
, addr
, attrs
, NULL
);
7504 return address_space_ldl_le(as
, addr
, attrs
, NULL
);
7508 static uint64_t arm_ldq_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
,
7509 ARMMMUIdx mmu_idx
, uint32_t *fsr
,
7510 ARMMMUFaultInfo
*fi
)
7512 ARMCPU
*cpu
= ARM_CPU(cs
);
7513 CPUARMState
*env
= &cpu
->env
;
7514 MemTxAttrs attrs
= {};
7517 attrs
.secure
= is_secure
;
7518 as
= arm_addressspace(cs
, attrs
);
7519 addr
= S1_ptw_translate(env
, mmu_idx
, addr
, attrs
, fsr
, fi
);
7523 if (regime_translation_big_endian(env
, mmu_idx
)) {
7524 return address_space_ldq_be(as
, addr
, attrs
, NULL
);
7526 return address_space_ldq_le(as
, addr
, attrs
, NULL
);
7530 static bool get_phys_addr_v5(CPUARMState
*env
, uint32_t address
,
7531 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
7532 hwaddr
*phys_ptr
, int *prot
,
7533 target_ulong
*page_size
, uint32_t *fsr
,
7534 ARMMMUFaultInfo
*fi
)
7536 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
7547 /* Pagetable walk. */
7548 /* Lookup l1 descriptor. */
7549 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
7550 /* Section translation fault if page walk is disabled by PD0 or PD1 */
7554 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
7557 domain
= (desc
>> 5) & 0x0f;
7558 if (regime_el(env
, mmu_idx
) == 1) {
7559 dacr
= env
->cp15
.dacr_ns
;
7561 dacr
= env
->cp15
.dacr_s
;
7563 domain_prot
= (dacr
>> (domain
* 2)) & 3;
7565 /* Section translation fault. */
7569 if (domain_prot
== 0 || domain_prot
== 2) {
7571 code
= 9; /* Section domain fault. */
7573 code
= 11; /* Page domain fault. */
7578 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
7579 ap
= (desc
>> 10) & 3;
7581 *page_size
= 1024 * 1024;
7583 /* Lookup l2 entry. */
7585 /* Coarse pagetable. */
7586 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
7588 /* Fine pagetable. */
7589 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
7591 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
7594 case 0: /* Page translation fault. */
7597 case 1: /* 64k page. */
7598 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
7599 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
7600 *page_size
= 0x10000;
7602 case 2: /* 4k page. */
7603 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
7604 ap
= (desc
>> (4 + ((address
>> 9) & 6))) & 3;
7605 *page_size
= 0x1000;
7607 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
7609 /* ARMv6/XScale extended small page format */
7610 if (arm_feature(env
, ARM_FEATURE_XSCALE
)
7611 || arm_feature(env
, ARM_FEATURE_V6
)) {
7612 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
7613 *page_size
= 0x1000;
7615 /* UNPREDICTABLE in ARMv5; we choose to take a
7616 * page translation fault.
7622 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
7625 ap
= (desc
>> 4) & 3;
7628 /* Never happens, but compiler isn't smart enough to tell. */
7633 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
7634 *prot
|= *prot
? PAGE_EXEC
: 0;
7635 if (!(*prot
& (1 << access_type
))) {
7636 /* Access permission fault. */
7639 *phys_ptr
= phys_addr
;
7642 *fsr
= code
| (domain
<< 4);
7646 static bool get_phys_addr_v6(CPUARMState
*env
, uint32_t address
,
7647 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
7648 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
7649 target_ulong
*page_size
, uint32_t *fsr
,
7650 ARMMMUFaultInfo
*fi
)
7652 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
7666 /* Pagetable walk. */
7667 /* Lookup l1 descriptor. */
7668 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
7669 /* Section translation fault if page walk is disabled by PD0 or PD1 */
7673 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
7676 if (type
== 0 || (type
== 3 && !arm_feature(env
, ARM_FEATURE_PXN
))) {
7677 /* Section translation fault, or attempt to use the encoding
7678 * which is Reserved on implementations without PXN.
7683 if ((type
== 1) || !(desc
& (1 << 18))) {
7684 /* Page or Section. */
7685 domain
= (desc
>> 5) & 0x0f;
7687 if (regime_el(env
, mmu_idx
) == 1) {
7688 dacr
= env
->cp15
.dacr_ns
;
7690 dacr
= env
->cp15
.dacr_s
;
7692 domain_prot
= (dacr
>> (domain
* 2)) & 3;
7693 if (domain_prot
== 0 || domain_prot
== 2) {
7695 code
= 9; /* Section domain fault. */
7697 code
= 11; /* Page domain fault. */
7702 if (desc
& (1 << 18)) {
7704 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
7705 phys_addr
|= (uint64_t)extract32(desc
, 20, 4) << 32;
7706 phys_addr
|= (uint64_t)extract32(desc
, 5, 4) << 36;
7707 *page_size
= 0x1000000;
7710 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
7711 *page_size
= 0x100000;
7713 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
7714 xn
= desc
& (1 << 4);
7717 ns
= extract32(desc
, 19, 1);
7719 if (arm_feature(env
, ARM_FEATURE_PXN
)) {
7720 pxn
= (desc
>> 2) & 1;
7722 ns
= extract32(desc
, 3, 1);
7723 /* Lookup l2 entry. */
7724 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
7725 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
7727 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
7729 case 0: /* Page translation fault. */
7732 case 1: /* 64k page. */
7733 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
7734 xn
= desc
& (1 << 15);
7735 *page_size
= 0x10000;
7737 case 2: case 3: /* 4k page. */
7738 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
7740 *page_size
= 0x1000;
7743 /* Never happens, but compiler isn't smart enough to tell. */
7748 if (domain_prot
== 3) {
7749 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
7751 if (pxn
&& !regime_is_user(env
, mmu_idx
)) {
7754 if (xn
&& access_type
== MMU_INST_FETCH
)
7757 if (arm_feature(env
, ARM_FEATURE_V6K
) &&
7758 (regime_sctlr(env
, mmu_idx
) & SCTLR_AFE
)) {
7759 /* The simplified model uses AP[0] as an access control bit. */
7760 if ((ap
& 1) == 0) {
7761 /* Access flag fault. */
7762 code
= (code
== 15) ? 6 : 3;
7765 *prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
>> 1);
7767 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
7772 if (!(*prot
& (1 << access_type
))) {
7773 /* Access permission fault. */
7778 /* The NS bit will (as required by the architecture) have no effect if
7779 * the CPU doesn't support TZ or this is a non-secure translation
7780 * regime, because the attribute will already be non-secure.
7782 attrs
->secure
= false;
7784 *phys_ptr
= phys_addr
;
7787 *fsr
= code
| (domain
<< 4);
7791 /* Fault type for long-descriptor MMU fault reporting; this corresponds
7792 * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
7795 translation_fault
= 1,
7797 permission_fault
= 3,
7801 * check_s2_mmu_setup
7803 * @is_aa64: True if the translation regime is in AArch64 state
7804 * @startlevel: Suggested starting level
7805 * @inputsize: Bitsize of IPAs
7806 * @stride: Page-table stride (See the ARM ARM)
7808 * Returns true if the suggested S2 translation parameters are OK and
7811 static bool check_s2_mmu_setup(ARMCPU
*cpu
, bool is_aa64
, int level
,
7812 int inputsize
, int stride
)
7814 const int grainsize
= stride
+ 3;
7817 /* Negative levels are never allowed. */
7822 startsizecheck
= inputsize
- ((3 - level
) * stride
+ grainsize
);
7823 if (startsizecheck
< 1 || startsizecheck
> stride
+ 4) {
7828 CPUARMState
*env
= &cpu
->env
;
7829 unsigned int pamax
= arm_pamax(cpu
);
7832 case 13: /* 64KB Pages. */
7833 if (level
== 0 || (level
== 1 && pamax
<= 42)) {
7837 case 11: /* 16KB Pages. */
7838 if (level
== 0 || (level
== 1 && pamax
<= 40)) {
7842 case 9: /* 4KB Pages. */
7843 if (level
== 0 && pamax
<= 42) {
7848 g_assert_not_reached();
7851 /* Inputsize checks. */
7852 if (inputsize
> pamax
&&
7853 (arm_el_is_aa64(env
, 1) || inputsize
> 40)) {
7854 /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */
7858 /* AArch32 only supports 4KB pages. Assert on that. */
7859 assert(stride
== 9);
7868 static bool get_phys_addr_lpae(CPUARMState
*env
, target_ulong address
,
7869 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
7870 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
, int *prot
,
7871 target_ulong
*page_size_ptr
, uint32_t *fsr
,
7872 ARMMMUFaultInfo
*fi
)
7874 ARMCPU
*cpu
= arm_env_get_cpu(env
);
7875 CPUState
*cs
= CPU(cpu
);
7876 /* Read an LPAE long-descriptor translation table. */
7877 MMUFaultType fault_type
= translation_fault
;
7884 hwaddr descaddr
, indexmask
, indexmask_grainsize
;
7885 uint32_t tableattrs
;
7886 target_ulong page_size
;
7892 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
7893 int ap
, ns
, xn
, pxn
;
7894 uint32_t el
= regime_el(env
, mmu_idx
);
7895 bool ttbr1_valid
= true;
7896 uint64_t descaddrmask
;
7897 bool aarch64
= arm_el_is_aa64(env
, el
);
7900 * This code does not handle the different format TCR for VTCR_EL2.
7901 * This code also does not support shareability levels.
7902 * Attribute and permission bit handling should also be checked when adding
7903 * support for those page table walks.
7909 if (mmu_idx
!= ARMMMUIdx_S2NS
) {
7910 tbi
= extract64(tcr
->raw_tcr
, 20, 1);
7913 if (extract64(address
, 55, 1)) {
7914 tbi
= extract64(tcr
->raw_tcr
, 38, 1);
7916 tbi
= extract64(tcr
->raw_tcr
, 37, 1);
7921 /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it
7925 ttbr1_valid
= false;
7930 /* There is no TTBR1 for EL2 */
7932 ttbr1_valid
= false;
7936 /* Determine whether this address is in the region controlled by
7937 * TTBR0 or TTBR1 (or if it is in neither region and should fault).
7938 * This is a Non-secure PL0/1 stage 1 translation, so controlled by
7939 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
7942 /* AArch64 translation. */
7943 t0sz
= extract32(tcr
->raw_tcr
, 0, 6);
7944 t0sz
= MIN(t0sz
, 39);
7945 t0sz
= MAX(t0sz
, 16);
7946 } else if (mmu_idx
!= ARMMMUIdx_S2NS
) {
7947 /* AArch32 stage 1 translation. */
7948 t0sz
= extract32(tcr
->raw_tcr
, 0, 3);
7950 /* AArch32 stage 2 translation. */
7951 bool sext
= extract32(tcr
->raw_tcr
, 4, 1);
7952 bool sign
= extract32(tcr
->raw_tcr
, 3, 1);
7953 /* Address size is 40-bit for a stage 2 translation,
7954 * and t0sz can be negative (from -8 to 7),
7955 * so we need to adjust it to use the TTBR selecting logic below.
7958 t0sz
= sextract32(tcr
->raw_tcr
, 0, 4) + 8;
7960 /* If the sign-extend bit is not the same as t0sz[3], the result
7961 * is unpredictable. Flag this as a guest error. */
7963 qemu_log_mask(LOG_GUEST_ERROR
,
7964 "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n");
7967 t1sz
= extract32(tcr
->raw_tcr
, 16, 6);
7969 t1sz
= MIN(t1sz
, 39);
7970 t1sz
= MAX(t1sz
, 16);
7972 if (t0sz
&& !extract64(address
, addrsize
- t0sz
, t0sz
- tbi
)) {
7973 /* there is a ttbr0 region and we are in it (high bits all zero) */
7975 } else if (ttbr1_valid
&& t1sz
&&
7976 !extract64(~address
, addrsize
- t1sz
, t1sz
- tbi
)) {
7977 /* there is a ttbr1 region and we are in it (high bits all one) */
7980 /* ttbr0 region is "everything not in the ttbr1 region" */
7982 } else if (!t1sz
&& ttbr1_valid
) {
7983 /* ttbr1 region is "everything not in the ttbr0 region" */
7986 /* in the gap between the two regions, this is a Translation fault */
7987 fault_type
= translation_fault
;
7991 /* Note that QEMU ignores shareability and cacheability attributes,
7992 * so we don't need to do anything with the SH, ORGN, IRGN fields
7993 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
7994 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
7995 * implement any ASID-like capability so we can ignore it (instead
7996 * we will always flush the TLB any time the ASID is changed).
7998 if (ttbr_select
== 0) {
7999 ttbr
= regime_ttbr(env
, mmu_idx
, 0);
8001 epd
= extract32(tcr
->raw_tcr
, 7, 1);
8003 inputsize
= addrsize
- t0sz
;
8005 tg
= extract32(tcr
->raw_tcr
, 14, 2);
8006 if (tg
== 1) { /* 64KB pages */
8009 if (tg
== 2) { /* 16KB pages */
8013 /* We should only be here if TTBR1 is valid */
8014 assert(ttbr1_valid
);
8016 ttbr
= regime_ttbr(env
, mmu_idx
, 1);
8017 epd
= extract32(tcr
->raw_tcr
, 23, 1);
8018 inputsize
= addrsize
- t1sz
;
8020 tg
= extract32(tcr
->raw_tcr
, 30, 2);
8021 if (tg
== 3) { /* 64KB pages */
8024 if (tg
== 1) { /* 16KB pages */
8029 /* Here we should have set up all the parameters for the translation:
8030 * inputsize, ttbr, epd, stride, tbi
8034 /* Translation table walk disabled => Translation fault on TLB miss
8035 * Note: This is always 0 on 64-bit EL2 and EL3.
8040 if (mmu_idx
!= ARMMMUIdx_S2NS
) {
8041 /* The starting level depends on the virtual address size (which can
8042 * be up to 48 bits) and the translation granule size. It indicates
8043 * the number of strides (stride bits at a time) needed to
8044 * consume the bits of the input address. In the pseudocode this is:
8045 * level = 4 - RoundUp((inputsize - grainsize) / stride)
8046 * where their 'inputsize' is our 'inputsize', 'grainsize' is
8047 * our 'stride + 3' and 'stride' is our 'stride'.
8048 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
8049 * = 4 - (inputsize - stride - 3 + stride - 1) / stride
8050 * = 4 - (inputsize - 4) / stride;
8052 level
= 4 - (inputsize
- 4) / stride
;
8054 /* For stage 2 translations the starting level is specified by the
8055 * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
8057 uint32_t sl0
= extract32(tcr
->raw_tcr
, 6, 2);
8058 uint32_t startlevel
;
8061 if (!aarch64
|| stride
== 9) {
8062 /* AArch32 or 4KB pages */
8063 startlevel
= 2 - sl0
;
8065 /* 16KB or 64KB pages */
8066 startlevel
= 3 - sl0
;
8069 /* Check that the starting level is valid. */
8070 ok
= check_s2_mmu_setup(cpu
, aarch64
, startlevel
,
8073 fault_type
= translation_fault
;
8079 indexmask_grainsize
= (1ULL << (stride
+ 3)) - 1;
8080 indexmask
= (1ULL << (inputsize
- (stride
* (4 - level
)))) - 1;
8082 /* Now we can extract the actual base address from the TTBR */
8083 descaddr
= extract64(ttbr
, 0, 48);
8084 descaddr
&= ~indexmask
;
8086 /* The address field in the descriptor goes up to bit 39 for ARMv7
8087 * but up to bit 47 for ARMv8, but we use the descaddrmask
8088 * up to bit 39 for AArch32, because we don't need other bits in that case
8089 * to construct next descriptor address (anyway they should be all zeroes).
8091 descaddrmask
= ((1ull << (aarch64
? 48 : 40)) - 1) &
8092 ~indexmask_grainsize
;
8094 /* Secure accesses start with the page table in secure memory and
8095 * can be downgraded to non-secure at any step. Non-secure accesses
8096 * remain non-secure. We implement this by just ORing in the NSTable/NS
8097 * bits at each step.
8099 tableattrs
= regime_is_secure(env
, mmu_idx
) ? 0 : (1 << 4);
8101 uint64_t descriptor
;
8104 descaddr
|= (address
>> (stride
* (4 - level
))) & indexmask
;
8106 nstable
= extract32(tableattrs
, 4, 1);
8107 descriptor
= arm_ldq_ptw(cs
, descaddr
, !nstable
, mmu_idx
, fsr
, fi
);
8112 if (!(descriptor
& 1) ||
8113 (!(descriptor
& 2) && (level
== 3))) {
8114 /* Invalid, or the Reserved level 3 encoding */
8117 descaddr
= descriptor
& descaddrmask
;
8119 if ((descriptor
& 2) && (level
< 3)) {
8120 /* Table entry. The top five bits are attributes which may
8121 * propagate down through lower levels of the table (and
8122 * which are all arranged so that 0 means "no effect", so
8123 * we can gather them up by ORing in the bits at each level).
8125 tableattrs
|= extract64(descriptor
, 59, 5);
8127 indexmask
= indexmask_grainsize
;
8130 /* Block entry at level 1 or 2, or page entry at level 3.
8131 * These are basically the same thing, although the number
8132 * of bits we pull in from the vaddr varies.
8134 page_size
= (1ULL << ((stride
* (4 - level
)) + 3));
8135 descaddr
|= (address
& (page_size
- 1));
8136 /* Extract attributes from the descriptor */
8137 attrs
= extract64(descriptor
, 2, 10)
8138 | (extract64(descriptor
, 52, 12) << 10);
8140 if (mmu_idx
== ARMMMUIdx_S2NS
) {
8141 /* Stage 2 table descriptors do not include any attribute fields */
8144 /* Merge in attributes from table descriptors */
8145 attrs
|= extract32(tableattrs
, 0, 2) << 11; /* XN, PXN */
8146 attrs
|= extract32(tableattrs
, 3, 1) << 5; /* APTable[1] => AP[2] */
8147 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
8148 * means "force PL1 access only", which means forcing AP[1] to 0.
8150 if (extract32(tableattrs
, 2, 1)) {
8153 attrs
|= nstable
<< 3; /* NS */
8156 /* Here descaddr is the final physical address, and attributes
8159 fault_type
= access_fault
;
8160 if ((attrs
& (1 << 8)) == 0) {
8165 ap
= extract32(attrs
, 4, 2);
8166 xn
= extract32(attrs
, 12, 1);
8168 if (mmu_idx
== ARMMMUIdx_S2NS
) {
8170 *prot
= get_S2prot(env
, ap
, xn
);
8172 ns
= extract32(attrs
, 3, 1);
8173 pxn
= extract32(attrs
, 11, 1);
8174 *prot
= get_S1prot(env
, mmu_idx
, aarch64
, ap
, ns
, xn
, pxn
);
8177 fault_type
= permission_fault
;
8178 if (!(*prot
& (1 << access_type
))) {
8183 /* The NS bit will (as required by the architecture) have no effect if
8184 * the CPU doesn't support TZ or this is a non-secure translation
8185 * regime, because the attribute will already be non-secure.
8187 txattrs
->secure
= false;
8189 *phys_ptr
= descaddr
;
8190 *page_size_ptr
= page_size
;
8194 /* Long-descriptor format IFSR/DFSR value */
8195 *fsr
= (1 << 9) | (fault_type
<< 2) | level
;
8196 /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */
8197 fi
->stage2
= fi
->s1ptw
|| (mmu_idx
== ARMMMUIdx_S2NS
);
8201 static inline void get_phys_addr_pmsav7_default(CPUARMState
*env
,
8203 int32_t address
, int *prot
)
8205 if (!arm_feature(env
, ARM_FEATURE_M
)) {
8206 *prot
= PAGE_READ
| PAGE_WRITE
;
8208 case 0xF0000000 ... 0xFFFFFFFF:
8209 if (regime_sctlr(env
, mmu_idx
) & SCTLR_V
) {
8210 /* hivecs execing is ok */
8214 case 0x00000000 ... 0x7FFFFFFF:
8219 /* Default system address map for M profile cores.
8220 * The architecture specifies which regions are execute-never;
8221 * at the MPU level no other checks are defined.
8224 case 0x00000000 ... 0x1fffffff: /* ROM */
8225 case 0x20000000 ... 0x3fffffff: /* SRAM */
8226 case 0x60000000 ... 0x7fffffff: /* RAM */
8227 case 0x80000000 ... 0x9fffffff: /* RAM */
8228 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
8230 case 0x40000000 ... 0x5fffffff: /* Peripheral */
8231 case 0xa0000000 ... 0xbfffffff: /* Device */
8232 case 0xc0000000 ... 0xdfffffff: /* Device */
8233 case 0xe0000000 ... 0xffffffff: /* System */
8234 *prot
= PAGE_READ
| PAGE_WRITE
;
8237 g_assert_not_reached();
8242 static bool pmsav7_use_background_region(ARMCPU
*cpu
,
8243 ARMMMUIdx mmu_idx
, bool is_user
)
8245 /* Return true if we should use the default memory map as a
8246 * "background" region if there are no hits against any MPU regions.
8248 CPUARMState
*env
= &cpu
->env
;
8254 if (arm_feature(env
, ARM_FEATURE_M
)) {
8255 return env
->v7m
.mpu_ctrl
[regime_is_secure(env
, mmu_idx
)]
8256 & R_V7M_MPU_CTRL_PRIVDEFENA_MASK
;
8258 return regime_sctlr(env
, mmu_idx
) & SCTLR_BR
;
8262 static inline bool m_is_ppb_region(CPUARMState
*env
, uint32_t address
)
8264 /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */
8265 return arm_feature(env
, ARM_FEATURE_M
) &&
8266 extract32(address
, 20, 12) == 0xe00;
8269 static inline bool m_is_system_region(CPUARMState
*env
, uint32_t address
)
8271 /* True if address is in the M profile system region
8272 * 0xe0000000 - 0xffffffff
8274 return arm_feature(env
, ARM_FEATURE_M
) && extract32(address
, 29, 3) == 0x7;
8277 static bool get_phys_addr_pmsav7(CPUARMState
*env
, uint32_t address
,
8278 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
8279 hwaddr
*phys_ptr
, int *prot
, uint32_t *fsr
)
8281 ARMCPU
*cpu
= arm_env_get_cpu(env
);
8283 bool is_user
= regime_is_user(env
, mmu_idx
);
8285 *phys_ptr
= address
;
8288 if (regime_translation_disabled(env
, mmu_idx
) ||
8289 m_is_ppb_region(env
, address
)) {
8290 /* MPU disabled or M profile PPB access: use default memory map.
8291 * The other case which uses the default memory map in the
8292 * v7M ARM ARM pseudocode is exception vector reads from the vector
8293 * table. In QEMU those accesses are done in arm_v7m_load_vector(),
8294 * which always does a direct read using address_space_ldl(), rather
8295 * than going via this function, so we don't need to check that here.
8297 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
8298 } else { /* MPU enabled */
8299 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
8301 uint32_t base
= env
->pmsav7
.drbar
[n
];
8302 uint32_t rsize
= extract32(env
->pmsav7
.drsr
[n
], 1, 5);
8306 if (!(env
->pmsav7
.drsr
[n
] & 0x1)) {
8311 qemu_log_mask(LOG_GUEST_ERROR
,
8312 "DRSR[%d]: Rsize field cannot be 0\n", n
);
8316 rmask
= (1ull << rsize
) - 1;
8319 qemu_log_mask(LOG_GUEST_ERROR
,
8320 "DRBAR[%d]: 0x%" PRIx32
" misaligned "
8321 "to DRSR region size, mask = 0x%" PRIx32
"\n",
8326 if (address
< base
|| address
> base
+ rmask
) {
8330 /* Region matched */
8332 if (rsize
>= 8) { /* no subregions for regions < 256 bytes */
8334 uint32_t srdis_mask
;
8336 rsize
-= 3; /* sub region size (power of 2) */
8337 snd
= ((address
- base
) >> rsize
) & 0x7;
8338 srdis
= extract32(env
->pmsav7
.drsr
[n
], snd
+ 8, 1);
8340 srdis_mask
= srdis
? 0x3 : 0x0;
8341 for (i
= 2; i
<= 8 && rsize
< TARGET_PAGE_BITS
; i
*= 2) {
8342 /* This will check in groups of 2, 4 and then 8, whether
8343 * the subregion bits are consistent. rsize is incremented
8344 * back up to give the region size, considering consistent
8345 * adjacent subregions as one region. Stop testing if rsize
8346 * is already big enough for an entire QEMU page.
8348 int snd_rounded
= snd
& ~(i
- 1);
8349 uint32_t srdis_multi
= extract32(env
->pmsav7
.drsr
[n
],
8350 snd_rounded
+ 8, i
);
8351 if (srdis_mask
^ srdis_multi
) {
8354 srdis_mask
= (srdis_mask
<< i
) | srdis_mask
;
8358 if (rsize
< TARGET_PAGE_BITS
) {
8359 qemu_log_mask(LOG_UNIMP
,
8360 "DRSR[%d]: No support for MPU (sub)region "
8361 "alignment of %" PRIu32
" bits. Minimum is %d\n",
8362 n
, rsize
, TARGET_PAGE_BITS
);
8371 if (n
== -1) { /* no hits */
8372 if (!pmsav7_use_background_region(cpu
, mmu_idx
, is_user
)) {
8373 /* background fault */
8377 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
8378 } else { /* a MPU hit! */
8379 uint32_t ap
= extract32(env
->pmsav7
.dracr
[n
], 8, 3);
8380 uint32_t xn
= extract32(env
->pmsav7
.dracr
[n
], 12, 1);
8382 if (m_is_system_region(env
, address
)) {
8383 /* System space is always execute never */
8387 if (is_user
) { /* User mode AP bit decoding */
8392 break; /* no access */
8394 *prot
|= PAGE_WRITE
;
8398 *prot
|= PAGE_READ
| PAGE_EXEC
;
8401 qemu_log_mask(LOG_GUEST_ERROR
,
8402 "DRACR[%d]: Bad value for AP bits: 0x%"
8403 PRIx32
"\n", n
, ap
);
8405 } else { /* Priv. mode AP bits decoding */
8408 break; /* no access */
8412 *prot
|= PAGE_WRITE
;
8416 *prot
|= PAGE_READ
| PAGE_EXEC
;
8419 qemu_log_mask(LOG_GUEST_ERROR
,
8420 "DRACR[%d]: Bad value for AP bits: 0x%"
8421 PRIx32
"\n", n
, ap
);
8427 *prot
&= ~PAGE_EXEC
;
8432 *fsr
= 0x00d; /* Permission fault */
8433 return !(*prot
& (1 << access_type
));
8436 static bool get_phys_addr_pmsav8(CPUARMState
*env
, uint32_t address
,
8437 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
8438 hwaddr
*phys_ptr
, int *prot
, uint32_t *fsr
)
8440 ARMCPU
*cpu
= arm_env_get_cpu(env
);
8441 bool is_user
= regime_is_user(env
, mmu_idx
);
8442 uint32_t secure
= regime_is_secure(env
, mmu_idx
);
8444 int matchregion
= -1;
8447 *phys_ptr
= address
;
8450 /* Unlike the ARM ARM pseudocode, we don't need to check whether this
8451 * was an exception vector read from the vector table (which is always
8452 * done using the default system address map), because those accesses
8453 * are done in arm_v7m_load_vector(), which always does a direct
8454 * read using address_space_ldl(), rather than going via this function.
8456 if (regime_translation_disabled(env
, mmu_idx
)) { /* MPU disabled */
8458 } else if (m_is_ppb_region(env
, address
)) {
8460 } else if (pmsav7_use_background_region(cpu
, mmu_idx
, is_user
)) {
8463 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
8465 /* Note that the base address is bits [31:5] from the register
8466 * with bits [4:0] all zeroes, but the limit address is bits
8467 * [31:5] from the register with bits [4:0] all ones.
8469 uint32_t base
= env
->pmsav8
.rbar
[secure
][n
] & ~0x1f;
8470 uint32_t limit
= env
->pmsav8
.rlar
[secure
][n
] | 0x1f;
8472 if (!(env
->pmsav8
.rlar
[secure
][n
] & 0x1)) {
8473 /* Region disabled */
8477 if (address
< base
|| address
> limit
) {
8482 /* Multiple regions match -- always a failure (unlike
8483 * PMSAv7 where highest-numbered-region wins)
8485 *fsr
= 0x00d; /* permission fault */
8492 if (base
& ~TARGET_PAGE_MASK
) {
8493 qemu_log_mask(LOG_UNIMP
,
8494 "MPU_RBAR[%d]: No support for MPU region base"
8495 "address of 0x%" PRIx32
". Minimum alignment is "
8497 n
, base
, TARGET_PAGE_BITS
);
8500 if ((limit
+ 1) & ~TARGET_PAGE_MASK
) {
8501 qemu_log_mask(LOG_UNIMP
,
8502 "MPU_RBAR[%d]: No support for MPU region limit"
8503 "address of 0x%" PRIx32
". Minimum alignment is "
8505 n
, limit
, TARGET_PAGE_BITS
);
8512 /* background fault */
8517 if (matchregion
== -1) {
8518 /* hit using the background region */
8519 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
8521 uint32_t ap
= extract32(env
->pmsav8
.rbar
[secure
][matchregion
], 1, 2);
8522 uint32_t xn
= extract32(env
->pmsav8
.rbar
[secure
][matchregion
], 0, 1);
8524 if (m_is_system_region(env
, address
)) {
8525 /* System space is always execute never */
8529 *prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
);
8533 /* We don't need to look the attribute up in the MAIR0/MAIR1
8534 * registers because that only tells us about cacheability.
8538 *fsr
= 0x00d; /* Permission fault */
8539 return !(*prot
& (1 << access_type
));
8542 static bool get_phys_addr_pmsav5(CPUARMState
*env
, uint32_t address
,
8543 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
8544 hwaddr
*phys_ptr
, int *prot
, uint32_t *fsr
)
8549 bool is_user
= regime_is_user(env
, mmu_idx
);
8551 if (regime_translation_disabled(env
, mmu_idx
)) {
8553 *phys_ptr
= address
;
8554 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
8558 *phys_ptr
= address
;
8559 for (n
= 7; n
>= 0; n
--) {
8560 base
= env
->cp15
.c6_region
[n
];
8561 if ((base
& 1) == 0) {
8564 mask
= 1 << ((base
>> 1) & 0x1f);
8565 /* Keep this shift separate from the above to avoid an
8566 (undefined) << 32. */
8567 mask
= (mask
<< 1) - 1;
8568 if (((base
^ address
) & ~mask
) == 0) {
8577 if (access_type
== MMU_INST_FETCH
) {
8578 mask
= env
->cp15
.pmsav5_insn_ap
;
8580 mask
= env
->cp15
.pmsav5_data_ap
;
8582 mask
= (mask
>> (n
* 4)) & 0xf;
8592 *prot
= PAGE_READ
| PAGE_WRITE
;
8597 *prot
|= PAGE_WRITE
;
8601 *prot
= PAGE_READ
| PAGE_WRITE
;
8614 /* Bad permission. */
8622 /* get_phys_addr - get the physical address for this virtual address
8624 * Find the physical address corresponding to the given virtual address,
8625 * by doing a translation table walk on MMU based systems or using the
8626 * MPU state on MPU based systems.
8628 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
8629 * prot and page_size may not be filled in, and the populated fsr value provides
8630 * information on why the translation aborted, in the format of a
8631 * DFSR/IFSR fault register, with the following caveats:
8632 * * we honour the short vs long DFSR format differences.
8633 * * the WnR bit is never set (the caller must do this).
8634 * * for PSMAv5 based systems we don't bother to return a full FSR format
8638 * @address: virtual address to get physical address for
8639 * @access_type: 0 for read, 1 for write, 2 for execute
8640 * @mmu_idx: MMU index indicating required translation regime
8641 * @phys_ptr: set to the physical address corresponding to the virtual address
8642 * @attrs: set to the memory transaction attributes to use
8643 * @prot: set to the permissions for the page containing phys_ptr
8644 * @page_size: set to the size of the page containing phys_ptr
8645 * @fsr: set to the DFSR/IFSR value on failure
8647 static bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
8648 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
8649 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
8650 target_ulong
*page_size
, uint32_t *fsr
,
8651 ARMMMUFaultInfo
*fi
)
8653 if (mmu_idx
== ARMMMUIdx_S12NSE0
|| mmu_idx
== ARMMMUIdx_S12NSE1
) {
8654 /* Call ourselves recursively to do the stage 1 and then stage 2
8657 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
8662 ret
= get_phys_addr(env
, address
, access_type
,
8663 stage_1_mmu_idx(mmu_idx
), &ipa
, attrs
,
8664 prot
, page_size
, fsr
, fi
);
8666 /* If S1 fails or S2 is disabled, return early. */
8667 if (ret
|| regime_translation_disabled(env
, ARMMMUIdx_S2NS
)) {
8672 /* S1 is done. Now do S2 translation. */
8673 ret
= get_phys_addr_lpae(env
, ipa
, access_type
, ARMMMUIdx_S2NS
,
8674 phys_ptr
, attrs
, &s2_prot
,
8675 page_size
, fsr
, fi
);
8677 /* Combine the S1 and S2 perms. */
8682 * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
8684 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
8688 /* The page table entries may downgrade secure to non-secure, but
8689 * cannot upgrade an non-secure translation regime's attributes
8692 attrs
->secure
= regime_is_secure(env
, mmu_idx
);
8693 attrs
->user
= regime_is_user(env
, mmu_idx
);
8695 /* Fast Context Switch Extension. This doesn't exist at all in v8.
8696 * In v7 and earlier it affects all stage 1 translations.
8698 if (address
< 0x02000000 && mmu_idx
!= ARMMMUIdx_S2NS
8699 && !arm_feature(env
, ARM_FEATURE_V8
)) {
8700 if (regime_el(env
, mmu_idx
) == 3) {
8701 address
+= env
->cp15
.fcseidr_s
;
8703 address
+= env
->cp15
.fcseidr_ns
;
8707 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
8709 *page_size
= TARGET_PAGE_SIZE
;
8711 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8713 ret
= get_phys_addr_pmsav8(env
, address
, access_type
, mmu_idx
,
8714 phys_ptr
, prot
, fsr
);
8715 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
8717 ret
= get_phys_addr_pmsav7(env
, address
, access_type
, mmu_idx
,
8718 phys_ptr
, prot
, fsr
);
8721 ret
= get_phys_addr_pmsav5(env
, address
, access_type
, mmu_idx
,
8722 phys_ptr
, prot
, fsr
);
8724 qemu_log_mask(CPU_LOG_MMU
, "PMSA MPU lookup for %s at 0x%08" PRIx32
8725 " mmu_idx %u -> %s (prot %c%c%c)\n",
8726 access_type
== MMU_DATA_LOAD
? "reading" :
8727 (access_type
== MMU_DATA_STORE
? "writing" : "execute"),
8728 (uint32_t)address
, mmu_idx
,
8729 ret
? "Miss" : "Hit",
8730 *prot
& PAGE_READ
? 'r' : '-',
8731 *prot
& PAGE_WRITE
? 'w' : '-',
8732 *prot
& PAGE_EXEC
? 'x' : '-');
8737 /* Definitely a real MMU, not an MPU */
8739 if (regime_translation_disabled(env
, mmu_idx
)) {
8741 *phys_ptr
= address
;
8742 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
8743 *page_size
= TARGET_PAGE_SIZE
;
8747 if (regime_using_lpae_format(env
, mmu_idx
)) {
8748 return get_phys_addr_lpae(env
, address
, access_type
, mmu_idx
, phys_ptr
,
8749 attrs
, prot
, page_size
, fsr
, fi
);
8750 } else if (regime_sctlr(env
, mmu_idx
) & SCTLR_XP
) {
8751 return get_phys_addr_v6(env
, address
, access_type
, mmu_idx
, phys_ptr
,
8752 attrs
, prot
, page_size
, fsr
, fi
);
8754 return get_phys_addr_v5(env
, address
, access_type
, mmu_idx
, phys_ptr
,
8755 prot
, page_size
, fsr
, fi
);
8759 /* Walk the page table and (if the mapping exists) add the page
8760 * to the TLB. Return false on success, or true on failure. Populate
8761 * fsr with ARM DFSR/IFSR fault register format value on failure.
8763 bool arm_tlb_fill(CPUState
*cs
, vaddr address
,
8764 MMUAccessType access_type
, int mmu_idx
, uint32_t *fsr
,
8765 ARMMMUFaultInfo
*fi
)
8767 ARMCPU
*cpu
= ARM_CPU(cs
);
8768 CPUARMState
*env
= &cpu
->env
;
8770 target_ulong page_size
;
8773 MemTxAttrs attrs
= {};
8775 ret
= get_phys_addr(env
, address
, access_type
,
8776 core_to_arm_mmu_idx(env
, mmu_idx
), &phys_addr
,
8777 &attrs
, &prot
, &page_size
, fsr
, fi
);
8779 /* Map a single [sub]page. */
8780 phys_addr
&= TARGET_PAGE_MASK
;
8781 address
&= TARGET_PAGE_MASK
;
8782 tlb_set_page_with_attrs(cs
, address
, phys_addr
, attrs
,
8783 prot
, mmu_idx
, page_size
);
8790 hwaddr
arm_cpu_get_phys_page_attrs_debug(CPUState
*cs
, vaddr addr
,
8793 ARMCPU
*cpu
= ARM_CPU(cs
);
8794 CPUARMState
*env
= &cpu
->env
;
8796 target_ulong page_size
;
8800 ARMMMUFaultInfo fi
= {};
8801 ARMMMUIdx mmu_idx
= core_to_arm_mmu_idx(env
, cpu_mmu_index(env
, false));
8803 *attrs
= (MemTxAttrs
) {};
8805 ret
= get_phys_addr(env
, addr
, 0, mmu_idx
, &phys_addr
,
8806 attrs
, &prot
, &page_size
, &fsr
, &fi
);
8814 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
8817 unsigned el
= arm_current_el(env
);
8819 /* First handle registers which unprivileged can read */
8822 case 0 ... 7: /* xPSR sub-fields */
8824 if ((reg
& 1) && el
) {
8825 mask
|= XPSR_EXCP
; /* IPSR (unpriv. reads as zero) */
8828 mask
|= XPSR_NZCV
| XPSR_Q
; /* APSR */
8830 /* EPSR reads as zero */
8831 return xpsr_read(env
) & mask
;
8833 case 20: /* CONTROL */
8834 return env
->v7m
.control
[env
->v7m
.secure
];
8838 return 0; /* unprivileged reads others as zero */
8843 return (env
->v7m
.control
[env
->v7m
.secure
] & R_V7M_CONTROL_SPSEL_MASK
) ?
8844 env
->v7m
.other_sp
: env
->regs
[13];
8846 return (env
->v7m
.control
[env
->v7m
.secure
] & R_V7M_CONTROL_SPSEL_MASK
) ?
8847 env
->regs
[13] : env
->v7m
.other_sp
;
8848 case 16: /* PRIMASK */
8849 return env
->v7m
.primask
[env
->v7m
.secure
];
8850 case 17: /* BASEPRI */
8851 case 18: /* BASEPRI_MAX */
8852 return env
->v7m
.basepri
[env
->v7m
.secure
];
8853 case 19: /* FAULTMASK */
8854 return env
->v7m
.faultmask
[env
->v7m
.secure
];
8856 qemu_log_mask(LOG_GUEST_ERROR
, "Attempt to read unknown special"
8857 " register %d\n", reg
);
8862 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t maskreg
, uint32_t val
)
8864 /* We're passed bits [11..0] of the instruction; extract
8865 * SYSm and the mask bits.
8866 * Invalid combinations of SYSm and mask are UNPREDICTABLE;
8867 * we choose to treat them as if the mask bits were valid.
8868 * NB that the pseudocode 'mask' variable is bits [11..10],
8869 * whereas ours is [11..8].
8871 uint32_t mask
= extract32(maskreg
, 8, 4);
8872 uint32_t reg
= extract32(maskreg
, 0, 8);
8874 if (arm_current_el(env
) == 0 && reg
> 7) {
8875 /* only xPSR sub-fields may be written by unprivileged */
8880 case 0 ... 7: /* xPSR sub-fields */
8881 /* only APSR is actually writable */
8883 uint32_t apsrmask
= 0;
8886 apsrmask
|= XPSR_NZCV
| XPSR_Q
;
8888 if ((mask
& 4) && arm_feature(env
, ARM_FEATURE_THUMB_DSP
)) {
8889 apsrmask
|= XPSR_GE
;
8891 xpsr_write(env
, val
, apsrmask
);
8895 if (env
->v7m
.control
[env
->v7m
.secure
] & R_V7M_CONTROL_SPSEL_MASK
) {
8896 env
->v7m
.other_sp
= val
;
8898 env
->regs
[13] = val
;
8902 if (env
->v7m
.control
[env
->v7m
.secure
] & R_V7M_CONTROL_SPSEL_MASK
) {
8903 env
->regs
[13] = val
;
8905 env
->v7m
.other_sp
= val
;
8908 case 16: /* PRIMASK */
8909 env
->v7m
.primask
[env
->v7m
.secure
] = val
& 1;
8911 case 17: /* BASEPRI */
8912 env
->v7m
.basepri
[env
->v7m
.secure
] = val
& 0xff;
8914 case 18: /* BASEPRI_MAX */
8916 if (val
!= 0 && (val
< env
->v7m
.basepri
[env
->v7m
.secure
]
8917 || env
->v7m
.basepri
[env
->v7m
.secure
] == 0)) {
8918 env
->v7m
.basepri
[env
->v7m
.secure
] = val
;
8921 case 19: /* FAULTMASK */
8922 env
->v7m
.faultmask
[env
->v7m
.secure
] = val
& 1;
8924 case 20: /* CONTROL */
8925 /* Writing to the SPSEL bit only has an effect if we are in
8926 * thread mode; other bits can be updated by any privileged code.
8927 * switch_v7m_sp() deals with updating the SPSEL bit in
8928 * env->v7m.control, so we only need update the others.
8930 if (!arm_v7m_is_handler_mode(env
)) {
8931 switch_v7m_sp(env
, (val
& R_V7M_CONTROL_SPSEL_MASK
) != 0);
8933 env
->v7m
.control
[env
->v7m
.secure
] &= ~R_V7M_CONTROL_NPRIV_MASK
;
8934 env
->v7m
.control
[env
->v7m
.secure
] |= val
& R_V7M_CONTROL_NPRIV_MASK
;
8937 qemu_log_mask(LOG_GUEST_ERROR
, "Attempt to write unknown special"
8938 " register %d\n", reg
);
8945 void HELPER(dc_zva
)(CPUARMState
*env
, uint64_t vaddr_in
)
8947 /* Implement DC ZVA, which zeroes a fixed-length block of memory.
8948 * Note that we do not implement the (architecturally mandated)
8949 * alignment fault for attempts to use this on Device memory
8950 * (which matches the usual QEMU behaviour of not implementing either
8951 * alignment faults or any memory attribute handling).
8954 ARMCPU
*cpu
= arm_env_get_cpu(env
);
8955 uint64_t blocklen
= 4 << cpu
->dcz_blocksize
;
8956 uint64_t vaddr
= vaddr_in
& ~(blocklen
- 1);
8958 #ifndef CONFIG_USER_ONLY
8960 /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
8961 * the block size so we might have to do more than one TLB lookup.
8962 * We know that in fact for any v8 CPU the page size is at least 4K
8963 * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
8964 * 1K as an artefact of legacy v5 subpage support being present in the
8965 * same QEMU executable.
8967 int maxidx
= DIV_ROUND_UP(blocklen
, TARGET_PAGE_SIZE
);
8968 void *hostaddr
[maxidx
];
8970 unsigned mmu_idx
= cpu_mmu_index(env
, false);
8971 TCGMemOpIdx oi
= make_memop_idx(MO_UB
, mmu_idx
);
8973 for (try = 0; try < 2; try++) {
8975 for (i
= 0; i
< maxidx
; i
++) {
8976 hostaddr
[i
] = tlb_vaddr_to_host(env
,
8977 vaddr
+ TARGET_PAGE_SIZE
* i
,
8984 /* If it's all in the TLB it's fair game for just writing to;
8985 * we know we don't need to update dirty status, etc.
8987 for (i
= 0; i
< maxidx
- 1; i
++) {
8988 memset(hostaddr
[i
], 0, TARGET_PAGE_SIZE
);
8990 memset(hostaddr
[i
], 0, blocklen
- (i
* TARGET_PAGE_SIZE
));
8993 /* OK, try a store and see if we can populate the tlb. This
8994 * might cause an exception if the memory isn't writable,
8995 * in which case we will longjmp out of here. We must for
8996 * this purpose use the actual register value passed to us
8997 * so that we get the fault address right.
8999 helper_ret_stb_mmu(env
, vaddr_in
, 0, oi
, GETPC());
9000 /* Now we can populate the other TLB entries, if any */
9001 for (i
= 0; i
< maxidx
; i
++) {
9002 uint64_t va
= vaddr
+ TARGET_PAGE_SIZE
* i
;
9003 if (va
!= (vaddr_in
& TARGET_PAGE_MASK
)) {
9004 helper_ret_stb_mmu(env
, va
, 0, oi
, GETPC());
9009 /* Slow path (probably attempt to do this to an I/O device or
9010 * similar, or clearing of a block of code we have translations
9011 * cached for). Just do a series of byte writes as the architecture
9012 * demands. It's not worth trying to use a cpu_physical_memory_map(),
9013 * memset(), unmap() sequence here because:
9014 * + we'd need to account for the blocksize being larger than a page
9015 * + the direct-RAM access case is almost always going to be dealt
9016 * with in the fastpath code above, so there's no speed benefit
9017 * + we would have to deal with the map returning NULL because the
9018 * bounce buffer was in use
9020 for (i
= 0; i
< blocklen
; i
++) {
9021 helper_ret_stb_mmu(env
, vaddr
+ i
, 0, oi
, GETPC());
9025 memset(g2h(vaddr
), 0, blocklen
);
9029 /* Note that signed overflow is undefined in C. The following routines are
9030 careful to use unsigned types where modulo arithmetic is required.
9031 Failure to do so _will_ break on newer gcc. */
9033 /* Signed saturating arithmetic. */
9035 /* Perform 16-bit signed saturating addition. */
9036 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
9041 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
9050 /* Perform 8-bit signed saturating addition. */
9051 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
9056 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
9065 /* Perform 16-bit signed saturating subtraction. */
9066 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
9071 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
9080 /* Perform 8-bit signed saturating subtraction. */
9081 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
9086 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
9095 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
9096 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
9097 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
9098 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
9101 #include "op_addsub.h"
9103 /* Unsigned saturating arithmetic. */
9104 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
9113 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
9121 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
9130 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
9138 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
9139 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
9140 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
9141 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
9144 #include "op_addsub.h"
9146 /* Signed modulo arithmetic. */
9147 #define SARITH16(a, b, n, op) do { \
9149 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
9150 RESULT(sum, n, 16); \
9152 ge |= 3 << (n * 2); \
9155 #define SARITH8(a, b, n, op) do { \
9157 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
9158 RESULT(sum, n, 8); \
9164 #define ADD16(a, b, n) SARITH16(a, b, n, +)
9165 #define SUB16(a, b, n) SARITH16(a, b, n, -)
9166 #define ADD8(a, b, n) SARITH8(a, b, n, +)
9167 #define SUB8(a, b, n) SARITH8(a, b, n, -)
9171 #include "op_addsub.h"
9173 /* Unsigned modulo arithmetic. */
9174 #define ADD16(a, b, n) do { \
9176 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
9177 RESULT(sum, n, 16); \
9178 if ((sum >> 16) == 1) \
9179 ge |= 3 << (n * 2); \
9182 #define ADD8(a, b, n) do { \
9184 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
9185 RESULT(sum, n, 8); \
9186 if ((sum >> 8) == 1) \
9190 #define SUB16(a, b, n) do { \
9192 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
9193 RESULT(sum, n, 16); \
9194 if ((sum >> 16) == 0) \
9195 ge |= 3 << (n * 2); \
9198 #define SUB8(a, b, n) do { \
9200 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
9201 RESULT(sum, n, 8); \
9202 if ((sum >> 8) == 0) \
9209 #include "op_addsub.h"
9211 /* Halved signed arithmetic. */
9212 #define ADD16(a, b, n) \
9213 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
9214 #define SUB16(a, b, n) \
9215 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
9216 #define ADD8(a, b, n) \
9217 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
9218 #define SUB8(a, b, n) \
9219 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
9222 #include "op_addsub.h"
9224 /* Halved unsigned arithmetic. */
9225 #define ADD16(a, b, n) \
9226 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
9227 #define SUB16(a, b, n) \
9228 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
9229 #define ADD8(a, b, n) \
9230 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
9231 #define SUB8(a, b, n) \
9232 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
9235 #include "op_addsub.h"
9237 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
9245 /* Unsigned sum of absolute byte differences. */
9246 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
9249 sum
= do_usad(a
, b
);
9250 sum
+= do_usad(a
>> 8, b
>> 8);
9251 sum
+= do_usad(a
>> 16, b
>>16);
9252 sum
+= do_usad(a
>> 24, b
>> 24);
9256 /* For ARMv6 SEL instruction. */
9257 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
9270 return (a
& mask
) | (b
& ~mask
);
9273 /* VFP support. We follow the convention used for VFP instructions:
9274 Single precision routines have a "s" suffix, double precision a
9277 /* Convert host exception flags to vfp form. */
9278 static inline int vfp_exceptbits_from_host(int host_bits
)
9280 int target_bits
= 0;
9282 if (host_bits
& float_flag_invalid
)
9284 if (host_bits
& float_flag_divbyzero
)
9286 if (host_bits
& float_flag_overflow
)
9288 if (host_bits
& (float_flag_underflow
| float_flag_output_denormal
))
9290 if (host_bits
& float_flag_inexact
)
9291 target_bits
|= 0x10;
9292 if (host_bits
& float_flag_input_denormal
)
9293 target_bits
|= 0x80;
9297 uint32_t HELPER(vfp_get_fpscr
)(CPUARMState
*env
)
9302 fpscr
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & 0xffc8ffff)
9303 | (env
->vfp
.vec_len
<< 16)
9304 | (env
->vfp
.vec_stride
<< 20);
9305 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
9306 i
|= get_float_exception_flags(&env
->vfp
.standard_fp_status
);
9307 fpscr
|= vfp_exceptbits_from_host(i
);
9311 uint32_t vfp_get_fpscr(CPUARMState
*env
)
9313 return HELPER(vfp_get_fpscr
)(env
);
9316 /* Convert vfp exception flags to target form. */
9317 static inline int vfp_exceptbits_to_host(int target_bits
)
9321 if (target_bits
& 1)
9322 host_bits
|= float_flag_invalid
;
9323 if (target_bits
& 2)
9324 host_bits
|= float_flag_divbyzero
;
9325 if (target_bits
& 4)
9326 host_bits
|= float_flag_overflow
;
9327 if (target_bits
& 8)
9328 host_bits
|= float_flag_underflow
;
9329 if (target_bits
& 0x10)
9330 host_bits
|= float_flag_inexact
;
9331 if (target_bits
& 0x80)
9332 host_bits
|= float_flag_input_denormal
;
9336 void HELPER(vfp_set_fpscr
)(CPUARMState
*env
, uint32_t val
)
9341 changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
9342 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = (val
& 0xffc8ffff);
9343 env
->vfp
.vec_len
= (val
>> 16) & 7;
9344 env
->vfp
.vec_stride
= (val
>> 20) & 3;
9347 if (changed
& (3 << 22)) {
9348 i
= (val
>> 22) & 3;
9350 case FPROUNDING_TIEEVEN
:
9351 i
= float_round_nearest_even
;
9353 case FPROUNDING_POSINF
:
9356 case FPROUNDING_NEGINF
:
9357 i
= float_round_down
;
9359 case FPROUNDING_ZERO
:
9360 i
= float_round_to_zero
;
9363 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
9365 if (changed
& (1 << 24)) {
9366 set_flush_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
9367 set_flush_inputs_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
9369 if (changed
& (1 << 25))
9370 set_default_nan_mode((val
& (1 << 25)) != 0, &env
->vfp
.fp_status
);
9372 i
= vfp_exceptbits_to_host(val
);
9373 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
9374 set_float_exception_flags(0, &env
->vfp
.standard_fp_status
);
9377 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
)
9379 HELPER(vfp_set_fpscr
)(env
, val
);
9382 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
9384 #define VFP_BINOP(name) \
9385 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
9387 float_status *fpst = fpstp; \
9388 return float32_ ## name(a, b, fpst); \
9390 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
9392 float_status *fpst = fpstp; \
9393 return float64_ ## name(a, b, fpst); \
9405 float32
VFP_HELPER(neg
, s
)(float32 a
)
9407 return float32_chs(a
);
9410 float64
VFP_HELPER(neg
, d
)(float64 a
)
9412 return float64_chs(a
);
9415 float32
VFP_HELPER(abs
, s
)(float32 a
)
9417 return float32_abs(a
);
9420 float64
VFP_HELPER(abs
, d
)(float64 a
)
9422 return float64_abs(a
);
9425 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUARMState
*env
)
9427 return float32_sqrt(a
, &env
->vfp
.fp_status
);
9430 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUARMState
*env
)
9432 return float64_sqrt(a
, &env
->vfp
.fp_status
);
9435 /* XXX: check quiet/signaling case */
9436 #define DO_VFP_cmp(p, type) \
9437 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
9440 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
9441 case 0: flags = 0x6; break; \
9442 case -1: flags = 0x8; break; \
9443 case 1: flags = 0x2; break; \
9444 default: case 2: flags = 0x3; break; \
9446 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
9447 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
9449 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
9452 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
9453 case 0: flags = 0x6; break; \
9454 case -1: flags = 0x8; break; \
9455 case 1: flags = 0x2; break; \
9456 default: case 2: flags = 0x3; break; \
9458 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
9459 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
9461 DO_VFP_cmp(s
, float32
)
9462 DO_VFP_cmp(d
, float64
)
9465 /* Integer to float and float to integer conversions */
9467 #define CONV_ITOF(name, fsz, sign) \
9468 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
9470 float_status *fpst = fpstp; \
9471 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
9474 #define CONV_FTOI(name, fsz, sign, round) \
9475 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
9477 float_status *fpst = fpstp; \
9478 if (float##fsz##_is_any_nan(x)) { \
9479 float_raise(float_flag_invalid, fpst); \
9482 return float##fsz##_to_##sign##int32##round(x, fpst); \
9485 #define FLOAT_CONVS(name, p, fsz, sign) \
9486 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
9487 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
9488 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
9490 FLOAT_CONVS(si
, s
, 32, )
9491 FLOAT_CONVS(si
, d
, 64, )
9492 FLOAT_CONVS(ui
, s
, 32, u
)
9493 FLOAT_CONVS(ui
, d
, 64, u
)
9499 /* floating point conversion */
9500 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUARMState
*env
)
9502 float64 r
= float32_to_float64(x
, &env
->vfp
.fp_status
);
9503 /* ARM requires that S<->D conversion of any kind of NaN generates
9504 * a quiet NaN by forcing the most significant frac bit to 1.
9506 return float64_maybe_silence_nan(r
, &env
->vfp
.fp_status
);
9509 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUARMState
*env
)
9511 float32 r
= float64_to_float32(x
, &env
->vfp
.fp_status
);
9512 /* ARM requires that S<->D conversion of any kind of NaN generates
9513 * a quiet NaN by forcing the most significant frac bit to 1.
9515 return float32_maybe_silence_nan(r
, &env
->vfp
.fp_status
);
9518 /* VFP3 fixed point conversion. */
9519 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
9520 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
9523 float_status *fpst = fpstp; \
9525 tmp = itype##_to_##float##fsz(x, fpst); \
9526 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
9529 /* Notice that we want only input-denormal exception flags from the
9530 * scalbn operation: the other possible flags (overflow+inexact if
9531 * we overflow to infinity, output-denormal) aren't correct for the
9532 * complete scale-and-convert operation.
9534 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
9535 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
9539 float_status *fpst = fpstp; \
9540 int old_exc_flags = get_float_exception_flags(fpst); \
9542 if (float##fsz##_is_any_nan(x)) { \
9543 float_raise(float_flag_invalid, fpst); \
9546 tmp = float##fsz##_scalbn(x, shift, fpst); \
9547 old_exc_flags |= get_float_exception_flags(fpst) \
9548 & float_flag_input_denormal; \
9549 set_float_exception_flags(old_exc_flags, fpst); \
9550 return float##fsz##_to_##itype##round(tmp, fpst); \
9553 #define VFP_CONV_FIX(name, p, fsz, isz, itype) \
9554 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
9555 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
9556 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
9558 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \
9559 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
9560 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
9562 VFP_CONV_FIX(sh
, d
, 64, 64, int16
)
9563 VFP_CONV_FIX(sl
, d
, 64, 64, int32
)
9564 VFP_CONV_FIX_A64(sq
, d
, 64, 64, int64
)
9565 VFP_CONV_FIX(uh
, d
, 64, 64, uint16
)
9566 VFP_CONV_FIX(ul
, d
, 64, 64, uint32
)
9567 VFP_CONV_FIX_A64(uq
, d
, 64, 64, uint64
)
9568 VFP_CONV_FIX(sh
, s
, 32, 32, int16
)
9569 VFP_CONV_FIX(sl
, s
, 32, 32, int32
)
9570 VFP_CONV_FIX_A64(sq
, s
, 32, 64, int64
)
9571 VFP_CONV_FIX(uh
, s
, 32, 32, uint16
)
9572 VFP_CONV_FIX(ul
, s
, 32, 32, uint32
)
9573 VFP_CONV_FIX_A64(uq
, s
, 32, 64, uint64
)
9575 #undef VFP_CONV_FIX_FLOAT
9576 #undef VFP_CONV_FLOAT_FIX_ROUND
9578 /* Set the current fp rounding mode and return the old one.
9579 * The argument is a softfloat float_round_ value.
9581 uint32_t HELPER(set_rmode
)(uint32_t rmode
, CPUARMState
*env
)
9583 float_status
*fp_status
= &env
->vfp
.fp_status
;
9585 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
9586 set_float_rounding_mode(rmode
, fp_status
);
9591 /* Set the current fp rounding mode in the standard fp status and return
9592 * the old one. This is for NEON instructions that need to change the
9593 * rounding mode but wish to use the standard FPSCR values for everything
9594 * else. Always set the rounding mode back to the correct value after
9596 * The argument is a softfloat float_round_ value.
9598 uint32_t HELPER(set_neon_rmode
)(uint32_t rmode
, CPUARMState
*env
)
9600 float_status
*fp_status
= &env
->vfp
.standard_fp_status
;
9602 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
9603 set_float_rounding_mode(rmode
, fp_status
);
9608 /* Half precision conversions. */
9609 static float32
do_fcvt_f16_to_f32(uint32_t a
, CPUARMState
*env
, float_status
*s
)
9611 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
9612 float32 r
= float16_to_float32(make_float16(a
), ieee
, s
);
9614 return float32_maybe_silence_nan(r
, s
);
9619 static uint32_t do_fcvt_f32_to_f16(float32 a
, CPUARMState
*env
, float_status
*s
)
9621 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
9622 float16 r
= float32_to_float16(a
, ieee
, s
);
9624 r
= float16_maybe_silence_nan(r
, s
);
9626 return float16_val(r
);
9629 float32
HELPER(neon_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
9631 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.standard_fp_status
);
9634 uint32_t HELPER(neon_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
9636 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.standard_fp_status
);
9639 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
9641 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.fp_status
);
9644 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
9646 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.fp_status
);
9649 float64
HELPER(vfp_fcvt_f16_to_f64
)(uint32_t a
, CPUARMState
*env
)
9651 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
9652 float64 r
= float16_to_float64(make_float16(a
), ieee
, &env
->vfp
.fp_status
);
9654 return float64_maybe_silence_nan(r
, &env
->vfp
.fp_status
);
9659 uint32_t HELPER(vfp_fcvt_f64_to_f16
)(float64 a
, CPUARMState
*env
)
9661 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
9662 float16 r
= float64_to_float16(a
, ieee
, &env
->vfp
.fp_status
);
9664 r
= float16_maybe_silence_nan(r
, &env
->vfp
.fp_status
);
9666 return float16_val(r
);
9669 #define float32_two make_float32(0x40000000)
9670 #define float32_three make_float32(0x40400000)
9671 #define float32_one_point_five make_float32(0x3fc00000)
9673 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
9675 float_status
*s
= &env
->vfp
.standard_fp_status
;
9676 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
9677 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
9678 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
9679 float_raise(float_flag_input_denormal
, s
);
9683 return float32_sub(float32_two
, float32_mul(a
, b
, s
), s
);
9686 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
9688 float_status
*s
= &env
->vfp
.standard_fp_status
;
9690 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
9691 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
9692 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
9693 float_raise(float_flag_input_denormal
, s
);
9695 return float32_one_point_five
;
9697 product
= float32_mul(a
, b
, s
);
9698 return float32_div(float32_sub(float32_three
, product
, s
), float32_two
, s
);
9703 /* Constants 256 and 512 are used in some helpers; we avoid relying on
9704 * int->float conversions at run-time. */
9705 #define float64_256 make_float64(0x4070000000000000LL)
9706 #define float64_512 make_float64(0x4080000000000000LL)
9707 #define float32_maxnorm make_float32(0x7f7fffff)
9708 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
9710 /* Reciprocal functions
9712 * The algorithm that must be used to calculate the estimate
9713 * is specified by the ARM ARM, see FPRecipEstimate()
9716 static float64
recip_estimate(float64 a
, float_status
*real_fp_status
)
9718 /* These calculations mustn't set any fp exception flags,
9719 * so we use a local copy of the fp_status.
9721 float_status dummy_status
= *real_fp_status
;
9722 float_status
*s
= &dummy_status
;
9723 /* q = (int)(a * 512.0) */
9724 float64 q
= float64_mul(float64_512
, a
, s
);
9725 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
9727 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
9728 q
= int64_to_float64(q_int
, s
);
9729 q
= float64_add(q
, float64_half
, s
);
9730 q
= float64_div(q
, float64_512
, s
);
9731 q
= float64_div(float64_one
, q
, s
);
9733 /* s = (int)(256.0 * r + 0.5) */
9734 q
= float64_mul(q
, float64_256
, s
);
9735 q
= float64_add(q
, float64_half
, s
);
9736 q_int
= float64_to_int64_round_to_zero(q
, s
);
9738 /* return (double)s / 256.0 */
9739 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
9742 /* Common wrapper to call recip_estimate */
9743 static float64
call_recip_estimate(float64 num
, int off
, float_status
*fpst
)
9745 uint64_t val64
= float64_val(num
);
9746 uint64_t frac
= extract64(val64
, 0, 52);
9747 int64_t exp
= extract64(val64
, 52, 11);
9749 float64 scaled
, estimate
;
9751 /* Generate the scaled number for the estimate function */
9753 if (extract64(frac
, 51, 1) == 0) {
9755 frac
= extract64(frac
, 0, 50) << 2;
9757 frac
= extract64(frac
, 0, 51) << 1;
9761 /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
9762 scaled
= make_float64((0x3feULL
<< 52)
9763 | extract64(frac
, 44, 8) << 44);
9765 estimate
= recip_estimate(scaled
, fpst
);
9767 /* Build new result */
9768 val64
= float64_val(estimate
);
9769 sbit
= 0x8000000000000000ULL
& val64
;
9771 frac
= extract64(val64
, 0, 52);
9774 frac
= 1ULL << 51 | extract64(frac
, 1, 51);
9775 } else if (exp
== -1) {
9776 frac
= 1ULL << 50 | extract64(frac
, 2, 50);
9780 return make_float64(sbit
| (exp
<< 52) | frac
);
9783 static bool round_to_inf(float_status
*fpst
, bool sign_bit
)
9785 switch (fpst
->float_rounding_mode
) {
9786 case float_round_nearest_even
: /* Round to Nearest */
9788 case float_round_up
: /* Round to +Inf */
9790 case float_round_down
: /* Round to -Inf */
9792 case float_round_to_zero
: /* Round to Zero */
9796 g_assert_not_reached();
9799 float32
HELPER(recpe_f32
)(float32 input
, void *fpstp
)
9801 float_status
*fpst
= fpstp
;
9802 float32 f32
= float32_squash_input_denormal(input
, fpst
);
9803 uint32_t f32_val
= float32_val(f32
);
9804 uint32_t f32_sbit
= 0x80000000ULL
& f32_val
;
9805 int32_t f32_exp
= extract32(f32_val
, 23, 8);
9806 uint32_t f32_frac
= extract32(f32_val
, 0, 23);
9812 if (float32_is_any_nan(f32
)) {
9814 if (float32_is_signaling_nan(f32
, fpst
)) {
9815 float_raise(float_flag_invalid
, fpst
);
9816 nan
= float32_maybe_silence_nan(f32
, fpst
);
9818 if (fpst
->default_nan_mode
) {
9819 nan
= float32_default_nan(fpst
);
9822 } else if (float32_is_infinity(f32
)) {
9823 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
9824 } else if (float32_is_zero(f32
)) {
9825 float_raise(float_flag_divbyzero
, fpst
);
9826 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
9827 } else if ((f32_val
& ~(1ULL << 31)) < (1ULL << 21)) {
9828 /* Abs(value) < 2.0^-128 */
9829 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
9830 if (round_to_inf(fpst
, f32_sbit
)) {
9831 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
9833 return float32_set_sign(float32_maxnorm
, float32_is_neg(f32
));
9835 } else if (f32_exp
>= 253 && fpst
->flush_to_zero
) {
9836 float_raise(float_flag_underflow
, fpst
);
9837 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
9841 f64
= make_float64(((int64_t)(f32_exp
) << 52) | (int64_t)(f32_frac
) << 29);
9842 r64
= call_recip_estimate(f64
, 253, fpst
);
9843 r64_val
= float64_val(r64
);
9844 r64_exp
= extract64(r64_val
, 52, 11);
9845 r64_frac
= extract64(r64_val
, 0, 52);
9847 /* result = sign : result_exp<7:0> : fraction<51:29>; */
9848 return make_float32(f32_sbit
|
9849 (r64_exp
& 0xff) << 23 |
9850 extract64(r64_frac
, 29, 24));
9853 float64
HELPER(recpe_f64
)(float64 input
, void *fpstp
)
9855 float_status
*fpst
= fpstp
;
9856 float64 f64
= float64_squash_input_denormal(input
, fpst
);
9857 uint64_t f64_val
= float64_val(f64
);
9858 uint64_t f64_sbit
= 0x8000000000000000ULL
& f64_val
;
9859 int64_t f64_exp
= extract64(f64_val
, 52, 11);
9865 /* Deal with any special cases */
9866 if (float64_is_any_nan(f64
)) {
9868 if (float64_is_signaling_nan(f64
, fpst
)) {
9869 float_raise(float_flag_invalid
, fpst
);
9870 nan
= float64_maybe_silence_nan(f64
, fpst
);
9872 if (fpst
->default_nan_mode
) {
9873 nan
= float64_default_nan(fpst
);
9876 } else if (float64_is_infinity(f64
)) {
9877 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
9878 } else if (float64_is_zero(f64
)) {
9879 float_raise(float_flag_divbyzero
, fpst
);
9880 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
9881 } else if ((f64_val
& ~(1ULL << 63)) < (1ULL << 50)) {
9882 /* Abs(value) < 2.0^-1024 */
9883 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
9884 if (round_to_inf(fpst
, f64_sbit
)) {
9885 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
9887 return float64_set_sign(float64_maxnorm
, float64_is_neg(f64
));
9889 } else if (f64_exp
>= 2045 && fpst
->flush_to_zero
) {
9890 float_raise(float_flag_underflow
, fpst
);
9891 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
9894 r64
= call_recip_estimate(f64
, 2045, fpst
);
9895 r64_val
= float64_val(r64
);
9896 r64_exp
= extract64(r64_val
, 52, 11);
9897 r64_frac
= extract64(r64_val
, 0, 52);
9899 /* result = sign : result_exp<10:0> : fraction<51:0> */
9900 return make_float64(f64_sbit
|
9901 ((r64_exp
& 0x7ff) << 52) |
9905 /* The algorithm that must be used to calculate the estimate
9906 * is specified by the ARM ARM.
9908 static float64
recip_sqrt_estimate(float64 a
, float_status
*real_fp_status
)
9910 /* These calculations mustn't set any fp exception flags,
9911 * so we use a local copy of the fp_status.
9913 float_status dummy_status
= *real_fp_status
;
9914 float_status
*s
= &dummy_status
;
9918 if (float64_lt(a
, float64_half
, s
)) {
9919 /* range 0.25 <= a < 0.5 */
9921 /* a in units of 1/512 rounded down */
9922 /* q0 = (int)(a * 512.0); */
9923 q
= float64_mul(float64_512
, a
, s
);
9924 q_int
= float64_to_int64_round_to_zero(q
, s
);
9926 /* reciprocal root r */
9927 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
9928 q
= int64_to_float64(q_int
, s
);
9929 q
= float64_add(q
, float64_half
, s
);
9930 q
= float64_div(q
, float64_512
, s
);
9931 q
= float64_sqrt(q
, s
);
9932 q
= float64_div(float64_one
, q
, s
);
9934 /* range 0.5 <= a < 1.0 */
9936 /* a in units of 1/256 rounded down */
9937 /* q1 = (int)(a * 256.0); */
9938 q
= float64_mul(float64_256
, a
, s
);
9939 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
9941 /* reciprocal root r */
9942 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
9943 q
= int64_to_float64(q_int
, s
);
9944 q
= float64_add(q
, float64_half
, s
);
9945 q
= float64_div(q
, float64_256
, s
);
9946 q
= float64_sqrt(q
, s
);
9947 q
= float64_div(float64_one
, q
, s
);
9949 /* r in units of 1/256 rounded to nearest */
9950 /* s = (int)(256.0 * r + 0.5); */
9952 q
= float64_mul(q
, float64_256
,s
);
9953 q
= float64_add(q
, float64_half
, s
);
9954 q_int
= float64_to_int64_round_to_zero(q
, s
);
9956 /* return (double)s / 256.0;*/
9957 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
9960 float32
HELPER(rsqrte_f32
)(float32 input
, void *fpstp
)
9962 float_status
*s
= fpstp
;
9963 float32 f32
= float32_squash_input_denormal(input
, s
);
9964 uint32_t val
= float32_val(f32
);
9965 uint32_t f32_sbit
= 0x80000000 & val
;
9966 int32_t f32_exp
= extract32(val
, 23, 8);
9967 uint32_t f32_frac
= extract32(val
, 0, 23);
9973 if (float32_is_any_nan(f32
)) {
9975 if (float32_is_signaling_nan(f32
, s
)) {
9976 float_raise(float_flag_invalid
, s
);
9977 nan
= float32_maybe_silence_nan(f32
, s
);
9979 if (s
->default_nan_mode
) {
9980 nan
= float32_default_nan(s
);
9983 } else if (float32_is_zero(f32
)) {
9984 float_raise(float_flag_divbyzero
, s
);
9985 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
9986 } else if (float32_is_neg(f32
)) {
9987 float_raise(float_flag_invalid
, s
);
9988 return float32_default_nan(s
);
9989 } else if (float32_is_infinity(f32
)) {
9990 return float32_zero
;
9993 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
9994 * preserving the parity of the exponent. */
9996 f64_frac
= ((uint64_t) f32_frac
) << 29;
9998 while (extract64(f64_frac
, 51, 1) == 0) {
9999 f64_frac
= f64_frac
<< 1;
10000 f32_exp
= f32_exp
-1;
10002 f64_frac
= extract64(f64_frac
, 0, 51) << 1;
10005 if (extract64(f32_exp
, 0, 1) == 0) {
10006 f64
= make_float64(((uint64_t) f32_sbit
) << 32
10010 f64
= make_float64(((uint64_t) f32_sbit
) << 32
10015 result_exp
= (380 - f32_exp
) / 2;
10017 f64
= recip_sqrt_estimate(f64
, s
);
10019 val64
= float64_val(f64
);
10021 val
= ((result_exp
& 0xff) << 23)
10022 | ((val64
>> 29) & 0x7fffff);
10023 return make_float32(val
);
10026 float64
HELPER(rsqrte_f64
)(float64 input
, void *fpstp
)
10028 float_status
*s
= fpstp
;
10029 float64 f64
= float64_squash_input_denormal(input
, s
);
10030 uint64_t val
= float64_val(f64
);
10031 uint64_t f64_sbit
= 0x8000000000000000ULL
& val
;
10032 int64_t f64_exp
= extract64(val
, 52, 11);
10033 uint64_t f64_frac
= extract64(val
, 0, 52);
10034 int64_t result_exp
;
10035 uint64_t result_frac
;
10037 if (float64_is_any_nan(f64
)) {
10039 if (float64_is_signaling_nan(f64
, s
)) {
10040 float_raise(float_flag_invalid
, s
);
10041 nan
= float64_maybe_silence_nan(f64
, s
);
10043 if (s
->default_nan_mode
) {
10044 nan
= float64_default_nan(s
);
10047 } else if (float64_is_zero(f64
)) {
10048 float_raise(float_flag_divbyzero
, s
);
10049 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
10050 } else if (float64_is_neg(f64
)) {
10051 float_raise(float_flag_invalid
, s
);
10052 return float64_default_nan(s
);
10053 } else if (float64_is_infinity(f64
)) {
10054 return float64_zero
;
10057 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
10058 * preserving the parity of the exponent. */
10060 if (f64_exp
== 0) {
10061 while (extract64(f64_frac
, 51, 1) == 0) {
10062 f64_frac
= f64_frac
<< 1;
10063 f64_exp
= f64_exp
- 1;
10065 f64_frac
= extract64(f64_frac
, 0, 51) << 1;
10068 if (extract64(f64_exp
, 0, 1) == 0) {
10069 f64
= make_float64(f64_sbit
10073 f64
= make_float64(f64_sbit
10078 result_exp
= (3068 - f64_exp
) / 2;
10080 f64
= recip_sqrt_estimate(f64
, s
);
10082 result_frac
= extract64(float64_val(f64
), 0, 52);
10084 return make_float64(f64_sbit
|
10085 ((result_exp
& 0x7ff) << 52) |
10089 uint32_t HELPER(recpe_u32
)(uint32_t a
, void *fpstp
)
10091 float_status
*s
= fpstp
;
10094 if ((a
& 0x80000000) == 0) {
10098 f64
= make_float64((0x3feULL
<< 52)
10099 | ((int64_t)(a
& 0x7fffffff) << 21));
10101 f64
= recip_estimate(f64
, s
);
10103 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
10106 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, void *fpstp
)
10108 float_status
*fpst
= fpstp
;
10111 if ((a
& 0xc0000000) == 0) {
10115 if (a
& 0x80000000) {
10116 f64
= make_float64((0x3feULL
<< 52)
10117 | ((uint64_t)(a
& 0x7fffffff) << 21));
10118 } else { /* bits 31-30 == '01' */
10119 f64
= make_float64((0x3fdULL
<< 52)
10120 | ((uint64_t)(a
& 0x3fffffff) << 22));
10123 f64
= recip_sqrt_estimate(f64
, fpst
);
10125 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
10128 /* VFPv4 fused multiply-accumulate */
10129 float32
VFP_HELPER(muladd
, s
)(float32 a
, float32 b
, float32 c
, void *fpstp
)
10131 float_status
*fpst
= fpstp
;
10132 return float32_muladd(a
, b
, c
, 0, fpst
);
10135 float64
VFP_HELPER(muladd
, d
)(float64 a
, float64 b
, float64 c
, void *fpstp
)
10137 float_status
*fpst
= fpstp
;
10138 return float64_muladd(a
, b
, c
, 0, fpst
);
10141 /* ARMv8 round to integral */
10142 float32
HELPER(rints_exact
)(float32 x
, void *fp_status
)
10144 return float32_round_to_int(x
, fp_status
);
10147 float64
HELPER(rintd_exact
)(float64 x
, void *fp_status
)
10149 return float64_round_to_int(x
, fp_status
);
10152 float32
HELPER(rints
)(float32 x
, void *fp_status
)
10154 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
10157 ret
= float32_round_to_int(x
, fp_status
);
10159 /* Suppress any inexact exceptions the conversion produced */
10160 if (!(old_flags
& float_flag_inexact
)) {
10161 new_flags
= get_float_exception_flags(fp_status
);
10162 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
10168 float64
HELPER(rintd
)(float64 x
, void *fp_status
)
10170 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
10173 ret
= float64_round_to_int(x
, fp_status
);
10175 new_flags
= get_float_exception_flags(fp_status
);
10177 /* Suppress any inexact exceptions the conversion produced */
10178 if (!(old_flags
& float_flag_inexact
)) {
10179 new_flags
= get_float_exception_flags(fp_status
);
10180 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
10186 /* Convert ARM rounding mode to softfloat */
10187 int arm_rmode_to_sf(int rmode
)
10190 case FPROUNDING_TIEAWAY
:
10191 rmode
= float_round_ties_away
;
10193 case FPROUNDING_ODD
:
10194 /* FIXME: add support for TIEAWAY and ODD */
10195 qemu_log_mask(LOG_UNIMP
, "arm: unimplemented rounding mode: %d\n",
10197 case FPROUNDING_TIEEVEN
:
10199 rmode
= float_round_nearest_even
;
10201 case FPROUNDING_POSINF
:
10202 rmode
= float_round_up
;
10204 case FPROUNDING_NEGINF
:
10205 rmode
= float_round_down
;
10207 case FPROUNDING_ZERO
:
10208 rmode
= float_round_to_zero
;
10215 * The upper bytes of val (above the number specified by 'bytes') must have
10216 * been zeroed out by the caller.
10218 uint32_t HELPER(crc32
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
10222 stl_le_p(buf
, val
);
10224 /* zlib crc32 converts the accumulator and output to one's complement. */
10225 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
10228 uint32_t HELPER(crc32c
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
10232 stl_le_p(buf
, val
);
10234 /* Linux crc32c converts the output to one's complement. */
10235 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;