4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
21 #include "qemu/osdep.h"
22 #include "qemu/error-report.h"
23 #include "qapi/error.h"
25 #include "internals.h"
26 #include "qemu-common.h"
27 #include "exec/exec-all.h"
28 #include "hw/qdev-properties.h"
29 #if !defined(CONFIG_USER_ONLY)
30 #include "hw/loader.h"
32 #include "hw/arm/arm.h"
33 #include "sysemu/sysemu.h"
34 #include "sysemu/hw_accel.h"
37 static void arm_cpu_set_pc(CPUState
*cs
, vaddr value
)
39 ARMCPU
*cpu
= ARM_CPU(cs
);
41 cpu
->env
.regs
[15] = value
;
44 static bool arm_cpu_has_work(CPUState
*cs
)
46 ARMCPU
*cpu
= ARM_CPU(cs
);
48 return (cpu
->power_state
!= PSCI_OFF
)
49 && cs
->interrupt_request
&
50 (CPU_INTERRUPT_FIQ
| CPU_INTERRUPT_HARD
51 | CPU_INTERRUPT_VFIQ
| CPU_INTERRUPT_VIRQ
52 | CPU_INTERRUPT_EXITTB
);
55 void arm_register_el_change_hook(ARMCPU
*cpu
, ARMELChangeHook
*hook
,
58 /* We currently only support registering a single hook function */
59 assert(!cpu
->el_change_hook
);
60 cpu
->el_change_hook
= hook
;
61 cpu
->el_change_hook_opaque
= opaque
;
64 static void cp_reg_reset(gpointer key
, gpointer value
, gpointer opaque
)
66 /* Reset a single ARMCPRegInfo register */
67 ARMCPRegInfo
*ri
= value
;
70 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
)) {
75 ri
->resetfn(&cpu
->env
, ri
);
79 /* A zero offset is never possible as it would be regs[0]
80 * so we use it to indicate that reset is being handled elsewhere.
81 * This is basically only used for fields in non-core coprocessors
82 * (like the pxa2xx ones).
84 if (!ri
->fieldoffset
) {
88 if (cpreg_field_is_64bit(ri
)) {
89 CPREG_FIELD64(&cpu
->env
, ri
) = ri
->resetvalue
;
91 CPREG_FIELD32(&cpu
->env
, ri
) = ri
->resetvalue
;
95 static void cp_reg_check_reset(gpointer key
, gpointer value
, gpointer opaque
)
97 /* Purely an assertion check: we've already done reset once,
98 * so now check that running the reset for the cpreg doesn't
99 * change its value. This traps bugs where two different cpregs
100 * both try to reset the same state field but to different values.
102 ARMCPRegInfo
*ri
= value
;
103 ARMCPU
*cpu
= opaque
;
104 uint64_t oldvalue
, newvalue
;
106 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
| ARM_CP_NO_RAW
)) {
110 oldvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
111 cp_reg_reset(key
, value
, opaque
);
112 newvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
113 assert(oldvalue
== newvalue
);
116 /* CPUClass::reset() */
117 static void arm_cpu_reset(CPUState
*s
)
119 ARMCPU
*cpu
= ARM_CPU(s
);
120 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(cpu
);
121 CPUARMState
*env
= &cpu
->env
;
123 acc
->parent_reset(s
);
125 memset(env
, 0, offsetof(CPUARMState
, end_reset_fields
));
127 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_reset
, cpu
);
128 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_check_reset
, cpu
);
130 env
->vfp
.xregs
[ARM_VFP_FPSID
] = cpu
->reset_fpsid
;
131 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = cpu
->mvfr0
;
132 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = cpu
->mvfr1
;
133 env
->vfp
.xregs
[ARM_VFP_MVFR2
] = cpu
->mvfr2
;
135 cpu
->power_state
= cpu
->start_powered_off
? PSCI_OFF
: PSCI_ON
;
136 s
->halted
= cpu
->start_powered_off
;
138 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
139 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
142 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
143 /* 64 bit CPUs always start in 64 bit mode */
145 #if defined(CONFIG_USER_ONLY)
146 env
->pstate
= PSTATE_MODE_EL0t
;
147 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
148 env
->cp15
.sctlr_el
[1] |= SCTLR_UCT
| SCTLR_UCI
| SCTLR_DZE
;
149 /* and to the FP/Neon instructions */
150 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 2, 3);
152 /* Reset into the highest available EL */
153 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
154 env
->pstate
= PSTATE_MODE_EL3h
;
155 } else if (arm_feature(env
, ARM_FEATURE_EL2
)) {
156 env
->pstate
= PSTATE_MODE_EL2h
;
158 env
->pstate
= PSTATE_MODE_EL1h
;
160 env
->pc
= cpu
->rvbar
;
163 #if defined(CONFIG_USER_ONLY)
164 /* Userspace expects access to cp10 and cp11 for FP/Neon */
165 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 4, 0xf);
169 #if defined(CONFIG_USER_ONLY)
170 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
171 /* For user mode we must enable access to coprocessors */
172 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
173 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
174 env
->cp15
.c15_cpar
= 3;
175 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
176 env
->cp15
.c15_cpar
= 1;
179 /* SVC mode with interrupts disabled. */
180 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
;
181 env
->daif
= PSTATE_D
| PSTATE_A
| PSTATE_I
| PSTATE_F
;
183 if (arm_feature(env
, ARM_FEATURE_M
)) {
184 uint32_t initial_msp
; /* Loaded from 0x0 */
185 uint32_t initial_pc
; /* Loaded from 0x4 */
188 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
189 env
->v7m
.secure
= true;
192 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
193 * that it resets to 1, so QEMU always does that rather than making
194 * it dependent on CPU model. In v8M it is RES1.
196 env
->v7m
.ccr
[M_REG_NS
] = R_V7M_CCR_STKALIGN_MASK
;
197 env
->v7m
.ccr
[M_REG_S
] = R_V7M_CCR_STKALIGN_MASK
;
198 if (arm_feature(env
, ARM_FEATURE_V8
)) {
199 /* in v8M the NONBASETHRDENA bit [0] is RES1 */
200 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
201 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
204 /* Unlike A/R profile, M profile defines the reset LR value */
205 env
->regs
[14] = 0xffffffff;
207 /* Load the initial SP and PC from the vector table at address 0 */
210 /* Address zero is covered by ROM which hasn't yet been
211 * copied into physical memory.
213 initial_msp
= ldl_p(rom
);
214 initial_pc
= ldl_p(rom
+ 4);
216 /* Address zero not covered by a ROM blob, or the ROM blob
217 * is in non-modifiable memory and this is a second reset after
218 * it got copied into memory. In the latter case, rom_ptr
219 * will return a NULL pointer and we should use ldl_phys instead.
221 initial_msp
= ldl_phys(s
->as
, 0);
222 initial_pc
= ldl_phys(s
->as
, 4);
225 env
->regs
[13] = initial_msp
& 0xFFFFFFFC;
226 env
->regs
[15] = initial_pc
& ~1;
227 env
->thumb
= initial_pc
& 1;
230 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
231 * executing as AArch32 then check if highvecs are enabled and
232 * adjust the PC accordingly.
234 if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
235 env
->regs
[15] = 0xFFFF0000;
238 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
241 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
242 if (cpu
->pmsav7_dregion
> 0) {
243 if (arm_feature(env
, ARM_FEATURE_V8
)) {
244 memset(env
->pmsav8
.rbar
[M_REG_NS
], 0,
245 sizeof(*env
->pmsav8
.rbar
[M_REG_NS
])
246 * cpu
->pmsav7_dregion
);
247 memset(env
->pmsav8
.rlar
[M_REG_NS
], 0,
248 sizeof(*env
->pmsav8
.rlar
[M_REG_NS
])
249 * cpu
->pmsav7_dregion
);
250 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
251 memset(env
->pmsav8
.rbar
[M_REG_S
], 0,
252 sizeof(*env
->pmsav8
.rbar
[M_REG_S
])
253 * cpu
->pmsav7_dregion
);
254 memset(env
->pmsav8
.rlar
[M_REG_S
], 0,
255 sizeof(*env
->pmsav8
.rlar
[M_REG_S
])
256 * cpu
->pmsav7_dregion
);
258 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
259 memset(env
->pmsav7
.drbar
, 0,
260 sizeof(*env
->pmsav7
.drbar
) * cpu
->pmsav7_dregion
);
261 memset(env
->pmsav7
.drsr
, 0,
262 sizeof(*env
->pmsav7
.drsr
) * cpu
->pmsav7_dregion
);
263 memset(env
->pmsav7
.dracr
, 0,
264 sizeof(*env
->pmsav7
.dracr
) * cpu
->pmsav7_dregion
);
267 env
->pmsav7
.rnr
[M_REG_NS
] = 0;
268 env
->pmsav7
.rnr
[M_REG_S
] = 0;
269 env
->pmsav8
.mair0
[M_REG_NS
] = 0;
270 env
->pmsav8
.mair0
[M_REG_S
] = 0;
271 env
->pmsav8
.mair1
[M_REG_NS
] = 0;
272 env
->pmsav8
.mair1
[M_REG_S
] = 0;
275 set_flush_to_zero(1, &env
->vfp
.standard_fp_status
);
276 set_flush_inputs_to_zero(1, &env
->vfp
.standard_fp_status
);
277 set_default_nan_mode(1, &env
->vfp
.standard_fp_status
);
278 set_float_detect_tininess(float_tininess_before_rounding
,
279 &env
->vfp
.fp_status
);
280 set_float_detect_tininess(float_tininess_before_rounding
,
281 &env
->vfp
.standard_fp_status
);
282 #ifndef CONFIG_USER_ONLY
284 kvm_arm_reset_vcpu(cpu
);
288 hw_breakpoint_update_all(cpu
);
289 hw_watchpoint_update_all(cpu
);
292 bool arm_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
294 CPUClass
*cc
= CPU_GET_CLASS(cs
);
295 CPUARMState
*env
= cs
->env_ptr
;
296 uint32_t cur_el
= arm_current_el(env
);
297 bool secure
= arm_is_secure(env
);
302 if (interrupt_request
& CPU_INTERRUPT_FIQ
) {
304 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
305 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
306 cs
->exception_index
= excp_idx
;
307 env
->exception
.target_el
= target_el
;
308 cc
->do_interrupt(cs
);
312 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
314 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
315 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
316 cs
->exception_index
= excp_idx
;
317 env
->exception
.target_el
= target_el
;
318 cc
->do_interrupt(cs
);
322 if (interrupt_request
& CPU_INTERRUPT_VIRQ
) {
323 excp_idx
= EXCP_VIRQ
;
325 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
326 cs
->exception_index
= excp_idx
;
327 env
->exception
.target_el
= target_el
;
328 cc
->do_interrupt(cs
);
332 if (interrupt_request
& CPU_INTERRUPT_VFIQ
) {
333 excp_idx
= EXCP_VFIQ
;
335 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
336 cs
->exception_index
= excp_idx
;
337 env
->exception
.target_el
= target_el
;
338 cc
->do_interrupt(cs
);
346 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
347 static bool arm_v7m_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
349 CPUClass
*cc
= CPU_GET_CLASS(cs
);
350 ARMCPU
*cpu
= ARM_CPU(cs
);
351 CPUARMState
*env
= &cpu
->env
;
354 /* ARMv7-M interrupt masking works differently than -A or -R.
355 * There is no FIQ/IRQ distinction. Instead of I and F bits
356 * masking FIQ and IRQ interrupts, an exception is taken only
357 * if it is higher priority than the current execution priority
358 * (which depends on state like BASEPRI, FAULTMASK and the
359 * currently active exception).
361 if (interrupt_request
& CPU_INTERRUPT_HARD
362 && (armv7m_nvic_can_take_pending_exception(env
->nvic
))) {
363 cs
->exception_index
= EXCP_IRQ
;
364 cc
->do_interrupt(cs
);
371 #ifndef CONFIG_USER_ONLY
372 static void arm_cpu_set_irq(void *opaque
, int irq
, int level
)
374 ARMCPU
*cpu
= opaque
;
375 CPUARMState
*env
= &cpu
->env
;
376 CPUState
*cs
= CPU(cpu
);
377 static const int mask
[] = {
378 [ARM_CPU_IRQ
] = CPU_INTERRUPT_HARD
,
379 [ARM_CPU_FIQ
] = CPU_INTERRUPT_FIQ
,
380 [ARM_CPU_VIRQ
] = CPU_INTERRUPT_VIRQ
,
381 [ARM_CPU_VFIQ
] = CPU_INTERRUPT_VFIQ
387 assert(arm_feature(env
, ARM_FEATURE_EL2
));
392 cpu_interrupt(cs
, mask
[irq
]);
394 cpu_reset_interrupt(cs
, mask
[irq
]);
398 g_assert_not_reached();
402 static void arm_cpu_kvm_set_irq(void *opaque
, int irq
, int level
)
405 ARMCPU
*cpu
= opaque
;
406 CPUState
*cs
= CPU(cpu
);
407 int kvm_irq
= KVM_ARM_IRQ_TYPE_CPU
<< KVM_ARM_IRQ_TYPE_SHIFT
;
411 kvm_irq
|= KVM_ARM_IRQ_CPU_IRQ
;
414 kvm_irq
|= KVM_ARM_IRQ_CPU_FIQ
;
417 g_assert_not_reached();
419 kvm_irq
|= cs
->cpu_index
<< KVM_ARM_IRQ_VCPU_SHIFT
;
420 kvm_set_irq(kvm_state
, kvm_irq
, level
? 1 : 0);
424 static bool arm_cpu_virtio_is_big_endian(CPUState
*cs
)
426 ARMCPU
*cpu
= ARM_CPU(cs
);
427 CPUARMState
*env
= &cpu
->env
;
429 cpu_synchronize_state(cs
);
430 return arm_cpu_data_is_big_endian(env
);
435 static inline void set_feature(CPUARMState
*env
, int feature
)
437 env
->features
|= 1ULL << feature
;
440 static inline void unset_feature(CPUARMState
*env
, int feature
)
442 env
->features
&= ~(1ULL << feature
);
446 print_insn_thumb1(bfd_vma pc
, disassemble_info
*info
)
448 return print_insn_arm(pc
| 1, info
);
451 static int arm_read_memory_func(bfd_vma memaddr
, bfd_byte
*b
,
452 int length
, struct disassemble_info
*info
)
454 assert(info
->read_memory_inner_func
);
455 assert((info
->flags
& INSN_ARM_BE32
) == 0 || length
== 2 || length
== 4);
457 if ((info
->flags
& INSN_ARM_BE32
) != 0 && length
== 2) {
458 assert(info
->endian
== BFD_ENDIAN_LITTLE
);
459 return info
->read_memory_inner_func(memaddr
^ 2, (bfd_byte
*)b
, 2,
462 return info
->read_memory_inner_func(memaddr
, b
, length
, info
);
466 static void arm_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
468 ARMCPU
*ac
= ARM_CPU(cpu
);
469 CPUARMState
*env
= &ac
->env
;
472 /* We might not be compiled with the A64 disassembler
473 * because it needs a C++ compiler. Leave print_insn
474 * unset in this case to use the caller default behaviour.
476 #if defined(CONFIG_ARM_A64_DIS)
477 info
->print_insn
= print_insn_arm_a64
;
479 } else if (env
->thumb
) {
480 info
->print_insn
= print_insn_thumb1
;
482 info
->print_insn
= print_insn_arm
;
484 if (bswap_code(arm_sctlr_b(env
))) {
485 #ifdef TARGET_WORDS_BIGENDIAN
486 info
->endian
= BFD_ENDIAN_LITTLE
;
488 info
->endian
= BFD_ENDIAN_BIG
;
491 if (info
->read_memory_inner_func
== NULL
) {
492 info
->read_memory_inner_func
= info
->read_memory_func
;
493 info
->read_memory_func
= arm_read_memory_func
;
495 info
->flags
&= ~INSN_ARM_BE32
;
496 if (arm_sctlr_b(env
)) {
497 info
->flags
|= INSN_ARM_BE32
;
501 uint64_t arm_cpu_mp_affinity(int idx
, uint8_t clustersz
)
503 uint32_t Aff1
= idx
/ clustersz
;
504 uint32_t Aff0
= idx
% clustersz
;
505 return (Aff1
<< ARM_AFF1_SHIFT
) | Aff0
;
508 static void arm_cpu_initfn(Object
*obj
)
510 CPUState
*cs
= CPU(obj
);
511 ARMCPU
*cpu
= ARM_CPU(obj
);
514 cs
->env_ptr
= &cpu
->env
;
515 cpu
->cp_regs
= g_hash_table_new_full(g_int_hash
, g_int_equal
,
518 #ifndef CONFIG_USER_ONLY
519 /* Our inbound IRQ and FIQ lines */
521 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
522 * the same interface as non-KVM CPUs.
524 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_kvm_set_irq
, 4);
526 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_set_irq
, 4);
529 cpu
->gt_timer
[GTIMER_PHYS
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
530 arm_gt_ptimer_cb
, cpu
);
531 cpu
->gt_timer
[GTIMER_VIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
532 arm_gt_vtimer_cb
, cpu
);
533 cpu
->gt_timer
[GTIMER_HYP
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
534 arm_gt_htimer_cb
, cpu
);
535 cpu
->gt_timer
[GTIMER_SEC
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
536 arm_gt_stimer_cb
, cpu
);
537 qdev_init_gpio_out(DEVICE(cpu
), cpu
->gt_timer_outputs
,
538 ARRAY_SIZE(cpu
->gt_timer_outputs
));
540 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->gicv3_maintenance_interrupt
,
541 "gicv3-maintenance-interrupt", 1);
542 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->pmu_interrupt
,
546 /* DTB consumers generally don't in fact care what the 'compatible'
547 * string is, so always provide some string and trust that a hypothetical
548 * picky DTB consumer will also provide a helpful error message.
550 cpu
->dtb_compatible
= "qemu,unknown";
551 cpu
->psci_version
= 1; /* By default assume PSCI v0.1 */
552 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_NONE
;
555 cpu
->psci_version
= 2; /* TCG implements PSCI 0.2 */
558 arm_translate_init();
563 static Property arm_cpu_reset_cbar_property
=
564 DEFINE_PROP_UINT64("reset-cbar", ARMCPU
, reset_cbar
, 0);
566 static Property arm_cpu_reset_hivecs_property
=
567 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU
, reset_hivecs
, false);
569 static Property arm_cpu_rvbar_property
=
570 DEFINE_PROP_UINT64("rvbar", ARMCPU
, rvbar
, 0);
572 static Property arm_cpu_has_el2_property
=
573 DEFINE_PROP_BOOL("has_el2", ARMCPU
, has_el2
, true);
575 static Property arm_cpu_has_el3_property
=
576 DEFINE_PROP_BOOL("has_el3", ARMCPU
, has_el3
, true);
578 static Property arm_cpu_cfgend_property
=
579 DEFINE_PROP_BOOL("cfgend", ARMCPU
, cfgend
, false);
581 /* use property name "pmu" to match other archs and virt tools */
582 static Property arm_cpu_has_pmu_property
=
583 DEFINE_PROP_BOOL("pmu", ARMCPU
, has_pmu
, true);
585 static Property arm_cpu_has_mpu_property
=
586 DEFINE_PROP_BOOL("has-mpu", ARMCPU
, has_mpu
, true);
588 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
589 * because the CPU initfn will have already set cpu->pmsav7_dregion to
590 * the right value for that particular CPU type, and we don't want
591 * to override that with an incorrect constant value.
593 static Property arm_cpu_pmsav7_dregion_property
=
594 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU
,
596 qdev_prop_uint32
, uint32_t);
598 static void arm_cpu_post_init(Object
*obj
)
600 ARMCPU
*cpu
= ARM_CPU(obj
);
602 /* M profile implies PMSA. We have to do this here rather than
603 * in realize with the other feature-implication checks because
604 * we look at the PMSA bit to see if we should add some properties.
606 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
607 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
610 if (arm_feature(&cpu
->env
, ARM_FEATURE_CBAR
) ||
611 arm_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
)) {
612 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_cbar_property
,
616 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
617 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_hivecs_property
,
621 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
622 qdev_property_add_static(DEVICE(obj
), &arm_cpu_rvbar_property
,
626 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
627 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
628 * prevent "has_el3" from existing on CPUs which cannot support EL3.
630 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el3_property
,
633 #ifndef CONFIG_USER_ONLY
634 object_property_add_link(obj
, "secure-memory",
636 (Object
**)&cpu
->secure_memory
,
637 qdev_prop_allow_set_link_before_realize
,
638 OBJ_PROP_LINK_UNREF_ON_RELEASE
,
643 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
)) {
644 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el2_property
,
648 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMU
)) {
649 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_pmu_property
,
653 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMSA
)) {
654 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_mpu_property
,
656 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
657 qdev_property_add_static(DEVICE(obj
),
658 &arm_cpu_pmsav7_dregion_property
,
663 qdev_property_add_static(DEVICE(obj
), &arm_cpu_cfgend_property
,
667 static void arm_cpu_finalizefn(Object
*obj
)
669 ARMCPU
*cpu
= ARM_CPU(obj
);
670 g_hash_table_destroy(cpu
->cp_regs
);
673 static void arm_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
675 CPUState
*cs
= CPU(dev
);
676 ARMCPU
*cpu
= ARM_CPU(dev
);
677 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(dev
);
678 CPUARMState
*env
= &cpu
->env
;
680 Error
*local_err
= NULL
;
682 cpu_exec_realizefn(cs
, &local_err
);
683 if (local_err
!= NULL
) {
684 error_propagate(errp
, local_err
);
688 /* Some features automatically imply others: */
689 if (arm_feature(env
, ARM_FEATURE_V8
)) {
690 set_feature(env
, ARM_FEATURE_V7
);
691 set_feature(env
, ARM_FEATURE_ARM_DIV
);
692 set_feature(env
, ARM_FEATURE_LPAE
);
694 if (arm_feature(env
, ARM_FEATURE_V7
)) {
695 set_feature(env
, ARM_FEATURE_VAPA
);
696 set_feature(env
, ARM_FEATURE_THUMB2
);
697 set_feature(env
, ARM_FEATURE_MPIDR
);
698 if (!arm_feature(env
, ARM_FEATURE_M
)) {
699 set_feature(env
, ARM_FEATURE_V6K
);
701 set_feature(env
, ARM_FEATURE_V6
);
704 /* Always define VBAR for V7 CPUs even if it doesn't exist in
705 * non-EL3 configs. This is needed by some legacy boards.
707 set_feature(env
, ARM_FEATURE_VBAR
);
709 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
710 set_feature(env
, ARM_FEATURE_V6
);
711 set_feature(env
, ARM_FEATURE_MVFR
);
713 if (arm_feature(env
, ARM_FEATURE_V6
)) {
714 set_feature(env
, ARM_FEATURE_V5
);
715 if (!arm_feature(env
, ARM_FEATURE_M
)) {
716 set_feature(env
, ARM_FEATURE_AUXCR
);
719 if (arm_feature(env
, ARM_FEATURE_V5
)) {
720 set_feature(env
, ARM_FEATURE_V4T
);
722 if (arm_feature(env
, ARM_FEATURE_M
)) {
723 set_feature(env
, ARM_FEATURE_THUMB_DIV
);
725 if (arm_feature(env
, ARM_FEATURE_ARM_DIV
)) {
726 set_feature(env
, ARM_FEATURE_THUMB_DIV
);
728 if (arm_feature(env
, ARM_FEATURE_VFP4
)) {
729 set_feature(env
, ARM_FEATURE_VFP3
);
730 set_feature(env
, ARM_FEATURE_VFP_FP16
);
732 if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
733 set_feature(env
, ARM_FEATURE_VFP
);
735 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
736 set_feature(env
, ARM_FEATURE_V7MP
);
737 set_feature(env
, ARM_FEATURE_PXN
);
739 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
740 set_feature(env
, ARM_FEATURE_CBAR
);
742 if (arm_feature(env
, ARM_FEATURE_THUMB2
) &&
743 !arm_feature(env
, ARM_FEATURE_M
)) {
744 set_feature(env
, ARM_FEATURE_THUMB_DSP
);
747 if (arm_feature(env
, ARM_FEATURE_V7
) &&
748 !arm_feature(env
, ARM_FEATURE_M
) &&
749 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
750 /* v7VMSA drops support for the old ARMv5 tiny pages, so we
755 /* For CPUs which might have tiny 1K pages, or which have an
756 * MPU and might have small region sizes, stick with 1K pages.
760 if (!set_preferred_target_page_bits(pagebits
)) {
761 /* This can only ever happen for hotplugging a CPU, or if
762 * the board code incorrectly creates a CPU which it has
763 * promised via minimum_page_size that it will not.
765 error_setg(errp
, "This CPU requires a smaller page size than the "
770 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
771 * We don't support setting cluster ID ([16..23]) (known as Aff2
772 * in later ARM ARM versions), or any of the higher affinity level fields,
773 * so these bits always RAZ.
775 if (cpu
->mp_affinity
== ARM64_AFFINITY_INVALID
) {
776 cpu
->mp_affinity
= arm_cpu_mp_affinity(cs
->cpu_index
,
777 ARM_DEFAULT_CPUS_PER_CLUSTER
);
780 if (cpu
->reset_hivecs
) {
781 cpu
->reset_sctlr
|= (1 << 13);
785 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
786 cpu
->reset_sctlr
|= SCTLR_EE
;
788 cpu
->reset_sctlr
|= SCTLR_B
;
793 /* If the has_el3 CPU property is disabled then we need to disable the
796 unset_feature(env
, ARM_FEATURE_EL3
);
798 /* Disable the security extension feature bits in the processor feature
799 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
801 cpu
->id_pfr1
&= ~0xf0;
802 cpu
->id_aa64pfr0
&= ~0xf000;
806 unset_feature(env
, ARM_FEATURE_EL2
);
810 unset_feature(env
, ARM_FEATURE_PMU
);
811 cpu
->id_aa64dfr0
&= ~0xf00;
814 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
815 /* Disable the hypervisor feature bits in the processor feature
816 * registers if we don't have EL2. These are id_pfr1[15:12] and
817 * id_aa64pfr0_el1[11:8].
819 cpu
->id_aa64pfr0
&= ~0xf00;
820 cpu
->id_pfr1
&= ~0xf000;
823 /* MPU can be configured out of a PMSA CPU either by setting has-mpu
824 * to false or by setting pmsav7-dregion to 0.
827 cpu
->pmsav7_dregion
= 0;
829 if (cpu
->pmsav7_dregion
== 0) {
830 cpu
->has_mpu
= false;
833 if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
834 arm_feature(env
, ARM_FEATURE_V7
)) {
835 uint32_t nr
= cpu
->pmsav7_dregion
;
838 error_setg(errp
, "PMSAv7 MPU #regions invalid %" PRIu32
, nr
);
843 if (arm_feature(env
, ARM_FEATURE_V8
)) {
845 env
->pmsav8
.rbar
[M_REG_NS
] = g_new0(uint32_t, nr
);
846 env
->pmsav8
.rlar
[M_REG_NS
] = g_new0(uint32_t, nr
);
847 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
848 env
->pmsav8
.rbar
[M_REG_S
] = g_new0(uint32_t, nr
);
849 env
->pmsav8
.rlar
[M_REG_S
] = g_new0(uint32_t, nr
);
852 env
->pmsav7
.drbar
= g_new0(uint32_t, nr
);
853 env
->pmsav7
.drsr
= g_new0(uint32_t, nr
);
854 env
->pmsav7
.dracr
= g_new0(uint32_t, nr
);
859 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
860 set_feature(env
, ARM_FEATURE_VBAR
);
863 register_cp_regs_for_features(cpu
);
864 arm_cpu_register_gdb_regs_for_features(cpu
);
866 init_cpreg_list(cpu
);
868 #ifndef CONFIG_USER_ONLY
869 if (cpu
->has_el3
|| arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
874 if (!cpu
->secure_memory
) {
875 cpu
->secure_memory
= cs
->memory
;
877 as
= address_space_init_shareable(cpu
->secure_memory
,
878 "cpu-secure-memory");
879 cpu_address_space_init(cs
, as
, ARMASIdx_S
);
884 cpu_address_space_init(cs
,
885 address_space_init_shareable(cs
->memory
,
893 acc
->parent_realize(dev
, errp
);
896 static ObjectClass
*arm_cpu_class_by_name(const char *cpu_model
)
906 cpuname
= g_strsplit(cpu_model
, ",", 1);
907 typename
= g_strdup_printf("%s-" TYPE_ARM_CPU
, cpuname
[0]);
908 oc
= object_class_by_name(typename
);
911 if (!oc
|| !object_class_dynamic_cast(oc
, TYPE_ARM_CPU
) ||
912 object_class_is_abstract(oc
)) {
918 /* CPU models. These are not needed for the AArch64 linux-user build. */
919 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
921 static void arm926_initfn(Object
*obj
)
923 ARMCPU
*cpu
= ARM_CPU(obj
);
925 cpu
->dtb_compatible
= "arm,arm926";
926 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
927 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
928 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
929 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
930 cpu
->midr
= 0x41069265;
931 cpu
->reset_fpsid
= 0x41011090;
932 cpu
->ctr
= 0x1dd20d2;
933 cpu
->reset_sctlr
= 0x00090078;
936 static void arm946_initfn(Object
*obj
)
938 ARMCPU
*cpu
= ARM_CPU(obj
);
940 cpu
->dtb_compatible
= "arm,arm946";
941 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
942 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
943 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
944 cpu
->midr
= 0x41059461;
945 cpu
->ctr
= 0x0f004006;
946 cpu
->reset_sctlr
= 0x00000078;
949 static void arm1026_initfn(Object
*obj
)
951 ARMCPU
*cpu
= ARM_CPU(obj
);
953 cpu
->dtb_compatible
= "arm,arm1026";
954 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
955 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
956 set_feature(&cpu
->env
, ARM_FEATURE_AUXCR
);
957 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
958 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
959 cpu
->midr
= 0x4106a262;
960 cpu
->reset_fpsid
= 0x410110a0;
961 cpu
->ctr
= 0x1dd20d2;
962 cpu
->reset_sctlr
= 0x00090078;
963 cpu
->reset_auxcr
= 1;
965 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
966 ARMCPRegInfo ifar
= {
967 .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
969 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifar_ns
),
972 define_one_arm_cp_reg(cpu
, &ifar
);
976 static void arm1136_r2_initfn(Object
*obj
)
978 ARMCPU
*cpu
= ARM_CPU(obj
);
979 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
980 * older core than plain "arm1136". In particular this does not
981 * have the v6K features.
982 * These ID register values are correct for 1136 but may be wrong
983 * for 1136_r2 (in particular r0p2 does not actually implement most
984 * of the ID registers).
987 cpu
->dtb_compatible
= "arm,arm1136";
988 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
989 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
990 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
991 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
992 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
993 cpu
->midr
= 0x4107b362;
994 cpu
->reset_fpsid
= 0x410120b4;
995 cpu
->mvfr0
= 0x11111111;
996 cpu
->mvfr1
= 0x00000000;
997 cpu
->ctr
= 0x1dd20d2;
998 cpu
->reset_sctlr
= 0x00050078;
999 cpu
->id_pfr0
= 0x111;
1003 cpu
->id_mmfr0
= 0x01130003;
1004 cpu
->id_mmfr1
= 0x10030302;
1005 cpu
->id_mmfr2
= 0x01222110;
1006 cpu
->id_isar0
= 0x00140011;
1007 cpu
->id_isar1
= 0x12002111;
1008 cpu
->id_isar2
= 0x11231111;
1009 cpu
->id_isar3
= 0x01102131;
1010 cpu
->id_isar4
= 0x141;
1011 cpu
->reset_auxcr
= 7;
1014 static void arm1136_initfn(Object
*obj
)
1016 ARMCPU
*cpu
= ARM_CPU(obj
);
1018 cpu
->dtb_compatible
= "arm,arm1136";
1019 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
1020 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
1021 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1022 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1023 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
1024 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
1025 cpu
->midr
= 0x4117b363;
1026 cpu
->reset_fpsid
= 0x410120b4;
1027 cpu
->mvfr0
= 0x11111111;
1028 cpu
->mvfr1
= 0x00000000;
1029 cpu
->ctr
= 0x1dd20d2;
1030 cpu
->reset_sctlr
= 0x00050078;
1031 cpu
->id_pfr0
= 0x111;
1035 cpu
->id_mmfr0
= 0x01130003;
1036 cpu
->id_mmfr1
= 0x10030302;
1037 cpu
->id_mmfr2
= 0x01222110;
1038 cpu
->id_isar0
= 0x00140011;
1039 cpu
->id_isar1
= 0x12002111;
1040 cpu
->id_isar2
= 0x11231111;
1041 cpu
->id_isar3
= 0x01102131;
1042 cpu
->id_isar4
= 0x141;
1043 cpu
->reset_auxcr
= 7;
1046 static void arm1176_initfn(Object
*obj
)
1048 ARMCPU
*cpu
= ARM_CPU(obj
);
1050 cpu
->dtb_compatible
= "arm,arm1176";
1051 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
1052 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1053 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
1054 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1055 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
1056 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
1057 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1058 cpu
->midr
= 0x410fb767;
1059 cpu
->reset_fpsid
= 0x410120b5;
1060 cpu
->mvfr0
= 0x11111111;
1061 cpu
->mvfr1
= 0x00000000;
1062 cpu
->ctr
= 0x1dd20d2;
1063 cpu
->reset_sctlr
= 0x00050078;
1064 cpu
->id_pfr0
= 0x111;
1065 cpu
->id_pfr1
= 0x11;
1066 cpu
->id_dfr0
= 0x33;
1068 cpu
->id_mmfr0
= 0x01130003;
1069 cpu
->id_mmfr1
= 0x10030302;
1070 cpu
->id_mmfr2
= 0x01222100;
1071 cpu
->id_isar0
= 0x0140011;
1072 cpu
->id_isar1
= 0x12002111;
1073 cpu
->id_isar2
= 0x11231121;
1074 cpu
->id_isar3
= 0x01102131;
1075 cpu
->id_isar4
= 0x01141;
1076 cpu
->reset_auxcr
= 7;
1079 static void arm11mpcore_initfn(Object
*obj
)
1081 ARMCPU
*cpu
= ARM_CPU(obj
);
1083 cpu
->dtb_compatible
= "arm,arm11mpcore";
1084 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
1085 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1086 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
1087 set_feature(&cpu
->env
, ARM_FEATURE_MPIDR
);
1088 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1089 cpu
->midr
= 0x410fb022;
1090 cpu
->reset_fpsid
= 0x410120b4;
1091 cpu
->mvfr0
= 0x11111111;
1092 cpu
->mvfr1
= 0x00000000;
1093 cpu
->ctr
= 0x1d192992; /* 32K icache 32K dcache */
1094 cpu
->id_pfr0
= 0x111;
1098 cpu
->id_mmfr0
= 0x01100103;
1099 cpu
->id_mmfr1
= 0x10020302;
1100 cpu
->id_mmfr2
= 0x01222000;
1101 cpu
->id_isar0
= 0x00100011;
1102 cpu
->id_isar1
= 0x12002111;
1103 cpu
->id_isar2
= 0x11221011;
1104 cpu
->id_isar3
= 0x01102131;
1105 cpu
->id_isar4
= 0x141;
1106 cpu
->reset_auxcr
= 1;
1109 static void cortex_m3_initfn(Object
*obj
)
1111 ARMCPU
*cpu
= ARM_CPU(obj
);
1112 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1113 set_feature(&cpu
->env
, ARM_FEATURE_M
);
1114 cpu
->midr
= 0x410fc231;
1115 cpu
->pmsav7_dregion
= 8;
1118 static void cortex_m4_initfn(Object
*obj
)
1120 ARMCPU
*cpu
= ARM_CPU(obj
);
1122 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1123 set_feature(&cpu
->env
, ARM_FEATURE_M
);
1124 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
);
1125 cpu
->midr
= 0x410fc240; /* r0p0 */
1126 cpu
->pmsav7_dregion
= 8;
1128 static void arm_v7m_class_init(ObjectClass
*oc
, void *data
)
1130 CPUClass
*cc
= CPU_CLASS(oc
);
1132 #ifndef CONFIG_USER_ONLY
1133 cc
->do_interrupt
= arm_v7m_cpu_do_interrupt
;
1136 cc
->cpu_exec_interrupt
= arm_v7m_cpu_exec_interrupt
;
1139 static const ARMCPRegInfo cortexr5_cp_reginfo
[] = {
1140 /* Dummy the TCM region regs for the moment */
1141 { .name
= "ATCM", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
1142 .access
= PL1_RW
, .type
= ARM_CP_CONST
},
1143 { .name
= "BTCM", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
1144 .access
= PL1_RW
, .type
= ARM_CP_CONST
},
1145 { .name
= "DCACHE_INVAL", .cp
= 15, .opc1
= 0, .crn
= 15, .crm
= 5,
1146 .opc2
= 0, .access
= PL1_W
, .type
= ARM_CP_NOP
},
1150 static void cortex_r5_initfn(Object
*obj
)
1152 ARMCPU
*cpu
= ARM_CPU(obj
);
1154 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1155 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DIV
);
1156 set_feature(&cpu
->env
, ARM_FEATURE_ARM_DIV
);
1157 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
1158 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
1159 cpu
->midr
= 0x411fc153; /* r1p3 */
1160 cpu
->id_pfr0
= 0x0131;
1161 cpu
->id_pfr1
= 0x001;
1162 cpu
->id_dfr0
= 0x010400;
1164 cpu
->id_mmfr0
= 0x0210030;
1165 cpu
->id_mmfr1
= 0x00000000;
1166 cpu
->id_mmfr2
= 0x01200000;
1167 cpu
->id_mmfr3
= 0x0211;
1168 cpu
->id_isar0
= 0x2101111;
1169 cpu
->id_isar1
= 0x13112111;
1170 cpu
->id_isar2
= 0x21232141;
1171 cpu
->id_isar3
= 0x01112131;
1172 cpu
->id_isar4
= 0x0010142;
1173 cpu
->id_isar5
= 0x0;
1174 cpu
->mp_is_up
= true;
1175 cpu
->pmsav7_dregion
= 16;
1176 define_arm_cp_regs(cpu
, cortexr5_cp_reginfo
);
1179 static const ARMCPRegInfo cortexa8_cp_reginfo
[] = {
1180 { .name
= "L2LOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 0,
1181 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1182 { .name
= "L2AUXCR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
1183 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1187 static void cortex_a8_initfn(Object
*obj
)
1189 ARMCPU
*cpu
= ARM_CPU(obj
);
1191 cpu
->dtb_compatible
= "arm,cortex-a8";
1192 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1193 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
1194 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1195 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1196 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1197 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1198 cpu
->midr
= 0x410fc080;
1199 cpu
->reset_fpsid
= 0x410330c0;
1200 cpu
->mvfr0
= 0x11110222;
1201 cpu
->mvfr1
= 0x00011111;
1202 cpu
->ctr
= 0x82048004;
1203 cpu
->reset_sctlr
= 0x00c50078;
1204 cpu
->id_pfr0
= 0x1031;
1205 cpu
->id_pfr1
= 0x11;
1206 cpu
->id_dfr0
= 0x400;
1208 cpu
->id_mmfr0
= 0x31100003;
1209 cpu
->id_mmfr1
= 0x20000000;
1210 cpu
->id_mmfr2
= 0x01202000;
1211 cpu
->id_mmfr3
= 0x11;
1212 cpu
->id_isar0
= 0x00101111;
1213 cpu
->id_isar1
= 0x12112111;
1214 cpu
->id_isar2
= 0x21232031;
1215 cpu
->id_isar3
= 0x11112131;
1216 cpu
->id_isar4
= 0x00111142;
1217 cpu
->dbgdidr
= 0x15141000;
1218 cpu
->clidr
= (1 << 27) | (2 << 24) | 3;
1219 cpu
->ccsidr
[0] = 0xe007e01a; /* 16k L1 dcache. */
1220 cpu
->ccsidr
[1] = 0x2007e01a; /* 16k L1 icache. */
1221 cpu
->ccsidr
[2] = 0xf0000000; /* No L2 icache. */
1222 cpu
->reset_auxcr
= 2;
1223 define_arm_cp_regs(cpu
, cortexa8_cp_reginfo
);
1226 static const ARMCPRegInfo cortexa9_cp_reginfo
[] = {
1227 /* power_control should be set to maximum latency. Again,
1228 * default to 0 and set by private hook
1230 { .name
= "A9_PWRCTL", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
1231 .access
= PL1_RW
, .resetvalue
= 0,
1232 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_control
) },
1233 { .name
= "A9_DIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 1,
1234 .access
= PL1_RW
, .resetvalue
= 0,
1235 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_diagnostic
) },
1236 { .name
= "A9_PWRDIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 2,
1237 .access
= PL1_RW
, .resetvalue
= 0,
1238 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_diagnostic
) },
1239 { .name
= "NEONBUSY", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
1240 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1241 /* TLB lockdown control */
1242 { .name
= "TLB_LOCKR", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 2,
1243 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
1244 { .name
= "TLB_LOCKW", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 4,
1245 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
1246 { .name
= "TLB_VA", .cp
= 15, .crn
= 15, .crm
= 5, .opc1
= 5, .opc2
= 2,
1247 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1248 { .name
= "TLB_PA", .cp
= 15, .crn
= 15, .crm
= 6, .opc1
= 5, .opc2
= 2,
1249 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1250 { .name
= "TLB_ATTR", .cp
= 15, .crn
= 15, .crm
= 7, .opc1
= 5, .opc2
= 2,
1251 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1255 static void cortex_a9_initfn(Object
*obj
)
1257 ARMCPU
*cpu
= ARM_CPU(obj
);
1259 cpu
->dtb_compatible
= "arm,cortex-a9";
1260 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1261 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
1262 set_feature(&cpu
->env
, ARM_FEATURE_VFP_FP16
);
1263 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1264 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1265 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1266 /* Note that A9 supports the MP extensions even for
1267 * A9UP and single-core A9MP (which are both different
1268 * and valid configurations; we don't model A9UP).
1270 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
1271 set_feature(&cpu
->env
, ARM_FEATURE_CBAR
);
1272 cpu
->midr
= 0x410fc090;
1273 cpu
->reset_fpsid
= 0x41033090;
1274 cpu
->mvfr0
= 0x11110222;
1275 cpu
->mvfr1
= 0x01111111;
1276 cpu
->ctr
= 0x80038003;
1277 cpu
->reset_sctlr
= 0x00c50078;
1278 cpu
->id_pfr0
= 0x1031;
1279 cpu
->id_pfr1
= 0x11;
1280 cpu
->id_dfr0
= 0x000;
1282 cpu
->id_mmfr0
= 0x00100103;
1283 cpu
->id_mmfr1
= 0x20000000;
1284 cpu
->id_mmfr2
= 0x01230000;
1285 cpu
->id_mmfr3
= 0x00002111;
1286 cpu
->id_isar0
= 0x00101111;
1287 cpu
->id_isar1
= 0x13112111;
1288 cpu
->id_isar2
= 0x21232041;
1289 cpu
->id_isar3
= 0x11112131;
1290 cpu
->id_isar4
= 0x00111142;
1291 cpu
->dbgdidr
= 0x35141000;
1292 cpu
->clidr
= (1 << 27) | (1 << 24) | 3;
1293 cpu
->ccsidr
[0] = 0xe00fe019; /* 16k L1 dcache. */
1294 cpu
->ccsidr
[1] = 0x200fe019; /* 16k L1 icache. */
1295 define_arm_cp_regs(cpu
, cortexa9_cp_reginfo
);
1298 #ifndef CONFIG_USER_ONLY
1299 static uint64_t a15_l2ctlr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1301 /* Linux wants the number of processors from here.
1302 * Might as well set the interrupt-controller bit too.
1304 return ((smp_cpus
- 1) << 24) | (1 << 23);
1308 static const ARMCPRegInfo cortexa15_cp_reginfo
[] = {
1309 #ifndef CONFIG_USER_ONLY
1310 { .name
= "L2CTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
1311 .access
= PL1_RW
, .resetvalue
= 0, .readfn
= a15_l2ctlr_read
,
1312 .writefn
= arm_cp_write_ignore
, },
1314 { .name
= "L2ECTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 3,
1315 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1319 static void cortex_a7_initfn(Object
*obj
)
1321 ARMCPU
*cpu
= ARM_CPU(obj
);
1323 cpu
->dtb_compatible
= "arm,cortex-a7";
1324 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1325 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
1326 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1327 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1328 set_feature(&cpu
->env
, ARM_FEATURE_ARM_DIV
);
1329 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
1330 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1331 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
1332 set_feature(&cpu
->env
, ARM_FEATURE_LPAE
);
1333 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1334 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A7
;
1335 cpu
->midr
= 0x410fc075;
1336 cpu
->reset_fpsid
= 0x41023075;
1337 cpu
->mvfr0
= 0x10110222;
1338 cpu
->mvfr1
= 0x11111111;
1339 cpu
->ctr
= 0x84448003;
1340 cpu
->reset_sctlr
= 0x00c50078;
1341 cpu
->id_pfr0
= 0x00001131;
1342 cpu
->id_pfr1
= 0x00011011;
1343 cpu
->id_dfr0
= 0x02010555;
1344 cpu
->pmceid0
= 0x00000000;
1345 cpu
->pmceid1
= 0x00000000;
1346 cpu
->id_afr0
= 0x00000000;
1347 cpu
->id_mmfr0
= 0x10101105;
1348 cpu
->id_mmfr1
= 0x40000000;
1349 cpu
->id_mmfr2
= 0x01240000;
1350 cpu
->id_mmfr3
= 0x02102211;
1351 cpu
->id_isar0
= 0x01101110;
1352 cpu
->id_isar1
= 0x13112111;
1353 cpu
->id_isar2
= 0x21232041;
1354 cpu
->id_isar3
= 0x11112131;
1355 cpu
->id_isar4
= 0x10011142;
1356 cpu
->dbgdidr
= 0x3515f005;
1357 cpu
->clidr
= 0x0a200023;
1358 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
1359 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
1360 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
1361 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
); /* Same as A15 */
1364 static void cortex_a15_initfn(Object
*obj
)
1366 ARMCPU
*cpu
= ARM_CPU(obj
);
1368 cpu
->dtb_compatible
= "arm,cortex-a15";
1369 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1370 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
1371 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1372 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1373 set_feature(&cpu
->env
, ARM_FEATURE_ARM_DIV
);
1374 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
1375 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1376 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
1377 set_feature(&cpu
->env
, ARM_FEATURE_LPAE
);
1378 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1379 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A15
;
1380 cpu
->midr
= 0x412fc0f1;
1381 cpu
->reset_fpsid
= 0x410430f0;
1382 cpu
->mvfr0
= 0x10110222;
1383 cpu
->mvfr1
= 0x11111111;
1384 cpu
->ctr
= 0x8444c004;
1385 cpu
->reset_sctlr
= 0x00c50078;
1386 cpu
->id_pfr0
= 0x00001131;
1387 cpu
->id_pfr1
= 0x00011011;
1388 cpu
->id_dfr0
= 0x02010555;
1389 cpu
->pmceid0
= 0x0000000;
1390 cpu
->pmceid1
= 0x00000000;
1391 cpu
->id_afr0
= 0x00000000;
1392 cpu
->id_mmfr0
= 0x10201105;
1393 cpu
->id_mmfr1
= 0x20000000;
1394 cpu
->id_mmfr2
= 0x01240000;
1395 cpu
->id_mmfr3
= 0x02102211;
1396 cpu
->id_isar0
= 0x02101110;
1397 cpu
->id_isar1
= 0x13112111;
1398 cpu
->id_isar2
= 0x21232041;
1399 cpu
->id_isar3
= 0x11112131;
1400 cpu
->id_isar4
= 0x10011142;
1401 cpu
->dbgdidr
= 0x3515f021;
1402 cpu
->clidr
= 0x0a200023;
1403 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
1404 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
1405 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
1406 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
);
1409 static void ti925t_initfn(Object
*obj
)
1411 ARMCPU
*cpu
= ARM_CPU(obj
);
1412 set_feature(&cpu
->env
, ARM_FEATURE_V4T
);
1413 set_feature(&cpu
->env
, ARM_FEATURE_OMAPCP
);
1414 cpu
->midr
= ARM_CPUID_TI925T
;
1415 cpu
->ctr
= 0x5109149;
1416 cpu
->reset_sctlr
= 0x00000070;
1419 static void sa1100_initfn(Object
*obj
)
1421 ARMCPU
*cpu
= ARM_CPU(obj
);
1423 cpu
->dtb_compatible
= "intel,sa1100";
1424 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
1425 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1426 cpu
->midr
= 0x4401A11B;
1427 cpu
->reset_sctlr
= 0x00000070;
1430 static void sa1110_initfn(Object
*obj
)
1432 ARMCPU
*cpu
= ARM_CPU(obj
);
1433 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
1434 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1435 cpu
->midr
= 0x6901B119;
1436 cpu
->reset_sctlr
= 0x00000070;
1439 static void pxa250_initfn(Object
*obj
)
1441 ARMCPU
*cpu
= ARM_CPU(obj
);
1443 cpu
->dtb_compatible
= "marvell,xscale";
1444 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1445 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1446 cpu
->midr
= 0x69052100;
1447 cpu
->ctr
= 0xd172172;
1448 cpu
->reset_sctlr
= 0x00000078;
1451 static void pxa255_initfn(Object
*obj
)
1453 ARMCPU
*cpu
= ARM_CPU(obj
);
1455 cpu
->dtb_compatible
= "marvell,xscale";
1456 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1457 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1458 cpu
->midr
= 0x69052d00;
1459 cpu
->ctr
= 0xd172172;
1460 cpu
->reset_sctlr
= 0x00000078;
1463 static void pxa260_initfn(Object
*obj
)
1465 ARMCPU
*cpu
= ARM_CPU(obj
);
1467 cpu
->dtb_compatible
= "marvell,xscale";
1468 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1469 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1470 cpu
->midr
= 0x69052903;
1471 cpu
->ctr
= 0xd172172;
1472 cpu
->reset_sctlr
= 0x00000078;
1475 static void pxa261_initfn(Object
*obj
)
1477 ARMCPU
*cpu
= ARM_CPU(obj
);
1479 cpu
->dtb_compatible
= "marvell,xscale";
1480 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1481 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1482 cpu
->midr
= 0x69052d05;
1483 cpu
->ctr
= 0xd172172;
1484 cpu
->reset_sctlr
= 0x00000078;
1487 static void pxa262_initfn(Object
*obj
)
1489 ARMCPU
*cpu
= ARM_CPU(obj
);
1491 cpu
->dtb_compatible
= "marvell,xscale";
1492 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1493 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1494 cpu
->midr
= 0x69052d06;
1495 cpu
->ctr
= 0xd172172;
1496 cpu
->reset_sctlr
= 0x00000078;
1499 static void pxa270a0_initfn(Object
*obj
)
1501 ARMCPU
*cpu
= ARM_CPU(obj
);
1503 cpu
->dtb_compatible
= "marvell,xscale";
1504 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1505 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1506 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1507 cpu
->midr
= 0x69054110;
1508 cpu
->ctr
= 0xd172172;
1509 cpu
->reset_sctlr
= 0x00000078;
1512 static void pxa270a1_initfn(Object
*obj
)
1514 ARMCPU
*cpu
= ARM_CPU(obj
);
1516 cpu
->dtb_compatible
= "marvell,xscale";
1517 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1518 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1519 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1520 cpu
->midr
= 0x69054111;
1521 cpu
->ctr
= 0xd172172;
1522 cpu
->reset_sctlr
= 0x00000078;
1525 static void pxa270b0_initfn(Object
*obj
)
1527 ARMCPU
*cpu
= ARM_CPU(obj
);
1529 cpu
->dtb_compatible
= "marvell,xscale";
1530 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1531 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1532 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1533 cpu
->midr
= 0x69054112;
1534 cpu
->ctr
= 0xd172172;
1535 cpu
->reset_sctlr
= 0x00000078;
1538 static void pxa270b1_initfn(Object
*obj
)
1540 ARMCPU
*cpu
= ARM_CPU(obj
);
1542 cpu
->dtb_compatible
= "marvell,xscale";
1543 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1544 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1545 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1546 cpu
->midr
= 0x69054113;
1547 cpu
->ctr
= 0xd172172;
1548 cpu
->reset_sctlr
= 0x00000078;
1551 static void pxa270c0_initfn(Object
*obj
)
1553 ARMCPU
*cpu
= ARM_CPU(obj
);
1555 cpu
->dtb_compatible
= "marvell,xscale";
1556 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1557 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1558 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1559 cpu
->midr
= 0x69054114;
1560 cpu
->ctr
= 0xd172172;
1561 cpu
->reset_sctlr
= 0x00000078;
1564 static void pxa270c5_initfn(Object
*obj
)
1566 ARMCPU
*cpu
= ARM_CPU(obj
);
1568 cpu
->dtb_compatible
= "marvell,xscale";
1569 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1570 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1571 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1572 cpu
->midr
= 0x69054117;
1573 cpu
->ctr
= 0xd172172;
1574 cpu
->reset_sctlr
= 0x00000078;
1577 #ifdef CONFIG_USER_ONLY
1578 static void arm_any_initfn(Object
*obj
)
1580 ARMCPU
*cpu
= ARM_CPU(obj
);
1581 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
1582 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
1583 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1584 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1585 set_feature(&cpu
->env
, ARM_FEATURE_V8_AES
);
1586 set_feature(&cpu
->env
, ARM_FEATURE_V8_SHA1
);
1587 set_feature(&cpu
->env
, ARM_FEATURE_V8_SHA256
);
1588 set_feature(&cpu
->env
, ARM_FEATURE_V8_PMULL
);
1589 set_feature(&cpu
->env
, ARM_FEATURE_CRC
);
1590 cpu
->midr
= 0xffffffff;
1594 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1596 typedef struct ARMCPUInfo
{
1598 void (*initfn
)(Object
*obj
);
1599 void (*class_init
)(ObjectClass
*oc
, void *data
);
1602 static const ARMCPUInfo arm_cpus
[] = {
1603 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1604 { .name
= "arm926", .initfn
= arm926_initfn
},
1605 { .name
= "arm946", .initfn
= arm946_initfn
},
1606 { .name
= "arm1026", .initfn
= arm1026_initfn
},
1607 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1608 * older core than plain "arm1136". In particular this does not
1609 * have the v6K features.
1611 { .name
= "arm1136-r2", .initfn
= arm1136_r2_initfn
},
1612 { .name
= "arm1136", .initfn
= arm1136_initfn
},
1613 { .name
= "arm1176", .initfn
= arm1176_initfn
},
1614 { .name
= "arm11mpcore", .initfn
= arm11mpcore_initfn
},
1615 { .name
= "cortex-m3", .initfn
= cortex_m3_initfn
,
1616 .class_init
= arm_v7m_class_init
},
1617 { .name
= "cortex-m4", .initfn
= cortex_m4_initfn
,
1618 .class_init
= arm_v7m_class_init
},
1619 { .name
= "cortex-r5", .initfn
= cortex_r5_initfn
},
1620 { .name
= "cortex-a7", .initfn
= cortex_a7_initfn
},
1621 { .name
= "cortex-a8", .initfn
= cortex_a8_initfn
},
1622 { .name
= "cortex-a9", .initfn
= cortex_a9_initfn
},
1623 { .name
= "cortex-a15", .initfn
= cortex_a15_initfn
},
1624 { .name
= "ti925t", .initfn
= ti925t_initfn
},
1625 { .name
= "sa1100", .initfn
= sa1100_initfn
},
1626 { .name
= "sa1110", .initfn
= sa1110_initfn
},
1627 { .name
= "pxa250", .initfn
= pxa250_initfn
},
1628 { .name
= "pxa255", .initfn
= pxa255_initfn
},
1629 { .name
= "pxa260", .initfn
= pxa260_initfn
},
1630 { .name
= "pxa261", .initfn
= pxa261_initfn
},
1631 { .name
= "pxa262", .initfn
= pxa262_initfn
},
1632 /* "pxa270" is an alias for "pxa270-a0" */
1633 { .name
= "pxa270", .initfn
= pxa270a0_initfn
},
1634 { .name
= "pxa270-a0", .initfn
= pxa270a0_initfn
},
1635 { .name
= "pxa270-a1", .initfn
= pxa270a1_initfn
},
1636 { .name
= "pxa270-b0", .initfn
= pxa270b0_initfn
},
1637 { .name
= "pxa270-b1", .initfn
= pxa270b1_initfn
},
1638 { .name
= "pxa270-c0", .initfn
= pxa270c0_initfn
},
1639 { .name
= "pxa270-c5", .initfn
= pxa270c5_initfn
},
1640 #ifdef CONFIG_USER_ONLY
1641 { .name
= "any", .initfn
= arm_any_initfn
},
1647 static Property arm_cpu_properties
[] = {
1648 DEFINE_PROP_BOOL("start-powered-off", ARMCPU
, start_powered_off
, false),
1649 DEFINE_PROP_UINT32("psci-conduit", ARMCPU
, psci_conduit
, 0),
1650 DEFINE_PROP_UINT32("midr", ARMCPU
, midr
, 0),
1651 DEFINE_PROP_UINT64("mp-affinity", ARMCPU
,
1652 mp_affinity
, ARM64_AFFINITY_INVALID
),
1653 DEFINE_PROP_INT32("node-id", ARMCPU
, node_id
, CPU_UNSET_NUMA_NODE_ID
),
1654 DEFINE_PROP_END_OF_LIST()
1657 #ifdef CONFIG_USER_ONLY
1658 static int arm_cpu_handle_mmu_fault(CPUState
*cs
, vaddr address
, int rw
,
1661 ARMCPU
*cpu
= ARM_CPU(cs
);
1662 CPUARMState
*env
= &cpu
->env
;
1664 env
->exception
.vaddress
= address
;
1666 cs
->exception_index
= EXCP_PREFETCH_ABORT
;
1668 cs
->exception_index
= EXCP_DATA_ABORT
;
1674 static gchar
*arm_gdb_arch_name(CPUState
*cs
)
1676 ARMCPU
*cpu
= ARM_CPU(cs
);
1677 CPUARMState
*env
= &cpu
->env
;
1679 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
1680 return g_strdup("iwmmxt");
1682 return g_strdup("arm");
1685 static void arm_cpu_class_init(ObjectClass
*oc
, void *data
)
1687 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
1688 CPUClass
*cc
= CPU_CLASS(acc
);
1689 DeviceClass
*dc
= DEVICE_CLASS(oc
);
1691 acc
->parent_realize
= dc
->realize
;
1692 dc
->realize
= arm_cpu_realizefn
;
1693 dc
->props
= arm_cpu_properties
;
1695 acc
->parent_reset
= cc
->reset
;
1696 cc
->reset
= arm_cpu_reset
;
1698 cc
->class_by_name
= arm_cpu_class_by_name
;
1699 cc
->has_work
= arm_cpu_has_work
;
1700 cc
->cpu_exec_interrupt
= arm_cpu_exec_interrupt
;
1701 cc
->dump_state
= arm_cpu_dump_state
;
1702 cc
->set_pc
= arm_cpu_set_pc
;
1703 cc
->gdb_read_register
= arm_cpu_gdb_read_register
;
1704 cc
->gdb_write_register
= arm_cpu_gdb_write_register
;
1705 #ifdef CONFIG_USER_ONLY
1706 cc
->handle_mmu_fault
= arm_cpu_handle_mmu_fault
;
1708 cc
->do_interrupt
= arm_cpu_do_interrupt
;
1709 cc
->do_unaligned_access
= arm_cpu_do_unaligned_access
;
1710 cc
->get_phys_page_attrs_debug
= arm_cpu_get_phys_page_attrs_debug
;
1711 cc
->asidx_from_attrs
= arm_asidx_from_attrs
;
1712 cc
->vmsd
= &vmstate_arm_cpu
;
1713 cc
->virtio_is_big_endian
= arm_cpu_virtio_is_big_endian
;
1714 cc
->write_elf64_note
= arm_cpu_write_elf64_note
;
1715 cc
->write_elf32_note
= arm_cpu_write_elf32_note
;
1717 cc
->gdb_num_core_regs
= 26;
1718 cc
->gdb_core_xml_file
= "arm-core.xml";
1719 cc
->gdb_arch_name
= arm_gdb_arch_name
;
1720 cc
->gdb_stop_before_watchpoint
= true;
1721 cc
->debug_excp_handler
= arm_debug_excp_handler
;
1722 cc
->debug_check_watchpoint
= arm_debug_check_watchpoint
;
1723 #if !defined(CONFIG_USER_ONLY)
1724 cc
->adjust_watchpoint_address
= arm_adjust_watchpoint_address
;
1727 cc
->disas_set_info
= arm_disas_set_info
;
1730 static void cpu_register(const ARMCPUInfo
*info
)
1732 TypeInfo type_info
= {
1733 .parent
= TYPE_ARM_CPU
,
1734 .instance_size
= sizeof(ARMCPU
),
1735 .instance_init
= info
->initfn
,
1736 .class_size
= sizeof(ARMCPUClass
),
1737 .class_init
= info
->class_init
,
1740 type_info
.name
= g_strdup_printf("%s-" TYPE_ARM_CPU
, info
->name
);
1741 type_register(&type_info
);
1742 g_free((void *)type_info
.name
);
1745 static const TypeInfo arm_cpu_type_info
= {
1746 .name
= TYPE_ARM_CPU
,
1748 .instance_size
= sizeof(ARMCPU
),
1749 .instance_init
= arm_cpu_initfn
,
1750 .instance_post_init
= arm_cpu_post_init
,
1751 .instance_finalize
= arm_cpu_finalizefn
,
1753 .class_size
= sizeof(ARMCPUClass
),
1754 .class_init
= arm_cpu_class_init
,
1757 static void arm_cpu_register_types(void)
1759 const ARMCPUInfo
*info
= arm_cpus
;
1761 type_register_static(&arm_cpu_type_info
);
1763 while (info
->name
) {
1769 type_init(arm_cpu_register_types
)