target-ppc/excp_helper.c

   1 /*
   2  *  PowerPC exception emulation helpers for QEMU.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "qemu/osdep.h"
  20 #include "cpu.h"
  21 #include "exec/helper-proto.h"
  22 #include "exec/exec-all.h"
  23 #include "exec/cpu_ldst.h"
  24
  25 #include "helper_regs.h"
  26
  27 //#define DEBUG_OP
  28 //#define DEBUG_SOFTWARE_TLB
  29 //#define DEBUG_EXCEPTIONS
  30
  31 #ifdef DEBUG_EXCEPTIONS
  32 #  define LOG_EXCP(...) qemu_log(__VA_ARGS__)
  33 #else
  34 #  define LOG_EXCP(...) do { } while (0)
  35 #endif
  36
  37 /*****************************************************************************/
  38 /* PowerPC Hypercall emulation */
  39
  40 void (*cpu_ppc_hypercall)(PowerPCCPU *);
  41
  42 /*****************************************************************************/
  43 /* Exception processing */
  44 #if defined(CONFIG_USER_ONLY)
  45 void ppc_cpu_do_interrupt(CPUState *cs)
  46 {
  47     PowerPCCPU *cpu = POWERPC_CPU(cs);
  48     CPUPPCState *env = &cpu->env;
  49
  50     cs->exception_index = POWERPC_EXCP_NONE;
  51     env->error_code = 0;
  52 }
  53
  54 static void ppc_hw_interrupt(CPUPPCState *env)
  55 {
  56     CPUState *cs = CPU(ppc_env_get_cpu(env));
  57
  58     cs->exception_index = POWERPC_EXCP_NONE;
  59     env->error_code = 0;
  60 }
  61 #else /* defined(CONFIG_USER_ONLY) */
  62 static inline void dump_syscall(CPUPPCState *env)
  63 {
  64     qemu_log_mask(CPU_LOG_INT, "syscall r0=%016" PRIx64 " r3=%016" PRIx64
  65                   " r4=%016" PRIx64 " r5=%016" PRIx64 " r6=%016" PRIx64
  66                   " nip=" TARGET_FMT_lx "\n",
  67                   ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3),
  68                   ppc_dump_gpr(env, 4), ppc_dump_gpr(env, 5),
  69                   ppc_dump_gpr(env, 6), env->nip);
  70 }
  71
  72 /* Note that this function should be greatly optimized
  73  * when called with a constant excp, from ppc_hw_interrupt
  74  */
  75 static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
  76 {
  77     CPUState *cs = CPU(cpu);
  78     CPUPPCState *env = &cpu->env;
  79     target_ulong msr, new_msr, vector;
  80     int srr0, srr1, asrr0, asrr1, lev, ail;
  81     bool lpes0;
  82
  83     qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
  84                   " => %08x (%02x)\n", env->nip, excp, env->error_code);
  85
  86     /* new srr1 value excluding must-be-zero bits */
  87     if (excp_model == POWERPC_EXCP_BOOKE) {
  88         msr = env->msr;
  89     } else {
  90         msr = env->msr & ~0x783f0000ULL;
  91     }
  92
  93     /* new interrupt handler msr preserves existing HV and ME unless
  94      * explicitly overriden
  95      */
  96     new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB);
  97
  98     /* target registers */
  99     srr0 = SPR_SRR0;
 100     srr1 = SPR_SRR1;
 101     asrr0 = -1;
 102     asrr1 = -1;
 103
 104     /* check for special resume at 0x100 from doze/nap/sleep/winkle on P7/P8 */
 105     if (env->in_pm_state) {
 106         env->in_pm_state = false;
 107
 108         /* Pretend to be returning from doze always as we don't lose state */
 109         msr |= (0x1ull << (63 - 47));
 110
 111         /* Non-machine check are routed to 0x100 with a wakeup cause
 112          * encoded in SRR1
 113          */
 114         if (excp != POWERPC_EXCP_MCHECK) {
 115             switch (excp) {
 116             case POWERPC_EXCP_RESET:
 117                 msr |= 0x4ull << (63 - 45);
 118                 break;
 119             case POWERPC_EXCP_EXTERNAL:
 120                 msr |= 0x8ull << (63 - 45);
 121                 break;
 122             case POWERPC_EXCP_DECR:
 123                 msr |= 0x6ull << (63 - 45);
 124                 break;
 125             case POWERPC_EXCP_SDOOR:
 126                 msr |= 0x5ull << (63 - 45);
 127                 break;
 128             case POWERPC_EXCP_SDOOR_HV:
 129                 msr |= 0x3ull << (63 - 45);
 130                 break;
 131             case POWERPC_EXCP_HV_MAINT:
 132                 msr |= 0xaull << (63 - 45);
 133                 break;
 134             default:
 135                 cpu_abort(cs, "Unsupported exception %d in Power Save mode\n",
 136                           excp);
 137             }
 138             excp = POWERPC_EXCP_RESET;
 139         }
 140     }
 141
 142     /* Exception targetting modifiers
 143      *
 144      * LPES0 is supported on POWER7/8
 145      * LPES1 is not supported (old iSeries mode)
 146      *
 147      * On anything else, we behave as if LPES0 is 1
 148      * (externals don't alter MSR:HV)
 149      *
 150      * AIL is initialized here but can be cleared by
 151      * selected exceptions
 152      */
 153 #if defined(TARGET_PPC64)
 154     if (excp_model == POWERPC_EXCP_POWER7 ||
 155         excp_model == POWERPC_EXCP_POWER8) {
 156         lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
 157         if (excp_model == POWERPC_EXCP_POWER8) {
 158             ail = (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT;
 159         } else {
 160             ail = 0;
 161         }
 162     } else
 163 #endif /* defined(TARGET_PPC64) */
 164     {
 165         lpes0 = true;
 166         ail = 0;
 167     }
 168
 169     /* Hypervisor emulation assistance interrupt only exists on server
 170      * arch 2.05 server or later. We also don't want to generate it if
 171      * we don't have HVB in msr_mask (PAPR mode).
 172      */
 173     if (excp == POWERPC_EXCP_HV_EMU
 174 #if defined(TARGET_PPC64)
 175         && !((env->mmu_model & POWERPC_MMU_64) && (env->msr_mask & MSR_HVB))
 176 #endif /* defined(TARGET_PPC64) */
 177
 178     ) {
 179         excp = POWERPC_EXCP_PROGRAM;
 180     }
 181
 182     switch (excp) {
 183     case POWERPC_EXCP_NONE:
 184         /* Should never happen */
 185         return;
 186     case POWERPC_EXCP_CRITICAL:    /* Critical input                         */
 187         switch (excp_model) {
 188         case POWERPC_EXCP_40x:
 189             srr0 = SPR_40x_SRR2;
 190             srr1 = SPR_40x_SRR3;
 191             break;
 192         case POWERPC_EXCP_BOOKE:
 193             srr0 = SPR_BOOKE_CSRR0;
 194             srr1 = SPR_BOOKE_CSRR1;
 195             break;
 196         case POWERPC_EXCP_G2:
 197             break;
 198         default:
 199             goto excp_invalid;
 200         }
 201         goto store_next;
 202     case POWERPC_EXCP_MCHECK:    /* Machine check exception                  */
 203         if (msr_me == 0) {
 204             /* Machine check exception is not enabled.
 205              * Enter checkstop state.
 206              */
 207             fprintf(stderr, "Machine check while not allowed. "
 208                     "Entering checkstop state\n");
 209             if (qemu_log_separate()) {
 210                 qemu_log("Machine check while not allowed. "
 211                         "Entering checkstop state\n");
 212             }
 213             cs->halted = 1;
 214             cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
 215         }
 216         new_msr |= (target_ulong)MSR_HVB;
 217         ail = 0;
 218
 219         /* machine check exceptions don't have ME set */
 220         new_msr &= ~((target_ulong)1 << MSR_ME);
 221
 222         /* XXX: should also have something loaded in DAR / DSISR */
 223         switch (excp_model) {
 224         case POWERPC_EXCP_40x:
 225             srr0 = SPR_40x_SRR2;
 226             srr1 = SPR_40x_SRR3;
 227             break;
 228         case POWERPC_EXCP_BOOKE:
 229             /* FIXME: choose one or the other based on CPU type */
 230             srr0 = SPR_BOOKE_MCSRR0;
 231             srr1 = SPR_BOOKE_MCSRR1;
 232             asrr0 = SPR_BOOKE_CSRR0;
 233             asrr1 = SPR_BOOKE_CSRR1;
 234             break;
 235         default:
 236             break;
 237         }
 238         goto store_next;
 239     case POWERPC_EXCP_DSI:       /* Data storage exception                   */
 240         LOG_EXCP("DSI exception: DSISR=" TARGET_FMT_lx" DAR=" TARGET_FMT_lx
 241                  "\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
 242         goto store_next;
 243     case POWERPC_EXCP_ISI:       /* Instruction storage exception            */
 244         LOG_EXCP("ISI exception: msr=" TARGET_FMT_lx ", nip=" TARGET_FMT_lx
 245                  "\n", msr, env->nip);
 246         msr |= env->error_code;
 247         goto store_next;
 248     case POWERPC_EXCP_EXTERNAL:  /* External input                           */
 249         cs = CPU(cpu);
 250
 251         if (!lpes0) {
 252             new_msr |= (target_ulong)MSR_HVB;
 253             new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
 254             srr0 = SPR_HSRR0;
 255             srr1 = SPR_HSRR1;
 256         }
 257         if (env->mpic_proxy) {
 258             /* IACK the IRQ on delivery */
 259             env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
 260         }
 261         goto store_next;
 262     case POWERPC_EXCP_ALIGN:     /* Alignment exception                      */
 263         /* XXX: this is false */
 264         /* Get rS/rD and rA from faulting opcode */
 265         env->spr[SPR_DSISR] |= (cpu_ldl_code(env, (env->nip - 4))
 266                                 & 0x03FF0000) >> 16;
 267         goto store_next;
 268     case POWERPC_EXCP_PROGRAM:   /* Program exception                        */
 269         switch (env->error_code & ~0xF) {
 270         case POWERPC_EXCP_FP:
 271             if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
 272                 LOG_EXCP("Ignore floating point exception\n");
 273                 cs->exception_index = POWERPC_EXCP_NONE;
 274                 env->error_code = 0;
 275                 return;
 276             }
 277             msr |= 0x00100000;
 278             if (msr_fe0 == msr_fe1) {
 279                 goto store_next;
 280             }
 281             msr |= 0x00010000;
 282             break;
 283         case POWERPC_EXCP_INVAL:
 284             LOG_EXCP("Invalid instruction at " TARGET_FMT_lx "\n", env->nip);
 285             msr |= 0x00080000;
 286             env->spr[SPR_BOOKE_ESR] = ESR_PIL;
 287             break;
 288         case POWERPC_EXCP_PRIV:
 289             msr |= 0x00040000;
 290             env->spr[SPR_BOOKE_ESR] = ESR_PPR;
 291             break;
 292         case POWERPC_EXCP_TRAP:
 293             msr |= 0x00020000;
 294             env->spr[SPR_BOOKE_ESR] = ESR_PTR;
 295             break;
 296         default:
 297             /* Should never occur */
 298             cpu_abort(cs, "Invalid program exception %d. Aborting\n",
 299                       env->error_code);
 300             break;
 301         }
 302         goto store_current;
 303     case POWERPC_EXCP_HV_EMU:
 304         srr0 = SPR_HSRR0;
 305         srr1 = SPR_HSRR1;
 306         new_msr |= (target_ulong)MSR_HVB;
 307         new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
 308         goto store_current;
 309     case POWERPC_EXCP_FPU:       /* Floating-point unavailable exception     */
 310         goto store_current;
 311     case POWERPC_EXCP_SYSCALL:   /* System call exception                    */
 312         dump_syscall(env);
 313         lev = env->error_code;
 314
 315         /* "PAPR mode" built-in hypercall emulation */
 316         if ((lev == 1) && cpu_ppc_hypercall) {
 317             cpu_ppc_hypercall(cpu);
 318             return;
 319         }
 320         if (lev == 1) {
 321             new_msr |= (target_ulong)MSR_HVB;
 322         }
 323         goto store_next;
 324     case POWERPC_EXCP_APU:       /* Auxiliary processor unavailable          */
 325         goto store_current;
 326     case POWERPC_EXCP_DECR:      /* Decrementer exception                    */
 327         goto store_next;
 328     case POWERPC_EXCP_FIT:       /* Fixed-interval timer interrupt           */
 329         /* FIT on 4xx */
 330         LOG_EXCP("FIT exception\n");
 331         goto store_next;
 332     case POWERPC_EXCP_WDT:       /* Watchdog timer interrupt                 */
 333         LOG_EXCP("WDT exception\n");
 334         switch (excp_model) {
 335         case POWERPC_EXCP_BOOKE:
 336             srr0 = SPR_BOOKE_CSRR0;
 337             srr1 = SPR_BOOKE_CSRR1;
 338             break;
 339         default:
 340             break;
 341         }
 342         goto store_next;
 343     case POWERPC_EXCP_DTLB:      /* Data TLB error                           */
 344         goto store_next;
 345     case POWERPC_EXCP_ITLB:      /* Instruction TLB error                    */
 346         goto store_next;
 347     case POWERPC_EXCP_DEBUG:     /* Debug interrupt                          */
 348         switch (excp_model) {
 349         case POWERPC_EXCP_BOOKE:
 350             /* FIXME: choose one or the other based on CPU type */
 351             srr0 = SPR_BOOKE_DSRR0;
 352             srr1 = SPR_BOOKE_DSRR1;
 353             asrr0 = SPR_BOOKE_CSRR0;
 354             asrr1 = SPR_BOOKE_CSRR1;
 355             break;
 356         default:
 357             break;
 358         }
 359         /* XXX: TODO */
 360         cpu_abort(cs, "Debug exception is not implemented yet !\n");
 361         goto store_next;
 362     case POWERPC_EXCP_SPEU:      /* SPE/embedded floating-point unavailable  */
 363         env->spr[SPR_BOOKE_ESR] = ESR_SPV;
 364         goto store_current;
 365     case POWERPC_EXCP_EFPDI:     /* Embedded floating-point data interrupt   */
 366         /* XXX: TODO */
 367         cpu_abort(cs, "Embedded floating point data exception "
 368                   "is not implemented yet !\n");
 369         env->spr[SPR_BOOKE_ESR] = ESR_SPV;
 370         goto store_next;
 371     case POWERPC_EXCP_EFPRI:     /* Embedded floating-point round interrupt  */
 372         /* XXX: TODO */
 373         cpu_abort(cs, "Embedded floating point round exception "
 374                   "is not implemented yet !\n");
 375         env->spr[SPR_BOOKE_ESR] = ESR_SPV;
 376         goto store_next;
 377     case POWERPC_EXCP_EPERFM:    /* Embedded performance monitor interrupt   */
 378         /* XXX: TODO */
 379         cpu_abort(cs,
 380                   "Performance counter exception is not implemented yet !\n");
 381         goto store_next;
 382     case POWERPC_EXCP_DOORI:     /* Embedded doorbell interrupt              */
 383         goto store_next;
 384     case POWERPC_EXCP_DOORCI:    /* Embedded doorbell critical interrupt     */
 385         srr0 = SPR_BOOKE_CSRR0;
 386         srr1 = SPR_BOOKE_CSRR1;
 387         goto store_next;
 388     case POWERPC_EXCP_RESET:     /* System reset exception                   */
 389         if (msr_pow) {
 390             /* indicate that we resumed from power save mode */
 391             msr |= 0x10000;
 392         } else {
 393             new_msr &= ~((target_ulong)1 << MSR_ME);
 394         }
 395
 396         new_msr |= (target_ulong)MSR_HVB;
 397         ail = 0;
 398         goto store_next;
 399     case POWERPC_EXCP_DSEG:      /* Data segment exception                   */
 400         goto store_next;
 401     case POWERPC_EXCP_ISEG:      /* Instruction segment exception            */
 402         goto store_next;
 403     case POWERPC_EXCP_HDECR:     /* Hypervisor decrementer exception         */
 404         srr0 = SPR_HSRR0;
 405         srr1 = SPR_HSRR1;
 406         new_msr |= (target_ulong)MSR_HVB;
 407         new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
 408         goto store_next;
 409     case POWERPC_EXCP_TRACE:     /* Trace exception                          */
 410         goto store_next;
 411     case POWERPC_EXCP_HDSI:      /* Hypervisor data storage exception        */
 412         srr0 = SPR_HSRR0;
 413         srr1 = SPR_HSRR1;
 414         new_msr |= (target_ulong)MSR_HVB;
 415         new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
 416         goto store_next;
 417     case POWERPC_EXCP_HISI:      /* Hypervisor instruction storage exception */
 418         srr0 = SPR_HSRR0;
 419         srr1 = SPR_HSRR1;
 420         new_msr |= (target_ulong)MSR_HVB;
 421         new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
 422         goto store_next;
 423     case POWERPC_EXCP_HDSEG:     /* Hypervisor data segment exception        */
 424         srr0 = SPR_HSRR0;
 425         srr1 = SPR_HSRR1;
 426         new_msr |= (target_ulong)MSR_HVB;
 427         new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
 428         goto store_next;
 429     case POWERPC_EXCP_HISEG:     /* Hypervisor instruction segment exception */
 430         srr0 = SPR_HSRR0;
 431         srr1 = SPR_HSRR1;
 432         new_msr |= (target_ulong)MSR_HVB;
 433         new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
 434         goto store_next;
 435     case POWERPC_EXCP_VPU:       /* Vector unavailable exception             */
 436         goto store_current;
 437     case POWERPC_EXCP_VSXU:       /* VSX unavailable exception               */
 438         goto store_current;
 439     case POWERPC_EXCP_FU:         /* Facility unavailable exception          */
 440         goto store_current;
 441     case POWERPC_EXCP_PIT:       /* Programmable interval timer interrupt    */
 442         LOG_EXCP("PIT exception\n");
 443         goto store_next;
 444     case POWERPC_EXCP_IO:        /* IO error exception                       */
 445         /* XXX: TODO */
 446         cpu_abort(cs, "601 IO error exception is not implemented yet !\n");
 447         goto store_next;
 448     case POWERPC_EXCP_RUNM:      /* Run mode exception                       */
 449         /* XXX: TODO */
 450         cpu_abort(cs, "601 run mode exception is not implemented yet !\n");
 451         goto store_next;
 452     case POWERPC_EXCP_EMUL:      /* Emulation trap exception                 */
 453         /* XXX: TODO */
 454         cpu_abort(cs, "602 emulation trap exception "
 455                   "is not implemented yet !\n");
 456         goto store_next;
 457     case POWERPC_EXCP_IFTLB:     /* Instruction fetch TLB error              */
 458         switch (excp_model) {
 459         case POWERPC_EXCP_602:
 460         case POWERPC_EXCP_603:
 461         case POWERPC_EXCP_603E:
 462         case POWERPC_EXCP_G2:
 463             goto tlb_miss_tgpr;
 464         case POWERPC_EXCP_7x5:
 465             goto tlb_miss;
 466         case POWERPC_EXCP_74xx:
 467             goto tlb_miss_74xx;
 468         default:
 469             cpu_abort(cs, "Invalid instruction TLB miss exception\n");
 470             break;
 471         }
 472         break;
 473     case POWERPC_EXCP_DLTLB:     /* Data load TLB miss                       */
 474         switch (excp_model) {
 475         case POWERPC_EXCP_602:
 476         case POWERPC_EXCP_603:
 477         case POWERPC_EXCP_603E:
 478         case POWERPC_EXCP_G2:
 479             goto tlb_miss_tgpr;
 480         case POWERPC_EXCP_7x5:
 481             goto tlb_miss;
 482         case POWERPC_EXCP_74xx:
 483             goto tlb_miss_74xx;
 484         default:
 485             cpu_abort(cs, "Invalid data load TLB miss exception\n");
 486             break;
 487         }
 488         break;
 489     case POWERPC_EXCP_DSTLB:     /* Data store TLB miss                      */
 490         switch (excp_model) {
 491         case POWERPC_EXCP_602:
 492         case POWERPC_EXCP_603:
 493         case POWERPC_EXCP_603E:
 494         case POWERPC_EXCP_G2:
 495         tlb_miss_tgpr:
 496             /* Swap temporary saved registers with GPRs */
 497             if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
 498                 new_msr |= (target_ulong)1 << MSR_TGPR;
 499                 hreg_swap_gpr_tgpr(env);
 500             }
 501             goto tlb_miss;
 502         case POWERPC_EXCP_7x5:
 503         tlb_miss:
 504 #if defined(DEBUG_SOFTWARE_TLB)
 505             if (qemu_log_enabled()) {
 506                 const char *es;
 507                 target_ulong *miss, *cmp;
 508                 int en;
 509
 510                 if (excp == POWERPC_EXCP_IFTLB) {
 511                     es = "I";
 512                     en = 'I';
 513                     miss = &env->spr[SPR_IMISS];
 514                     cmp = &env->spr[SPR_ICMP];
 515                 } else {
 516                     if (excp == POWERPC_EXCP_DLTLB) {
 517                         es = "DL";
 518                     } else {
 519                         es = "DS";
 520                     }
 521                     en = 'D';
 522                     miss = &env->spr[SPR_DMISS];
 523                     cmp = &env->spr[SPR_DCMP];
 524                 }
 525                 qemu_log("6xx %sTLB miss: %cM " TARGET_FMT_lx " %cC "
 526                          TARGET_FMT_lx " H1 " TARGET_FMT_lx " H2 "
 527                          TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp,
 528                          env->spr[SPR_HASH1], env->spr[SPR_HASH2],
 529                          env->error_code);
 530             }
 531 #endif
 532             msr |= env->crf[0] << 28;
 533             msr |= env->error_code; /* key, D/I, S/L bits */
 534             /* Set way using a LRU mechanism */
 535             msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
 536             break;
 537         case POWERPC_EXCP_74xx:
 538         tlb_miss_74xx:
 539 #if defined(DEBUG_SOFTWARE_TLB)
 540             if (qemu_log_enabled()) {
 541                 const char *es;
 542                 target_ulong *miss, *cmp;
 543                 int en;
 544
 545                 if (excp == POWERPC_EXCP_IFTLB) {
 546                     es = "I";
 547                     en = 'I';
 548                     miss = &env->spr[SPR_TLBMISS];
 549                     cmp = &env->spr[SPR_PTEHI];
 550                 } else {
 551                     if (excp == POWERPC_EXCP_DLTLB) {
 552                         es = "DL";
 553                     } else {
 554                         es = "DS";
 555                     }
 556                     en = 'D';
 557                     miss = &env->spr[SPR_TLBMISS];
 558                     cmp = &env->spr[SPR_PTEHI];
 559                 }
 560                 qemu_log("74xx %sTLB miss: %cM " TARGET_FMT_lx " %cC "
 561                          TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp,
 562                          env->error_code);
 563             }
 564 #endif
 565             msr |= env->error_code; /* key bit */
 566             break;
 567         default:
 568             cpu_abort(cs, "Invalid data store TLB miss exception\n");
 569             break;
 570         }
 571         goto store_next;
 572     case POWERPC_EXCP_FPA:       /* Floating-point assist exception          */
 573         /* XXX: TODO */
 574         cpu_abort(cs, "Floating point assist exception "
 575                   "is not implemented yet !\n");
 576         goto store_next;
 577     case POWERPC_EXCP_DABR:      /* Data address breakpoint                  */
 578         /* XXX: TODO */
 579         cpu_abort(cs, "DABR exception is not implemented yet !\n");
 580         goto store_next;
 581     case POWERPC_EXCP_IABR:      /* Instruction address breakpoint           */
 582         /* XXX: TODO */
 583         cpu_abort(cs, "IABR exception is not implemented yet !\n");
 584         goto store_next;
 585     case POWERPC_EXCP_SMI:       /* System management interrupt              */
 586         /* XXX: TODO */
 587         cpu_abort(cs, "SMI exception is not implemented yet !\n");
 588         goto store_next;
 589     case POWERPC_EXCP_THERM:     /* Thermal interrupt                        */
 590         /* XXX: TODO */
 591         cpu_abort(cs, "Thermal management exception "
 592                   "is not implemented yet !\n");
 593         goto store_next;
 594     case POWERPC_EXCP_PERFM:     /* Embedded performance monitor interrupt   */
 595         /* XXX: TODO */
 596         cpu_abort(cs,
 597                   "Performance counter exception is not implemented yet !\n");
 598         goto store_next;
 599     case POWERPC_EXCP_VPUA:      /* Vector assist exception                  */
 600         /* XXX: TODO */
 601         cpu_abort(cs, "VPU assist exception is not implemented yet !\n");
 602         goto store_next;
 603     case POWERPC_EXCP_SOFTP:     /* Soft patch exception                     */
 604         /* XXX: TODO */
 605         cpu_abort(cs,
 606                   "970 soft-patch exception is not implemented yet !\n");
 607         goto store_next;
 608     case POWERPC_EXCP_MAINT:     /* Maintenance exception                    */
 609         /* XXX: TODO */
 610         cpu_abort(cs,
 611                   "970 maintenance exception is not implemented yet !\n");
 612         goto store_next;
 613     case POWERPC_EXCP_MEXTBR:    /* Maskable external breakpoint             */
 614         /* XXX: TODO */
 615         cpu_abort(cs, "Maskable external exception "
 616                   "is not implemented yet !\n");
 617         goto store_next;
 618     case POWERPC_EXCP_NMEXTBR:   /* Non maskable external breakpoint         */
 619         /* XXX: TODO */
 620         cpu_abort(cs, "Non maskable external exception "
 621                   "is not implemented yet !\n");
 622         goto store_next;
 623     default:
 624     excp_invalid:
 625         cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
 626         break;
 627     store_current:
 628         /* save current instruction location */
 629         env->spr[srr0] = env->nip - 4;
 630         break;
 631     store_next:
 632         /* save next instruction location */
 633         env->spr[srr0] = env->nip;
 634         break;
 635     }
 636     /* Save MSR */
 637     env->spr[srr1] = msr;
 638
 639     /* Sanity check */
 640     if (!(env->msr_mask & MSR_HVB) && (srr0 == SPR_HSRR0)) {
 641         cpu_abort(cs, "Trying to deliver HV exception %d with "
 642                   "no HV support\n", excp);
 643     }
 644
 645     /* If any alternate SRR register are defined, duplicate saved values */
 646     if (asrr0 != -1) {
 647         env->spr[asrr0] = env->spr[srr0];
 648     }
 649     if (asrr1 != -1) {
 650         env->spr[asrr1] = env->spr[srr1];
 651     }
 652
 653     /* Sort out endianness of interrupt, this differs depending on the
 654      * CPU, the HV mode, etc...
 655      */
 656 #ifdef TARGET_PPC64
 657     if (excp_model == POWERPC_EXCP_POWER7) {
 658         if (!(new_msr & MSR_HVB) && (env->spr[SPR_LPCR] & LPCR_ILE)) {
 659             new_msr |= (target_ulong)1 << MSR_LE;
 660         }
 661     } else if (excp_model == POWERPC_EXCP_POWER8) {
 662         if (new_msr & MSR_HVB) {
 663             if (env->spr[SPR_HID0] & HID0_HILE) {
 664                 new_msr |= (target_ulong)1 << MSR_LE;
 665             }
 666         } else if (env->spr[SPR_LPCR] & LPCR_ILE) {
 667             new_msr |= (target_ulong)1 << MSR_LE;
 668         }
 669     } else if (msr_ile) {
 670         new_msr |= (target_ulong)1 << MSR_LE;
 671     }
 672 #else
 673     if (msr_ile) {
 674         new_msr |= (target_ulong)1 << MSR_LE;
 675     }
 676 #endif
 677
 678     /* Jump to handler */
 679     vector = env->excp_vectors[excp];
 680     if (vector == (target_ulong)-1ULL) {
 681         cpu_abort(cs, "Raised an exception without defined vector %d\n",
 682                   excp);
 683     }
 684     vector |= env->excp_prefix;
 685
 686     /* AIL only works if there is no HV transition and we are running with
 687      * translations enabled
 688      */
 689     if (!((msr >> MSR_IR) & 1) || !((msr >> MSR_DR) & 1) ||
 690         ((new_msr & MSR_HVB) && !(msr & MSR_HVB))) {
 691         ail = 0;
 692     }
 693     /* Handle AIL */
 694     if (ail) {
 695         new_msr |= (1 << MSR_IR) | (1 << MSR_DR);
 696         switch(ail) {
 697         case AIL_0001_8000:
 698             vector |= 0x18000;
 699             break;
 700         case AIL_C000_0000_0000_4000:
 701             vector |= 0xc000000000004000ull;
 702             break;
 703         default:
 704             cpu_abort(cs, "Invalid AIL combination %d\n", ail);
 705             break;
 706         }
 707     }
 708
 709 #if defined(TARGET_PPC64)
 710     if (excp_model == POWERPC_EXCP_BOOKE) {
 711         if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
 712             /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
 713             new_msr |= (target_ulong)1 << MSR_CM;
 714         } else {
 715             vector = (uint32_t)vector;
 716         }
 717     } else {
 718         if (!msr_isf && !(env->mmu_model & POWERPC_MMU_64)) {
 719             vector = (uint32_t)vector;
 720         } else {
 721             new_msr |= (target_ulong)1 << MSR_SF;
 722         }
 723     }
 724 #endif
 725     /* We don't use hreg_store_msr here as already have treated
 726      * any special case that could occur. Just store MSR and update hflags
 727      *
 728      * Note: We *MUST* not use hreg_store_msr() as-is anyway because it
 729      * will prevent setting of the HV bit which some exceptions might need
 730      * to do.
 731      */
 732     env->msr = new_msr & env->msr_mask;
 733     hreg_compute_hflags(env);
 734     env->nip = vector;
 735     /* Reset exception state */
 736     cs->exception_index = POWERPC_EXCP_NONE;
 737     env->error_code = 0;
 738
 739     /* Any interrupt is context synchronizing, check if TCG TLB
 740      * needs a delayed flush on ppc64
 741      */
 742     check_tlb_flush(env);
 743 }
 744
 745 void ppc_cpu_do_interrupt(CPUState *cs)
 746 {
 747     PowerPCCPU *cpu = POWERPC_CPU(cs);
 748     CPUPPCState *env = &cpu->env;
 749
 750     powerpc_excp(cpu, env->excp_model, cs->exception_index);
 751 }
 752
 753 static void ppc_hw_interrupt(CPUPPCState *env)
 754 {
 755     PowerPCCPU *cpu = ppc_env_get_cpu(env);
 756 #if 0
 757     CPUState *cs = CPU(cpu);
 758
 759     qemu_log_mask(CPU_LOG_INT, "%s: %p pending %08x req %08x me %d ee %d\n",
 760                   __func__, env, env->pending_interrupts,
 761                   cs->interrupt_request, (int)msr_me, (int)msr_ee);
 762 #endif
 763     /* External reset */
 764     if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) {
 765         env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET);
 766         powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_RESET);
 767         return;
 768     }
 769     /* Machine check exception */
 770     if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) {
 771         env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK);
 772         powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_MCHECK);
 773         return;
 774     }
 775 #if 0 /* TODO */
 776     /* External debug exception */
 777     if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) {
 778         env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG);
 779         powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DEBUG);
 780         return;
 781     }
 782 #endif
 783     /* Hypervisor decrementer exception */
 784     if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) {
 785         /* LPCR will be clear when not supported so this will work */
 786         bool hdice = !!(env->spr[SPR_LPCR] & LPCR_HDICE);
 787         if ((msr_ee != 0 || msr_hv == 0) && hdice) {
 788             /* HDEC clears on delivery */
 789             env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
 790             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_HDECR);
 791             return;
 792         }
 793     }
 794     /* Extermal interrupt can ignore MSR:EE under some circumstances */
 795     if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
 796         bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
 797         if (msr_ee != 0 || (env->has_hv_mode && msr_hv == 0 && !lpes0)) {
 798             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_EXTERNAL);
 799             return;
 800         }
 801     }
 802     if (msr_ce != 0) {
 803         /* External critical interrupt */
 804         if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) {
 805             /* Taking a critical external interrupt does not clear the external
 806              * critical interrupt status
 807              */
 808 #if 0
 809             env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CEXT);
 810 #endif
 811             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_CRITICAL);
 812             return;
 813         }
 814     }
 815     if (msr_ee != 0) {
 816         /* Watchdog timer on embedded PowerPC */
 817         if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) {
 818             env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT);
 819             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_WDT);
 820             return;
 821         }
 822         if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) {
 823             env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL);
 824             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DOORCI);
 825             return;
 826         }
 827         /* Fixed interval timer on embedded PowerPC */
 828         if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) {
 829             env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT);
 830             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_FIT);
 831             return;
 832         }
 833         /* Programmable interval timer on embedded PowerPC */
 834         if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) {
 835             env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT);
 836             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_PIT);
 837             return;
 838         }
 839         /* Decrementer exception */
 840         if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) {
 841             if (ppc_decr_clear_on_delivery(env)) {
 842                 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR);
 843             }
 844             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DECR);
 845             return;
 846         }
 847         if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) {
 848             env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL);
 849             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DOORI);
 850             return;
 851         }
 852         if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) {
 853             env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM);
 854             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_PERFM);
 855             return;
 856         }
 857         /* Thermal interrupt */
 858         if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) {
 859             env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
 860             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_THERM);
 861             return;
 862         }
 863     }
 864 }
 865
 866 void ppc_cpu_do_system_reset(CPUState *cs)
 867 {
 868     PowerPCCPU *cpu = POWERPC_CPU(cs);
 869     CPUPPCState *env = &cpu->env;
 870
 871     powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_RESET);
 872 }
 873 #endif /* !CONFIG_USER_ONLY */
 874
 875 bool ppc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 876 {
 877     PowerPCCPU *cpu = POWERPC_CPU(cs);
 878     CPUPPCState *env = &cpu->env;
 879
 880     if (interrupt_request & CPU_INTERRUPT_HARD) {
 881         ppc_hw_interrupt(env);
 882         if (env->pending_interrupts == 0) {
 883             cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
 884         }
 885         return true;
 886     }
 887     return false;
 888 }
 889
 890 #if defined(DEBUG_OP)
 891 static void cpu_dump_rfi(target_ulong RA, target_ulong msr)
 892 {
 893     qemu_log("Return from exception at " TARGET_FMT_lx " with flags "
 894              TARGET_FMT_lx "\n", RA, msr);
 895 }
 896 #endif
 897
 898 /*****************************************************************************/
 899 /* Exceptions processing helpers */
 900
 901 void helper_raise_exception_err(CPUPPCState *env, uint32_t exception,
 902                                 uint32_t error_code)
 903 {
 904     CPUState *cs = CPU(ppc_env_get_cpu(env));
 905
 906 #if 0
 907     printf("Raise exception %3x code : %d\n", exception, error_code);
 908 #endif
 909     cs->exception_index = exception;
 910     env->error_code = error_code;
 911     cpu_loop_exit(cs);
 912 }
 913
 914 void helper_raise_exception(CPUPPCState *env, uint32_t exception)
 915 {
 916     helper_raise_exception_err(env, exception, 0);
 917 }
 918
 919 #if !defined(CONFIG_USER_ONLY)
 920 void helper_store_msr(CPUPPCState *env, target_ulong val)
 921 {
 922     CPUState *cs;
 923
 924     val = hreg_store_msr(env, val, 0);
 925     if (val != 0) {
 926         cs = CPU(ppc_env_get_cpu(env));
 927         cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
 928         helper_raise_exception(env, val);
 929     }
 930 }
 931
 932 #if defined(TARGET_PPC64)
 933 void helper_pminsn(CPUPPCState *env, powerpc_pm_insn_t insn)
 934 {
 935     CPUState *cs;
 936
 937     cs = CPU(ppc_env_get_cpu(env));
 938     cs->halted = 1;
 939     env->in_pm_state = true;
 940
 941     /* The architecture specifies that HDEC interrupts are
 942      * discarded in PM states
 943      */
 944     env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
 945
 946     /* Technically, nap doesn't set EE, but if we don't set it
 947      * then ppc_hw_interrupt() won't deliver. We could add some
 948      * other tests there based on LPCR but it's simpler to just
 949      * whack EE in. It will be cleared by the 0x100 at wakeup
 950      * anyway. It will still be observable by the guest in SRR1
 951      * but this doesn't seem to be a problem.
 952      */
 953     env->msr |= (1ull << MSR_EE);
 954     helper_raise_exception(env, EXCP_HLT);
 955 }
 956 #endif /* defined(TARGET_PPC64) */
 957
 958 static inline void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr)
 959 {
 960     CPUState *cs = CPU(ppc_env_get_cpu(env));
 961
 962     /* MSR:POW cannot be set by any form of rfi */
 963     msr &= ~(1ULL << MSR_POW);
 964
 965 #if defined(TARGET_PPC64)
 966     /* Switching to 32-bit ? Crop the nip */
 967     if (!msr_is_64bit(env, msr)) {
 968         nip = (uint32_t)nip;
 969     }
 970 #else
 971     nip = (uint32_t)nip;
 972 #endif
 973     /* XXX: beware: this is false if VLE is supported */
 974     env->nip = nip & ~((target_ulong)0x00000003);
 975     hreg_store_msr(env, msr, 1);
 976 #if defined(DEBUG_OP)
 977     cpu_dump_rfi(env->nip, env->msr);
 978 #endif
 979     /* No need to raise an exception here,
 980      * as rfi is always the last insn of a TB
 981      */
 982     cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
 983
 984     /* Context synchronizing: check if TCG TLB needs flush */
 985     check_tlb_flush(env);
 986 }
 987
 988 void helper_rfi(CPUPPCState *env)
 989 {
 990     do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1] & 0xfffffffful);
 991 }
 992
 993 #define MSR_BOOK3S_MASK
 994 #if defined(TARGET_PPC64)
 995 void helper_rfid(CPUPPCState *env)
 996 {
 997     /* The architeture defines a number of rules for which bits
 998      * can change but in practice, we handle this in hreg_store_msr()
 999      * which will be called by do_rfi(), so there is no need to filter
1000      * here
1001      */
1002     do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1]);
1003 }
1004
1005 void helper_hrfid(CPUPPCState *env)
1006 {
1007     do_rfi(env, env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
1008 }
1009 #endif
1010
1011 /*****************************************************************************/
1012 /* Embedded PowerPC specific helpers */
1013 void helper_40x_rfci(CPUPPCState *env)
1014 {
1015     do_rfi(env, env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3]);
1016 }
1017
1018 void helper_rfci(CPUPPCState *env)
1019 {
1020     do_rfi(env, env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1]);
1021 }
1022
1023 void helper_rfdi(CPUPPCState *env)
1024 {
1025     /* FIXME: choose CSRR1 or DSRR1 based on cpu type */
1026     do_rfi(env, env->spr[SPR_BOOKE_DSRR0], env->spr[SPR_BOOKE_DSRR1]);
1027 }
1028
1029 void helper_rfmci(CPUPPCState *env)
1030 {
1031     /* FIXME: choose CSRR1 or MCSRR1 based on cpu type */
1032     do_rfi(env, env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
1033 }
1034 #endif
1035
1036 void helper_tw(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
1037                uint32_t flags)
1038 {
1039     if (!likely(!(((int32_t)arg1 < (int32_t)arg2 && (flags & 0x10)) ||
1040                   ((int32_t)arg1 > (int32_t)arg2 && (flags & 0x08)) ||
1041                   ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) ||
1042                   ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) ||
1043                   ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) {
1044         helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
1045                                    POWERPC_EXCP_TRAP);
1046     }
1047 }
1048
1049 #if defined(TARGET_PPC64)
1050 void helper_td(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
1051                uint32_t flags)
1052 {
1053     if (!likely(!(((int64_t)arg1 < (int64_t)arg2 && (flags & 0x10)) ||
1054                   ((int64_t)arg1 > (int64_t)arg2 && (flags & 0x08)) ||
1055                   ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) ||
1056                   ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) ||
1057                   ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01))))) {
1058         helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
1059                                    POWERPC_EXCP_TRAP);
1060     }
1061 }
1062 #endif
1063
1064 #if !defined(CONFIG_USER_ONLY)
1065 /*****************************************************************************/
1066 /* PowerPC 601 specific instructions (POWER bridge) */
1067
1068 void helper_rfsvc(CPUPPCState *env)
1069 {
1070     do_rfi(env, env->lr, env->ctr & 0x0000FFFF);
1071 }
1072
1073 /* Embedded.Processor Control */
1074 static int dbell2irq(target_ulong rb)
1075 {
1076     int msg = rb & DBELL_TYPE_MASK;
1077     int irq = -1;
1078
1079     switch (msg) {
1080     case DBELL_TYPE_DBELL:
1081         irq = PPC_INTERRUPT_DOORBELL;
1082         break;
1083     case DBELL_TYPE_DBELL_CRIT:
1084         irq = PPC_INTERRUPT_CDOORBELL;
1085         break;
1086     case DBELL_TYPE_G_DBELL:
1087     case DBELL_TYPE_G_DBELL_CRIT:
1088     case DBELL_TYPE_G_DBELL_MC:
1089         /* XXX implement */
1090     default:
1091         break;
1092     }
1093
1094     return irq;
1095 }
1096
1097 void helper_msgclr(CPUPPCState *env, target_ulong rb)
1098 {
1099     int irq = dbell2irq(rb);
1100
1101     if (irq < 0) {
1102         return;
1103     }
1104
1105     env->pending_interrupts &= ~(1 << irq);
1106 }
1107
1108 void helper_msgsnd(target_ulong rb)
1109 {
1110     int irq = dbell2irq(rb);
1111     int pir = rb & DBELL_PIRTAG_MASK;
1112     CPUState *cs;
1113
1114     if (irq < 0) {
1115         return;
1116     }
1117
1118     CPU_FOREACH(cs) {
1119         PowerPCCPU *cpu = POWERPC_CPU(cs);
1120         CPUPPCState *cenv = &cpu->env;
1121
1122         if ((rb & DBELL_BRDCAST) || (cenv->spr[SPR_BOOKE_PIR] == pir)) {
1123             cenv->pending_interrupts |= 1 << irq;
1124             cpu_interrupt(cs, CPU_INTERRUPT_HARD);
1125         }
1126     }
1127 }
1128 #endif