2 * QEMU educational PCI device
4 * Copyright (c) 2012-2015 Jiri Slaby
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 #include "qemu/osdep.h"
26 #include "hw/pci/pci.h"
27 #include "qemu/timer.h"
28 #include "qemu/main-loop.h" /* iothread mutex */
29 #include "qapi/visitor.h"
31 #define EDU(obj) OBJECT_CHECK(EduState, obj, "edu")
33 #define FACT_IRQ 0x00000001
34 #define DMA_IRQ 0x00000100
36 #define DMA_START 0x40000
50 #define EDU_STATUS_COMPUTING 0x01
51 #define EDU_STATUS_IRQFACT 0x80
56 #define EDU_DMA_RUN 0x1
57 #define EDU_DMA_DIR(cmd) (((cmd) & 0x2) >> 1)
58 # define EDU_DMA_FROM_PCI 0
59 # define EDU_DMA_TO_PCI 1
60 #define EDU_DMA_IRQ 0x4
68 char dma_buf
[DMA_SIZE
];
72 static void edu_raise_irq(EduState
*edu
, uint32_t val
)
74 edu
->irq_status
|= val
;
75 if (edu
->irq_status
) {
76 pci_set_irq(&edu
->pdev
, 1);
80 static void edu_lower_irq(EduState
*edu
, uint32_t val
)
82 edu
->irq_status
&= ~val
;
84 if (!edu
->irq_status
) {
85 pci_set_irq(&edu
->pdev
, 0);
89 static bool within(uint32_t addr
, uint32_t start
, uint32_t end
)
91 return start
<= addr
&& addr
< end
;
94 static void edu_check_range(uint32_t addr
, uint32_t size1
, uint32_t start
,
97 uint32_t end1
= addr
+ size1
;
98 uint32_t end2
= start
+ size2
;
100 if (within(addr
, start
, end2
) &&
101 end1
> addr
&& within(end1
, start
, end2
)) {
105 hw_error("EDU: DMA range 0x%.8x-0x%.8x out of bounds (0x%.8x-0x%.8x)!",
106 addr
, end1
- 1, start
, end2
- 1);
109 static dma_addr_t
edu_clamp_addr(const EduState
*edu
, dma_addr_t addr
)
111 dma_addr_t res
= addr
& edu
->dma_mask
;
114 printf("EDU: clamping DMA %#.16"PRIx64
" to %#.16"PRIx64
"!\n", addr
, res
);
120 static void edu_dma_timer(void *opaque
)
122 EduState
*edu
= opaque
;
123 bool raise_irq
= false;
125 if (!(edu
->dma
.cmd
& EDU_DMA_RUN
)) {
129 if (EDU_DMA_DIR(edu
->dma
.cmd
) == EDU_DMA_FROM_PCI
) {
130 uint32_t dst
= edu
->dma
.dst
;
131 edu_check_range(dst
, edu
->dma
.cnt
, DMA_START
, DMA_SIZE
);
133 pci_dma_read(&edu
->pdev
, edu_clamp_addr(edu
, edu
->dma
.src
),
134 edu
->dma_buf
+ dst
, edu
->dma
.cnt
);
136 uint32_t src
= edu
->dma
.src
;
137 edu_check_range(src
, edu
->dma
.cnt
, DMA_START
, DMA_SIZE
);
139 pci_dma_write(&edu
->pdev
, edu_clamp_addr(edu
, edu
->dma
.dst
),
140 edu
->dma_buf
+ src
, edu
->dma
.cnt
);
143 edu
->dma
.cmd
&= ~EDU_DMA_RUN
;
144 if (edu
->dma
.cmd
& EDU_DMA_IRQ
) {
149 edu_raise_irq(edu
, DMA_IRQ
);
153 static void dma_rw(EduState
*edu
, bool write
, dma_addr_t
*val
, dma_addr_t
*dma
,
156 if (write
&& (edu
->dma
.cmd
& EDU_DMA_RUN
)) {
167 timer_mod(&edu
->dma_timer
, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL
) + 100);
171 static uint64_t edu_mmio_read(void *opaque
, hwaddr addr
, unsigned size
)
173 EduState
*edu
= opaque
;
174 uint64_t val
= ~0ULL;
188 qemu_mutex_lock(&edu
->thr_mutex
);
190 qemu_mutex_unlock(&edu
->thr_mutex
);
193 val
= atomic_read(&edu
->status
);
196 val
= edu
->irq_status
;
199 dma_rw(edu
, false, &val
, &edu
->dma
.src
, false);
202 dma_rw(edu
, false, &val
, &edu
->dma
.dst
, false);
205 dma_rw(edu
, false, &val
, &edu
->dma
.cnt
, false);
208 dma_rw(edu
, false, &val
, &edu
->dma
.cmd
, false);
215 static void edu_mmio_write(void *opaque
, hwaddr addr
, uint64_t val
,
218 EduState
*edu
= opaque
;
220 if (addr
< 0x80 && size
!= 4) {
224 if (addr
>= 0x80 && size
!= 4 && size
!= 8) {
233 if (atomic_read(&edu
->status
) & EDU_STATUS_COMPUTING
) {
236 /* EDU_STATUS_COMPUTING cannot go 0->1 concurrently, because it is only
237 * set in this function and it is under the iothread mutex.
239 qemu_mutex_lock(&edu
->thr_mutex
);
241 atomic_or(&edu
->status
, EDU_STATUS_COMPUTING
);
242 qemu_cond_signal(&edu
->thr_cond
);
243 qemu_mutex_unlock(&edu
->thr_mutex
);
246 if (val
& EDU_STATUS_IRQFACT
) {
247 atomic_or(&edu
->status
, EDU_STATUS_IRQFACT
);
249 atomic_and(&edu
->status
, ~EDU_STATUS_IRQFACT
);
253 edu_raise_irq(edu
, val
);
256 edu_lower_irq(edu
, val
);
259 dma_rw(edu
, true, &val
, &edu
->dma
.src
, false);
262 dma_rw(edu
, true, &val
, &edu
->dma
.dst
, false);
265 dma_rw(edu
, true, &val
, &edu
->dma
.cnt
, false);
268 if (!(val
& EDU_DMA_RUN
)) {
271 dma_rw(edu
, true, &val
, &edu
->dma
.cmd
, true);
276 static const MemoryRegionOps edu_mmio_ops
= {
277 .read
= edu_mmio_read
,
278 .write
= edu_mmio_write
,
279 .endianness
= DEVICE_NATIVE_ENDIAN
,
283 * We purposely use a thread, so that users are forced to wait for the status
286 static void *edu_fact_thread(void *opaque
)
288 EduState
*edu
= opaque
;
291 uint32_t val
, ret
= 1;
293 qemu_mutex_lock(&edu
->thr_mutex
);
294 while ((atomic_read(&edu
->status
) & EDU_STATUS_COMPUTING
) == 0 &&
296 qemu_cond_wait(&edu
->thr_cond
, &edu
->thr_mutex
);
300 qemu_mutex_unlock(&edu
->thr_mutex
);
305 qemu_mutex_unlock(&edu
->thr_mutex
);
312 * We should sleep for a random period here, so that students are
313 * forced to check the status properly.
316 qemu_mutex_lock(&edu
->thr_mutex
);
318 qemu_mutex_unlock(&edu
->thr_mutex
);
319 atomic_and(&edu
->status
, ~EDU_STATUS_COMPUTING
);
321 if (atomic_read(&edu
->status
) & EDU_STATUS_IRQFACT
) {
322 qemu_mutex_lock_iothread();
323 edu_raise_irq(edu
, FACT_IRQ
);
324 qemu_mutex_unlock_iothread();
331 static void pci_edu_realize(PCIDevice
*pdev
, Error
**errp
)
333 EduState
*edu
= DO_UPCAST(EduState
, pdev
, pdev
);
334 uint8_t *pci_conf
= pdev
->config
;
336 timer_init_ms(&edu
->dma_timer
, QEMU_CLOCK_VIRTUAL
, edu_dma_timer
, edu
);
338 qemu_mutex_init(&edu
->thr_mutex
);
339 qemu_cond_init(&edu
->thr_cond
);
340 qemu_thread_create(&edu
->thread
, "edu", edu_fact_thread
,
341 edu
, QEMU_THREAD_JOINABLE
);
343 pci_config_set_interrupt_pin(pci_conf
, 1);
345 memory_region_init_io(&edu
->mmio
, OBJECT(edu
), &edu_mmio_ops
, edu
,
346 "edu-mmio", 1 << 20);
347 pci_register_bar(pdev
, 0, PCI_BASE_ADDRESS_SPACE_MEMORY
, &edu
->mmio
);
350 static void pci_edu_uninit(PCIDevice
*pdev
)
352 EduState
*edu
= DO_UPCAST(EduState
, pdev
, pdev
);
354 qemu_mutex_lock(&edu
->thr_mutex
);
355 edu
->stopping
= true;
356 qemu_mutex_unlock(&edu
->thr_mutex
);
357 qemu_cond_signal(&edu
->thr_cond
);
358 qemu_thread_join(&edu
->thread
);
360 qemu_cond_destroy(&edu
->thr_cond
);
361 qemu_mutex_destroy(&edu
->thr_mutex
);
363 timer_del(&edu
->dma_timer
);
366 static void edu_obj_uint64(Object
*obj
, Visitor
*v
, const char *name
,
367 void *opaque
, Error
**errp
)
369 uint64_t *val
= opaque
;
371 visit_type_uint64(v
, name
, val
, errp
);
374 static void edu_instance_init(Object
*obj
)
376 EduState
*edu
= EDU(obj
);
378 edu
->dma_mask
= (1UL << 28) - 1;
379 object_property_add(obj
, "dma_mask", "uint64", edu_obj_uint64
,
380 edu_obj_uint64
, NULL
, &edu
->dma_mask
, NULL
);
383 static void edu_class_init(ObjectClass
*class, void *data
)
385 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(class);
387 k
->realize
= pci_edu_realize
;
388 k
->exit
= pci_edu_uninit
;
389 k
->vendor_id
= PCI_VENDOR_ID_QEMU
;
390 k
->device_id
= 0x11e8;
392 k
->class_id
= PCI_CLASS_OTHERS
;
395 static void pci_edu_register_types(void)
397 static const TypeInfo edu_info
= {
399 .parent
= TYPE_PCI_DEVICE
,
400 .instance_size
= sizeof(EduState
),
401 .instance_init
= edu_instance_init
,
402 .class_init
= edu_class_init
,
405 type_register_static(&edu_info
);
407 type_init(pci_edu_register_types
)