hw/misc/imx31_ccm.c

   1 /*
   2  * IMX31 Clock Control Module
   3  *
   4  * Copyright (C) 2012 NICTA
   5  * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
   6  *
   7  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   8  * See the COPYING file in the top-level directory.
   9  *
  10  * To get the timer frequencies right, we need to emulate at least part of
  11  * the i.MX31 CCM.
  12  */
  13
  14 #include "qemu/osdep.h"
  15 #include "hw/misc/imx31_ccm.h"
  16
  17 #define CKIH_FREQ 26000000 /* 26MHz crystal input */
  18
  19 #ifndef DEBUG_IMX31_CCM
  20 #define DEBUG_IMX31_CCM 0
  21 #endif
  22
  23 #define DPRINTF(fmt, args...) \
  24     do { \
  25         if (DEBUG_IMX31_CCM) { \
  26             fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX31_CCM, \
  27                                              __func__, ##args); \
  28         } \
  29     } while (0)
  30
  31 static char const *imx31_ccm_reg_name(uint32_t reg)
  32 {
  33     static char unknown[20];
  34
  35     switch (reg) {
  36     case IMX31_CCM_CCMR_REG:
  37         return "CCMR";
  38     case IMX31_CCM_PDR0_REG:
  39         return "PDR0";
  40     case IMX31_CCM_PDR1_REG:
  41         return "PDR1";
  42     case IMX31_CCM_RCSR_REG:
  43         return "RCSR";
  44     case IMX31_CCM_MPCTL_REG:
  45         return "MPCTL";
  46     case IMX31_CCM_UPCTL_REG:
  47         return "UPCTL";
  48     case IMX31_CCM_SPCTL_REG:
  49         return "SPCTL";
  50     case IMX31_CCM_COSR_REG:
  51         return "COSR";
  52     case IMX31_CCM_CGR0_REG:
  53         return "CGR0";
  54     case IMX31_CCM_CGR1_REG:
  55         return "CGR1";
  56     case IMX31_CCM_CGR2_REG:
  57         return "CGR2";
  58     case IMX31_CCM_WIMR_REG:
  59         return "WIMR";
  60     case IMX31_CCM_LDC_REG:
  61         return "LDC";
  62     case IMX31_CCM_DCVR0_REG:
  63         return "DCVR0";
  64     case IMX31_CCM_DCVR1_REG:
  65         return "DCVR1";
  66     case IMX31_CCM_DCVR2_REG:
  67         return "DCVR2";
  68     case IMX31_CCM_DCVR3_REG:
  69         return "DCVR3";
  70     case IMX31_CCM_LTR0_REG:
  71         return "LTR0";
  72     case IMX31_CCM_LTR1_REG:
  73         return "LTR1";
  74     case IMX31_CCM_LTR2_REG:
  75         return "LTR2";
  76     case IMX31_CCM_LTR3_REG:
  77         return "LTR3";
  78     case IMX31_CCM_LTBR0_REG:
  79         return "LTBR0";
  80     case IMX31_CCM_LTBR1_REG:
  81         return "LTBR1";
  82     case IMX31_CCM_PMCR0_REG:
  83         return "PMCR0";
  84     case IMX31_CCM_PMCR1_REG:
  85         return "PMCR1";
  86     case IMX31_CCM_PDR2_REG:
  87         return "PDR2";
  88     default:
  89         sprintf(unknown, "[%d ?]", reg);
  90         return unknown;
  91     }
  92 }
  93
  94 static const VMStateDescription vmstate_imx31_ccm = {
  95     .name = TYPE_IMX31_CCM,
  96     .version_id = 2,
  97     .minimum_version_id = 2,
  98     .fields = (VMStateField[]) {
  99         VMSTATE_UINT32_ARRAY(reg, IMX31CCMState, IMX31_CCM_MAX_REG),
 100         VMSTATE_END_OF_LIST()
 101     },
 102 };
 103
 104 static uint32_t imx31_ccm_get_pll_ref_clk(IMXCCMState *dev)
 105 {
 106     uint32_t freq = 0;
 107     IMX31CCMState *s = IMX31_CCM(dev);
 108
 109     if ((s->reg[IMX31_CCM_CCMR_REG] & CCMR_PRCS) == 2) {
 110         if (s->reg[IMX31_CCM_CCMR_REG] & CCMR_FPME) {
 111             freq = CKIL_FREQ;
 112             if (s->reg[IMX31_CCM_CCMR_REG] & CCMR_FPMF) {
 113                 freq *= 1024;
 114             }
 115         }
 116     } else {
 117         freq = CKIH_FREQ;
 118     }
 119
 120     DPRINTF("freq = %d\n", freq);
 121
 122     return freq;
 123 }
 124
 125 static uint32_t imx31_ccm_get_mpll_clk(IMXCCMState *dev)
 126 {
 127     uint32_t freq;
 128     IMX31CCMState *s = IMX31_CCM(dev);
 129
 130     freq = imx_ccm_calc_pll(s->reg[IMX31_CCM_MPCTL_REG],
 131                             imx31_ccm_get_pll_ref_clk(dev));
 132
 133     DPRINTF("freq = %d\n", freq);
 134
 135     return freq;
 136 }
 137
 138 static uint32_t imx31_ccm_get_mcu_main_clk(IMXCCMState *dev)
 139 {
 140     uint32_t freq;
 141     IMX31CCMState *s = IMX31_CCM(dev);
 142
 143     if ((s->reg[IMX31_CCM_CCMR_REG] & CCMR_MDS) ||
 144         !(s->reg[IMX31_CCM_CCMR_REG] & CCMR_MPE)) {
 145         freq = imx31_ccm_get_pll_ref_clk(dev);
 146     } else {
 147         freq = imx31_ccm_get_mpll_clk(dev);
 148     }
 149
 150     DPRINTF("freq = %d\n", freq);
 151
 152     return freq;
 153 }
 154
 155 static uint32_t imx31_ccm_get_mcu_clk(IMXCCMState *dev)
 156 {
 157     uint32_t freq;
 158     IMX31CCMState *s = IMX31_CCM(dev);
 159
 160     freq = imx31_ccm_get_mcu_main_clk(dev)
 161            / (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], MCU));
 162
 163     DPRINTF("freq = %d\n", freq);
 164
 165     return freq;
 166 }
 167
 168 static uint32_t imx31_ccm_get_hsp_clk(IMXCCMState *dev)
 169 {
 170     uint32_t freq;
 171     IMX31CCMState *s = IMX31_CCM(dev);
 172
 173     freq = imx31_ccm_get_mcu_main_clk(dev)
 174            / (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], HSP));
 175
 176     DPRINTF("freq = %d\n", freq);
 177
 178     return freq;
 179 }
 180
 181 static uint32_t imx31_ccm_get_hclk_clk(IMXCCMState *dev)
 182 {
 183     uint32_t freq;
 184     IMX31CCMState *s = IMX31_CCM(dev);
 185
 186     freq = imx31_ccm_get_mcu_main_clk(dev)
 187            / (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], MAX));
 188
 189     DPRINTF("freq = %d\n", freq);
 190
 191     return freq;
 192 }
 193
 194 static uint32_t imx31_ccm_get_ipg_clk(IMXCCMState *dev)
 195 {
 196     uint32_t freq;
 197     IMX31CCMState *s = IMX31_CCM(dev);
 198
 199     freq = imx31_ccm_get_hclk_clk(dev)
 200            / (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], IPG));
 201
 202     DPRINTF("freq = %d\n", freq);
 203
 204     return freq;
 205 }
 206
 207 static uint32_t imx31_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
 208 {
 209     uint32_t freq = 0;
 210
 211     switch (clock) {
 212     case NOCLK:
 213         break;
 214     case CLK_MCU:
 215         freq = imx31_ccm_get_mcu_clk(dev);
 216         break;
 217     case CLK_HSP:
 218         freq = imx31_ccm_get_hsp_clk(dev);
 219         break;
 220     case CLK_IPG:
 221         freq = imx31_ccm_get_ipg_clk(dev);
 222         break;
 223     case CLK_32k:
 224         freq = CKIL_FREQ;
 225         break;
 226     default:
 227         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: unsupported clock %d\n",
 228                       TYPE_IMX31_CCM, __func__, clock);
 229         break;
 230     }
 231
 232     DPRINTF("Clock = %d) = %d\n", clock, freq);
 233
 234     return freq;
 235 }
 236
 237 static void imx31_ccm_reset(DeviceState *dev)
 238 {
 239     IMX31CCMState *s = IMX31_CCM(dev);
 240
 241     DPRINTF("()\n");
 242
 243     memset(s->reg, 0, sizeof(uint32_t) * IMX31_CCM_MAX_REG);
 244
 245     s->reg[IMX31_CCM_CCMR_REG]   = 0x074b0b7d;
 246     s->reg[IMX31_CCM_PDR0_REG]   = 0xff870b48;
 247     s->reg[IMX31_CCM_PDR1_REG]   = 0x49fcfe7f;
 248     s->reg[IMX31_CCM_RCSR_REG]   = 0x007f0000;
 249     s->reg[IMX31_CCM_MPCTL_REG]  = 0x04001800;
 250     s->reg[IMX31_CCM_UPCTL_REG]  = 0x04051c03;
 251     s->reg[IMX31_CCM_SPCTL_REG]  = 0x04043001;
 252     s->reg[IMX31_CCM_COSR_REG]   = 0x00000280;
 253     s->reg[IMX31_CCM_CGR0_REG]   = 0xffffffff;
 254     s->reg[IMX31_CCM_CGR1_REG]   = 0xffffffff;
 255     s->reg[IMX31_CCM_CGR2_REG]   = 0xffffffff;
 256     s->reg[IMX31_CCM_WIMR_REG]   = 0xffffffff;
 257     s->reg[IMX31_CCM_LTR1_REG]   = 0x00004040;
 258     s->reg[IMX31_CCM_PMCR0_REG]  = 0x80209828;
 259     s->reg[IMX31_CCM_PMCR1_REG]  = 0x00aa0000;
 260     s->reg[IMX31_CCM_PDR2_REG]   = 0x00000285;
 261 }
 262
 263 static uint64_t imx31_ccm_read(void *opaque, hwaddr offset, unsigned size)
 264 {
 265     uint32_t value = 0;
 266     IMX31CCMState *s = (IMX31CCMState *)opaque;
 267
 268     if ((offset >> 2) < IMX31_CCM_MAX_REG) {
 269         value = s->reg[offset >> 2];
 270     } else {
 271         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
 272                       HWADDR_PRIx "\n", TYPE_IMX31_CCM, __func__, offset);
 273     }
 274
 275     DPRINTF("reg[%s] => 0x%" PRIx32 "\n", imx31_ccm_reg_name(offset >> 2),
 276             value);
 277
 278     return (uint64_t)value;
 279 }
 280
 281 static void imx31_ccm_write(void *opaque, hwaddr offset, uint64_t value,
 282                             unsigned size)
 283 {
 284     IMX31CCMState *s = (IMX31CCMState *)opaque;
 285
 286     DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx31_ccm_reg_name(offset >> 2),
 287             (uint32_t)value);
 288
 289     switch (offset >> 2) {
 290     case IMX31_CCM_CCMR_REG:
 291         s->reg[IMX31_CCM_CCMR_REG] = CCMR_FPMF | (value & 0x3b6fdfff);
 292         break;
 293     case IMX31_CCM_PDR0_REG:
 294         s->reg[IMX31_CCM_PDR0_REG] = value & 0xff9f3fff;
 295         break;
 296     case IMX31_CCM_PDR1_REG:
 297         s->reg[IMX31_CCM_PDR1_REG] = value;
 298         break;
 299     case IMX31_CCM_MPCTL_REG:
 300         s->reg[IMX31_CCM_MPCTL_REG] = value & 0xbfff3fff;
 301         break;
 302     case IMX31_CCM_SPCTL_REG:
 303         s->reg[IMX31_CCM_SPCTL_REG] = value & 0xbfff3fff;
 304         break;
 305     case IMX31_CCM_CGR0_REG:
 306         s->reg[IMX31_CCM_CGR0_REG] = value;
 307         break;
 308     case IMX31_CCM_CGR1_REG:
 309         s->reg[IMX31_CCM_CGR1_REG] = value;
 310         break;
 311     case IMX31_CCM_CGR2_REG:
 312         s->reg[IMX31_CCM_CGR2_REG] = value;
 313         break;
 314     default:
 315         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
 316                       HWADDR_PRIx "\n", TYPE_IMX31_CCM, __func__, offset);
 317         break;
 318     }
 319 }
 320
 321 static const struct MemoryRegionOps imx31_ccm_ops = {
 322     .read = imx31_ccm_read,
 323     .write = imx31_ccm_write,
 324     .endianness = DEVICE_NATIVE_ENDIAN,
 325     .valid = {
 326         /*
 327          * Our device would not work correctly if the guest was doing
 328          * unaligned access. This might not be a limitation on the real
 329          * device but in practice there is no reason for a guest to access
 330          * this device unaligned.
 331          */
 332         .min_access_size = 4,
 333         .max_access_size = 4,
 334         .unaligned = false,
 335     },
 336
 337 };
 338
 339 static void imx31_ccm_init(Object *obj)
 340 {
 341     DeviceState *dev = DEVICE(obj);
 342     SysBusDevice *sd = SYS_BUS_DEVICE(obj);
 343     IMX31CCMState *s = IMX31_CCM(obj);
 344
 345     memory_region_init_io(&s->iomem, OBJECT(dev), &imx31_ccm_ops, s,
 346                           TYPE_IMX31_CCM, 0x1000);
 347     sysbus_init_mmio(sd, &s->iomem);
 348 }
 349
 350 static void imx31_ccm_class_init(ObjectClass *klass, void *data)
 351 {
 352     DeviceClass *dc  = DEVICE_CLASS(klass);
 353     IMXCCMClass *ccm = IMX_CCM_CLASS(klass);
 354
 355     dc->reset = imx31_ccm_reset;
 356     dc->vmsd  = &vmstate_imx31_ccm;
 357     dc->desc  = "i.MX31 Clock Control Module";
 358
 359     ccm->get_clock_frequency = imx31_ccm_get_clock_frequency;
 360 }
 361
 362 static const TypeInfo imx31_ccm_info = {
 363     .name          = TYPE_IMX31_CCM,
 364     .parent        = TYPE_IMX_CCM,
 365     .instance_size = sizeof(IMX31CCMState),
 366     .instance_init = imx31_ccm_init,
 367     .class_init    = imx31_ccm_class_init,
 368 };
 369
 370 static void imx31_ccm_register_types(void)
 371 {
 372     type_register_static(&imx31_ccm_info);
 373 }
 374
 375 type_init(imx31_ccm_register_types)