hw/acpi/pcihp.c

   1 /*
   2  * QEMU<->ACPI BIOS PCI hotplug interface
   3  *
   4  * QEMU supports PCI hotplug via ACPI. This module
   5  * implements the interface between QEMU and the ACPI BIOS.
   6  * Interface specification - see docs/specs/acpi_pci_hotplug.txt
   7  *
   8  * Copyright (c) 2013, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
   9  * Copyright (c) 2006 Fabrice Bellard
  10  *
  11  * This library is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU Lesser General Public
  13  * License version 2 as published by the Free Software Foundation.
  14  *
  15  * This library is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18  * Lesser General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU Lesser General Public
  21  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  22  *
  23  * Contributions after 2012-01-13 are licensed under the terms of the
  24  * GNU GPL, version 2 or (at your option) any later version.
  25  */
  26
  27 #include "qemu/osdep.h"
  28 #include "hw/acpi/pcihp.h"
  29
  30 #include "hw/hw.h"
  31 #include "hw/i386/pc.h"
  32 #include "hw/pci/pci.h"
  33 #include "hw/acpi/acpi.h"
  34 #include "sysemu/sysemu.h"
  35 #include "exec/ioport.h"
  36 #include "exec/address-spaces.h"
  37 #include "hw/pci/pci_bus.h"
  38 #include "qom/qom-qobject.h"
  39 #include "qapi/qmp/qint.h"
  40
  41 //#define DEBUG
  42
  43 #ifdef DEBUG
  44 # define ACPI_PCIHP_DPRINTF(format, ...)     printf(format, ## __VA_ARGS__)
  45 #else
  46 # define ACPI_PCIHP_DPRINTF(format, ...)     do { } while (0)
  47 #endif
  48
  49 #define ACPI_PCIHP_ADDR 0xae00
  50 #define ACPI_PCIHP_SIZE 0x0014
  51 #define ACPI_PCIHP_LEGACY_SIZE 0x000f
  52 #define PCI_UP_BASE 0x0000
  53 #define PCI_DOWN_BASE 0x0004
  54 #define PCI_EJ_BASE 0x0008
  55 #define PCI_RMV_BASE 0x000c
  56 #define PCI_SEL_BASE 0x0010
  57
  58 typedef struct AcpiPciHpFind {
  59     int bsel;
  60     PCIBus *bus;
  61 } AcpiPciHpFind;
  62
  63 static int acpi_pcihp_get_bsel(PCIBus *bus)
  64 {
  65     Error *local_err = NULL;
  66     int64_t bsel = object_property_get_int(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
  67                                            &local_err);
  68
  69     if (local_err || bsel < 0 || bsel >= ACPI_PCIHP_MAX_HOTPLUG_BUS) {
  70         if (local_err) {
  71             error_free(local_err);
  72         }
  73         return -1;
  74     } else {
  75         return bsel;
  76     }
  77 }
  78
  79 static void acpi_pcihp_test_hotplug_bus(PCIBus *bus, void *opaque)
  80 {
  81     AcpiPciHpFind *find = opaque;
  82     if (find->bsel == acpi_pcihp_get_bsel(bus)) {
  83         find->bus = bus;
  84     }
  85 }
  86
  87 static PCIBus *acpi_pcihp_find_hotplug_bus(AcpiPciHpState *s, int bsel)
  88 {
  89     AcpiPciHpFind find = { .bsel = bsel, .bus = NULL };
  90
  91     if (bsel < 0) {
  92         return NULL;
  93     }
  94
  95     pci_for_each_bus(s->root, acpi_pcihp_test_hotplug_bus, &find);
  96
  97     /* Make bsel 0 eject root bus if bsel property is not set,
  98      * for compatibility with non acpi setups.
  99      * TODO: really needed?
 100      */
 101     if (!bsel && !find.bus) {
 102         find.bus = s->root;
 103     }
 104     return find.bus;
 105 }
 106
 107 static bool acpi_pcihp_pc_no_hotplug(AcpiPciHpState *s, PCIDevice *dev)
 108 {
 109     PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
 110     DeviceClass *dc = DEVICE_GET_CLASS(dev);
 111     /*
 112      * ACPI doesn't allow hotplug of bridge devices.  Don't allow
 113      * hot-unplug of bridge devices unless they were added by hotplug
 114      * (and so, not described by acpi).
 115      */
 116     return (pc->is_bridge && !dev->qdev.hotplugged) || !dc->hotpluggable;
 117 }
 118
 119 static void acpi_pcihp_eject_slot(AcpiPciHpState *s, unsigned bsel, unsigned slots)
 120 {
 121     BusChild *kid, *next;
 122     int slot = ctz32(slots);
 123     PCIBus *bus = acpi_pcihp_find_hotplug_bus(s, bsel);
 124
 125     if (!bus) {
 126         return;
 127     }
 128
 129     /* Mark request as complete */
 130     s->acpi_pcihp_pci_status[bsel].down &= ~(1U << slot);
 131     s->acpi_pcihp_pci_status[bsel].up &= ~(1U << slot);
 132
 133     QTAILQ_FOREACH_SAFE(kid, &bus->qbus.children, sibling, next) {
 134         DeviceState *qdev = kid->child;
 135         PCIDevice *dev = PCI_DEVICE(qdev);
 136         if (PCI_SLOT(dev->devfn) == slot) {
 137             if (!acpi_pcihp_pc_no_hotplug(s, dev)) {
 138                 object_unparent(OBJECT(qdev));
 139             }
 140         }
 141     }
 142 }
 143
 144 static void acpi_pcihp_update_hotplug_bus(AcpiPciHpState *s, int bsel)
 145 {
 146     BusChild *kid, *next;
 147     PCIBus *bus = acpi_pcihp_find_hotplug_bus(s, bsel);
 148
 149     /* Execute any pending removes during reset */
 150     while (s->acpi_pcihp_pci_status[bsel].down) {
 151         acpi_pcihp_eject_slot(s, bsel, s->acpi_pcihp_pci_status[bsel].down);
 152     }
 153
 154     s->acpi_pcihp_pci_status[bsel].hotplug_enable = ~0;
 155
 156     if (!bus) {
 157         return;
 158     }
 159     QTAILQ_FOREACH_SAFE(kid, &bus->qbus.children, sibling, next) {
 160         DeviceState *qdev = kid->child;
 161         PCIDevice *pdev = PCI_DEVICE(qdev);
 162         int slot = PCI_SLOT(pdev->devfn);
 163
 164         if (acpi_pcihp_pc_no_hotplug(s, pdev)) {
 165             s->acpi_pcihp_pci_status[bsel].hotplug_enable &= ~(1U << slot);
 166         }
 167     }
 168 }
 169
 170 static void acpi_pcihp_update(AcpiPciHpState *s)
 171 {
 172     int i;
 173
 174     for (i = 0; i < ACPI_PCIHP_MAX_HOTPLUG_BUS; ++i) {
 175         acpi_pcihp_update_hotplug_bus(s, i);
 176     }
 177 }
 178
 179 void acpi_pcihp_reset(AcpiPciHpState *s)
 180 {
 181     acpi_pcihp_update(s);
 182 }
 183
 184 void acpi_pcihp_device_plug_cb(ACPIREGS *ar, qemu_irq irq, AcpiPciHpState *s,
 185                                DeviceState *dev, Error **errp)
 186 {
 187     PCIDevice *pdev = PCI_DEVICE(dev);
 188     int slot = PCI_SLOT(pdev->devfn);
 189     int bsel = acpi_pcihp_get_bsel(pdev->bus);
 190     if (bsel < 0) {
 191         error_setg(errp, "Unsupported bus. Bus doesn't have property '"
 192                    ACPI_PCIHP_PROP_BSEL "' set");
 193         return;
 194     }
 195
 196     /* Don't send event when device is enabled during qemu machine creation:
 197      * it is present on boot, no hotplug event is necessary. We do send an
 198      * event when the device is disabled later. */
 199     if (!dev->hotplugged) {
 200         return;
 201     }
 202
 203     s->acpi_pcihp_pci_status[bsel].up |= (1U << slot);
 204
 205     acpi_send_gpe_event(ar, irq, ACPI_PCI_HOTPLUG_STATUS);
 206 }
 207
 208 void acpi_pcihp_device_unplug_cb(ACPIREGS *ar, qemu_irq irq, AcpiPciHpState *s,
 209                                  DeviceState *dev, Error **errp)
 210 {
 211     PCIDevice *pdev = PCI_DEVICE(dev);
 212     int slot = PCI_SLOT(pdev->devfn);
 213     int bsel = acpi_pcihp_get_bsel(pdev->bus);
 214     if (bsel < 0) {
 215         error_setg(errp, "Unsupported bus. Bus doesn't have property '"
 216                    ACPI_PCIHP_PROP_BSEL "' set");
 217         return;
 218     }
 219
 220     s->acpi_pcihp_pci_status[bsel].down |= (1U << slot);
 221
 222     acpi_send_gpe_event(ar, irq, ACPI_PCI_HOTPLUG_STATUS);
 223 }
 224
 225 static uint64_t pci_read(void *opaque, hwaddr addr, unsigned int size)
 226 {
 227     AcpiPciHpState *s = opaque;
 228     uint32_t val = 0;
 229     int bsel = s->hotplug_select;
 230
 231     if (bsel < 0 || bsel >= ACPI_PCIHP_MAX_HOTPLUG_BUS) {
 232         return 0;
 233     }
 234
 235     switch (addr) {
 236     case PCI_UP_BASE:
 237         val = s->acpi_pcihp_pci_status[bsel].up;
 238         if (!s->legacy_piix) {
 239             s->acpi_pcihp_pci_status[bsel].up = 0;
 240         }
 241         ACPI_PCIHP_DPRINTF("pci_up_read %" PRIu32 "\n", val);
 242         break;
 243     case PCI_DOWN_BASE:
 244         val = s->acpi_pcihp_pci_status[bsel].down;
 245         ACPI_PCIHP_DPRINTF("pci_down_read %" PRIu32 "\n", val);
 246         break;
 247     case PCI_EJ_BASE:
 248         /* No feature defined yet */
 249         ACPI_PCIHP_DPRINTF("pci_features_read %" PRIu32 "\n", val);
 250         break;
 251     case PCI_RMV_BASE:
 252         val = s->acpi_pcihp_pci_status[bsel].hotplug_enable;
 253         ACPI_PCIHP_DPRINTF("pci_rmv_read %" PRIu32 "\n", val);
 254         break;
 255     case PCI_SEL_BASE:
 256         val = s->hotplug_select;
 257         ACPI_PCIHP_DPRINTF("pci_sel_read %" PRIu32 "\n", val);
 258     default:
 259         break;
 260     }
 261
 262     return val;
 263 }
 264
 265 static void pci_write(void *opaque, hwaddr addr, uint64_t data,
 266                       unsigned int size)
 267 {
 268     AcpiPciHpState *s = opaque;
 269     switch (addr) {
 270     case PCI_EJ_BASE:
 271         if (s->hotplug_select >= ACPI_PCIHP_MAX_HOTPLUG_BUS) {
 272             break;
 273         }
 274         acpi_pcihp_eject_slot(s, s->hotplug_select, data);
 275         ACPI_PCIHP_DPRINTF("pciej write %" HWADDR_PRIx " <== %" PRIu64 "\n",
 276                       addr, data);
 277         break;
 278     case PCI_SEL_BASE:
 279         s->hotplug_select = data;
 280         ACPI_PCIHP_DPRINTF("pcisel write %" HWADDR_PRIx " <== %" PRIu64 "\n",
 281                       addr, data);
 282     default:
 283         break;
 284     }
 285 }
 286
 287 static const MemoryRegionOps acpi_pcihp_io_ops = {
 288     .read = pci_read,
 289     .write = pci_write,
 290     .endianness = DEVICE_LITTLE_ENDIAN,
 291     .valid = {
 292         .min_access_size = 4,
 293         .max_access_size = 4,
 294     },
 295 };
 296
 297 void acpi_pcihp_init(Object *owner, AcpiPciHpState *s, PCIBus *root_bus,
 298                      MemoryRegion *address_space_io, bool bridges_enabled)
 299 {
 300     s->io_len = ACPI_PCIHP_SIZE;
 301     s->io_base = ACPI_PCIHP_ADDR;
 302
 303     s->root= root_bus;
 304     s->legacy_piix = !bridges_enabled;
 305
 306     if (s->legacy_piix) {
 307         unsigned *bus_bsel = g_malloc(sizeof *bus_bsel);
 308
 309         s->io_len = ACPI_PCIHP_LEGACY_SIZE;
 310
 311         *bus_bsel = ACPI_PCIHP_BSEL_DEFAULT;
 312         object_property_add_uint32_ptr(OBJECT(root_bus), ACPI_PCIHP_PROP_BSEL,
 313                                        bus_bsel, NULL);
 314     }
 315
 316     memory_region_init_io(&s->io, owner, &acpi_pcihp_io_ops, s,
 317                           "acpi-pci-hotplug", s->io_len);
 318     memory_region_add_subregion(address_space_io, s->io_base, &s->io);
 319
 320     object_property_add_uint16_ptr(owner, ACPI_PCIHP_IO_BASE_PROP, &s->io_base,
 321                                    &error_abort);
 322     object_property_add_uint16_ptr(owner, ACPI_PCIHP_IO_LEN_PROP, &s->io_len,
 323                                    &error_abort);
 324 }
 325
 326 const VMStateDescription vmstate_acpi_pcihp_pci_status = {
 327     .name = "acpi_pcihp_pci_status",
 328     .version_id = 1,
 329     .minimum_version_id = 1,
 330     .fields = (VMStateField[]) {
 331         VMSTATE_UINT32(up, AcpiPciHpPciStatus),
 332         VMSTATE_UINT32(down, AcpiPciHpPciStatus),
 333         VMSTATE_END_OF_LIST()
 334     }
 335 };