2 * ASPEED AST2400 SMC Controller (SPI Flash Only)
4 * Copyright (C) 2016 IBM Corp.
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "hw/sysbus.h"
27 #include "sysemu/sysemu.h"
29 #include "include/qemu/error-report.h"
30 #include "exec/address-spaces.h"
32 #include "hw/ssi/aspeed_smc.h"
34 /* CE Type Setting Register */
35 #define R_CONF (0x00 / 4)
36 #define CONF_LEGACY_DISABLE (1 << 31)
37 #define CONF_ENABLE_W4 20
38 #define CONF_ENABLE_W3 19
39 #define CONF_ENABLE_W2 18
40 #define CONF_ENABLE_W1 17
41 #define CONF_ENABLE_W0 16
42 #define CONF_FLASH_TYPE4 9
43 #define CONF_FLASH_TYPE3 7
44 #define CONF_FLASH_TYPE2 5
45 #define CONF_FLASH_TYPE1 3
46 #define CONF_FLASH_TYPE0 1
48 /* CE Control Register */
49 #define R_CE_CTRL (0x04 / 4)
50 #define CTRL_EXTENDED4 4 /* 32 bit addressing for SPI */
51 #define CTRL_EXTENDED3 3 /* 32 bit addressing for SPI */
52 #define CTRL_EXTENDED2 2 /* 32 bit addressing for SPI */
53 #define CTRL_EXTENDED1 1 /* 32 bit addressing for SPI */
54 #define CTRL_EXTENDED0 0 /* 32 bit addressing for SPI */
56 /* Interrupt Control and Status Register */
57 #define R_INTR_CTRL (0x08 / 4)
58 #define INTR_CTRL_DMA_STATUS (1 << 11)
59 #define INTR_CTRL_CMD_ABORT_STATUS (1 << 10)
60 #define INTR_CTRL_WRITE_PROTECT_STATUS (1 << 9)
61 #define INTR_CTRL_DMA_EN (1 << 3)
62 #define INTR_CTRL_CMD_ABORT_EN (1 << 2)
63 #define INTR_CTRL_WRITE_PROTECT_EN (1 << 1)
65 /* CEx Control Register */
66 #define R_CTRL0 (0x10 / 4)
67 #define CTRL_CMD_SHIFT 16
68 #define CTRL_CMD_MASK 0xff
69 #define CTRL_CE_STOP_ACTIVE (1 << 2)
70 #define CTRL_CMD_MODE_MASK 0x3
71 #define CTRL_READMODE 0x0
72 #define CTRL_FREADMODE 0x1
73 #define CTRL_WRITEMODE 0x2
74 #define CTRL_USERMODE 0x3
75 #define R_CTRL1 (0x14 / 4)
76 #define R_CTRL2 (0x18 / 4)
77 #define R_CTRL3 (0x1C / 4)
78 #define R_CTRL4 (0x20 / 4)
80 /* CEx Segment Address Register */
81 #define R_SEG_ADDR0 (0x30 / 4)
82 #define SEG_SIZE_SHIFT 24 /* 8MB units */
83 #define SEG_SIZE_MASK 0x7f
84 #define SEG_START_SHIFT 16 /* address bit [A29-A23] */
85 #define SEG_START_MASK 0x7f
86 #define R_SEG_ADDR1 (0x34 / 4)
87 #define R_SEG_ADDR2 (0x38 / 4)
88 #define R_SEG_ADDR3 (0x3C / 4)
89 #define R_SEG_ADDR4 (0x40 / 4)
91 /* Misc Control Register #1 */
92 #define R_MISC_CTRL1 (0x50 / 4)
94 /* Misc Control Register #2 */
95 #define R_MISC_CTRL2 (0x54 / 4)
97 /* DMA Control/Status Register */
98 #define R_DMA_CTRL (0x80 / 4)
99 #define DMA_CTRL_DELAY_MASK 0xf
100 #define DMA_CTRL_DELAY_SHIFT 8
101 #define DMA_CTRL_FREQ_MASK 0xf
102 #define DMA_CTRL_FREQ_SHIFT 4
103 #define DMA_CTRL_MODE (1 << 3)
104 #define DMA_CTRL_CKSUM (1 << 2)
105 #define DMA_CTRL_DIR (1 << 1)
106 #define DMA_CTRL_EN (1 << 0)
108 /* DMA Flash Side Address */
109 #define R_DMA_FLASH_ADDR (0x84 / 4)
111 /* DMA DRAM Side Address */
112 #define R_DMA_DRAM_ADDR (0x88 / 4)
114 /* DMA Length Register */
115 #define R_DMA_LEN (0x8C / 4)
117 /* Checksum Calculation Result */
118 #define R_DMA_CHECKSUM (0x90 / 4)
120 /* Misc Control Register #2 */
121 #define R_TIMINGS (0x94 / 4)
123 /* SPI controller registers and bits */
124 #define R_SPI_CONF (0x00 / 4)
125 #define SPI_CONF_ENABLE_W0 0
126 #define R_SPI_CTRL0 (0x4 / 4)
127 #define R_SPI_MISC_CTRL (0x10 / 4)
128 #define R_SPI_TIMINGS (0x14 / 4)
131 * Default segments mapping addresses and size for each slave per
132 * controller. These can be changed when board is initialized with the
133 * Segment Address Registers but they don't seem do be used on the
136 static const AspeedSegments aspeed_segments_legacy
[] = {
137 { 0x10000000, 32 * 1024 * 1024 },
140 static const AspeedSegments aspeed_segments_fmc
[] = {
141 { 0x20000000, 64 * 1024 * 1024 },
142 { 0x24000000, 32 * 1024 * 1024 },
143 { 0x26000000, 32 * 1024 * 1024 },
144 { 0x28000000, 32 * 1024 * 1024 },
145 { 0x2A000000, 32 * 1024 * 1024 }
148 static const AspeedSegments aspeed_segments_spi
[] = {
149 { 0x30000000, 64 * 1024 * 1024 },
152 static const AspeedSMCController controllers
[] = {
153 { "aspeed.smc.smc", R_CONF
, R_CE_CTRL
, R_CTRL0
, R_TIMINGS
,
154 CONF_ENABLE_W0
, 5, aspeed_segments_legacy
, 0x6000000 },
155 { "aspeed.smc.fmc", R_CONF
, R_CE_CTRL
, R_CTRL0
, R_TIMINGS
,
156 CONF_ENABLE_W0
, 5, aspeed_segments_fmc
, 0x10000000 },
157 { "aspeed.smc.spi", R_SPI_CONF
, 0xff, R_SPI_CTRL0
, R_SPI_TIMINGS
,
158 SPI_CONF_ENABLE_W0
, 1, aspeed_segments_spi
, 0x10000000 },
161 static uint64_t aspeed_smc_flash_default_read(void *opaque
, hwaddr addr
,
164 qemu_log_mask(LOG_GUEST_ERROR
, "%s: To 0x%" HWADDR_PRIx
" of size %u"
165 PRIx64
"\n", __func__
, addr
, size
);
169 static void aspeed_smc_flash_default_write(void *opaque
, hwaddr addr
,
170 uint64_t data
, unsigned size
)
172 qemu_log_mask(LOG_GUEST_ERROR
, "%s: To 0x%" HWADDR_PRIx
" of size %u: 0x%"
173 PRIx64
"\n", __func__
, addr
, size
, data
);
176 static const MemoryRegionOps aspeed_smc_flash_default_ops
= {
177 .read
= aspeed_smc_flash_default_read
,
178 .write
= aspeed_smc_flash_default_write
,
179 .endianness
= DEVICE_LITTLE_ENDIAN
,
181 .min_access_size
= 1,
182 .max_access_size
= 4,
186 static inline int aspeed_smc_flash_mode(const AspeedSMCState
*s
, int cs
)
188 return s
->regs
[s
->r_ctrl0
+ cs
] & CTRL_CMD_MODE_MASK
;
191 static inline bool aspeed_smc_is_usermode(const AspeedSMCState
*s
, int cs
)
193 return aspeed_smc_flash_mode(s
, cs
) == CTRL_USERMODE
;
196 static inline bool aspeed_smc_is_writable(const AspeedSMCState
*s
, int cs
)
198 return s
->regs
[s
->r_conf
] & (1 << (s
->conf_enable_w0
+ cs
));
201 static uint64_t aspeed_smc_flash_read(void *opaque
, hwaddr addr
, unsigned size
)
203 AspeedSMCFlash
*fl
= opaque
;
204 const AspeedSMCState
*s
= fl
->controller
;
208 if (aspeed_smc_is_usermode(s
, fl
->id
)) {
209 for (i
= 0; i
< size
; i
++) {
210 ret
|= ssi_transfer(s
->spi
, 0x0) << (8 * i
);
213 qemu_log_mask(LOG_UNIMP
, "%s: usermode not implemented\n",
221 static void aspeed_smc_flash_write(void *opaque
, hwaddr addr
, uint64_t data
,
224 AspeedSMCFlash
*fl
= opaque
;
225 const AspeedSMCState
*s
= fl
->controller
;
228 if (!aspeed_smc_is_writable(s
, fl
->id
)) {
229 qemu_log_mask(LOG_GUEST_ERROR
, "%s: flash is not writable at 0x%"
230 HWADDR_PRIx
"\n", __func__
, addr
);
234 if (!aspeed_smc_is_usermode(s
, fl
->id
)) {
235 qemu_log_mask(LOG_UNIMP
, "%s: usermode not implemented\n",
240 for (i
= 0; i
< size
; i
++) {
241 ssi_transfer(s
->spi
, (data
>> (8 * i
)) & 0xff);
245 static const MemoryRegionOps aspeed_smc_flash_ops
= {
246 .read
= aspeed_smc_flash_read
,
247 .write
= aspeed_smc_flash_write
,
248 .endianness
= DEVICE_LITTLE_ENDIAN
,
250 .min_access_size
= 1,
251 .max_access_size
= 4,
255 static bool aspeed_smc_is_ce_stop_active(const AspeedSMCState
*s
, int cs
)
257 return s
->regs
[s
->r_ctrl0
+ cs
] & CTRL_CE_STOP_ACTIVE
;
260 static void aspeed_smc_update_cs(const AspeedSMCState
*s
)
264 for (i
= 0; i
< s
->num_cs
; ++i
) {
265 qemu_set_irq(s
->cs_lines
[i
], aspeed_smc_is_ce_stop_active(s
, i
));
269 static void aspeed_smc_reset(DeviceState
*d
)
271 AspeedSMCState
*s
= ASPEED_SMC(d
);
274 memset(s
->regs
, 0, sizeof s
->regs
);
276 /* Unselect all slaves */
277 for (i
= 0; i
< s
->num_cs
; ++i
) {
278 s
->regs
[s
->r_ctrl0
+ i
] |= CTRL_CE_STOP_ACTIVE
;
281 aspeed_smc_update_cs(s
);
284 static uint64_t aspeed_smc_read(void *opaque
, hwaddr addr
, unsigned int size
)
286 AspeedSMCState
*s
= ASPEED_SMC(opaque
);
290 if (addr
>= ARRAY_SIZE(s
->regs
)) {
291 qemu_log_mask(LOG_GUEST_ERROR
,
292 "%s: Out-of-bounds read at 0x%" HWADDR_PRIx
"\n",
297 if (addr
== s
->r_conf
||
298 addr
== s
->r_timings
||
299 addr
== s
->r_ce_ctrl
||
300 (addr
>= s
->r_ctrl0
&& addr
< s
->r_ctrl0
+ s
->num_cs
)) {
301 return s
->regs
[addr
];
303 qemu_log_mask(LOG_UNIMP
, "%s: not implemented: 0x%" HWADDR_PRIx
"\n",
309 static void aspeed_smc_write(void *opaque
, hwaddr addr
, uint64_t data
,
312 AspeedSMCState
*s
= ASPEED_SMC(opaque
);
313 uint32_t value
= data
;
317 if (addr
>= ARRAY_SIZE(s
->regs
)) {
318 qemu_log_mask(LOG_GUEST_ERROR
,
319 "%s: Out-of-bounds write at 0x%" HWADDR_PRIx
"\n",
324 if (addr
== s
->r_conf
||
325 addr
== s
->r_timings
||
326 addr
== s
->r_ce_ctrl
) {
327 s
->regs
[addr
] = value
;
328 } else if (addr
>= s
->r_ctrl0
&& addr
< s
->r_ctrl0
+ s
->num_cs
) {
329 s
->regs
[addr
] = value
;
330 aspeed_smc_update_cs(s
);
332 qemu_log_mask(LOG_UNIMP
, "%s: not implemented: 0x%" HWADDR_PRIx
"\n",
338 static const MemoryRegionOps aspeed_smc_ops
= {
339 .read
= aspeed_smc_read
,
340 .write
= aspeed_smc_write
,
341 .endianness
= DEVICE_LITTLE_ENDIAN
,
342 .valid
.unaligned
= true,
345 static void aspeed_smc_realize(DeviceState
*dev
, Error
**errp
)
347 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
348 AspeedSMCState
*s
= ASPEED_SMC(dev
);
349 AspeedSMCClass
*mc
= ASPEED_SMC_GET_CLASS(s
);
356 /* keep a copy under AspeedSMCState to speed up accesses */
357 s
->r_conf
= s
->ctrl
->r_conf
;
358 s
->r_ce_ctrl
= s
->ctrl
->r_ce_ctrl
;
359 s
->r_ctrl0
= s
->ctrl
->r_ctrl0
;
360 s
->r_timings
= s
->ctrl
->r_timings
;
361 s
->conf_enable_w0
= s
->ctrl
->conf_enable_w0
;
363 /* Enforce some real HW limits */
364 if (s
->num_cs
> s
->ctrl
->max_slaves
) {
365 qemu_log_mask(LOG_GUEST_ERROR
, "%s: num_cs cannot exceed: %d\n",
366 __func__
, s
->ctrl
->max_slaves
);
367 s
->num_cs
= s
->ctrl
->max_slaves
;
370 s
->spi
= ssi_create_bus(dev
, "spi");
372 /* Setup cs_lines for slaves */
373 sysbus_init_irq(sbd
, &s
->irq
);
374 s
->cs_lines
= g_new0(qemu_irq
, s
->num_cs
);
375 ssi_auto_connect_slaves(dev
, s
->cs_lines
, s
->spi
);
377 for (i
= 0; i
< s
->num_cs
; ++i
) {
378 sysbus_init_irq(sbd
, &s
->cs_lines
[i
]);
381 aspeed_smc_reset(dev
);
383 memory_region_init_io(&s
->mmio
, OBJECT(s
), &aspeed_smc_ops
, s
,
384 s
->ctrl
->name
, ASPEED_SMC_R_MAX
* 4);
385 sysbus_init_mmio(sbd
, &s
->mmio
);
388 * Memory region where flash modules are remapped
390 snprintf(name
, sizeof(name
), "%s.flash", s
->ctrl
->name
);
392 memory_region_init_io(&s
->mmio_flash
, OBJECT(s
),
393 &aspeed_smc_flash_default_ops
, s
, name
,
394 s
->ctrl
->mapping_window_size
);
395 sysbus_init_mmio(sbd
, &s
->mmio_flash
);
397 s
->flashes
= g_new0(AspeedSMCFlash
, s
->num_cs
);
399 for (i
= 0; i
< s
->num_cs
; ++i
) {
400 AspeedSMCFlash
*fl
= &s
->flashes
[i
];
402 snprintf(name
, sizeof(name
), "%s.%d", s
->ctrl
->name
, i
);
406 fl
->size
= s
->ctrl
->segments
[i
].size
;
407 memory_region_init_io(&fl
->mmio
, OBJECT(s
), &aspeed_smc_flash_ops
,
409 memory_region_add_subregion(&s
->mmio_flash
, offset
, &fl
->mmio
);
414 static const VMStateDescription vmstate_aspeed_smc
= {
415 .name
= "aspeed.smc",
417 .minimum_version_id
= 1,
418 .fields
= (VMStateField
[]) {
419 VMSTATE_UINT32_ARRAY(regs
, AspeedSMCState
, ASPEED_SMC_R_MAX
),
420 VMSTATE_END_OF_LIST()
424 static Property aspeed_smc_properties
[] = {
425 DEFINE_PROP_UINT32("num-cs", AspeedSMCState
, num_cs
, 1),
426 DEFINE_PROP_END_OF_LIST(),
429 static void aspeed_smc_class_init(ObjectClass
*klass
, void *data
)
431 DeviceClass
*dc
= DEVICE_CLASS(klass
);
432 AspeedSMCClass
*mc
= ASPEED_SMC_CLASS(klass
);
434 dc
->realize
= aspeed_smc_realize
;
435 dc
->reset
= aspeed_smc_reset
;
436 dc
->props
= aspeed_smc_properties
;
437 dc
->vmsd
= &vmstate_aspeed_smc
;
441 static const TypeInfo aspeed_smc_info
= {
442 .name
= TYPE_ASPEED_SMC
,
443 .parent
= TYPE_SYS_BUS_DEVICE
,
444 .instance_size
= sizeof(AspeedSMCState
),
445 .class_size
= sizeof(AspeedSMCClass
),
449 static void aspeed_smc_register_types(void)
453 type_register_static(&aspeed_smc_info
);
454 for (i
= 0; i
< ARRAY_SIZE(controllers
); ++i
) {
456 .name
= controllers
[i
].name
,
457 .parent
= TYPE_ASPEED_SMC
,
458 .class_init
= aspeed_smc_class_init
,
459 .class_data
= (void *)&controllers
[i
],
465 type_init(aspeed_smc_register_types
)