tcg/tcg.h

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2008 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #ifndef TCG_H
  26 #define TCG_H
  27
  28 #include "qemu-common.h"
  29 #include "qemu/bitops.h"
  30 #include "tcg-target.h"
  31
  32 /* Default target word size to pointer size.  */
  33 #ifndef TCG_TARGET_REG_BITS
  34 # if UINTPTR_MAX == UINT32_MAX
  35 #  define TCG_TARGET_REG_BITS 32
  36 # elif UINTPTR_MAX == UINT64_MAX
  37 #  define TCG_TARGET_REG_BITS 64
  38 # else
  39 #  error Unknown pointer size for tcg target
  40 # endif
  41 #endif
  42
  43 #if TCG_TARGET_REG_BITS == 32
  44 typedef int32_t tcg_target_long;
  45 typedef uint32_t tcg_target_ulong;
  46 #define TCG_PRIlx PRIx32
  47 #define TCG_PRIld PRId32
  48 #elif TCG_TARGET_REG_BITS == 64
  49 typedef int64_t tcg_target_long;
  50 typedef uint64_t tcg_target_ulong;
  51 #define TCG_PRIlx PRIx64
  52 #define TCG_PRIld PRId64
  53 #else
  54 #error unsupported
  55 #endif
  56
  57 #if TCG_TARGET_NB_REGS <= 32
  58 typedef uint32_t TCGRegSet;
  59 #elif TCG_TARGET_NB_REGS <= 64
  60 typedef uint64_t TCGRegSet;
  61 #else
  62 #error unsupported
  63 #endif
  64
  65 #if TCG_TARGET_REG_BITS == 32
  66 /* Turn some undef macros into false macros.  */
  67 #define TCG_TARGET_HAS_trunc_shr_i32    0
  68 #define TCG_TARGET_HAS_div_i64          0
  69 #define TCG_TARGET_HAS_rem_i64          0
  70 #define TCG_TARGET_HAS_div2_i64         0
  71 #define TCG_TARGET_HAS_rot_i64          0
  72 #define TCG_TARGET_HAS_ext8s_i64        0
  73 #define TCG_TARGET_HAS_ext16s_i64       0
  74 #define TCG_TARGET_HAS_ext32s_i64       0
  75 #define TCG_TARGET_HAS_ext8u_i64        0
  76 #define TCG_TARGET_HAS_ext16u_i64       0
  77 #define TCG_TARGET_HAS_ext32u_i64       0
  78 #define TCG_TARGET_HAS_bswap16_i64      0
  79 #define TCG_TARGET_HAS_bswap32_i64      0
  80 #define TCG_TARGET_HAS_bswap64_i64      0
  81 #define TCG_TARGET_HAS_neg_i64          0
  82 #define TCG_TARGET_HAS_not_i64          0
  83 #define TCG_TARGET_HAS_andc_i64         0
  84 #define TCG_TARGET_HAS_orc_i64          0
  85 #define TCG_TARGET_HAS_eqv_i64          0
  86 #define TCG_TARGET_HAS_nand_i64         0
  87 #define TCG_TARGET_HAS_nor_i64          0
  88 #define TCG_TARGET_HAS_deposit_i64      0
  89 #define TCG_TARGET_HAS_movcond_i64      0
  90 #define TCG_TARGET_HAS_add2_i64         0
  91 #define TCG_TARGET_HAS_sub2_i64         0
  92 #define TCG_TARGET_HAS_mulu2_i64        0
  93 #define TCG_TARGET_HAS_muls2_i64        0
  94 #define TCG_TARGET_HAS_muluh_i64        0
  95 #define TCG_TARGET_HAS_mulsh_i64        0
  96 /* Turn some undef macros into true macros.  */
  97 #define TCG_TARGET_HAS_add2_i32         1
  98 #define TCG_TARGET_HAS_sub2_i32         1
  99 #endif
 100
 101 #ifndef TCG_TARGET_deposit_i32_valid
 102 #define TCG_TARGET_deposit_i32_valid(ofs, len) 1
 103 #endif
 104 #ifndef TCG_TARGET_deposit_i64_valid
 105 #define TCG_TARGET_deposit_i64_valid(ofs, len) 1
 106 #endif
 107
 108 /* Only one of DIV or DIV2 should be defined.  */
 109 #if defined(TCG_TARGET_HAS_div_i32)
 110 #define TCG_TARGET_HAS_div2_i32         0
 111 #elif defined(TCG_TARGET_HAS_div2_i32)
 112 #define TCG_TARGET_HAS_div_i32          0
 113 #define TCG_TARGET_HAS_rem_i32          0
 114 #endif
 115 #if defined(TCG_TARGET_HAS_div_i64)
 116 #define TCG_TARGET_HAS_div2_i64         0
 117 #elif defined(TCG_TARGET_HAS_div2_i64)
 118 #define TCG_TARGET_HAS_div_i64          0
 119 #define TCG_TARGET_HAS_rem_i64          0
 120 #endif
 121
 122 /* For 32-bit targets, some sort of unsigned widening multiply is required.  */
 123 #if TCG_TARGET_REG_BITS == 32 \
 124     && !(defined(TCG_TARGET_HAS_mulu2_i32) \
 125          || defined(TCG_TARGET_HAS_muluh_i32))
 126 # error "Missing unsigned widening multiply"
 127 #endif
 128
 129 typedef enum TCGOpcode {
 130 #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name,
 131 #include "tcg-opc.h"
 132 #undef DEF
 133     NB_OPS,
 134 } TCGOpcode;
 135
 136 #define tcg_regset_clear(d) (d) = 0
 137 #define tcg_regset_set(d, s) (d) = (s)
 138 #define tcg_regset_set32(d, reg, val32) (d) |= (val32) << (reg)
 139 #define tcg_regset_set_reg(d, r) (d) |= 1L << (r)
 140 #define tcg_regset_reset_reg(d, r) (d) &= ~(1L << (r))
 141 #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1)
 142 #define tcg_regset_or(d, a, b) (d) = (a) | (b)
 143 #define tcg_regset_and(d, a, b) (d) = (a) & (b)
 144 #define tcg_regset_andnot(d, a, b) (d) = (a) & ~(b)
 145 #define tcg_regset_not(d, a) (d) = ~(a)
 146
 147 #ifndef TCG_TARGET_INSN_UNIT_SIZE
 148 # error "Missing TCG_TARGET_INSN_UNIT_SIZE"
 149 #elif TCG_TARGET_INSN_UNIT_SIZE == 1
 150 typedef uint8_t tcg_insn_unit;
 151 #elif TCG_TARGET_INSN_UNIT_SIZE == 2
 152 typedef uint16_t tcg_insn_unit;
 153 #elif TCG_TARGET_INSN_UNIT_SIZE == 4
 154 typedef uint32_t tcg_insn_unit;
 155 #elif TCG_TARGET_INSN_UNIT_SIZE == 8
 156 typedef uint64_t tcg_insn_unit;
 157 #else
 158 /* The port better have done this.  */
 159 #endif
 160
 161
 162 typedef struct TCGRelocation {
 163     struct TCGRelocation *next;
 164     int type;
 165     tcg_insn_unit *ptr;
 166     intptr_t addend;
 167 } TCGRelocation;
 168
 169 typedef struct TCGLabel {
 170     unsigned has_value : 1;
 171     unsigned id : 31;
 172     union {
 173         uintptr_t value;
 174         tcg_insn_unit *value_ptr;
 175         TCGRelocation *first_reloc;
 176     } u;
 177 } TCGLabel;
 178
 179 typedef struct TCGPool {
 180     struct TCGPool *next;
 181     int size;
 182     uint8_t data[0] __attribute__ ((aligned));
 183 } TCGPool;
 184
 185 #define TCG_POOL_CHUNK_SIZE 32768
 186
 187 #define TCG_MAX_TEMPS 512
 188
 189 /* when the size of the arguments of a called function is smaller than
 190    this value, they are statically allocated in the TB stack frame */
 191 #define TCG_STATIC_CALL_ARGS_SIZE 128
 192
 193 typedef enum TCGType {
 194     TCG_TYPE_I32,
 195     TCG_TYPE_I64,
 196     TCG_TYPE_COUNT, /* number of different types */
 197
 198     /* An alias for the size of the host register.  */
 199 #if TCG_TARGET_REG_BITS == 32
 200     TCG_TYPE_REG = TCG_TYPE_I32,
 201 #else
 202     TCG_TYPE_REG = TCG_TYPE_I64,
 203 #endif
 204
 205     /* An alias for the size of the native pointer.  */
 206 #if UINTPTR_MAX == UINT32_MAX
 207     TCG_TYPE_PTR = TCG_TYPE_I32,
 208 #else
 209     TCG_TYPE_PTR = TCG_TYPE_I64,
 210 #endif
 211
 212     /* An alias for the size of the target "long", aka register.  */
 213 #if TARGET_LONG_BITS == 64
 214     TCG_TYPE_TL = TCG_TYPE_I64,
 215 #else
 216     TCG_TYPE_TL = TCG_TYPE_I32,
 217 #endif
 218 } TCGType;
 219
 220 /* Constants for qemu_ld and qemu_st for the Memory Operation field.  */
 221 typedef enum TCGMemOp {
 222     MO_8     = 0,
 223     MO_16    = 1,
 224     MO_32    = 2,
 225     MO_64    = 3,
 226     MO_SIZE  = 3,   /* Mask for the above.  */
 227
 228     MO_SIGN  = 4,   /* Sign-extended, otherwise zero-extended.  */
 229
 230     MO_BSWAP = 8,   /* Host reverse endian.  */
 231 #ifdef HOST_WORDS_BIGENDIAN
 232     MO_LE    = MO_BSWAP,
 233     MO_BE    = 0,
 234 #else
 235     MO_LE    = 0,
 236     MO_BE    = MO_BSWAP,
 237 #endif
 238 #ifdef TARGET_WORDS_BIGENDIAN
 239     MO_TE    = MO_BE,
 240 #else
 241     MO_TE    = MO_LE,
 242 #endif
 243
 244     /* MO_UNALN accesses are never checked for alignment.
 245        MO_ALIGN accesses will result in a call to the CPU's
 246        do_unaligned_access hook if the guest address is not aligned.
 247        The default depends on whether the target CPU defines ALIGNED_ONLY.  */
 248     MO_AMASK = 16,
 249 #ifdef ALIGNED_ONLY
 250     MO_ALIGN = 0,
 251     MO_UNALN = MO_AMASK,
 252 #else
 253     MO_ALIGN = MO_AMASK,
 254     MO_UNALN = 0,
 255 #endif
 256
 257     /* Combinations of the above, for ease of use.  */
 258     MO_UB    = MO_8,
 259     MO_UW    = MO_16,
 260     MO_UL    = MO_32,
 261     MO_SB    = MO_SIGN | MO_8,
 262     MO_SW    = MO_SIGN | MO_16,
 263     MO_SL    = MO_SIGN | MO_32,
 264     MO_Q     = MO_64,
 265
 266     MO_LEUW  = MO_LE | MO_UW,
 267     MO_LEUL  = MO_LE | MO_UL,
 268     MO_LESW  = MO_LE | MO_SW,
 269     MO_LESL  = MO_LE | MO_SL,
 270     MO_LEQ   = MO_LE | MO_Q,
 271
 272     MO_BEUW  = MO_BE | MO_UW,
 273     MO_BEUL  = MO_BE | MO_UL,
 274     MO_BESW  = MO_BE | MO_SW,
 275     MO_BESL  = MO_BE | MO_SL,
 276     MO_BEQ   = MO_BE | MO_Q,
 277
 278     MO_TEUW  = MO_TE | MO_UW,
 279     MO_TEUL  = MO_TE | MO_UL,
 280     MO_TESW  = MO_TE | MO_SW,
 281     MO_TESL  = MO_TE | MO_SL,
 282     MO_TEQ   = MO_TE | MO_Q,
 283
 284     MO_SSIZE = MO_SIZE | MO_SIGN,
 285 } TCGMemOp;
 286
 287 typedef tcg_target_ulong TCGArg;
 288
 289 /* Define a type and accessor macros for variables.  Using pointer types
 290    is nice because it gives some level of type safely.  Converting to and
 291    from intptr_t rather than int reduces the number of sign-extension
 292    instructions that get implied on 64-bit hosts.  Users of tcg_gen_* don't
 293    need to know about any of this, and should treat TCGv as an opaque type.
 294    In addition we do typechecking for different types of variables.  TCGv_i32
 295    and TCGv_i64 are 32/64-bit variables respectively.  TCGv and TCGv_ptr
 296    are aliases for target_ulong and host pointer sized values respectively.  */
 297
 298 typedef struct TCGv_i32_d *TCGv_i32;
 299 typedef struct TCGv_i64_d *TCGv_i64;
 300 typedef struct TCGv_ptr_d *TCGv_ptr;
 301
 302 static inline TCGv_i32 QEMU_ARTIFICIAL MAKE_TCGV_I32(intptr_t i)
 303 {
 304     return (TCGv_i32)i;
 305 }
 306
 307 static inline TCGv_i64 QEMU_ARTIFICIAL MAKE_TCGV_I64(intptr_t i)
 308 {
 309     return (TCGv_i64)i;
 310 }
 311
 312 static inline TCGv_ptr QEMU_ARTIFICIAL MAKE_TCGV_PTR(intptr_t i)
 313 {
 314     return (TCGv_ptr)i;
 315 }
 316
 317 static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_I32(TCGv_i32 t)
 318 {
 319     return (intptr_t)t;
 320 }
 321
 322 static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_I64(TCGv_i64 t)
 323 {
 324     return (intptr_t)t;
 325 }
 326
 327 static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_PTR(TCGv_ptr t)
 328 {
 329     return (intptr_t)t;
 330 }
 331
 332 #if TCG_TARGET_REG_BITS == 32
 333 #define TCGV_LOW(t) MAKE_TCGV_I32(GET_TCGV_I64(t))
 334 #define TCGV_HIGH(t) MAKE_TCGV_I32(GET_TCGV_I64(t) + 1)
 335 #endif
 336
 337 #define TCGV_EQUAL_I32(a, b) (GET_TCGV_I32(a) == GET_TCGV_I32(b))
 338 #define TCGV_EQUAL_I64(a, b) (GET_TCGV_I64(a) == GET_TCGV_I64(b))
 339 #define TCGV_EQUAL_PTR(a, b) (GET_TCGV_PTR(a) == GET_TCGV_PTR(b))
 340
 341 /* Dummy definition to avoid compiler warnings.  */
 342 #define TCGV_UNUSED_I32(x) x = MAKE_TCGV_I32(-1)
 343 #define TCGV_UNUSED_I64(x) x = MAKE_TCGV_I64(-1)
 344 #define TCGV_UNUSED_PTR(x) x = MAKE_TCGV_PTR(-1)
 345
 346 #define TCGV_IS_UNUSED_I32(x) (GET_TCGV_I32(x) == -1)
 347 #define TCGV_IS_UNUSED_I64(x) (GET_TCGV_I64(x) == -1)
 348 #define TCGV_IS_UNUSED_PTR(x) (GET_TCGV_PTR(x) == -1)
 349
 350 /* call flags */
 351 /* Helper does not read globals (either directly or through an exception). It
 352    implies TCG_CALL_NO_WRITE_GLOBALS. */
 353 #define TCG_CALL_NO_READ_GLOBALS    0x0010
 354 /* Helper does not write globals */
 355 #define TCG_CALL_NO_WRITE_GLOBALS   0x0020
 356 /* Helper can be safely suppressed if the return value is not used. */
 357 #define TCG_CALL_NO_SIDE_EFFECTS    0x0040
 358
 359 /* convenience version of most used call flags */
 360 #define TCG_CALL_NO_RWG         TCG_CALL_NO_READ_GLOBALS
 361 #define TCG_CALL_NO_WG          TCG_CALL_NO_WRITE_GLOBALS
 362 #define TCG_CALL_NO_SE          TCG_CALL_NO_SIDE_EFFECTS
 363 #define TCG_CALL_NO_RWG_SE      (TCG_CALL_NO_RWG | TCG_CALL_NO_SE)
 364 #define TCG_CALL_NO_WG_SE       (TCG_CALL_NO_WG | TCG_CALL_NO_SE)
 365
 366 /* used to align parameters */
 367 #define TCG_CALL_DUMMY_TCGV     MAKE_TCGV_I32(-1)
 368 #define TCG_CALL_DUMMY_ARG      ((TCGArg)(-1))
 369
 370 /* Conditions.  Note that these are laid out for easy manipulation by
 371    the functions below:
 372      bit 0 is used for inverting;
 373      bit 1 is signed,
 374      bit 2 is unsigned,
 375      bit 3 is used with bit 0 for swapping signed/unsigned.  */
 376 typedef enum {
 377     /* non-signed */
 378     TCG_COND_NEVER  = 0 | 0 | 0 | 0,
 379     TCG_COND_ALWAYS = 0 | 0 | 0 | 1,
 380     TCG_COND_EQ     = 8 | 0 | 0 | 0,
 381     TCG_COND_NE     = 8 | 0 | 0 | 1,
 382     /* signed */
 383     TCG_COND_LT     = 0 | 0 | 2 | 0,
 384     TCG_COND_GE     = 0 | 0 | 2 | 1,
 385     TCG_COND_LE     = 8 | 0 | 2 | 0,
 386     TCG_COND_GT     = 8 | 0 | 2 | 1,
 387     /* unsigned */
 388     TCG_COND_LTU    = 0 | 4 | 0 | 0,
 389     TCG_COND_GEU    = 0 | 4 | 0 | 1,
 390     TCG_COND_LEU    = 8 | 4 | 0 | 0,
 391     TCG_COND_GTU    = 8 | 4 | 0 | 1,
 392 } TCGCond;
 393
 394 /* Invert the sense of the comparison.  */
 395 static inline TCGCond tcg_invert_cond(TCGCond c)
 396 {
 397     return (TCGCond)(c ^ 1);
 398 }
 399
 400 /* Swap the operands in a comparison.  */
 401 static inline TCGCond tcg_swap_cond(TCGCond c)
 402 {
 403     return c & 6 ? (TCGCond)(c ^ 9) : c;
 404 }
 405
 406 /* Create an "unsigned" version of a "signed" comparison.  */
 407 static inline TCGCond tcg_unsigned_cond(TCGCond c)
 408 {
 409     return c & 2 ? (TCGCond)(c ^ 6) : c;
 410 }
 411
 412 /* Must a comparison be considered unsigned?  */
 413 static inline bool is_unsigned_cond(TCGCond c)
 414 {
 415     return (c & 4) != 0;
 416 }
 417
 418 /* Create a "high" version of a double-word comparison.
 419    This removes equality from a LTE or GTE comparison.  */
 420 static inline TCGCond tcg_high_cond(TCGCond c)
 421 {
 422     switch (c) {
 423     case TCG_COND_GE:
 424     case TCG_COND_LE:
 425     case TCG_COND_GEU:
 426     case TCG_COND_LEU:
 427         return (TCGCond)(c ^ 8);
 428     default:
 429         return c;
 430     }
 431 }
 432
 433 typedef enum TCGTempVal {
 434     TEMP_VAL_DEAD,
 435     TEMP_VAL_REG,
 436     TEMP_VAL_MEM,
 437     TEMP_VAL_CONST,
 438 } TCGTempVal;
 439
 440 typedef struct TCGTemp {
 441     unsigned int reg:8;
 442     unsigned int mem_reg:8;
 443     TCGTempVal val_type:8;
 444     TCGType base_type:8;
 445     TCGType type:8;
 446     unsigned int fixed_reg:1;
 447     unsigned int mem_coherent:1;
 448     unsigned int mem_allocated:1;
 449     unsigned int temp_local:1; /* If true, the temp is saved across
 450                                   basic blocks. Otherwise, it is not
 451                                   preserved across basic blocks. */
 452     unsigned int temp_allocated:1; /* never used for code gen */
 453
 454     tcg_target_long val;
 455     intptr_t mem_offset;
 456     const char *name;
 457 } TCGTemp;
 458
 459 typedef struct TCGContext TCGContext;
 460
 461 typedef struct TCGTempSet {
 462     unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)];
 463 } TCGTempSet;
 464
 465 typedef struct TCGOp {
 466     TCGOpcode opc   : 8;
 467
 468     /* The number of out and in parameter for a call.  */
 469     unsigned callo  : 2;
 470     unsigned calli  : 6;
 471
 472     /* Index of the arguments for this op, or -1 for zero-operand ops.  */
 473     signed args     : 16;
 474
 475     /* Index of the prex/next op, or -1 for the end of the list.  */
 476     signed prev     : 16;
 477     signed next     : 16;
 478 } TCGOp;
 479
 480 QEMU_BUILD_BUG_ON(NB_OPS > 0xff);
 481 QEMU_BUILD_BUG_ON(OPC_BUF_SIZE >= 0x7fff);
 482 QEMU_BUILD_BUG_ON(OPPARAM_BUF_SIZE >= 0x7fff);
 483
 484 struct TCGContext {
 485     uint8_t *pool_cur, *pool_end;
 486     TCGPool *pool_first, *pool_current, *pool_first_large;
 487     int nb_labels;
 488     int nb_globals;
 489     int nb_temps;
 490
 491     /* goto_tb support */
 492     tcg_insn_unit *code_buf;
 493     uintptr_t *tb_next;
 494     uint16_t *tb_next_offset;
 495     uint16_t *tb_jmp_offset; /* != NULL if USE_DIRECT_JUMP */
 496
 497     /* liveness analysis */
 498     uint16_t *op_dead_args; /* for each operation, each bit tells if the
 499                                corresponding argument is dead */
 500     uint8_t *op_sync_args;  /* for each operation, each bit tells if the
 501                                corresponding output argument needs to be
 502                                sync to memory. */
 503
 504     TCGRegSet reserved_regs;
 505     intptr_t current_frame_offset;
 506     intptr_t frame_start;
 507     intptr_t frame_end;
 508     int frame_reg;
 509
 510     tcg_insn_unit *code_ptr;
 511
 512     GHashTable *helpers;
 513
 514 #ifdef CONFIG_PROFILER
 515     /* profiling info */
 516     int64_t tb_count1;
 517     int64_t tb_count;
 518     int64_t op_count; /* total insn count */
 519     int op_count_max; /* max insn per TB */
 520     int64_t temp_count;
 521     int temp_count_max;
 522     int64_t del_op_count;
 523     int64_t code_in_len;
 524     int64_t code_out_len;
 525     int64_t interm_time;
 526     int64_t code_time;
 527     int64_t la_time;
 528     int64_t opt_time;
 529     int64_t restore_count;
 530     int64_t restore_time;
 531 #endif
 532
 533 #ifdef CONFIG_DEBUG_TCG
 534     int temps_in_use;
 535     int goto_tb_issue_mask;
 536 #endif
 537
 538     int gen_first_op_idx;
 539     int gen_last_op_idx;
 540     int gen_next_op_idx;
 541     int gen_next_parm_idx;
 542
 543     /* Code generation.  Note that we specifically do not use tcg_insn_unit
 544        here, because there's too much arithmetic throughout that relies
 545        on addition and subtraction working on bytes.  Rely on the GCC
 546        extension that allows arithmetic on void*.  */
 547     int code_gen_max_blocks;
 548     void *code_gen_prologue;
 549     void *code_gen_buffer;
 550     size_t code_gen_buffer_size;
 551     /* threshold to flush the translated code buffer */
 552     size_t code_gen_buffer_max_size;
 553     void *code_gen_ptr;
 554
 555     TBContext tb_ctx;
 556
 557     /* The TCGBackendData structure is private to tcg-target.c.  */
 558     struct TCGBackendData *be;
 559
 560     TCGTempSet free_temps[TCG_TYPE_COUNT * 2];
 561     TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */
 562
 563     /* tells in which temporary a given register is. It does not take
 564        into account fixed registers */
 565     int reg_to_temp[TCG_TARGET_NB_REGS];
 566
 567     TCGOp gen_op_buf[OPC_BUF_SIZE];
 568     TCGArg gen_opparam_buf[OPPARAM_BUF_SIZE];
 569
 570     target_ulong gen_opc_pc[OPC_BUF_SIZE];
 571     uint16_t gen_opc_icount[OPC_BUF_SIZE];
 572     uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
 573 };
 574
 575 extern TCGContext tcg_ctx;
 576
 577 /* The number of opcodes emitted so far.  */
 578 static inline int tcg_op_buf_count(void)
 579 {
 580     return tcg_ctx.gen_next_op_idx;
 581 }
 582
 583 /* Test for whether to terminate the TB for using too many opcodes.  */
 584 static inline bool tcg_op_buf_full(void)
 585 {
 586     return tcg_op_buf_count() >= OPC_MAX_SIZE;
 587 }
 588
 589 /* pool based memory allocation */
 590
 591 void *tcg_malloc_internal(TCGContext *s, int size);
 592 void tcg_pool_reset(TCGContext *s);
 593 void tcg_pool_delete(TCGContext *s);
 594
 595 static inline void *tcg_malloc(int size)
 596 {
 597     TCGContext *s = &tcg_ctx;
 598     uint8_t *ptr, *ptr_end;
 599     size = (size + sizeof(long) - 1) & ~(sizeof(long) - 1);
 600     ptr = s->pool_cur;
 601     ptr_end = ptr + size;
 602     if (unlikely(ptr_end > s->pool_end)) {
 603         return tcg_malloc_internal(&tcg_ctx, size);
 604     } else {
 605         s->pool_cur = ptr_end;
 606         return ptr;
 607     }
 608 }
 609
 610 void tcg_context_init(TCGContext *s);
 611 void tcg_prologue_init(TCGContext *s);
 612 void tcg_func_start(TCGContext *s);
 613
 614 int tcg_gen_code(TCGContext *s, tcg_insn_unit *gen_code_buf);
 615 int tcg_gen_code_search_pc(TCGContext *s, tcg_insn_unit *gen_code_buf,
 616                            long offset);
 617
 618 void tcg_set_frame(TCGContext *s, int reg, intptr_t start, intptr_t size);
 619
 620 TCGv_i32 tcg_global_reg_new_i32(int reg, const char *name);
 621 TCGv_i32 tcg_global_mem_new_i32(int reg, intptr_t offset, const char *name);
 622 TCGv_i32 tcg_temp_new_internal_i32(int temp_local);
 623 static inline TCGv_i32 tcg_temp_new_i32(void)
 624 {
 625     return tcg_temp_new_internal_i32(0);
 626 }
 627 static inline TCGv_i32 tcg_temp_local_new_i32(void)
 628 {
 629     return tcg_temp_new_internal_i32(1);
 630 }
 631 void tcg_temp_free_i32(TCGv_i32 arg);
 632 char *tcg_get_arg_str_i32(TCGContext *s, char *buf, int buf_size, TCGv_i32 arg);
 633
 634 TCGv_i64 tcg_global_reg_new_i64(int reg, const char *name);
 635 TCGv_i64 tcg_global_mem_new_i64(int reg, intptr_t offset, const char *name);
 636 TCGv_i64 tcg_temp_new_internal_i64(int temp_local);
 637 static inline TCGv_i64 tcg_temp_new_i64(void)
 638 {
 639     return tcg_temp_new_internal_i64(0);
 640 }
 641 static inline TCGv_i64 tcg_temp_local_new_i64(void)
 642 {
 643     return tcg_temp_new_internal_i64(1);
 644 }
 645 void tcg_temp_free_i64(TCGv_i64 arg);
 646 char *tcg_get_arg_str_i64(TCGContext *s, char *buf, int buf_size, TCGv_i64 arg);
 647
 648 #if defined(CONFIG_DEBUG_TCG)
 649 /* If you call tcg_clear_temp_count() at the start of a section of
 650  * code which is not supposed to leak any TCG temporaries, then
 651  * calling tcg_check_temp_count() at the end of the section will
 652  * return 1 if the section did in fact leak a temporary.
 653  */
 654 void tcg_clear_temp_count(void);
 655 int tcg_check_temp_count(void);
 656 #else
 657 #define tcg_clear_temp_count() do { } while (0)
 658 #define tcg_check_temp_count() 0
 659 #endif
 660
 661 void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf);
 662 void tcg_dump_op_count(FILE *f, fprintf_function cpu_fprintf);
 663
 664 #define TCG_CT_ALIAS  0x80
 665 #define TCG_CT_IALIAS 0x40
 666 #define TCG_CT_REG    0x01
 667 #define TCG_CT_CONST  0x02 /* any constant of register size */
 668
 669 typedef struct TCGArgConstraint {
 670     uint16_t ct;
 671     uint8_t alias_index;
 672     union {
 673         TCGRegSet regs;
 674     } u;
 675 } TCGArgConstraint;
 676
 677 #define TCG_MAX_OP_ARGS 16
 678
 679 /* Bits for TCGOpDef->flags, 8 bits available.  */
 680 enum {
 681     /* Instruction defines the end of a basic block.  */
 682     TCG_OPF_BB_END       = 0x01,
 683     /* Instruction clobbers call registers and potentially update globals.  */
 684     TCG_OPF_CALL_CLOBBER = 0x02,
 685     /* Instruction has side effects: it cannot be removed if its outputs
 686        are not used, and might trigger exceptions.  */
 687     TCG_OPF_SIDE_EFFECTS = 0x04,
 688     /* Instruction operands are 64-bits (otherwise 32-bits).  */
 689     TCG_OPF_64BIT        = 0x08,
 690     /* Instruction is optional and not implemented by the host, or insn
 691        is generic and should not be implemened by the host.  */
 692     TCG_OPF_NOT_PRESENT  = 0x10,
 693 };
 694
 695 typedef struct TCGOpDef {
 696     const char *name;
 697     uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args;
 698     uint8_t flags;
 699     TCGArgConstraint *args_ct;
 700     int *sorted_args;
 701 #if defined(CONFIG_DEBUG_TCG)
 702     int used;
 703 #endif
 704 } TCGOpDef;
 705
 706 extern TCGOpDef tcg_op_defs[];
 707 extern const size_t tcg_op_defs_max;
 708
 709 typedef struct TCGTargetOpDef {
 710     TCGOpcode op;
 711     const char *args_ct_str[TCG_MAX_OP_ARGS];
 712 } TCGTargetOpDef;
 713
 714 #define tcg_abort() \
 715 do {\
 716     fprintf(stderr, "%s:%d: tcg fatal error\n", __FILE__, __LINE__);\
 717     abort();\
 718 } while (0)
 719
 720 #ifdef CONFIG_DEBUG_TCG
 721 # define tcg_debug_assert(X) do { assert(X); } while (0)
 722 #elif QEMU_GNUC_PREREQ(4, 5)
 723 # define tcg_debug_assert(X) \
 724     do { if (!(X)) { __builtin_unreachable(); } } while (0)
 725 #else
 726 # define tcg_debug_assert(X) do { (void)(X); } while (0)
 727 #endif
 728
 729 void tcg_add_target_add_op_defs(const TCGTargetOpDef *tdefs);
 730
 731 #if UINTPTR_MAX == UINT32_MAX
 732 #define TCGV_NAT_TO_PTR(n) MAKE_TCGV_PTR(GET_TCGV_I32(n))
 733 #define TCGV_PTR_TO_NAT(n) MAKE_TCGV_I32(GET_TCGV_PTR(n))
 734
 735 #define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i32((intptr_t)(V)))
 736 #define tcg_global_reg_new_ptr(R, N) \
 737     TCGV_NAT_TO_PTR(tcg_global_reg_new_i32((R), (N)))
 738 #define tcg_global_mem_new_ptr(R, O, N) \
 739     TCGV_NAT_TO_PTR(tcg_global_mem_new_i32((R), (O), (N)))
 740 #define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i32())
 741 #define tcg_temp_free_ptr(T) tcg_temp_free_i32(TCGV_PTR_TO_NAT(T))
 742 #else
 743 #define TCGV_NAT_TO_PTR(n) MAKE_TCGV_PTR(GET_TCGV_I64(n))
 744 #define TCGV_PTR_TO_NAT(n) MAKE_TCGV_I64(GET_TCGV_PTR(n))
 745
 746 #define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i64((intptr_t)(V)))
 747 #define tcg_global_reg_new_ptr(R, N) \
 748     TCGV_NAT_TO_PTR(tcg_global_reg_new_i64((R), (N)))
 749 #define tcg_global_mem_new_ptr(R, O, N) \
 750     TCGV_NAT_TO_PTR(tcg_global_mem_new_i64((R), (O), (N)))
 751 #define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i64())
 752 #define tcg_temp_free_ptr(T) tcg_temp_free_i64(TCGV_PTR_TO_NAT(T))
 753 #endif
 754
 755 void tcg_gen_callN(TCGContext *s, void *func,
 756                    TCGArg ret, int nargs, TCGArg *args);
 757
 758 void tcg_op_remove(TCGContext *s, TCGOp *op);
 759 void tcg_optimize(TCGContext *s);
 760
 761 /* only used for debugging purposes */
 762 void tcg_dump_ops(TCGContext *s);
 763
 764 void dump_ops(const uint16_t *opc_buf, const TCGArg *opparam_buf);
 765 TCGv_i32 tcg_const_i32(int32_t val);
 766 TCGv_i64 tcg_const_i64(int64_t val);
 767 TCGv_i32 tcg_const_local_i32(int32_t val);
 768 TCGv_i64 tcg_const_local_i64(int64_t val);
 769
 770 TCGLabel *gen_new_label(void);
 771
 772 /**
 773  * label_arg
 774  * @l: label
 775  *
 776  * Encode a label for storage in the TCG opcode stream.
 777  */
 778
 779 static inline TCGArg label_arg(TCGLabel *l)
 780 {
 781     return (uintptr_t)l;
 782 }
 783
 784 /**
 785  * arg_label
 786  * @i: value
 787  *
 788  * The opposite of label_arg.  Retrieve a label from the
 789  * encoding of the TCG opcode stream.
 790  */
 791
 792 static inline TCGLabel *arg_label(TCGArg i)
 793 {
 794     return (TCGLabel *)(uintptr_t)i;
 795 }
 796
 797 /**
 798  * tcg_ptr_byte_diff
 799  * @a, @b: addresses to be differenced
 800  *
 801  * There are many places within the TCG backends where we need a byte
 802  * difference between two pointers.  While this can be accomplished
 803  * with local casting, it's easy to get wrong -- especially if one is
 804  * concerned with the signedness of the result.
 805  *
 806  * This version relies on GCC's void pointer arithmetic to get the
 807  * correct result.
 808  */
 809
 810 static inline ptrdiff_t tcg_ptr_byte_diff(void *a, void *b)
 811 {
 812     return a - b;
 813 }
 814
 815 /**
 816  * tcg_pcrel_diff
 817  * @s: the tcg context
 818  * @target: address of the target
 819  *
 820  * Produce a pc-relative difference, from the current code_ptr
 821  * to the destination address.
 822  */
 823
 824 static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, void *target)
 825 {
 826     return tcg_ptr_byte_diff(target, s->code_ptr);
 827 }
 828
 829 /**
 830  * tcg_current_code_size
 831  * @s: the tcg context
 832  *
 833  * Compute the current code size within the translation block.
 834  * This is used to fill in qemu's data structures for goto_tb.
 835  */
 836
 837 static inline size_t tcg_current_code_size(TCGContext *s)
 838 {
 839     return tcg_ptr_byte_diff(s->code_ptr, s->code_buf);
 840 }
 841
 842 /* Combine the TCGMemOp and mmu_idx parameters into a single value.  */
 843 typedef uint32_t TCGMemOpIdx;
 844
 845 /**
 846  * make_memop_idx
 847  * @op: memory operation
 848  * @idx: mmu index
 849  *
 850  * Encode these values into a single parameter.
 851  */
 852 static inline TCGMemOpIdx make_memop_idx(TCGMemOp op, unsigned idx)
 853 {
 854     tcg_debug_assert(idx <= 15);
 855     return (op << 4) | idx;
 856 }
 857
 858 /**
 859  * get_memop
 860  * @oi: combined op/idx parameter
 861  *
 862  * Extract the memory operation from the combined value.
 863  */
 864 static inline TCGMemOp get_memop(TCGMemOpIdx oi)
 865 {
 866     return oi >> 4;
 867 }
 868
 869 /**
 870  * get_mmuidx
 871  * @oi: combined op/idx parameter
 872  *
 873  * Extract the mmu index from the combined value.
 874  */
 875 static inline unsigned get_mmuidx(TCGMemOpIdx oi)
 876 {
 877     return oi & 15;
 878 }
 879
 880 /**
 881  * tcg_qemu_tb_exec:
 882  * @env: CPUArchState * for the CPU
 883  * @tb_ptr: address of generated code for the TB to execute
 884  *
 885  * Start executing code from a given translation block.
 886  * Where translation blocks have been linked, execution
 887  * may proceed from the given TB into successive ones.
 888  * Control eventually returns only when some action is needed
 889  * from the top-level loop: either control must pass to a TB
 890  * which has not yet been directly linked, or an asynchronous
 891  * event such as an interrupt needs handling.
 892  *
 893  * The return value is a pointer to the next TB to execute
 894  * (if known; otherwise zero). This pointer is assumed to be
 895  * 4-aligned, and the bottom two bits are used to return further
 896  * information:
 897  *  0, 1: the link between this TB and the next is via the specified
 898  *        TB index (0 or 1). That is, we left the TB via (the equivalent
 899  *        of) "goto_tb <index>". The main loop uses this to determine
 900  *        how to link the TB just executed to the next.
 901  *  2:    we are using instruction counting code generation, and we
 902  *        did not start executing this TB because the instruction counter
 903  *        would hit zero midway through it. In this case the next-TB pointer
 904  *        returned is the TB we were about to execute, and the caller must
 905  *        arrange to execute the remaining count of instructions.
 906  *  3:    we stopped because the CPU's exit_request flag was set
 907  *        (usually meaning that there is an interrupt that needs to be
 908  *        handled). The next-TB pointer returned is the TB we were
 909  *        about to execute when we noticed the pending exit request.
 910  *
 911  * If the bottom two bits indicate an exit-via-index then the CPU
 912  * state is correctly synchronised and ready for execution of the next
 913  * TB (and in particular the guest PC is the address to execute next).
 914  * Otherwise, we gave up on execution of this TB before it started, and
 915  * the caller must fix up the CPU state by calling the CPU's
 916  * synchronize_from_tb() method with the next-TB pointer we return (falling
 917  * back to calling the CPU's set_pc method with tb->pb if no
 918  * synchronize_from_tb() method exists).
 919  *
 920  * Note that TCG targets may use a different definition of tcg_qemu_tb_exec
 921  * to this default (which just calls the prologue.code emitted by
 922  * tcg_target_qemu_prologue()).
 923  */
 924 #define TB_EXIT_MASK 3
 925 #define TB_EXIT_IDX0 0
 926 #define TB_EXIT_IDX1 1
 927 #define TB_EXIT_ICOUNT_EXPIRED 2
 928 #define TB_EXIT_REQUESTED 3
 929
 930 #if !defined(tcg_qemu_tb_exec)
 931 # define tcg_qemu_tb_exec(env, tb_ptr) \
 932     ((uintptr_t (*)(void *, void *))tcg_ctx.code_gen_prologue)(env, tb_ptr)
 933 #endif
 934
 935 void tcg_register_jit(void *buf, size_t buf_size);
 936
 937 /*
 938  * Memory helpers that will be used by TCG generated code.
 939  */
 940 #ifdef CONFIG_SOFTMMU
 941 /* Value zero-extended to tcg register size.  */
 942 tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr,
 943                                      TCGMemOpIdx oi, uintptr_t retaddr);
 944 tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr,
 945                                     TCGMemOpIdx oi, uintptr_t retaddr);
 946 tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr,
 947                                     TCGMemOpIdx oi, uintptr_t retaddr);
 948 uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr,
 949                            TCGMemOpIdx oi, uintptr_t retaddr);
 950 tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr,
 951                                     TCGMemOpIdx oi, uintptr_t retaddr);
 952 tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr,
 953                                     TCGMemOpIdx oi, uintptr_t retaddr);
 954 uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr,
 955                            TCGMemOpIdx oi, uintptr_t retaddr);
 956
 957 /* Value sign-extended to tcg register size.  */
 958 tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr,
 959                                      TCGMemOpIdx oi, uintptr_t retaddr);
 960 tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr,
 961                                     TCGMemOpIdx oi, uintptr_t retaddr);
 962 tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr,
 963                                     TCGMemOpIdx oi, uintptr_t retaddr);
 964 tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr,
 965                                     TCGMemOpIdx oi, uintptr_t retaddr);
 966 tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr,
 967                                     TCGMemOpIdx oi, uintptr_t retaddr);
 968
 969 void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
 970                         TCGMemOpIdx oi, uintptr_t retaddr);
 971 void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
 972                        TCGMemOpIdx oi, uintptr_t retaddr);
 973 void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
 974                        TCGMemOpIdx oi, uintptr_t retaddr);
 975 void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
 976                        TCGMemOpIdx oi, uintptr_t retaddr);
 977 void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
 978                        TCGMemOpIdx oi, uintptr_t retaddr);
 979 void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
 980                        TCGMemOpIdx oi, uintptr_t retaddr);
 981 void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
 982                        TCGMemOpIdx oi, uintptr_t retaddr);
 983
 984 /* Temporary aliases until backends are converted.  */
 985 #ifdef TARGET_WORDS_BIGENDIAN
 986 # define helper_ret_ldsw_mmu  helper_be_ldsw_mmu
 987 # define helper_ret_lduw_mmu  helper_be_lduw_mmu
 988 # define helper_ret_ldsl_mmu  helper_be_ldsl_mmu
 989 # define helper_ret_ldul_mmu  helper_be_ldul_mmu
 990 # define helper_ret_ldq_mmu   helper_be_ldq_mmu
 991 # define helper_ret_stw_mmu   helper_be_stw_mmu
 992 # define helper_ret_stl_mmu   helper_be_stl_mmu
 993 # define helper_ret_stq_mmu   helper_be_stq_mmu
 994 #else
 995 # define helper_ret_ldsw_mmu  helper_le_ldsw_mmu
 996 # define helper_ret_lduw_mmu  helper_le_lduw_mmu
 997 # define helper_ret_ldsl_mmu  helper_le_ldsl_mmu
 998 # define helper_ret_ldul_mmu  helper_le_ldul_mmu
 999 # define helper_ret_ldq_mmu   helper_le_ldq_mmu
1000 # define helper_ret_stw_mmu   helper_le_stw_mmu
1001 # define helper_ret_stl_mmu   helper_le_stl_mmu
1002 # define helper_ret_stq_mmu   helper_le_stq_mmu
1003 #endif
1004
1005 #endif /* CONFIG_SOFTMMU */
1006
1007 #endif /* TCG_H */