hw/ide/via.c

   1 /*
   2  * QEMU IDE Emulation: PCI VIA82C686B support.
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  * Copyright (c) 2006 Openedhand Ltd.
   6  * Copyright (c) 2010 Huacai Chen <zltjiangshi@gmail.com>
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  */
  26
  27 #include "qemu/osdep.h"
  28 #include "hw/pci/pci.h"
  29 #include "migration/vmstate.h"
  30 #include "qemu/module.h"
  31 #include "qemu/range.h"
  32 #include "sysemu/dma.h"
  33 #include "hw/isa/vt82c686.h"
  34 #include "hw/ide/pci.h"
  35 #include "hw/irq.h"
  36 #include "trace.h"
  37
  38 static uint64_t bmdma_read(void *opaque, hwaddr addr,
  39                            unsigned size)
  40 {
  41     BMDMAState *bm = opaque;
  42     uint32_t val;
  43
  44     if (size != 1) {
  45         return ((uint64_t)1 << (size * 8)) - 1;
  46     }
  47
  48     switch (addr & 3) {
  49     case 0:
  50         val = bm->cmd;
  51         break;
  52     case 2:
  53         val = bm->status;
  54         break;
  55     default:
  56         val = 0xff;
  57         break;
  58     }
  59
  60     trace_bmdma_read_via(addr, val);
  61     return val;
  62 }
  63
  64 static void bmdma_write(void *opaque, hwaddr addr,
  65                         uint64_t val, unsigned size)
  66 {
  67     BMDMAState *bm = opaque;
  68
  69     if (size != 1) {
  70         return;
  71     }
  72
  73     trace_bmdma_write_via(addr, val);
  74     switch (addr & 3) {
  75     case 0:
  76         bmdma_cmd_writeb(bm, val);
  77         break;
  78     case 2:
  79         bmdma_status_writeb(bm, val);
  80         break;
  81     default:;
  82     }
  83 }
  84
  85 static const MemoryRegionOps via_bmdma_ops = {
  86     .read = bmdma_read,
  87     .write = bmdma_write,
  88 };
  89
  90 static void bmdma_setup_bar(PCIIDEState *d)
  91 {
  92     int i;
  93
  94     memory_region_init(&d->bmdma_bar, OBJECT(d), "via-bmdma-container", 16);
  95     for (i = 0; i < ARRAY_SIZE(d->bmdma); i++) {
  96         BMDMAState *bm = &d->bmdma[i];
  97
  98         memory_region_init_io(&bm->extra_io, OBJECT(d), &via_bmdma_ops, bm,
  99                               "via-bmdma", 4);
 100         memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
 101         memory_region_init_io(&bm->addr_ioport, OBJECT(d),
 102                               &bmdma_addr_ioport_ops, bm, "bmdma", 4);
 103         memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
 104     }
 105 }
 106
 107 static void via_ide_set_irq(void *opaque, int n, int level)
 108 {
 109     PCIIDEState *s = opaque;
 110     PCIDevice *d = PCI_DEVICE(s);
 111
 112     if (level) {
 113         d->config[0x70 + n * 8] |= 0x80;
 114     } else {
 115         d->config[0x70 + n * 8] &= ~0x80;
 116     }
 117
 118     qemu_set_irq(s->isa_irq[n], level);
 119 }
 120
 121 static void via_ide_reset(DeviceState *dev)
 122 {
 123     PCIIDEState *d = PCI_IDE(dev);
 124     PCIDevice *pd = PCI_DEVICE(dev);
 125     uint8_t *pci_conf = pd->config;
 126     int i;
 127
 128     for (i = 0; i < ARRAY_SIZE(d->bus); i++) {
 129         ide_bus_reset(&d->bus[i]);
 130     }
 131
 132     pci_config_set_prog_interface(pci_conf, 0x8a); /* legacy mode */
 133     pci_ide_update_mode(d);
 134
 135     pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_WAIT);
 136     pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK |
 137                  PCI_STATUS_DEVSEL_MEDIUM);
 138
 139     pci_set_byte(pci_conf + PCI_INTERRUPT_LINE, 0xe);
 140
 141     /* IDE chip enable, IDE configuration 1/2, IDE FIFO Configuration*/
 142     pci_set_long(pci_conf + 0x40, 0x0a090600);
 143     /* IDE misc configuration 1/2/3 */
 144     pci_set_long(pci_conf + 0x44, 0x00c00068);
 145     /* IDE Timing control */
 146     pci_set_long(pci_conf + 0x48, 0xa8a8a8a8);
 147     /* IDE Address Setup Time */
 148     pci_set_long(pci_conf + 0x4c, 0x000000ff);
 149     /* UltraDMA Extended Timing Control*/
 150     pci_set_long(pci_conf + 0x50, 0x07070707);
 151     /* UltraDMA FIFO Control */
 152     pci_set_long(pci_conf + 0x54, 0x00000004);
 153     /* IDE primary sector size */
 154     pci_set_long(pci_conf + 0x60, 0x00000200);
 155     /* IDE secondary sector size */
 156     pci_set_long(pci_conf + 0x68, 0x00000200);
 157     /* PCI PM Block */
 158     pci_set_long(pci_conf + 0xc0, 0x00020001);
 159 }
 160
 161 static uint32_t via_ide_cfg_read(PCIDevice *pd, uint32_t addr, int len)
 162 {
 163     uint32_t val = pci_default_read_config(pd, addr, len);
 164     uint8_t mode = pd->config[PCI_CLASS_PROG];
 165
 166     if ((mode & 0xf) == 0xa) {
 167         if (ranges_overlap(addr, len, PCI_BASE_ADDRESS_0, 16)) {
 168             /* BARs 0-3 always read back zero in legacy mode */
 169             for (int i = addr; i < addr + len; i++) {
 170                 if (i >= PCI_BASE_ADDRESS_0 && i < PCI_BASE_ADDRESS_0 + 16) {
 171                     val &= ~(0xffULL << ((i - addr) << 3));
 172                 }
 173             }
 174         }
 175         if (addr == PCI_BASE_ADDRESS_4 && val == PCI_BASE_ADDRESS_SPACE_IO) {
 176             /* BAR4 default value if unset */
 177             val = 0xcc00 | PCI_BASE_ADDRESS_SPACE_IO;
 178         }
 179     }
 180
 181     return val;
 182 }
 183
 184 static void via_ide_cfg_write(PCIDevice *pd, uint32_t addr,
 185                               uint32_t val, int len)
 186 {
 187     PCIIDEState *d = PCI_IDE(pd);
 188
 189     pci_default_write_config(pd, addr, val, len);
 190
 191     if (range_covers_byte(addr, len, PCI_CLASS_PROG)) {
 192         pci_ide_update_mode(d);
 193     }
 194 }
 195
 196 static void via_ide_realize(PCIDevice *dev, Error **errp)
 197 {
 198     PCIIDEState *d = PCI_IDE(dev);
 199     DeviceState *ds = DEVICE(dev);
 200     uint8_t *pci_conf = dev->config;
 201     int i;
 202
 203     pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
 204     dev->wmask[PCI_INTERRUPT_LINE] = 0;
 205     dev->wmask[PCI_CLASS_PROG] = 5;
 206
 207     memory_region_init_io(&d->data_bar[0], OBJECT(d), &pci_ide_data_le_ops,
 208                           &d->bus[0], "via-ide0-data", 8);
 209     pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[0]);
 210
 211     memory_region_init_io(&d->cmd_bar[0], OBJECT(d), &pci_ide_cmd_le_ops,
 212                           &d->bus[0], "via-ide0-cmd", 4);
 213     pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[0]);
 214
 215     memory_region_init_io(&d->data_bar[1], OBJECT(d), &pci_ide_data_le_ops,
 216                           &d->bus[1], "via-ide1-data", 8);
 217     pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[1]);
 218
 219     memory_region_init_io(&d->cmd_bar[1], OBJECT(d), &pci_ide_cmd_le_ops,
 220                           &d->bus[1], "via-ide1-cmd", 4);
 221     pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[1]);
 222
 223     bmdma_setup_bar(d);
 224     pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
 225
 226     qdev_init_gpio_in(ds, via_ide_set_irq, ARRAY_SIZE(d->bus));
 227     for (i = 0; i < ARRAY_SIZE(d->bus); i++) {
 228         ide_bus_init(&d->bus[i], sizeof(d->bus[i]), ds, i, MAX_IDE_DEVS);
 229         ide_bus_init_output_irq(&d->bus[i], qdev_get_gpio_in(ds, i));
 230
 231         bmdma_init(&d->bus[i], &d->bmdma[i], d);
 232         ide_bus_register_restart_cb(&d->bus[i]);
 233     }
 234 }
 235
 236 static void via_ide_exitfn(PCIDevice *dev)
 237 {
 238     PCIIDEState *d = PCI_IDE(dev);
 239     unsigned i;
 240
 241     for (i = 0; i < ARRAY_SIZE(d->bmdma); ++i) {
 242         memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
 243         memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
 244     }
 245 }
 246
 247 static void via_ide_class_init(ObjectClass *klass, void *data)
 248 {
 249     DeviceClass *dc = DEVICE_CLASS(klass);
 250     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 251
 252     dc->reset = via_ide_reset;
 253     dc->vmsd = &vmstate_ide_pci;
 254     /* Reason: only works as function of VIA southbridge */
 255     dc->user_creatable = false;
 256
 257     k->config_read = via_ide_cfg_read;
 258     k->config_write = via_ide_cfg_write;
 259     k->realize = via_ide_realize;
 260     k->exit = via_ide_exitfn;
 261     k->vendor_id = PCI_VENDOR_ID_VIA;
 262     k->device_id = PCI_DEVICE_ID_VIA_IDE;
 263     k->revision = 0x06;
 264     k->class_id = PCI_CLASS_STORAGE_IDE;
 265     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 266 }
 267
 268 static const TypeInfo via_ide_info = {
 269     .name          = TYPE_VIA_IDE,
 270     .parent        = TYPE_PCI_IDE,
 271     .class_init    = via_ide_class_init,
 272 };
 273
 274 static void via_ide_register_types(void)
 275 {
 276     type_register_static(&via_ide_info);
 277 }
 278
 279 type_init(via_ide_register_types)