hw/spapr.h

   1 #if !defined(__HW_SPAPR_H__)
   2 #define __HW_SPAPR_H__
   3
   4 #include "hw/xics.h"
   5
   6 struct VIOsPAPRBus;
   7 struct sPAPRPHBState;
   8 struct icp_state;
   9
  10 typedef struct sPAPREnvironment {
  11     struct VIOsPAPRBus *vio_bus;
  12     QLIST_HEAD(, sPAPRPHBState) phbs;
  13     struct icp_state *icp;
  14
  15     target_phys_addr_t ram_limit;
  16     void *htab;
  17     long htab_size;
  18     target_phys_addr_t fdt_addr, rtas_addr;
  19     long rtas_size;
  20     void *fdt_skel;
  21     target_ulong entry_point;
  22     int next_irq;
  23     int rtc_offset;
  24     char *cpu_model;
  25 } sPAPREnvironment;
  26
  27 #define H_SUCCESS         0
  28 #define H_BUSY            1        /* Hardware busy -- retry later */
  29 #define H_CLOSED          2        /* Resource closed */
  30 #define H_NOT_AVAILABLE   3
  31 #define H_CONSTRAINED     4        /* Resource request constrained to max allowed */
  32 #define H_PARTIAL         5
  33 #define H_IN_PROGRESS     14       /* Kind of like busy */
  34 #define H_PAGE_REGISTERED 15
  35 #define H_PARTIAL_STORE   16
  36 #define H_PENDING         17       /* returned from H_POLL_PENDING */
  37 #define H_CONTINUE        18       /* Returned from H_Join on success */
  38 #define H_LONG_BUSY_START_RANGE         9900  /* Start of long busy range */
  39 #define H_LONG_BUSY_ORDER_1_MSEC        9900  /* Long busy, hint that 1msec \
  40                                                  is a good time to retry */
  41 #define H_LONG_BUSY_ORDER_10_MSEC       9901  /* Long busy, hint that 10msec \
  42                                                  is a good time to retry */
  43 #define H_LONG_BUSY_ORDER_100_MSEC      9902  /* Long busy, hint that 100msec \
  44                                                  is a good time to retry */
  45 #define H_LONG_BUSY_ORDER_1_SEC         9903  /* Long busy, hint that 1sec \
  46                                                  is a good time to retry */
  47 #define H_LONG_BUSY_ORDER_10_SEC        9904  /* Long busy, hint that 10sec \
  48                                                  is a good time to retry */
  49 #define H_LONG_BUSY_ORDER_100_SEC       9905  /* Long busy, hint that 100sec \
  50                                                  is a good time to retry */
  51 #define H_LONG_BUSY_END_RANGE           9905  /* End of long busy range */
  52 #define H_HARDWARE        -1       /* Hardware error */
  53 #define H_FUNCTION        -2       /* Function not supported */
  54 #define H_PRIVILEGE       -3       /* Caller not privileged */
  55 #define H_PARAMETER       -4       /* Parameter invalid, out-of-range or conflicting */
  56 #define H_BAD_MODE        -5       /* Illegal msr value */
  57 #define H_PTEG_FULL       -6       /* PTEG is full */
  58 #define H_NOT_FOUND       -7       /* PTE was not found" */
  59 #define H_RESERVED_DABR   -8       /* DABR address is reserved by the hypervisor on this processor" */
  60 #define H_NO_MEM          -9
  61 #define H_AUTHORITY       -10
  62 #define H_PERMISSION      -11
  63 #define H_DROPPED         -12
  64 #define H_SOURCE_PARM     -13
  65 #define H_DEST_PARM       -14
  66 #define H_REMOTE_PARM     -15
  67 #define H_RESOURCE        -16
  68 #define H_ADAPTER_PARM    -17
  69 #define H_RH_PARM         -18
  70 #define H_RCQ_PARM        -19
  71 #define H_SCQ_PARM        -20
  72 #define H_EQ_PARM         -21
  73 #define H_RT_PARM         -22
  74 #define H_ST_PARM         -23
  75 #define H_SIGT_PARM       -24
  76 #define H_TOKEN_PARM      -25
  77 #define H_MLENGTH_PARM    -27
  78 #define H_MEM_PARM        -28
  79 #define H_MEM_ACCESS_PARM -29
  80 #define H_ATTR_PARM       -30
  81 #define H_PORT_PARM       -31
  82 #define H_MCG_PARM        -32
  83 #define H_VL_PARM         -33
  84 #define H_TSIZE_PARM      -34
  85 #define H_TRACE_PARM      -35
  86
  87 #define H_MASK_PARM       -37
  88 #define H_MCG_FULL        -38
  89 #define H_ALIAS_EXIST     -39
  90 #define H_P_COUNTER       -40
  91 #define H_TABLE_FULL      -41
  92 #define H_ALT_TABLE       -42
  93 #define H_MR_CONDITION    -43
  94 #define H_NOT_ENOUGH_RESOURCES -44
  95 #define H_R_STATE         -45
  96 #define H_RESCINDEND      -46
  97 #define H_MULTI_THREADS_ACTIVE -9005
  98
  99
 100 /* Long Busy is a condition that can be returned by the firmware
 101  * when a call cannot be completed now, but the identical call
 102  * should be retried later.  This prevents calls blocking in the
 103  * firmware for long periods of time.  Annoyingly the firmware can return
 104  * a range of return codes, hinting at how long we should wait before
 105  * retrying.  If you don't care for the hint, the macro below is a good
 106  * way to check for the long_busy return codes
 107  */
 108 #define H_IS_LONG_BUSY(x)  ((x >= H_LONG_BUSY_START_RANGE) \
 109                             && (x <= H_LONG_BUSY_END_RANGE))
 110
 111 /* Flags */
 112 #define H_LARGE_PAGE      (1ULL<<(63-16))
 113 #define H_EXACT           (1ULL<<(63-24))       /* Use exact PTE or return H_PTEG_FULL */
 114 #define H_R_XLATE         (1ULL<<(63-25))       /* include a valid logical page num in the pte if the valid bit is set */
 115 #define H_READ_4          (1ULL<<(63-26))       /* Return 4 PTEs */
 116 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28))
 117 #define H_PAGE_UNUSED     ((1ULL<<(63-29)) | (1ULL<<(63-30)))
 118 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED)
 119 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31)))
 120 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE
 121 #define H_AVPN            (1ULL<<(63-32))       /* An avpn is provided as a sanity test */
 122 #define H_ANDCOND         (1ULL<<(63-33))
 123 #define H_ICACHE_INVALIDATE (1ULL<<(63-40))     /* icbi, etc.  (ignored for IO pages) */
 124 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41))    /* dcbst, icbi, etc (ignored for IO pages */
 125 #define H_ZERO_PAGE       (1ULL<<(63-48))       /* zero the page before mapping (ignored for IO pages) */
 126 #define H_COPY_PAGE       (1ULL<<(63-49))
 127 #define H_N               (1ULL<<(63-61))
 128 #define H_PP1             (1ULL<<(63-62))
 129 #define H_PP2             (1ULL<<(63-63))
 130
 131 /* VASI States */
 132 #define H_VASI_INVALID    0
 133 #define H_VASI_ENABLED    1
 134 #define H_VASI_ABORTED    2
 135 #define H_VASI_SUSPENDING 3
 136 #define H_VASI_SUSPENDED  4
 137 #define H_VASI_RESUMED    5
 138 #define H_VASI_COMPLETED  6
 139
 140 /* DABRX flags */
 141 #define H_DABRX_HYPERVISOR (1ULL<<(63-61))
 142 #define H_DABRX_KERNEL     (1ULL<<(63-62))
 143 #define H_DABRX_USER       (1ULL<<(63-63))
 144
 145 /* Each control block has to be on a 4K boundary */
 146 #define H_CB_ALIGNMENT     4096
 147
 148 /* pSeries hypervisor opcodes */
 149 #define H_REMOVE                0x04
 150 #define H_ENTER                 0x08
 151 #define H_READ                  0x0c
 152 #define H_CLEAR_MOD             0x10
 153 #define H_CLEAR_REF             0x14
 154 #define H_PROTECT               0x18
 155 #define H_GET_TCE               0x1c
 156 #define H_PUT_TCE               0x20
 157 #define H_SET_SPRG0             0x24
 158 #define H_SET_DABR              0x28
 159 #define H_PAGE_INIT             0x2c
 160 #define H_SET_ASR               0x30
 161 #define H_ASR_ON                0x34
 162 #define H_ASR_OFF               0x38
 163 #define H_LOGICAL_CI_LOAD       0x3c
 164 #define H_LOGICAL_CI_STORE      0x40
 165 #define H_LOGICAL_CACHE_LOAD    0x44
 166 #define H_LOGICAL_CACHE_STORE   0x48
 167 #define H_LOGICAL_ICBI          0x4c
 168 #define H_LOGICAL_DCBF          0x50
 169 #define H_GET_TERM_CHAR         0x54
 170 #define H_PUT_TERM_CHAR         0x58
 171 #define H_REAL_TO_LOGICAL       0x5c
 172 #define H_HYPERVISOR_DATA       0x60
 173 #define H_EOI                   0x64
 174 #define H_CPPR                  0x68
 175 #define H_IPI                   0x6c
 176 #define H_IPOLL                 0x70
 177 #define H_XIRR                  0x74
 178 #define H_PERFMON               0x7c
 179 #define H_MIGRATE_DMA           0x78
 180 #define H_REGISTER_VPA          0xDC
 181 #define H_CEDE                  0xE0
 182 #define H_CONFER                0xE4
 183 #define H_PROD                  0xE8
 184 #define H_GET_PPP               0xEC
 185 #define H_SET_PPP               0xF0
 186 #define H_PURR                  0xF4
 187 #define H_PIC                   0xF8
 188 #define H_REG_CRQ               0xFC
 189 #define H_FREE_CRQ              0x100
 190 #define H_VIO_SIGNAL            0x104
 191 #define H_SEND_CRQ              0x108
 192 #define H_COPY_RDMA             0x110
 193 #define H_REGISTER_LOGICAL_LAN  0x114
 194 #define H_FREE_LOGICAL_LAN      0x118
 195 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C
 196 #define H_SEND_LOGICAL_LAN      0x120
 197 #define H_BULK_REMOVE           0x124
 198 #define H_MULTICAST_CTRL        0x130
 199 #define H_SET_XDABR             0x134
 200 #define H_STUFF_TCE             0x138
 201 #define H_PUT_TCE_INDIRECT      0x13C
 202 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C
 203 #define H_VTERM_PARTNER_INFO    0x150
 204 #define H_REGISTER_VTERM        0x154
 205 #define H_FREE_VTERM            0x158
 206 #define H_RESET_EVENTS          0x15C
 207 #define H_ALLOC_RESOURCE        0x160
 208 #define H_FREE_RESOURCE         0x164
 209 #define H_MODIFY_QP             0x168
 210 #define H_QUERY_QP              0x16C
 211 #define H_REREGISTER_PMR        0x170
 212 #define H_REGISTER_SMR          0x174
 213 #define H_QUERY_MR              0x178
 214 #define H_QUERY_MW              0x17C
 215 #define H_QUERY_HCA             0x180
 216 #define H_QUERY_PORT            0x184
 217 #define H_MODIFY_PORT           0x188
 218 #define H_DEFINE_AQP1           0x18C
 219 #define H_GET_TRACE_BUFFER      0x190
 220 #define H_DEFINE_AQP0           0x194
 221 #define H_RESIZE_MR             0x198
 222 #define H_ATTACH_MCQP           0x19C
 223 #define H_DETACH_MCQP           0x1A0
 224 #define H_CREATE_RPT            0x1A4
 225 #define H_REMOVE_RPT            0x1A8
 226 #define H_REGISTER_RPAGES       0x1AC
 227 #define H_DISABLE_AND_GETC      0x1B0
 228 #define H_ERROR_DATA            0x1B4
 229 #define H_GET_HCA_INFO          0x1B8
 230 #define H_GET_PERF_COUNT        0x1BC
 231 #define H_MANAGE_TRACE          0x1C0
 232 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4
 233 #define H_QUERY_INT_STATE       0x1E4
 234 #define H_POLL_PENDING          0x1D8
 235 #define H_ILLAN_ATTRIBUTES      0x244
 236 #define H_MODIFY_HEA_QP         0x250
 237 #define H_QUERY_HEA_QP          0x254
 238 #define H_QUERY_HEA             0x258
 239 #define H_QUERY_HEA_PORT        0x25C
 240 #define H_MODIFY_HEA_PORT       0x260
 241 #define H_REG_BCMC              0x264
 242 #define H_DEREG_BCMC            0x268
 243 #define H_REGISTER_HEA_RPAGES   0x26C
 244 #define H_DISABLE_AND_GET_HEA   0x270
 245 #define H_GET_HEA_INFO          0x274
 246 #define H_ALLOC_HEA_RESOURCE    0x278
 247 #define H_ADD_CONN              0x284
 248 #define H_DEL_CONN              0x288
 249 #define H_JOIN                  0x298
 250 #define H_VASI_STATE            0x2A4
 251 #define H_ENABLE_CRQ            0x2B0
 252 #define H_GET_EM_PARMS          0x2B8
 253 #define H_SET_MPP               0x2D0
 254 #define H_GET_MPP               0x2D4
 255 #define MAX_HCALL_OPCODE        H_GET_MPP
 256
 257 /* The hcalls above are standardized in PAPR and implemented by pHyp
 258  * as well.
 259  *
 260  * We also need some hcalls which are specific to qemu / KVM-on-POWER.
 261  * So far we just need one for H_RTAS, but in future we'll need more
 262  * for extensions like virtio.  We put those into the 0xf000-0xfffc
 263  * range which is reserved by PAPR for "platform-specific" hcalls.
 264  */
 265 #define KVMPPC_HCALL_BASE       0xf000
 266 #define KVMPPC_H_RTAS           (KVMPPC_HCALL_BASE + 0x0)
 267 #define KVMPPC_HCALL_MAX        KVMPPC_H_RTAS
 268
 269 extern sPAPREnvironment *spapr;
 270
 271 /*#define DEBUG_SPAPR_HCALLS*/
 272
 273 #ifdef DEBUG_SPAPR_HCALLS
 274 #define hcall_dprintf(fmt, ...) \
 275     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
 276 #else
 277 #define hcall_dprintf(fmt, ...) \
 278     do { } while (0)
 279 #endif
 280
 281 typedef target_ulong (*spapr_hcall_fn)(CPUPPCState *env, sPAPREnvironment *spapr,
 282                                        target_ulong opcode,
 283                                        target_ulong *args);
 284
 285 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn);
 286 target_ulong spapr_hypercall(CPUPPCState *env, target_ulong opcode,
 287                              target_ulong *args);
 288
 289 qemu_irq spapr_allocate_irq(uint32_t hint, uint32_t *irq_num,
 290                             enum xics_irq_type type);
 291
 292 static inline qemu_irq spapr_allocate_msi(uint32_t hint, uint32_t *irq_num)
 293 {
 294     return spapr_allocate_irq(hint, irq_num, XICS_MSI);
 295 }
 296
 297 static inline qemu_irq spapr_allocate_lsi(uint32_t hint, uint32_t *irq_num)
 298 {
 299     return spapr_allocate_irq(hint, irq_num, XICS_LSI);
 300 }
 301
 302 static inline uint32_t rtas_ld(target_ulong phys, int n)
 303 {
 304     return ldl_be_phys(phys + 4*n);
 305 }
 306
 307 static inline void rtas_st(target_ulong phys, int n, uint32_t val)
 308 {
 309     stl_be_phys(phys + 4*n, val);
 310 }
 311
 312 typedef void (*spapr_rtas_fn)(sPAPREnvironment *spapr, uint32_t token,
 313                               uint32_t nargs, target_ulong args,
 314                               uint32_t nret, target_ulong rets);
 315 void spapr_rtas_register(const char *name, spapr_rtas_fn fn);
 316 target_ulong spapr_rtas_call(sPAPREnvironment *spapr,
 317                              uint32_t token, uint32_t nargs, target_ulong args,
 318                              uint32_t nret, target_ulong rets);
 319 int spapr_rtas_device_tree_setup(void *fdt, target_phys_addr_t rtas_addr,
 320                                  target_phys_addr_t rtas_size);
 321
 322 #endif /* !defined (__HW_SPAPR_H__) */