target-mips/cpu.h

   1 #if !defined (__MIPS_CPU_H__)
   2 #define __MIPS_CPU_H__
   3
   4 //#define DEBUG_OP
   5
   6 #define ALIGNED_ONLY
   7 #define TARGET_HAS_ICE 1
   8
   9 #define ELF_MACHINE     EM_MIPS
  10
  11 #define CPUArchState struct CPUMIPSState
  12
  13 #include "config.h"
  14 #include "qemu-common.h"
  15 #include "mips-defs.h"
  16 #include "exec/cpu-defs.h"
  17 #include "fpu/softfloat.h"
  18
  19 struct CPUMIPSState;
  20
  21 typedef struct r4k_tlb_t r4k_tlb_t;
  22 struct r4k_tlb_t {
  23     target_ulong VPN;
  24     uint32_t PageMask;
  25     uint_fast8_t ASID;
  26     uint_fast16_t G:1;
  27     uint_fast16_t C0:3;
  28     uint_fast16_t C1:3;
  29     uint_fast16_t V0:1;
  30     uint_fast16_t V1:1;
  31     uint_fast16_t D0:1;
  32     uint_fast16_t D1:1;
  33     target_ulong PFN[2];
  34 };
  35
  36 #if !defined(CONFIG_USER_ONLY)
  37 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
  38 struct CPUMIPSTLBContext {
  39     uint32_t nb_tlb;
  40     uint32_t tlb_in_use;
  41     int (*map_address) (struct CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, int rw, int access_type);
  42     void (*helper_tlbwi)(struct CPUMIPSState *env);
  43     void (*helper_tlbwr)(struct CPUMIPSState *env);
  44     void (*helper_tlbp)(struct CPUMIPSState *env);
  45     void (*helper_tlbr)(struct CPUMIPSState *env);
  46     union {
  47         struct {
  48             r4k_tlb_t tlb[MIPS_TLB_MAX];
  49         } r4k;
  50     } mmu;
  51 };
  52 #endif
  53
  54 typedef union fpr_t fpr_t;
  55 union fpr_t {
  56     float64  fd;   /* ieee double precision */
  57     float32  fs[2];/* ieee single precision */
  58     uint64_t d;    /* binary double fixed-point */
  59     uint32_t w[2]; /* binary single fixed-point */
  60 };
  61 /* define FP_ENDIAN_IDX to access the same location
  62  * in the fpr_t union regardless of the host endianness
  63  */
  64 #if defined(HOST_WORDS_BIGENDIAN)
  65 #  define FP_ENDIAN_IDX 1
  66 #else
  67 #  define FP_ENDIAN_IDX 0
  68 #endif
  69
  70 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
  71 struct CPUMIPSFPUContext {
  72     /* Floating point registers */
  73     fpr_t fpr[32];
  74     float_status fp_status;
  75     /* fpu implementation/revision register (fir) */
  76     uint32_t fcr0;
  77 #define FCR0_UFRP 28
  78 #define FCR0_F64 22
  79 #define FCR0_L 21
  80 #define FCR0_W 20
  81 #define FCR0_3D 19
  82 #define FCR0_PS 18
  83 #define FCR0_D 17
  84 #define FCR0_S 16
  85 #define FCR0_PRID 8
  86 #define FCR0_REV 0
  87     /* fcsr */
  88     uint32_t fcr31;
  89 #define SET_FP_COND(num,env)     do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
  90 #define CLEAR_FP_COND(num,env)   do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
  91 #define GET_FP_COND(env)         ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
  92 #define GET_FP_CAUSE(reg)        (((reg) >> 12) & 0x3f)
  93 #define GET_FP_ENABLE(reg)       (((reg) >>  7) & 0x1f)
  94 #define GET_FP_FLAGS(reg)        (((reg) >>  2) & 0x1f)
  95 #define SET_FP_CAUSE(reg,v)      do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
  96 #define SET_FP_ENABLE(reg,v)     do { (reg) = ((reg) & ~(0x1f <<  7)) | ((v & 0x1f) << 7); } while(0)
  97 #define SET_FP_FLAGS(reg,v)      do { (reg) = ((reg) & ~(0x1f <<  2)) | ((v & 0x1f) << 2); } while(0)
  98 #define UPDATE_FP_FLAGS(reg,v)   do { (reg) |= ((v & 0x1f) << 2); } while(0)
  99 #define FP_INEXACT        1
 100 #define FP_UNDERFLOW      2
 101 #define FP_OVERFLOW       4
 102 #define FP_DIV0           8
 103 #define FP_INVALID        16
 104 #define FP_UNIMPLEMENTED  32
 105 };
 106
 107 #define NB_MMU_MODES 3
 108
 109 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
 110 struct CPUMIPSMVPContext {
 111     int32_t CP0_MVPControl;
 112 #define CP0MVPCo_CPA    3
 113 #define CP0MVPCo_STLB   2
 114 #define CP0MVPCo_VPC    1
 115 #define CP0MVPCo_EVP    0
 116     int32_t CP0_MVPConf0;
 117 #define CP0MVPC0_M      31
 118 #define CP0MVPC0_TLBS   29
 119 #define CP0MVPC0_GS     28
 120 #define CP0MVPC0_PCP    27
 121 #define CP0MVPC0_PTLBE  16
 122 #define CP0MVPC0_TCA    15
 123 #define CP0MVPC0_PVPE   10
 124 #define CP0MVPC0_PTC    0
 125     int32_t CP0_MVPConf1;
 126 #define CP0MVPC1_CIM    31
 127 #define CP0MVPC1_CIF    30
 128 #define CP0MVPC1_PCX    20
 129 #define CP0MVPC1_PCP2   10
 130 #define CP0MVPC1_PCP1   0
 131 };
 132
 133 typedef struct mips_def_t mips_def_t;
 134
 135 #define MIPS_SHADOW_SET_MAX 16
 136 #define MIPS_TC_MAX 5
 137 #define MIPS_FPU_MAX 1
 138 #define MIPS_DSP_ACC 4
 139
 140 typedef struct TCState TCState;
 141 struct TCState {
 142     target_ulong gpr[32];
 143     target_ulong PC;
 144     target_ulong HI[MIPS_DSP_ACC];
 145     target_ulong LO[MIPS_DSP_ACC];
 146     target_ulong ACX[MIPS_DSP_ACC];
 147     target_ulong DSPControl;
 148     int32_t CP0_TCStatus;
 149 #define CP0TCSt_TCU3    31
 150 #define CP0TCSt_TCU2    30
 151 #define CP0TCSt_TCU1    29
 152 #define CP0TCSt_TCU0    28
 153 #define CP0TCSt_TMX     27
 154 #define CP0TCSt_RNST    23
 155 #define CP0TCSt_TDS     21
 156 #define CP0TCSt_DT      20
 157 #define CP0TCSt_DA      15
 158 #define CP0TCSt_A       13
 159 #define CP0TCSt_TKSU    11
 160 #define CP0TCSt_IXMT    10
 161 #define CP0TCSt_TASID   0
 162     int32_t CP0_TCBind;
 163 #define CP0TCBd_CurTC   21
 164 #define CP0TCBd_TBE     17
 165 #define CP0TCBd_CurVPE  0
 166     target_ulong CP0_TCHalt;
 167     target_ulong CP0_TCContext;
 168     target_ulong CP0_TCSchedule;
 169     target_ulong CP0_TCScheFBack;
 170     int32_t CP0_Debug_tcstatus;
 171 };
 172
 173 typedef struct CPUMIPSState CPUMIPSState;
 174 struct CPUMIPSState {
 175     TCState active_tc;
 176     CPUMIPSFPUContext active_fpu;
 177
 178     uint32_t current_tc;
 179     uint32_t current_fpu;
 180
 181     uint32_t SEGBITS;
 182     uint32_t PABITS;
 183     target_ulong SEGMask;
 184     target_ulong PAMask;
 185
 186     int32_t CP0_Index;
 187     /* CP0_MVP* are per MVP registers. */
 188     int32_t CP0_Random;
 189     int32_t CP0_VPEControl;
 190 #define CP0VPECo_YSI    21
 191 #define CP0VPECo_GSI    20
 192 #define CP0VPECo_EXCPT  16
 193 #define CP0VPECo_TE     15
 194 #define CP0VPECo_TargTC 0
 195     int32_t CP0_VPEConf0;
 196 #define CP0VPEC0_M      31
 197 #define CP0VPEC0_XTC    21
 198 #define CP0VPEC0_TCS    19
 199 #define CP0VPEC0_SCS    18
 200 #define CP0VPEC0_DSC    17
 201 #define CP0VPEC0_ICS    16
 202 #define CP0VPEC0_MVP    1
 203 #define CP0VPEC0_VPA    0
 204     int32_t CP0_VPEConf1;
 205 #define CP0VPEC1_NCX    20
 206 #define CP0VPEC1_NCP2   10
 207 #define CP0VPEC1_NCP1   0
 208     target_ulong CP0_YQMask;
 209     target_ulong CP0_VPESchedule;
 210     target_ulong CP0_VPEScheFBack;
 211     int32_t CP0_VPEOpt;
 212 #define CP0VPEOpt_IWX7  15
 213 #define CP0VPEOpt_IWX6  14
 214 #define CP0VPEOpt_IWX5  13
 215 #define CP0VPEOpt_IWX4  12
 216 #define CP0VPEOpt_IWX3  11
 217 #define CP0VPEOpt_IWX2  10
 218 #define CP0VPEOpt_IWX1  9
 219 #define CP0VPEOpt_IWX0  8
 220 #define CP0VPEOpt_DWX7  7
 221 #define CP0VPEOpt_DWX6  6
 222 #define CP0VPEOpt_DWX5  5
 223 #define CP0VPEOpt_DWX4  4
 224 #define CP0VPEOpt_DWX3  3
 225 #define CP0VPEOpt_DWX2  2
 226 #define CP0VPEOpt_DWX1  1
 227 #define CP0VPEOpt_DWX0  0
 228     target_ulong CP0_EntryLo0;
 229     target_ulong CP0_EntryLo1;
 230     target_ulong CP0_Context;
 231     int32_t CP0_PageMask;
 232     int32_t CP0_PageGrain;
 233     int32_t CP0_Wired;
 234     int32_t CP0_SRSConf0_rw_bitmask;
 235     int32_t CP0_SRSConf0;
 236 #define CP0SRSC0_M      31
 237 #define CP0SRSC0_SRS3   20
 238 #define CP0SRSC0_SRS2   10
 239 #define CP0SRSC0_SRS1   0
 240     int32_t CP0_SRSConf1_rw_bitmask;
 241     int32_t CP0_SRSConf1;
 242 #define CP0SRSC1_M      31
 243 #define CP0SRSC1_SRS6   20
 244 #define CP0SRSC1_SRS5   10
 245 #define CP0SRSC1_SRS4   0
 246     int32_t CP0_SRSConf2_rw_bitmask;
 247     int32_t CP0_SRSConf2;
 248 #define CP0SRSC2_M      31
 249 #define CP0SRSC2_SRS9   20
 250 #define CP0SRSC2_SRS8   10
 251 #define CP0SRSC2_SRS7   0
 252     int32_t CP0_SRSConf3_rw_bitmask;
 253     int32_t CP0_SRSConf3;
 254 #define CP0SRSC3_M      31
 255 #define CP0SRSC3_SRS12  20
 256 #define CP0SRSC3_SRS11  10
 257 #define CP0SRSC3_SRS10  0
 258     int32_t CP0_SRSConf4_rw_bitmask;
 259     int32_t CP0_SRSConf4;
 260 #define CP0SRSC4_SRS15  20
 261 #define CP0SRSC4_SRS14  10
 262 #define CP0SRSC4_SRS13  0
 263     int32_t CP0_HWREna;
 264     target_ulong CP0_BadVAddr;
 265     int32_t CP0_Count;
 266     target_ulong CP0_EntryHi;
 267     int32_t CP0_Compare;
 268     int32_t CP0_Status;
 269 #define CP0St_CU3   31
 270 #define CP0St_CU2   30
 271 #define CP0St_CU1   29
 272 #define CP0St_CU0   28
 273 #define CP0St_RP    27
 274 #define CP0St_FR    26
 275 #define CP0St_RE    25
 276 #define CP0St_MX    24
 277 #define CP0St_PX    23
 278 #define CP0St_BEV   22
 279 #define CP0St_TS    21
 280 #define CP0St_SR    20
 281 #define CP0St_NMI   19
 282 #define CP0St_IM    8
 283 #define CP0St_KX    7
 284 #define CP0St_SX    6
 285 #define CP0St_UX    5
 286 #define CP0St_KSU   3
 287 #define CP0St_ERL   2
 288 #define CP0St_EXL   1
 289 #define CP0St_IE    0
 290     int32_t CP0_IntCtl;
 291 #define CP0IntCtl_IPTI 29
 292 #define CP0IntCtl_IPPC1 26
 293 #define CP0IntCtl_VS 5
 294     int32_t CP0_SRSCtl;
 295 #define CP0SRSCtl_HSS 26
 296 #define CP0SRSCtl_EICSS 18
 297 #define CP0SRSCtl_ESS 12
 298 #define CP0SRSCtl_PSS 6
 299 #define CP0SRSCtl_CSS 0
 300     int32_t CP0_SRSMap;
 301 #define CP0SRSMap_SSV7 28
 302 #define CP0SRSMap_SSV6 24
 303 #define CP0SRSMap_SSV5 20
 304 #define CP0SRSMap_SSV4 16
 305 #define CP0SRSMap_SSV3 12
 306 #define CP0SRSMap_SSV2 8
 307 #define CP0SRSMap_SSV1 4
 308 #define CP0SRSMap_SSV0 0
 309     int32_t CP0_Cause;
 310 #define CP0Ca_BD   31
 311 #define CP0Ca_TI   30
 312 #define CP0Ca_CE   28
 313 #define CP0Ca_DC   27
 314 #define CP0Ca_PCI  26
 315 #define CP0Ca_IV   23
 316 #define CP0Ca_WP   22
 317 #define CP0Ca_IP    8
 318 #define CP0Ca_IP_mask 0x0000FF00
 319 #define CP0Ca_EC    2
 320     target_ulong CP0_EPC;
 321     int32_t CP0_PRid;
 322     int32_t CP0_EBase;
 323     int32_t CP0_Config0;
 324 #define CP0C0_M    31
 325 #define CP0C0_K23  28
 326 #define CP0C0_KU   25
 327 #define CP0C0_MDU  20
 328 #define CP0C0_MM   17
 329 #define CP0C0_BM   16
 330 #define CP0C0_BE   15
 331 #define CP0C0_AT   13
 332 #define CP0C0_AR   10
 333 #define CP0C0_MT   7
 334 #define CP0C0_VI   3
 335 #define CP0C0_K0   0
 336     int32_t CP0_Config1;
 337 #define CP0C1_M    31
 338 #define CP0C1_MMU  25
 339 #define CP0C1_IS   22
 340 #define CP0C1_IL   19
 341 #define CP0C1_IA   16
 342 #define CP0C1_DS   13
 343 #define CP0C1_DL   10
 344 #define CP0C1_DA   7
 345 #define CP0C1_C2   6
 346 #define CP0C1_MD   5
 347 #define CP0C1_PC   4
 348 #define CP0C1_WR   3
 349 #define CP0C1_CA   2
 350 #define CP0C1_EP   1
 351 #define CP0C1_FP   0
 352     int32_t CP0_Config2;
 353 #define CP0C2_M    31
 354 #define CP0C2_TU   28
 355 #define CP0C2_TS   24
 356 #define CP0C2_TL   20
 357 #define CP0C2_TA   16
 358 #define CP0C2_SU   12
 359 #define CP0C2_SS   8
 360 #define CP0C2_SL   4
 361 #define CP0C2_SA   0
 362     int32_t CP0_Config3;
 363 #define CP0C3_M    31
 364 #define CP0C3_ISA_ON_EXC 16
 365 #define CP0C3_DSPP 10
 366 #define CP0C3_LPA  7
 367 #define CP0C3_VEIC 6
 368 #define CP0C3_VInt 5
 369 #define CP0C3_SP   4
 370 #define CP0C3_MT   2
 371 #define CP0C3_SM   1
 372 #define CP0C3_TL   0
 373     uint32_t CP0_Config4;
 374     uint32_t CP0_Config4_rw_bitmask;
 375 #define CP0C4_M    31
 376     uint32_t CP0_Config5;
 377     uint32_t CP0_Config5_rw_bitmask;
 378 #define CP0C5_M          31
 379 #define CP0C5_K          30
 380 #define CP0C5_CV         29
 381 #define CP0C5_EVA        28
 382 #define CP0C5_MSAEn      27
 383 #define CP0C5_UFR        2
 384 #define CP0C5_NFExists   0
 385     int32_t CP0_Config6;
 386     int32_t CP0_Config7;
 387     /* XXX: Maybe make LLAddr per-TC? */
 388     target_ulong lladdr;
 389     target_ulong llval;
 390     target_ulong llnewval;
 391     target_ulong llreg;
 392     target_ulong CP0_LLAddr_rw_bitmask;
 393     int CP0_LLAddr_shift;
 394     target_ulong CP0_WatchLo[8];
 395     int32_t CP0_WatchHi[8];
 396     target_ulong CP0_XContext;
 397     int32_t CP0_Framemask;
 398     int32_t CP0_Debug;
 399 #define CP0DB_DBD  31
 400 #define CP0DB_DM   30
 401 #define CP0DB_LSNM 28
 402 #define CP0DB_Doze 27
 403 #define CP0DB_Halt 26
 404 #define CP0DB_CNT  25
 405 #define CP0DB_IBEP 24
 406 #define CP0DB_DBEP 21
 407 #define CP0DB_IEXI 20
 408 #define CP0DB_VER  15
 409 #define CP0DB_DEC  10
 410 #define CP0DB_SSt  8
 411 #define CP0DB_DINT 5
 412 #define CP0DB_DIB  4
 413 #define CP0DB_DDBS 3
 414 #define CP0DB_DDBL 2
 415 #define CP0DB_DBp  1
 416 #define CP0DB_DSS  0
 417     target_ulong CP0_DEPC;
 418     int32_t CP0_Performance0;
 419     int32_t CP0_TagLo;
 420     int32_t CP0_DataLo;
 421     int32_t CP0_TagHi;
 422     int32_t CP0_DataHi;
 423     target_ulong CP0_ErrorEPC;
 424     int32_t CP0_DESAVE;
 425     /* We waste some space so we can handle shadow registers like TCs. */
 426     TCState tcs[MIPS_SHADOW_SET_MAX];
 427     CPUMIPSFPUContext fpus[MIPS_FPU_MAX];
 428     /* QEMU */
 429     int error_code;
 430     uint32_t hflags;    /* CPU State */
 431     /* TMASK defines different execution modes */
 432 #define MIPS_HFLAG_TMASK  0xC07FF
 433 #define MIPS_HFLAG_MODE   0x00007 /* execution modes                    */
 434     /* The KSU flags must be the lowest bits in hflags. The flag order
 435        must be the same as defined for CP0 Status. This allows to use
 436        the bits as the value of mmu_idx. */
 437 #define MIPS_HFLAG_KSU    0x00003 /* kernel/supervisor/user mode mask   */
 438 #define MIPS_HFLAG_UM     0x00002 /* user mode flag                     */
 439 #define MIPS_HFLAG_SM     0x00001 /* supervisor mode flag               */
 440 #define MIPS_HFLAG_KM     0x00000 /* kernel mode flag                   */
 441 #define MIPS_HFLAG_DM     0x00004 /* Debug mode                         */
 442 #define MIPS_HFLAG_64     0x00008 /* 64-bit instructions enabled        */
 443 #define MIPS_HFLAG_CP0    0x00010 /* CP0 enabled                        */
 444 #define MIPS_HFLAG_FPU    0x00020 /* FPU enabled                        */
 445 #define MIPS_HFLAG_F64    0x00040 /* 64-bit FPU enabled                 */
 446     /* True if the MIPS IV COP1X instructions can be used.  This also
 447        controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
 448        and RSQRT.D.  */
 449 #define MIPS_HFLAG_COP1X  0x00080 /* COP1X instructions enabled         */
 450 #define MIPS_HFLAG_RE     0x00100 /* Reversed endianness                */
 451 #define MIPS_HFLAG_UX     0x00200 /* 64-bit user mode                   */
 452 #define MIPS_HFLAG_M16    0x00400 /* MIPS16 mode flag                   */
 453 #define MIPS_HFLAG_M16_SHIFT 10
 454     /* If translation is interrupted between the branch instruction and
 455      * the delay slot, record what type of branch it is so that we can
 456      * resume translation properly.  It might be possible to reduce
 457      * this from three bits to two.  */
 458 #define MIPS_HFLAG_BMASK_BASE  0x03800
 459 #define MIPS_HFLAG_B      0x00800 /* Unconditional branch               */
 460 #define MIPS_HFLAG_BC     0x01000 /* Conditional branch                 */
 461 #define MIPS_HFLAG_BL     0x01800 /* Likely branch                      */
 462 #define MIPS_HFLAG_BR     0x02000 /* branch to register (can't link TB) */
 463     /* Extra flags about the current pending branch.  */
 464 #define MIPS_HFLAG_BMASK_EXT 0x3C000
 465 #define MIPS_HFLAG_B16    0x04000 /* branch instruction was 16 bits     */
 466 #define MIPS_HFLAG_BDS16  0x08000 /* branch requires 16-bit delay slot  */
 467 #define MIPS_HFLAG_BDS32  0x10000 /* branch requires 32-bit delay slot  */
 468 #define MIPS_HFLAG_BX     0x20000 /* branch exchanges execution mode    */
 469 #define MIPS_HFLAG_BMASK  (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT)
 470     /* MIPS DSP resources access. */
 471 #define MIPS_HFLAG_DSP   0x40000  /* Enable access to MIPS DSP resources. */
 472 #define MIPS_HFLAG_DSPR2 0x80000  /* Enable access to MIPS DSPR2 resources. */
 473     target_ulong btarget;        /* Jump / branch target               */
 474     target_ulong bcond;          /* Branch condition (if needed)       */
 475
 476     int SYNCI_Step; /* Address step size for SYNCI */
 477     int CCRes; /* Cycle count resolution/divisor */
 478     uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
 479     uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
 480     int insn_flags; /* Supported instruction set */
 481
 482     target_ulong tls_value; /* For usermode emulation */
 483
 484     CPU_COMMON
 485
 486     /* Fields from here on are preserved across CPU reset. */
 487     CPUMIPSMVPContext *mvp;
 488 #if !defined(CONFIG_USER_ONLY)
 489     CPUMIPSTLBContext *tlb;
 490 #endif
 491
 492     const mips_def_t *cpu_model;
 493     void *irq[8];
 494     QEMUTimer *timer; /* Internal timer */
 495 };
 496
 497 #include "cpu-qom.h"
 498
 499 #if !defined(CONFIG_USER_ONLY)
 500 int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
 501                         target_ulong address, int rw, int access_type);
 502 int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
 503                            target_ulong address, int rw, int access_type);
 504 int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
 505                      target_ulong address, int rw, int access_type);
 506 void r4k_helper_tlbwi(CPUMIPSState *env);
 507 void r4k_helper_tlbwr(CPUMIPSState *env);
 508 void r4k_helper_tlbp(CPUMIPSState *env);
 509 void r4k_helper_tlbr(CPUMIPSState *env);
 510
 511 void mips_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
 512                                 bool is_write, bool is_exec, int unused,
 513                                 unsigned size);
 514 #endif
 515
 516 void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
 517
 518 #define cpu_exec cpu_mips_exec
 519 #define cpu_gen_code cpu_mips_gen_code
 520 #define cpu_signal_handler cpu_mips_signal_handler
 521 #define cpu_list mips_cpu_list
 522
 523 extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env);
 524 extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
 525
 526 #define CPU_SAVE_VERSION 3
 527
 528 /* MMU modes definitions. We carefully match the indices with our
 529    hflags layout. */
 530 #define MMU_MODE0_SUFFIX _kernel
 531 #define MMU_MODE1_SUFFIX _super
 532 #define MMU_MODE2_SUFFIX _user
 533 #define MMU_USER_IDX 2
 534 static inline int cpu_mmu_index (CPUMIPSState *env)
 535 {
 536     return env->hflags & MIPS_HFLAG_KSU;
 537 }
 538
 539 static inline int cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
 540 {
 541     int32_t pending;
 542     int32_t status;
 543     int r;
 544
 545     if (!(env->CP0_Status & (1 << CP0St_IE)) ||
 546         (env->CP0_Status & (1 << CP0St_EXL)) ||
 547         (env->CP0_Status & (1 << CP0St_ERL)) ||
 548         /* Note that the TCStatus IXMT field is initialized to zero,
 549            and only MT capable cores can set it to one. So we don't
 550            need to check for MT capabilities here.  */
 551         (env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT)) ||
 552         (env->hflags & MIPS_HFLAG_DM)) {
 553         /* Interrupts are disabled */
 554         return 0;
 555     }
 556
 557     pending = env->CP0_Cause & CP0Ca_IP_mask;
 558     status = env->CP0_Status & CP0Ca_IP_mask;
 559
 560     if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
 561         /* A MIPS configured with a vectorizing external interrupt controller
 562            will feed a vector into the Cause pending lines. The core treats
 563            the status lines as a vector level, not as indiviual masks.  */
 564         r = pending > status;
 565     } else {
 566         /* A MIPS configured with compatibility or VInt (Vectored Interrupts)
 567            treats the pending lines as individual interrupt lines, the status
 568            lines are individual masks.  */
 569         r = pending & status;
 570     }
 571     return r;
 572 }
 573
 574 #include "exec/cpu-all.h"
 575
 576 /* Memory access type :
 577  * may be needed for precise access rights control and precise exceptions.
 578  */
 579 enum {
 580     /* 1 bit to define user level / supervisor access */
 581     ACCESS_USER  = 0x00,
 582     ACCESS_SUPER = 0x01,
 583     /* 1 bit to indicate direction */
 584     ACCESS_STORE = 0x02,
 585     /* Type of instruction that generated the access */
 586     ACCESS_CODE  = 0x10, /* Code fetch access                */
 587     ACCESS_INT   = 0x20, /* Integer load/store access        */
 588     ACCESS_FLOAT = 0x30, /* floating point load/store access */
 589 };
 590
 591 /* Exceptions */
 592 enum {
 593     EXCP_NONE          = -1,
 594     EXCP_RESET         = 0,
 595     EXCP_SRESET,
 596     EXCP_DSS,
 597     EXCP_DINT,
 598     EXCP_DDBL,
 599     EXCP_DDBS,
 600     EXCP_NMI,
 601     EXCP_MCHECK,
 602     EXCP_EXT_INTERRUPT, /* 8 */
 603     EXCP_DFWATCH,
 604     EXCP_DIB,
 605     EXCP_IWATCH,
 606     EXCP_AdEL,
 607     EXCP_AdES,
 608     EXCP_TLBF,
 609     EXCP_IBE,
 610     EXCP_DBp, /* 16 */
 611     EXCP_SYSCALL,
 612     EXCP_BREAK,
 613     EXCP_CpU,
 614     EXCP_RI,
 615     EXCP_OVERFLOW,
 616     EXCP_TRAP,
 617     EXCP_FPE,
 618     EXCP_DWATCH, /* 24 */
 619     EXCP_LTLBL,
 620     EXCP_TLBL,
 621     EXCP_TLBS,
 622     EXCP_DBE,
 623     EXCP_THREAD,
 624     EXCP_MDMX,
 625     EXCP_C2E,
 626     EXCP_CACHE, /* 32 */
 627     EXCP_DSPDIS,
 628
 629     EXCP_LAST = EXCP_DSPDIS,
 630 };
 631 /* Dummy exception for conditional stores.  */
 632 #define EXCP_SC 0x100
 633
 634 /*
 635  * This is an interrnally generated WAKE request line.
 636  * It is driven by the CPU itself. Raised when the MT
 637  * block wants to wake a VPE from an inactive state and
 638  * cleared when VPE goes from active to inactive.
 639  */
 640 #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
 641
 642 int cpu_mips_exec(CPUMIPSState *s);
 643 void mips_tcg_init(void);
 644 MIPSCPU *cpu_mips_init(const char *cpu_model);
 645 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
 646
 647 static inline CPUMIPSState *cpu_init(const char *cpu_model)
 648 {
 649     MIPSCPU *cpu = cpu_mips_init(cpu_model);
 650     if (cpu == NULL) {
 651         return NULL;
 652     }
 653     return &cpu->env;
 654 }
 655
 656 /* TODO QOM'ify CPU reset and remove */
 657 void cpu_state_reset(CPUMIPSState *s);
 658
 659 /* mips_timer.c */
 660 uint32_t cpu_mips_get_random (CPUMIPSState *env);
 661 uint32_t cpu_mips_get_count (CPUMIPSState *env);
 662 void cpu_mips_store_count (CPUMIPSState *env, uint32_t value);
 663 void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value);
 664 void cpu_mips_start_count(CPUMIPSState *env);
 665 void cpu_mips_stop_count(CPUMIPSState *env);
 666
 667 /* mips_int.c */
 668 void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
 669
 670 /* helper.c */
 671 int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
 672                               int mmu_idx);
 673 #if !defined(CONFIG_USER_ONLY)
 674 void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra);
 675 hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address,
 676                                                int rw);
 677 #endif
 678 target_ulong exception_resume_pc (CPUMIPSState *env);
 679
 680 static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc,
 681                                         target_ulong *cs_base, int *flags)
 682 {
 683     *pc = env->active_tc.PC;
 684     *cs_base = 0;
 685     *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
 686 }
 687
 688 static inline int mips_vpe_active(CPUMIPSState *env)
 689 {
 690     int active = 1;
 691
 692     /* Check that the VPE is enabled.  */
 693     if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
 694         active = 0;
 695     }
 696     /* Check that the VPE is activated.  */
 697     if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
 698         active = 0;
 699     }
 700
 701     /* Now verify that there are active thread contexts in the VPE.
 702
 703        This assumes the CPU model will internally reschedule threads
 704        if the active one goes to sleep. If there are no threads available
 705        the active one will be in a sleeping state, and we can turn off
 706        the entire VPE.  */
 707     if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
 708         /* TC is not activated.  */
 709         active = 0;
 710     }
 711     if (env->active_tc.CP0_TCHalt & 1) {
 712         /* TC is in halt state.  */
 713         active = 0;
 714     }
 715
 716     return active;
 717 }
 718
 719 #include "exec/exec-all.h"
 720
 721 static inline void compute_hflags(CPUMIPSState *env)
 722 {
 723     env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
 724                      MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
 725                      MIPS_HFLAG_UX | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2);
 726     if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
 727         !(env->CP0_Status & (1 << CP0St_ERL)) &&
 728         !(env->hflags & MIPS_HFLAG_DM)) {
 729         env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
 730     }
 731 #if defined(TARGET_MIPS64)
 732     if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
 733         (env->CP0_Status & (1 << CP0St_PX)) ||
 734         (env->CP0_Status & (1 << CP0St_UX))) {
 735         env->hflags |= MIPS_HFLAG_64;
 736     }
 737     if (env->CP0_Status & (1 << CP0St_UX)) {
 738         env->hflags |= MIPS_HFLAG_UX;
 739     }
 740 #endif
 741     if ((env->CP0_Status & (1 << CP0St_CU0)) ||
 742         !(env->hflags & MIPS_HFLAG_KSU)) {
 743         env->hflags |= MIPS_HFLAG_CP0;
 744     }
 745     if (env->CP0_Status & (1 << CP0St_CU1)) {
 746         env->hflags |= MIPS_HFLAG_FPU;
 747     }
 748     if (env->CP0_Status & (1 << CP0St_FR)) {
 749         env->hflags |= MIPS_HFLAG_F64;
 750     }
 751     if (env->insn_flags & ASE_DSPR2) {
 752         /* Enables access MIPS DSP resources, now our cpu is DSP ASER2,
 753            so enable to access DSPR2 resources. */
 754         if (env->CP0_Status & (1 << CP0St_MX)) {
 755             env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2;
 756         }
 757
 758     } else if (env->insn_flags & ASE_DSP) {
 759         /* Enables access MIPS DSP resources, now our cpu is DSP ASE,
 760            so enable to access DSP resources. */
 761         if (env->CP0_Status & (1 << CP0St_MX)) {
 762             env->hflags |= MIPS_HFLAG_DSP;
 763         }
 764
 765     }
 766     if (env->insn_flags & ISA_MIPS32R2) {
 767         if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
 768             env->hflags |= MIPS_HFLAG_COP1X;
 769         }
 770     } else if (env->insn_flags & ISA_MIPS32) {
 771         if (env->hflags & MIPS_HFLAG_64) {
 772             env->hflags |= MIPS_HFLAG_COP1X;
 773         }
 774     } else if (env->insn_flags & ISA_MIPS4) {
 775         /* All supported MIPS IV CPUs use the XX (CU3) to enable
 776            and disable the MIPS IV extensions to the MIPS III ISA.
 777            Some other MIPS IV CPUs ignore the bit, so the check here
 778            would be too restrictive for them.  */
 779         if (env->CP0_Status & (1U << CP0St_CU3)) {
 780             env->hflags |= MIPS_HFLAG_COP1X;
 781         }
 782     }
 783 }
 784
 785 #endif /* !defined (__MIPS_CPU_H__) */