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Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20171003.0' into...
[qemu/kevin.git] / target / ppc / cpu.h
blob64aef17f6fb7a0b7ecc753e8df36d8c2875630fc
1 /*
2 * PowerPC emulation cpu definitions for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef PPC_CPU_H
21 #define PPC_CPU_H
22
23 #include "qemu-common.h"
24 #include "qemu/int128.h"
25
26 //#define PPC_EMULATE_32BITS_HYPV
27
28 #if defined (TARGET_PPC64)
29 /* PowerPC 64 definitions */
30 #define TARGET_LONG_BITS 64
31 #define TARGET_PAGE_BITS 12
32
33 #define TCG_GUEST_DEFAULT_MO 0
34
35 /* Note that the official physical address space bits is 62-M where M
36 is implementation dependent. I've not looked up M for the set of
37 cpus we emulate at the system level. */
38 #define TARGET_PHYS_ADDR_SPACE_BITS 62
39
40 /* Note that the PPC environment architecture talks about 80 bit virtual
41 addresses, with segmentation. Obviously that's not all visible to a
42 single process, which is all we're concerned with here. */
43 #ifdef TARGET_ABI32
44 # define TARGET_VIRT_ADDR_SPACE_BITS 32
45 #else
46 # define TARGET_VIRT_ADDR_SPACE_BITS 64
47 #endif
48
49 #define TARGET_PAGE_BITS_64K 16
50 #define TARGET_PAGE_BITS_16M 24
51
52 #else /* defined (TARGET_PPC64) */
53 /* PowerPC 32 definitions */
54 #define TARGET_LONG_BITS 32
55
56 #if defined(TARGET_PPCEMB)
57 /* Specific definitions for PowerPC embedded */
58 /* BookE have 36 bits physical address space */
59 #if defined(CONFIG_USER_ONLY)
60 /* It looks like a lot of Linux programs assume page size
61 * is 4kB long. This is evil, but we have to deal with it...
62 */
63 #define TARGET_PAGE_BITS 12
64 #else /* defined(CONFIG_USER_ONLY) */
65 /* Pages can be 1 kB small */
66 #define TARGET_PAGE_BITS 10
67 #endif /* defined(CONFIG_USER_ONLY) */
68 #else /* defined(TARGET_PPCEMB) */
69 /* "standard" PowerPC 32 definitions */
70 #define TARGET_PAGE_BITS 12
71 #endif /* defined(TARGET_PPCEMB) */
72
73 #define TARGET_PHYS_ADDR_SPACE_BITS 36
74 #define TARGET_VIRT_ADDR_SPACE_BITS 32
75
76 #endif /* defined (TARGET_PPC64) */
77
78 #define CPUArchState struct CPUPPCState
79
80 #include "exec/cpu-defs.h"
81 #include "cpu-qom.h"
82 #include "fpu/softfloat.h"
83
84 #if defined (TARGET_PPC64)
85 #define PPC_ELF_MACHINE EM_PPC64
86 #else
87 #define PPC_ELF_MACHINE EM_PPC
88 #endif
89
90 /*****************************************************************************/
91 /* Exception vectors definitions */
92 enum {
93 POWERPC_EXCP_NONE = -1,
94 /* The 64 first entries are used by the PowerPC embedded specification */
95 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
96 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
97 POWERPC_EXCP_DSI = 2, /* Data storage exception */
98 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
99 POWERPC_EXCP_EXTERNAL = 4, /* External input */
100 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
101 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
102 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
103 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
104 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
105 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
106 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
107 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
108 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
109 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
110 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
111 /* Vectors 16 to 31 are reserved */
112 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
113 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
114 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
115 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
116 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
117 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
118 POWERPC_EXCP_GDOORI = 38, /* Embedded guest doorbell interrupt */
119 POWERPC_EXCP_GDOORCI = 39, /* Embedded guest doorbell critical interrupt*/
120 POWERPC_EXCP_HYPPRIV = 41, /* Embedded hypervisor priv instruction */
121 /* Vectors 42 to 63 are reserved */
122 /* Exceptions defined in the PowerPC server specification */
123 /* Server doorbell variants */
124 #define POWERPC_EXCP_SDOOR POWERPC_EXCP_GDOORI
125 #define POWERPC_EXCP_SDOOR_HV POWERPC_EXCP_DOORI
126 POWERPC_EXCP_RESET = 64, /* System reset exception */
127 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
128 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
129 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
130 POWERPC_EXCP_TRACE = 68, /* Trace exception */
131 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
132 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
133 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
134 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
135 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
136 /* 40x specific exceptions */
137 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
138 /* 601 specific exceptions */
139 POWERPC_EXCP_IO = 75, /* IO error exception */
140 POWERPC_EXCP_RUNM = 76, /* Run mode exception */
141 /* 602 specific exceptions */
142 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
143 /* 602/603 specific exceptions */
144 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
145 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
146 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
147 /* Exceptions available on most PowerPC */
148 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
149 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
150 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
151 POWERPC_EXCP_SMI = 84, /* System management interrupt */
152 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
153 /* 7xx/74xx specific exceptions */
154 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
155 /* 74xx specific exceptions */
156 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
157 /* 970FX specific exceptions */
158 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
159 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
160 /* Freescale embedded cores specific exceptions */
161 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
162 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
163 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
164 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
165 /* VSX Unavailable (Power ISA 2.06 and later) */
166 POWERPC_EXCP_VSXU = 94, /* VSX Unavailable */
167 POWERPC_EXCP_FU = 95, /* Facility Unavailable */
168 /* Additional ISA 2.06 and later server exceptions */
169 POWERPC_EXCP_HV_EMU = 96, /* HV emulation assistance */
170 POWERPC_EXCP_HV_MAINT = 97, /* HMI */
171 POWERPC_EXCP_HV_FU = 98, /* Hypervisor Facility unavailable */
172 /* EOL */
173 POWERPC_EXCP_NB = 99,
174 /* QEMU exceptions: used internally during code translation */
175 POWERPC_EXCP_STOP = 0x200, /* stop translation */
176 POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
177 /* QEMU exceptions: special cases we want to stop translation */
178 POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
179 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
180 POWERPC_EXCP_STCX = 0x204 /* Conditional stores in user mode */
181 };
182
183 /* Exceptions error codes */
184 enum {
185 /* Exception subtypes for POWERPC_EXCP_ALIGN */
186 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
187 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
188 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
189 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
190 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
191 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
192 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
193 /* FP exceptions */
194 POWERPC_EXCP_FP = 0x10,
195 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
196 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
197 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
198 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
199 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
200 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
201 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
202 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
203 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
204 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
205 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
206 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
207 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
208 /* Invalid instruction */
209 POWERPC_EXCP_INVAL = 0x20,
210 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
211 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
212 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
213 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
214 /* Privileged instruction */
215 POWERPC_EXCP_PRIV = 0x30,
216 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
217 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
218 /* Trap */
219 POWERPC_EXCP_TRAP = 0x40,
220 };
221
222 #define PPC_INPUT(env) (env->bus_model)
223
224 /*****************************************************************************/
225 typedef struct opc_handler_t opc_handler_t;
226
227 /*****************************************************************************/
228 /* Types used to describe some PowerPC registers etc. */
229 typedef struct DisasContext DisasContext;
230 typedef struct ppc_spr_t ppc_spr_t;
231 typedef union ppc_avr_t ppc_avr_t;
232 typedef union ppc_tlb_t ppc_tlb_t;
233 typedef struct ppc_hash_pte64 ppc_hash_pte64_t;
234
235 /* SPR access micro-ops generations callbacks */
236 struct ppc_spr_t {
237 void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num);
238 void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num);
239 #if !defined(CONFIG_USER_ONLY)
240 void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num);
241 void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num);
242 void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num);
243 void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num);
244 #endif
245 const char *name;
246 target_ulong default_value;
247 #ifdef CONFIG_KVM
248 /* We (ab)use the fact that all the SPRs will have ids for the
249 * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
250 * don't sync this */
251 uint64_t one_reg_id;
252 #endif
253 };
254
255 /* Altivec registers (128 bits) */
256 union ppc_avr_t {
257 float32 f[4];
258 uint8_t u8[16];
259 uint16_t u16[8];
260 uint32_t u32[4];
261 int8_t s8[16];
262 int16_t s16[8];
263 int32_t s32[4];
264 uint64_t u64[2];
265 int64_t s64[2];
266 #ifdef CONFIG_INT128
267 __uint128_t u128;
268 #endif
269 Int128 s128;
270 };
271
272 #if !defined(CONFIG_USER_ONLY)
273 /* Software TLB cache */
274 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
275 struct ppc6xx_tlb_t {
276 target_ulong pte0;
277 target_ulong pte1;
278 target_ulong EPN;
279 };
280
281 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
282 struct ppcemb_tlb_t {
283 uint64_t RPN;
284 target_ulong EPN;
285 target_ulong PID;
286 target_ulong size;
287 uint32_t prot;
288 uint32_t attr; /* Storage attributes */
289 };
290
291 typedef struct ppcmas_tlb_t {
292 uint32_t mas8;
293 uint32_t mas1;
294 uint64_t mas2;
295 uint64_t mas7_3;
296 } ppcmas_tlb_t;
297
298 union ppc_tlb_t {
299 ppc6xx_tlb_t *tlb6;
300 ppcemb_tlb_t *tlbe;
301 ppcmas_tlb_t *tlbm;
302 };
303
304 /* possible TLB variants */
305 #define TLB_NONE 0
306 #define TLB_6XX 1
307 #define TLB_EMB 2
308 #define TLB_MAS 3
309 #endif
310
311 typedef struct ppc_slb_t ppc_slb_t;
312 struct ppc_slb_t {
313 uint64_t esid;
314 uint64_t vsid;
315 const struct ppc_one_seg_page_size *sps;
316 };
317
318 #define MAX_SLB_ENTRIES 64
319 #define SEGMENT_SHIFT_256M 28
320 #define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
321
322 #define SEGMENT_SHIFT_1T 40
323 #define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1))
324
325
326 /*****************************************************************************/
327 /* Machine state register bits definition */
328 #define MSR_SF 63 /* Sixty-four-bit mode hflags */
329 #define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
330 #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
331 #define MSR_SHV 60 /* hypervisor state hflags */
332 #define MSR_TS0 34 /* Transactional state, 2 bits (Book3s) */
333 #define MSR_TS1 33
334 #define MSR_TM 32 /* Transactional Memory Available (Book3s) */
335 #define MSR_CM 31 /* Computation mode for BookE hflags */
336 #define MSR_ICM 30 /* Interrupt computation mode for BookE */
337 #define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
338 #define MSR_GS 28 /* guest state for BookE */
339 #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
340 #define MSR_VR 25 /* altivec available x hflags */
341 #define MSR_SPE 25 /* SPE enable for BookE x hflags */
342 #define MSR_AP 23 /* Access privilege state on 602 hflags */
343 #define MSR_VSX 23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */
344 #define MSR_SA 22 /* Supervisor access mode on 602 hflags */
345 #define MSR_KEY 19 /* key bit on 603e */
346 #define MSR_POW 18 /* Power management */
347 #define MSR_TGPR 17 /* TGPR usage on 602/603 x */
348 #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
349 #define MSR_ILE 16 /* Interrupt little-endian mode */
350 #define MSR_EE 15 /* External interrupt enable */
351 #define MSR_PR 14 /* Problem state hflags */
352 #define MSR_FP 13 /* Floating point available hflags */
353 #define MSR_ME 12 /* Machine check interrupt enable */
354 #define MSR_FE0 11 /* Floating point exception mode 0 hflags */
355 #define MSR_SE 10 /* Single-step trace enable x hflags */
356 #define MSR_DWE 10 /* Debug wait enable on 405 x */
357 #define MSR_UBLE 10 /* User BTB lock enable on e500 x */
358 #define MSR_BE 9 /* Branch trace enable x hflags */
359 #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
360 #define MSR_FE1 8 /* Floating point exception mode 1 hflags */
361 #define MSR_AL 7 /* AL bit on POWER */
362 #define MSR_EP 6 /* Exception prefix on 601 */
363 #define MSR_IR 5 /* Instruction relocate */
364 #define MSR_DR 4 /* Data relocate */
365 #define MSR_IS 5 /* Instruction address space (BookE) */
366 #define MSR_DS 4 /* Data address space (BookE) */
367 #define MSR_PE 3 /* Protection enable on 403 */
368 #define MSR_PX 2 /* Protection exclusive on 403 x */
369 #define MSR_PMM 2 /* Performance monitor mark on POWER x */
370 #define MSR_RI 1 /* Recoverable interrupt 1 */
371 #define MSR_LE 0 /* Little-endian mode 1 hflags */
372
373 /* LPCR bits */
374 #define LPCR_VPM0 (1ull << (63 - 0))
375 #define LPCR_VPM1 (1ull << (63 - 1))
376 #define LPCR_ISL (1ull << (63 - 2))
377 #define LPCR_KBV (1ull << (63 - 3))
378 #define LPCR_DPFD_SHIFT (63 - 11)
379 #define LPCR_DPFD (0x7ull << LPCR_DPFD_SHIFT)
380 #define LPCR_VRMASD_SHIFT (63 - 16)
381 #define LPCR_VRMASD (0x1full << LPCR_VRMASD_SHIFT)
382 /* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask */
383 #define LPCR_PECE_U_SHIFT (63 - 19)
384 #define LPCR_PECE_U_MASK (0x7ull << LPCR_PECE_U_SHIFT)
385 #define LPCR_HVEE (1ull << (63 - 17)) /* Hypervisor Virt Exit Enable */
386 #define LPCR_RMLS_SHIFT (63 - 37)
387 #define LPCR_RMLS (0xfull << LPCR_RMLS_SHIFT)
388 #define LPCR_ILE (1ull << (63 - 38))
389 #define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */
390 #define LPCR_AIL (3ull << LPCR_AIL_SHIFT)
391 #define LPCR_UPRT (1ull << (63 - 41)) /* Use Process Table */
392 #define LPCR_EVIRT (1ull << (63 - 42)) /* Enhanced Virtualisation */
393 #define LPCR_ONL (1ull << (63 - 45))
394 #define LPCR_LD (1ull << (63 - 46)) /* Large Decrementer */
395 #define LPCR_P7_PECE0 (1ull << (63 - 49))
396 #define LPCR_P7_PECE1 (1ull << (63 - 50))
397 #define LPCR_P7_PECE2 (1ull << (63 - 51))
398 #define LPCR_P8_PECE0 (1ull << (63 - 47))
399 #define LPCR_P8_PECE1 (1ull << (63 - 48))
400 #define LPCR_P8_PECE2 (1ull << (63 - 49))
401 #define LPCR_P8_PECE3 (1ull << (63 - 50))
402 #define LPCR_P8_PECE4 (1ull << (63 - 51))
403 /* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask */
404 #define LPCR_PECE_L_SHIFT (63 - 51)
405 #define LPCR_PECE_L_MASK (0x1full << LPCR_PECE_L_SHIFT)
406 #define LPCR_PDEE (1ull << (63 - 47)) /* Privileged Doorbell Exit EN */
407 #define LPCR_HDEE (1ull << (63 - 48)) /* Hyperv Doorbell Exit Enable */
408 #define LPCR_EEE (1ull << (63 - 49)) /* External Exit Enable */
409 #define LPCR_DEE (1ull << (63 - 50)) /* Decrementer Exit Enable */
410 #define LPCR_OEE (1ull << (63 - 51)) /* Other Exit Enable */
411 #define LPCR_MER (1ull << (63 - 52))
412 #define LPCR_GTSE (1ull << (63 - 53)) /* Guest Translation Shootdown */
413 #define LPCR_TC (1ull << (63 - 54))
414 #define LPCR_HEIC (1ull << (63 - 59)) /* HV Extern Interrupt Control */
415 #define LPCR_LPES0 (1ull << (63 - 60))
416 #define LPCR_LPES1 (1ull << (63 - 61))
417 #define LPCR_RMI (1ull << (63 - 62))
418 #define LPCR_HVICE (1ull << (63 - 62)) /* HV Virtualisation Int Enable */
419 #define LPCR_HDICE (1ull << (63 - 63))
420
421 #define msr_sf ((env->msr >> MSR_SF) & 1)
422 #define msr_isf ((env->msr >> MSR_ISF) & 1)
423 #define msr_shv ((env->msr >> MSR_SHV) & 1)
424 #define msr_cm ((env->msr >> MSR_CM) & 1)
425 #define msr_icm ((env->msr >> MSR_ICM) & 1)
426 #define msr_thv ((env->msr >> MSR_THV) & 1)
427 #define msr_gs ((env->msr >> MSR_GS) & 1)
428 #define msr_ucle ((env->msr >> MSR_UCLE) & 1)
429 #define msr_vr ((env->msr >> MSR_VR) & 1)
430 #define msr_spe ((env->msr >> MSR_SPE) & 1)
431 #define msr_ap ((env->msr >> MSR_AP) & 1)
432 #define msr_vsx ((env->msr >> MSR_VSX) & 1)
433 #define msr_sa ((env->msr >> MSR_SA) & 1)
434 #define msr_key ((env->msr >> MSR_KEY) & 1)
435 #define msr_pow ((env->msr >> MSR_POW) & 1)
436 #define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
437 #define msr_ce ((env->msr >> MSR_CE) & 1)
438 #define msr_ile ((env->msr >> MSR_ILE) & 1)
439 #define msr_ee ((env->msr >> MSR_EE) & 1)
440 #define msr_pr ((env->msr >> MSR_PR) & 1)
441 #define msr_fp ((env->msr >> MSR_FP) & 1)
442 #define msr_me ((env->msr >> MSR_ME) & 1)
443 #define msr_fe0 ((env->msr >> MSR_FE0) & 1)
444 #define msr_se ((env->msr >> MSR_SE) & 1)
445 #define msr_dwe ((env->msr >> MSR_DWE) & 1)
446 #define msr_uble ((env->msr >> MSR_UBLE) & 1)
447 #define msr_be ((env->msr >> MSR_BE) & 1)
448 #define msr_de ((env->msr >> MSR_DE) & 1)
449 #define msr_fe1 ((env->msr >> MSR_FE1) & 1)
450 #define msr_al ((env->msr >> MSR_AL) & 1)
451 #define msr_ep ((env->msr >> MSR_EP) & 1)
452 #define msr_ir ((env->msr >> MSR_IR) & 1)
453 #define msr_dr ((env->msr >> MSR_DR) & 1)
454 #define msr_is ((env->msr >> MSR_IS) & 1)
455 #define msr_ds ((env->msr >> MSR_DS) & 1)
456 #define msr_pe ((env->msr >> MSR_PE) & 1)
457 #define msr_px ((env->msr >> MSR_PX) & 1)
458 #define msr_pmm ((env->msr >> MSR_PMM) & 1)
459 #define msr_ri ((env->msr >> MSR_RI) & 1)
460 #define msr_le ((env->msr >> MSR_LE) & 1)
461 #define msr_ts ((env->msr >> MSR_TS1) & 3)
462 #define msr_tm ((env->msr >> MSR_TM) & 1)
463
464 /* Hypervisor bit is more specific */
465 #if defined(TARGET_PPC64)
466 #define MSR_HVB (1ULL << MSR_SHV)
467 #define msr_hv msr_shv
468 #else
469 #if defined(PPC_EMULATE_32BITS_HYPV)
470 #define MSR_HVB (1ULL << MSR_THV)
471 #define msr_hv msr_thv
472 #else
473 #define MSR_HVB (0ULL)
474 #define msr_hv (0)
475 #endif
476 #endif
477
478 /* DSISR */
479 #define DSISR_NOPTE 0x40000000
480 /* Not permitted by access authority of encoded access authority */
481 #define DSISR_PROTFAULT 0x08000000
482 #define DSISR_ISSTORE 0x02000000
483 /* Not permitted by virtual page class key protection */
484 #define DSISR_AMR 0x00200000
485 /* Unsupported Radix Tree Configuration */
486 #define DSISR_R_BADCONFIG 0x00080000
487
488 /* SRR1 error code fields */
489
490 #define SRR1_NOPTE DSISR_NOPTE
491 /* Not permitted due to no-execute or guard bit set */
492 #define SRR1_NOEXEC_GUARD 0x10000000
493 #define SRR1_PROTFAULT DSISR_PROTFAULT
494 #define SRR1_IAMR DSISR_AMR
495
496 /* Facility Status and Control (FSCR) bits */
497 #define FSCR_EBB (63 - 56) /* Event-Based Branch Facility */
498 #define FSCR_TAR (63 - 55) /* Target Address Register */
499 /* Interrupt cause mask and position in FSCR. HFSCR has the same format */
500 #define FSCR_IC_MASK (0xFFULL)
501 #define FSCR_IC_POS (63 - 7)
502 #define FSCR_IC_DSCR_SPR3 2
503 #define FSCR_IC_PMU 3
504 #define FSCR_IC_BHRB 4
505 #define FSCR_IC_TM 5
506 #define FSCR_IC_EBB 7
507 #define FSCR_IC_TAR 8
508
509 /* Exception state register bits definition */
510 #define ESR_PIL (1 << (63 - 36)) /* Illegal Instruction */
511 #define ESR_PPR (1 << (63 - 37)) /* Privileged Instruction */
512 #define ESR_PTR (1 << (63 - 38)) /* Trap */
513 #define ESR_FP (1 << (63 - 39)) /* Floating-Point Operation */
514 #define ESR_ST (1 << (63 - 40)) /* Store Operation */
515 #define ESR_AP (1 << (63 - 44)) /* Auxiliary Processor Operation */
516 #define ESR_PUO (1 << (63 - 45)) /* Unimplemented Operation */
517 #define ESR_BO (1 << (63 - 46)) /* Byte Ordering */
518 #define ESR_PIE (1 << (63 - 47)) /* Imprecise exception */
519 #define ESR_DATA (1 << (63 - 53)) /* Data Access (Embedded page table) */
520 #define ESR_TLBI (1 << (63 - 54)) /* TLB Ineligible (Embedded page table) */
521 #define ESR_PT (1 << (63 - 55)) /* Page Table (Embedded page table) */
522 #define ESR_SPV (1 << (63 - 56)) /* SPE/VMX operation */
523 #define ESR_EPID (1 << (63 - 57)) /* External Process ID operation */
524 #define ESR_VLEMI (1 << (63 - 58)) /* VLE operation */
525 #define ESR_MIF (1 << (63 - 62)) /* Misaligned instruction (VLE) */
526
527 /* Transaction EXception And Summary Register bits */
528 #define TEXASR_FAILURE_PERSISTENT (63 - 7)
529 #define TEXASR_DISALLOWED (63 - 8)
530 #define TEXASR_NESTING_OVERFLOW (63 - 9)
531 #define TEXASR_FOOTPRINT_OVERFLOW (63 - 10)
532 #define TEXASR_SELF_INDUCED_CONFLICT (63 - 11)
533 #define TEXASR_NON_TRANSACTIONAL_CONFLICT (63 - 12)
534 #define TEXASR_TRANSACTION_CONFLICT (63 - 13)
535 #define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
536 #define TEXASR_IMPLEMENTATION_SPECIFIC (63 - 15)
537 #define TEXASR_INSTRUCTION_FETCH_CONFLICT (63 - 16)
538 #define TEXASR_ABORT (63 - 31)
539 #define TEXASR_SUSPENDED (63 - 32)
540 #define TEXASR_PRIVILEGE_HV (63 - 34)
541 #define TEXASR_PRIVILEGE_PR (63 - 35)
542 #define TEXASR_FAILURE_SUMMARY (63 - 36)
543 #define TEXASR_TFIAR_EXACT (63 - 37)
544 #define TEXASR_ROT (63 - 38)
545 #define TEXASR_TRANSACTION_LEVEL (63 - 52) /* 12 bits */
546
547 enum {
548 POWERPC_FLAG_NONE = 0x00000000,
549 /* Flag for MSR bit 25 signification (VRE/SPE) */
550 POWERPC_FLAG_SPE = 0x00000001,
551 POWERPC_FLAG_VRE = 0x00000002,
552 /* Flag for MSR bit 17 signification (TGPR/CE) */
553 POWERPC_FLAG_TGPR = 0x00000004,
554 POWERPC_FLAG_CE = 0x00000008,
555 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
556 POWERPC_FLAG_SE = 0x00000010,
557 POWERPC_FLAG_DWE = 0x00000020,
558 POWERPC_FLAG_UBLE = 0x00000040,
559 /* Flag for MSR bit 9 signification (BE/DE) */
560 POWERPC_FLAG_BE = 0x00000080,
561 POWERPC_FLAG_DE = 0x00000100,
562 /* Flag for MSR bit 2 signification (PX/PMM) */
563 POWERPC_FLAG_PX = 0x00000200,
564 POWERPC_FLAG_PMM = 0x00000400,
565 /* Flag for special features */
566 /* Decrementer clock: RTC clock (POWER, 601) or bus clock */
567 POWERPC_FLAG_RTC_CLK = 0x00010000,
568 POWERPC_FLAG_BUS_CLK = 0x00020000,
569 /* Has CFAR */
570 POWERPC_FLAG_CFAR = 0x00040000,
571 /* Has VSX */
572 POWERPC_FLAG_VSX = 0x00080000,
573 /* Has Transaction Memory (ISA 2.07) */
574 POWERPC_FLAG_TM = 0x00100000,
575 };
576
577 /*****************************************************************************/
578 /* Floating point status and control register */
579 #define FPSCR_FX 31 /* Floating-point exception summary */
580 #define FPSCR_FEX 30 /* Floating-point enabled exception summary */
581 #define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
582 #define FPSCR_OX 28 /* Floating-point overflow exception */
583 #define FPSCR_UX 27 /* Floating-point underflow exception */
584 #define FPSCR_ZX 26 /* Floating-point zero divide exception */
585 #define FPSCR_XX 25 /* Floating-point inexact exception */
586 #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
587 #define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */
588 #define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */
589 #define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */
590 #define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */
591 #define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */
592 #define FPSCR_FR 18 /* Floating-point fraction rounded */
593 #define FPSCR_FI 17 /* Floating-point fraction inexact */
594 #define FPSCR_C 16 /* Floating-point result class descriptor */
595 #define FPSCR_FL 15 /* Floating-point less than or negative */
596 #define FPSCR_FG 14 /* Floating-point greater than or negative */
597 #define FPSCR_FE 13 /* Floating-point equal or zero */
598 #define FPSCR_FU 12 /* Floating-point unordered or NaN */
599 #define FPSCR_FPCC 12 /* Floating-point condition code */
600 #define FPSCR_FPRF 12 /* Floating-point result flags */
601 #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
602 #define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */
603 #define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
604 #define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
605 #define FPSCR_OE 6 /* Floating-point overflow exception enable */
606 #define FPSCR_UE 5 /* Floating-point undeflow exception enable */
607 #define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
608 #define FPSCR_XE 3 /* Floating-point inexact exception enable */
609 #define FPSCR_NI 2 /* Floating-point non-IEEE mode */
610 #define FPSCR_RN1 1
611 #define FPSCR_RN 0 /* Floating-point rounding control */
612 #define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
613 #define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
614 #define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
615 #define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
616 #define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
617 #define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
618 #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
619 #define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
620 #define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
621 #define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
622 #define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
623 #define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
624 #define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
625 #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
626 #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
627 #define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
628 #define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
629 #define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
630 #define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
631 #define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
632 #define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
633 #define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
634 #define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3)
635 /* Invalid operation exception summary */
636 #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
637 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
638 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
639 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
640 (1 << FPSCR_VXCVI)))
641 /* exception summary */
642 #define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
643 /* enabled exception summary */
644 #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
645 0x1F)
646
647 #define FP_FX (1ull << FPSCR_FX)
648 #define FP_FEX (1ull << FPSCR_FEX)
649 #define FP_VX (1ull << FPSCR_VX)
650 #define FP_OX (1ull << FPSCR_OX)
651 #define FP_UX (1ull << FPSCR_UX)
652 #define FP_ZX (1ull << FPSCR_ZX)
653 #define FP_XX (1ull << FPSCR_XX)
654 #define FP_VXSNAN (1ull << FPSCR_VXSNAN)
655 #define FP_VXISI (1ull << FPSCR_VXISI)
656 #define FP_VXIDI (1ull << FPSCR_VXIDI)
657 #define FP_VXZDZ (1ull << FPSCR_VXZDZ)
658 #define FP_VXIMZ (1ull << FPSCR_VXIMZ)
659 #define FP_VXVC (1ull << FPSCR_VXVC)
660 #define FP_FR (1ull << FSPCR_FR)
661 #define FP_FI (1ull << FPSCR_FI)
662 #define FP_C (1ull << FPSCR_C)
663 #define FP_FL (1ull << FPSCR_FL)
664 #define FP_FG (1ull << FPSCR_FG)
665 #define FP_FE (1ull << FPSCR_FE)
666 #define FP_FU (1ull << FPSCR_FU)
667 #define FP_FPCC (FP_FL | FP_FG | FP_FE | FP_FU)
668 #define FP_FPRF (FP_C | FP_FL | FP_FG | FP_FE | FP_FU)
669 #define FP_VXSOFT (1ull << FPSCR_VXSOFT)
670 #define FP_VXSQRT (1ull << FPSCR_VXSQRT)
671 #define FP_VXCVI (1ull << FPSCR_VXCVI)
672 #define FP_VE (1ull << FPSCR_VE)
673 #define FP_OE (1ull << FPSCR_OE)
674 #define FP_UE (1ull << FPSCR_UE)
675 #define FP_ZE (1ull << FPSCR_ZE)
676 #define FP_XE (1ull << FPSCR_XE)
677 #define FP_NI (1ull << FPSCR_NI)
678 #define FP_RN1 (1ull << FPSCR_RN1)
679 #define FP_RN (1ull << FPSCR_RN)
680
681 /* the exception bits which can be cleared by mcrfs - includes FX */
682 #define FP_EX_CLEAR_BITS (FP_FX | FP_OX | FP_UX | FP_ZX | \
683 FP_XX | FP_VXSNAN | FP_VXISI | FP_VXIDI | \
684 FP_VXZDZ | FP_VXIMZ | FP_VXVC | FP_VXSOFT | \
685 FP_VXSQRT | FP_VXCVI)
686
687 /*****************************************************************************/
688 /* Vector status and control register */
689 #define VSCR_NJ 16 /* Vector non-java */
690 #define VSCR_SAT 0 /* Vector saturation */
691 #define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1)
692 #define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1)
693
694 /*****************************************************************************/
695 /* BookE e500 MMU registers */
696
697 #define MAS0_NV_SHIFT 0
698 #define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT)
699
700 #define MAS0_WQ_SHIFT 12
701 #define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT)
702 /* Write TLB entry regardless of reservation */
703 #define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT)
704 /* Write TLB entry only already in use */
705 #define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT)
706 /* Clear TLB entry */
707 #define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT)
708
709 #define MAS0_HES_SHIFT 14
710 #define MAS0_HES (1 << MAS0_HES_SHIFT)
711
712 #define MAS0_ESEL_SHIFT 16
713 #define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT)
714
715 #define MAS0_TLBSEL_SHIFT 28
716 #define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT)
717 #define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT)
718 #define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT)
719 #define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT)
720 #define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT)
721
722 #define MAS0_ATSEL_SHIFT 31
723 #define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT)
724 #define MAS0_ATSEL_TLB 0
725 #define MAS0_ATSEL_LRAT MAS0_ATSEL
726
727 #define MAS1_TSIZE_SHIFT 7
728 #define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT)
729
730 #define MAS1_TS_SHIFT 12
731 #define MAS1_TS (1 << MAS1_TS_SHIFT)
732
733 #define MAS1_IND_SHIFT 13
734 #define MAS1_IND (1 << MAS1_IND_SHIFT)
735
736 #define MAS1_TID_SHIFT 16
737 #define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT)
738
739 #define MAS1_IPROT_SHIFT 30
740 #define MAS1_IPROT (1 << MAS1_IPROT_SHIFT)
741
742 #define MAS1_VALID_SHIFT 31
743 #define MAS1_VALID 0x80000000
744
745 #define MAS2_EPN_SHIFT 12
746 #define MAS2_EPN_MASK (~0ULL << MAS2_EPN_SHIFT)
747
748 #define MAS2_ACM_SHIFT 6
749 #define MAS2_ACM (1 << MAS2_ACM_SHIFT)
750
751 #define MAS2_VLE_SHIFT 5
752 #define MAS2_VLE (1 << MAS2_VLE_SHIFT)
753
754 #define MAS2_W_SHIFT 4
755 #define MAS2_W (1 << MAS2_W_SHIFT)
756
757 #define MAS2_I_SHIFT 3
758 #define MAS2_I (1 << MAS2_I_SHIFT)
759
760 #define MAS2_M_SHIFT 2
761 #define MAS2_M (1 << MAS2_M_SHIFT)
762
763 #define MAS2_G_SHIFT 1
764 #define MAS2_G (1 << MAS2_G_SHIFT)
765
766 #define MAS2_E_SHIFT 0
767 #define MAS2_E (1 << MAS2_E_SHIFT)
768
769 #define MAS3_RPN_SHIFT 12
770 #define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT)
771
772 #define MAS3_U0 0x00000200
773 #define MAS3_U1 0x00000100
774 #define MAS3_U2 0x00000080
775 #define MAS3_U3 0x00000040
776 #define MAS3_UX 0x00000020
777 #define MAS3_SX 0x00000010
778 #define MAS3_UW 0x00000008
779 #define MAS3_SW 0x00000004
780 #define MAS3_UR 0x00000002
781 #define MAS3_SR 0x00000001
782 #define MAS3_SPSIZE_SHIFT 1
783 #define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT)
784
785 #define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT
786 #define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK
787 #define MAS4_TIDSELD_MASK 0x00030000
788 #define MAS4_TIDSELD_PID0 0x00000000
789 #define MAS4_TIDSELD_PID1 0x00010000
790 #define MAS4_TIDSELD_PID2 0x00020000
791 #define MAS4_TIDSELD_PIDZ 0x00030000
792 #define MAS4_INDD 0x00008000 /* Default IND */
793 #define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT
794 #define MAS4_TSIZED_MASK MAS1_TSIZE_MASK
795 #define MAS4_ACMD 0x00000040
796 #define MAS4_VLED 0x00000020
797 #define MAS4_WD 0x00000010
798 #define MAS4_ID 0x00000008
799 #define MAS4_MD 0x00000004
800 #define MAS4_GD 0x00000002
801 #define MAS4_ED 0x00000001
802 #define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */
803 #define MAS4_WIMGED_SHIFT 0
804
805 #define MAS5_SGS 0x80000000
806 #define MAS5_SLPID_MASK 0x00000fff
807
808 #define MAS6_SPID0 0x3fff0000
809 #define MAS6_SPID1 0x00007ffe
810 #define MAS6_ISIZE(x) MAS1_TSIZE(x)
811 #define MAS6_SAS 0x00000001
812 #define MAS6_SPID MAS6_SPID0
813 #define MAS6_SIND 0x00000002 /* Indirect page */
814 #define MAS6_SIND_SHIFT 1
815 #define MAS6_SPID_MASK 0x3fff0000
816 #define MAS6_SPID_SHIFT 16
817 #define MAS6_ISIZE_MASK 0x00000f80
818 #define MAS6_ISIZE_SHIFT 7
819
820 #define MAS7_RPN 0xffffffff
821
822 #define MAS8_TGS 0x80000000
823 #define MAS8_VF 0x40000000
824 #define MAS8_TLBPID 0x00000fff
825
826 /* Bit definitions for MMUCFG */
827 #define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
828 #define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
829 #define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
830 #define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
831 #define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
832 #define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
833 #define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
834 #define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
835 #define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
836
837 /* Bit definitions for MMUCSR0 */
838 #define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
839 #define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
840 #define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
841 #define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
842 #define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
843 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
844 #define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
845 #define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
846 #define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
847 #define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
848
849 /* TLBnCFG encoding */
850 #define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
851 #define TLBnCFG_HES 0x00002000 /* HW select supported */
852 #define TLBnCFG_AVAIL 0x00004000 /* variable page size */
853 #define TLBnCFG_IPROT 0x00008000 /* IPROT supported */
854 #define TLBnCFG_GTWE 0x00010000 /* Guest can write */
855 #define TLBnCFG_IND 0x00020000 /* IND entries supported */
856 #define TLBnCFG_PT 0x00040000 /* Can load from page table */
857 #define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
858 #define TLBnCFG_MINSIZE_SHIFT 20
859 #define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
860 #define TLBnCFG_MAXSIZE_SHIFT 16
861 #define TLBnCFG_ASSOC 0xff000000 /* Associativity */
862 #define TLBnCFG_ASSOC_SHIFT 24
863
864 /* TLBnPS encoding */
865 #define TLBnPS_4K 0x00000004
866 #define TLBnPS_8K 0x00000008
867 #define TLBnPS_16K 0x00000010
868 #define TLBnPS_32K 0x00000020
869 #define TLBnPS_64K 0x00000040
870 #define TLBnPS_128K 0x00000080
871 #define TLBnPS_256K 0x00000100
872 #define TLBnPS_512K 0x00000200
873 #define TLBnPS_1M 0x00000400
874 #define TLBnPS_2M 0x00000800
875 #define TLBnPS_4M 0x00001000
876 #define TLBnPS_8M 0x00002000
877 #define TLBnPS_16M 0x00004000
878 #define TLBnPS_32M 0x00008000
879 #define TLBnPS_64M 0x00010000
880 #define TLBnPS_128M 0x00020000
881 #define TLBnPS_256M 0x00040000
882 #define TLBnPS_512M 0x00080000
883 #define TLBnPS_1G 0x00100000
884 #define TLBnPS_2G 0x00200000
885 #define TLBnPS_4G 0x00400000
886 #define TLBnPS_8G 0x00800000
887 #define TLBnPS_16G 0x01000000
888 #define TLBnPS_32G 0x02000000
889 #define TLBnPS_64G 0x04000000
890 #define TLBnPS_128G 0x08000000
891 #define TLBnPS_256G 0x10000000
892
893 /* tlbilx action encoding */
894 #define TLBILX_T_ALL 0
895 #define TLBILX_T_TID 1
896 #define TLBILX_T_FULLMATCH 3
897 #define TLBILX_T_CLASS0 4
898 #define TLBILX_T_CLASS1 5
899 #define TLBILX_T_CLASS2 6
900 #define TLBILX_T_CLASS3 7
901
902 /* BookE 2.06 helper defines */
903
904 #define BOOKE206_FLUSH_TLB0 (1 << 0)
905 #define BOOKE206_FLUSH_TLB1 (1 << 1)
906 #define BOOKE206_FLUSH_TLB2 (1 << 2)
907 #define BOOKE206_FLUSH_TLB3 (1 << 3)
908
909 /* number of possible TLBs */
910 #define BOOKE206_MAX_TLBN 4
911
912 /*****************************************************************************/
913 /* Embedded.Processor Control */
914
915 #define DBELL_TYPE_SHIFT 27
916 #define DBELL_TYPE_MASK (0x1f << DBELL_TYPE_SHIFT)
917 #define DBELL_TYPE_DBELL (0x00 << DBELL_TYPE_SHIFT)
918 #define DBELL_TYPE_DBELL_CRIT (0x01 << DBELL_TYPE_SHIFT)
919 #define DBELL_TYPE_G_DBELL (0x02 << DBELL_TYPE_SHIFT)
920 #define DBELL_TYPE_G_DBELL_CRIT (0x03 << DBELL_TYPE_SHIFT)
921 #define DBELL_TYPE_G_DBELL_MC (0x04 << DBELL_TYPE_SHIFT)
922
923 #define DBELL_BRDCAST (1 << 26)
924 #define DBELL_LPIDTAG_SHIFT 14
925 #define DBELL_LPIDTAG_MASK (0xfff << DBELL_LPIDTAG_SHIFT)
926 #define DBELL_PIRTAG_MASK 0x3fff
927
928 /*****************************************************************************/
929 /* Segment page size information, used by recent hash MMUs
930 * The format of this structure mirrors kvm_ppc_smmu_info
931 */
932
933 #define PPC_PAGE_SIZES_MAX_SZ 8
934
935 struct ppc_one_page_size {
936 uint32_t page_shift; /* Page shift (or 0) */
937 uint32_t pte_enc; /* Encoding in the HPTE (>>12) */
938 };
939
940 struct ppc_one_seg_page_size {
941 uint32_t page_shift; /* Base page shift of segment (or 0) */
942 uint32_t slb_enc; /* SLB encoding for BookS */
943 struct ppc_one_page_size enc[PPC_PAGE_SIZES_MAX_SZ];
944 };
945
946 struct ppc_segment_page_sizes {
947 struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
948 };
949
950 struct ppc_radix_page_info {
951 uint32_t count;
952 uint32_t entries[PPC_PAGE_SIZES_MAX_SZ];
953 };
954
955 /*****************************************************************************/
956 /* The whole PowerPC CPU context */
957 #define NB_MMU_MODES 8
958
959 #define PPC_CPU_OPCODES_LEN 0x40
960 #define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
961
962 struct CPUPPCState {
963 /* First are the most commonly used resources
964 * during translated code execution
965 */
966 /* general purpose registers */
967 target_ulong gpr[32];
968 /* Storage for GPR MSB, used by the SPE extension */
969 target_ulong gprh[32];
970 /* LR */
971 target_ulong lr;
972 /* CTR */
973 target_ulong ctr;
974 /* condition register */
975 uint32_t crf[8];
976 #if defined(TARGET_PPC64)
977 /* CFAR */
978 target_ulong cfar;
979 #endif
980 /* XER (with SO, OV, CA split out) */
981 target_ulong xer;
982 target_ulong so;
983 target_ulong ov;
984 target_ulong ca;
985 target_ulong ov32;
986 target_ulong ca32;
987 /* Reservation address */
988 target_ulong reserve_addr;
989 /* Reservation value */
990 target_ulong reserve_val;
991 target_ulong reserve_val2;
992 /* Reservation store address */
993 target_ulong reserve_ea;
994 /* Reserved store source register and size */
995 target_ulong reserve_info;
996
997 /* Those ones are used in supervisor mode only */
998 /* machine state register */
999 target_ulong msr;
1000 /* temporary general purpose registers */
1001 target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
1002
1003 /* Floating point execution context */
1004 float_status fp_status;
1005 /* floating point registers */
1006 float64 fpr[32];
1007 /* floating point status and control register */
1008 target_ulong fpscr;
1009
1010 /* Next instruction pointer */
1011 target_ulong nip;
1012
1013 int access_type; /* when a memory exception occurs, the access
1014 type is stored here */
1015
1016 CPU_COMMON
1017
1018 /* MMU context - only relevant for full system emulation */
1019 #if !defined(CONFIG_USER_ONLY)
1020 #if defined(TARGET_PPC64)
1021 /* PowerPC 64 SLB area */
1022 ppc_slb_t slb[MAX_SLB_ENTRIES];
1023 int32_t slb_nr;
1024 /* tcg TLB needs flush (deferred slb inval instruction typically) */
1025 #endif
1026 /* segment registers */
1027 target_ulong sr[32];
1028 /* BATs */
1029 uint32_t nb_BATs;
1030 target_ulong DBAT[2][8];
1031 target_ulong IBAT[2][8];
1032 /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
1033 int32_t nb_tlb; /* Total number of TLB */
1034 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
1035 int nb_ways; /* Number of ways in the TLB set */
1036 int last_way; /* Last used way used to allocate TLB in a LRU way */
1037 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
1038 int nb_pids; /* Number of available PID registers */
1039 int tlb_type; /* Type of TLB we're dealing with */
1040 ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
1041 /* 403 dedicated access protection registers */
1042 target_ulong pb[4];
1043 bool tlb_dirty; /* Set to non-zero when modifying TLB */
1044 bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
1045 uint32_t tlb_need_flush; /* Delayed flush needed */
1046 #define TLB_NEED_LOCAL_FLUSH 0x1
1047 #define TLB_NEED_GLOBAL_FLUSH 0x2
1048 #endif
1049
1050 /* Other registers */
1051 /* Special purpose registers */
1052 target_ulong spr[1024];
1053 ppc_spr_t spr_cb[1024];
1054 /* Altivec registers */
1055 ppc_avr_t avr[32];
1056 uint32_t vscr;
1057 /* VSX registers */
1058 uint64_t vsr[32];
1059 /* SPE registers */
1060 uint64_t spe_acc;
1061 uint32_t spe_fscr;
1062 /* SPE and Altivec can share a status since they will never be used
1063 * simultaneously */
1064 float_status vec_status;
1065
1066 /* Internal devices resources */
1067 /* Time base and decrementer */
1068 ppc_tb_t *tb_env;
1069 /* Device control registers */
1070 ppc_dcr_t *dcr_env;
1071
1072 int dcache_line_size;
1073 int icache_line_size;
1074
1075 /* Those resources are used during exception processing */
1076 /* CPU model definition */
1077 target_ulong msr_mask;
1078 powerpc_mmu_t mmu_model;
1079 powerpc_excp_t excp_model;
1080 powerpc_input_t bus_model;
1081 int bfd_mach;
1082 uint32_t flags;
1083 uint64_t insns_flags;
1084 uint64_t insns_flags2;
1085 #if defined(TARGET_PPC64)
1086 struct ppc_segment_page_sizes sps;
1087 ppc_slb_t vrma_slb;
1088 target_ulong rmls;
1089 bool ci_large_pages;
1090 #endif
1091
1092 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1093 uint64_t vpa_addr;
1094 uint64_t slb_shadow_addr, slb_shadow_size;
1095 uint64_t dtl_addr, dtl_size;
1096 #endif /* TARGET_PPC64 */
1097
1098 int error_code;
1099 uint32_t pending_interrupts;
1100 #if !defined(CONFIG_USER_ONLY)
1101 /* This is the IRQ controller, which is implementation dependent
1102 * and only relevant when emulating a complete machine.
1103 */
1104 uint32_t irq_input_state;
1105 void **irq_inputs;
1106 /* Exception vectors */
1107 target_ulong excp_vectors[POWERPC_EXCP_NB];
1108 target_ulong excp_prefix;
1109 target_ulong ivor_mask;
1110 target_ulong ivpr_mask;
1111 target_ulong hreset_vector;
1112 hwaddr mpic_iack;
1113 /* true when the external proxy facility mode is enabled */
1114 bool mpic_proxy;
1115 /* set when the processor has an HV mode, thus HV priv
1116 * instructions and SPRs are diallowed if MSR:HV is 0
1117 */
1118 bool has_hv_mode;
1119 /* On P7/P8, set when in PM state, we need to handle resume
1120 * in a special way (such as routing some resume causes to
1121 * 0x100), so flag this here.
1122 */
1123 bool in_pm_state;
1124 #endif
1125
1126 /* Those resources are used only during code translation */
1127 /* opcode handlers */
1128 opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
1129
1130 /* Those resources are used only in QEMU core */
1131 target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
1132 target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */
1133 int immu_idx; /* precomputed MMU index to speed up insn access */
1134 int dmmu_idx; /* precomputed MMU index to speed up data accesses */
1135
1136 /* Power management */
1137 int (*check_pow)(CPUPPCState *env);
1138
1139 #if !defined(CONFIG_USER_ONLY)
1140 void *load_info; /* Holds boot loading state. */
1141 #endif
1142
1143 /* booke timers */
1144
1145 /* Specifies bit locations of the Time Base used to signal a fixed timer
1146 * exception on a transition from 0 to 1. (watchdog or fixed-interval timer)
1147 *
1148 * 0 selects the least significant bit.
1149 * 63 selects the most significant bit.
1150 */
1151 uint8_t fit_period[4];
1152 uint8_t wdt_period[4];
1153
1154 /* Transactional memory state */
1155 target_ulong tm_gpr[32];
1156 ppc_avr_t tm_vsr[64];
1157 uint64_t tm_cr;
1158 uint64_t tm_lr;
1159 uint64_t tm_ctr;
1160 uint64_t tm_fpscr;
1161 uint64_t tm_amr;
1162 uint64_t tm_ppr;
1163 uint64_t tm_vrsave;
1164 uint32_t tm_vscr;
1165 uint64_t tm_dscr;
1166 uint64_t tm_tar;
1167 };
1168
1169 #define SET_FIT_PERIOD(a_, b_, c_, d_) \
1170 do { \
1171 env->fit_period[0] = (a_); \
1172 env->fit_period[1] = (b_); \
1173 env->fit_period[2] = (c_); \
1174 env->fit_period[3] = (d_); \
1175 } while (0)
1176
1177 #define SET_WDT_PERIOD(a_, b_, c_, d_) \
1178 do { \
1179 env->wdt_period[0] = (a_); \
1180 env->wdt_period[1] = (b_); \
1181 env->wdt_period[2] = (c_); \
1182 env->wdt_period[3] = (d_); \
1183 } while (0)
1184
1185 typedef struct PPCVirtualHypervisor PPCVirtualHypervisor;
1186 typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
1187
1188 /**
1189 * PowerPCCPU:
1190 * @env: #CPUPPCState
1191 * @vcpu_id: vCPU identifier given to KVM
1192 * @compat_pvr: Current logical PVR, zero if in "raw" mode
1193 *
1194 * A PowerPC CPU.
1195 */
1196 struct PowerPCCPU {
1197 /*< private >*/
1198 CPUState parent_obj;
1199 /*< public >*/
1200
1201 CPUPPCState env;
1202 int vcpu_id;
1203 uint32_t compat_pvr;
1204 PPCVirtualHypervisor *vhyp;
1205 Object *intc;
1206 int32_t node_id; /* NUMA node this CPU belongs to */
1207
1208 /* Fields related to migration compatibility hacks */
1209 bool pre_2_8_migration;
1210 target_ulong mig_msr_mask;
1211 uint64_t mig_insns_flags;
1212 uint64_t mig_insns_flags2;
1213 uint32_t mig_nb_BATs;
1214 bool pre_2_10_migration;
1215 };
1216
1217 static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env)
1218 {
1219 return container_of(env, PowerPCCPU, env);
1220 }
1221
1222 #define ENV_GET_CPU(e) CPU(ppc_env_get_cpu(e))
1223
1224 #define ENV_OFFSET offsetof(PowerPCCPU, env)
1225
1226 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
1227 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
1228 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc);
1229
1230 struct PPCVirtualHypervisor {
1231 Object parent;
1232 };
1233
1234 struct PPCVirtualHypervisorClass {
1235 InterfaceClass parent;
1236 void (*hypercall)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1237 hwaddr (*hpt_mask)(PPCVirtualHypervisor *vhyp);
1238 const ppc_hash_pte64_t *(*map_hptes)(PPCVirtualHypervisor *vhyp,
1239 hwaddr ptex, int n);
1240 void (*unmap_hptes)(PPCVirtualHypervisor *vhyp,
1241 const ppc_hash_pte64_t *hptes,
1242 hwaddr ptex, int n);
1243 void (*store_hpte)(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1244 uint64_t pte0, uint64_t pte1);
1245 uint64_t (*get_patbe)(PPCVirtualHypervisor *vhyp);
1246 target_ulong (*encode_hpt_for_kvm_pr)(PPCVirtualHypervisor *vhyp);
1247 };
1248
1249 #define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor"
1250 #define PPC_VIRTUAL_HYPERVISOR(obj) \
1251 OBJECT_CHECK(PPCVirtualHypervisor, (obj), TYPE_PPC_VIRTUAL_HYPERVISOR)
1252 #define PPC_VIRTUAL_HYPERVISOR_CLASS(klass) \
1253 OBJECT_CLASS_CHECK(PPCVirtualHypervisorClass, (klass), \
1254 TYPE_PPC_VIRTUAL_HYPERVISOR)
1255 #define PPC_VIRTUAL_HYPERVISOR_GET_CLASS(obj) \
1256 OBJECT_GET_CLASS(PPCVirtualHypervisorClass, (obj), \
1257 TYPE_PPC_VIRTUAL_HYPERVISOR)
1258
1259 void ppc_cpu_do_interrupt(CPUState *cpu);
1260 bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req);
1261 void ppc_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
1262 int flags);
1263 void ppc_cpu_dump_statistics(CPUState *cpu, FILE *f,
1264 fprintf_function cpu_fprintf, int flags);
1265 hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
1266 int ppc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
1267 int ppc_cpu_gdb_read_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1268 int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1269 int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1270 int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1271 int cpuid, void *opaque);
1272 int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
1273 int cpuid, void *opaque);
1274 #ifndef CONFIG_USER_ONLY
1275 void ppc_cpu_do_system_reset(CPUState *cs);
1276 extern const struct VMStateDescription vmstate_ppc_cpu;
1277 #endif
1278
1279 /*****************************************************************************/
1280 void ppc_translate_init(void);
1281 const char *ppc_cpu_lookup_alias(const char *alias);
1282 /* you can call this signal handler from your SIGBUS and SIGSEGV
1283 signal handlers to inform the virtual CPU of exceptions. non zero
1284 is returned if the signal was handled by the virtual CPU. */
1285 int cpu_ppc_signal_handler (int host_signum, void *pinfo,
1286 void *puc);
1287 #if defined(CONFIG_USER_ONLY)
1288 int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
1289 int mmu_idx);
1290 #endif
1291
1292 #if !defined(CONFIG_USER_ONLY)
1293 void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
1294 #endif /* !defined(CONFIG_USER_ONLY) */
1295 void ppc_store_msr (CPUPPCState *env, target_ulong value);
1296
1297 void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
1298 #if defined(TARGET_PPC64)
1299 #endif
1300
1301 /* Time-base and decrementer management */
1302 #ifndef NO_CPU_IO_DEFS
1303 uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
1304 uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
1305 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
1306 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
1307 uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
1308 uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
1309 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
1310 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
1311 bool ppc_decr_clear_on_delivery(CPUPPCState *env);
1312 uint32_t cpu_ppc_load_decr (CPUPPCState *env);
1313 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
1314 uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
1315 void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
1316 uint64_t cpu_ppc_load_purr (CPUPPCState *env);
1317 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
1318 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
1319 #if !defined(CONFIG_USER_ONLY)
1320 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
1321 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
1322 target_ulong load_40x_pit (CPUPPCState *env);
1323 void store_40x_pit (CPUPPCState *env, target_ulong val);
1324 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
1325 void store_40x_sler (CPUPPCState *env, uint32_t val);
1326 void store_booke_tcr (CPUPPCState *env, target_ulong val);
1327 void store_booke_tsr (CPUPPCState *env, target_ulong val);
1328 void ppc_tlb_invalidate_all (CPUPPCState *env);
1329 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
1330 void cpu_ppc_set_papr(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp);
1331 #endif
1332 #endif
1333
1334 void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask);
1335
1336 static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1337 {
1338 uint64_t gprv;
1339
1340 gprv = env->gpr[gprn];
1341 if (env->flags & POWERPC_FLAG_SPE) {
1342 /* If the CPU implements the SPE extension, we have to get the
1343 * high bits of the GPR from the gprh storage area
1344 */
1345 gprv &= 0xFFFFFFFFULL;
1346 gprv |= (uint64_t)env->gprh[gprn] << 32;
1347 }
1348
1349 return gprv;
1350 }
1351
1352 /* Device control registers */
1353 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1354 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1355
1356 #define cpu_init(cpu_model) cpu_generic_init(TYPE_POWERPC_CPU, cpu_model)
1357
1358 #define POWERPC_CPU_TYPE_SUFFIX "-" TYPE_POWERPC_CPU
1359 #define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX
1360
1361 #define cpu_signal_handler cpu_ppc_signal_handler
1362 #define cpu_list ppc_cpu_list
1363
1364 /* MMU modes definitions */
1365 #define MMU_USER_IDX 0
1366 static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
1367 {
1368 return ifetch ? env->immu_idx : env->dmmu_idx;
1369 }
1370
1371 /* Compatibility modes */
1372 #if defined(TARGET_PPC64)
1373 bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr,
1374 uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1375 void ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp);
1376 #if !defined(CONFIG_USER_ONLY)
1377 void ppc_set_compat_all(uint32_t compat_pvr, Error **errp);
1378 #endif
1379 int ppc_compat_max_threads(PowerPCCPU *cpu);
1380 void ppc_compat_add_property(Object *obj, const char *name,
1381 uint32_t *compat_pvr, const char *basedesc,
1382 Error **errp);
1383 #endif /* defined(TARGET_PPC64) */
1384
1385 #include "exec/cpu-all.h"
1386
1387 /*****************************************************************************/
1388 /* CRF definitions */
1389 #define CRF_LT_BIT 3
1390 #define CRF_GT_BIT 2
1391 #define CRF_EQ_BIT 1
1392 #define CRF_SO_BIT 0
1393 #define CRF_LT (1 << CRF_LT_BIT)
1394 #define CRF_GT (1 << CRF_GT_BIT)
1395 #define CRF_EQ (1 << CRF_EQ_BIT)
1396 #define CRF_SO (1 << CRF_SO_BIT)
1397 /* For SPE extensions */
1398 #define CRF_CH (1 << CRF_LT_BIT)
1399 #define CRF_CL (1 << CRF_GT_BIT)
1400 #define CRF_CH_OR_CL (1 << CRF_EQ_BIT)
1401 #define CRF_CH_AND_CL (1 << CRF_SO_BIT)
1402
1403 /* XER definitions */
1404 #define XER_SO 31
1405 #define XER_OV 30
1406 #define XER_CA 29
1407 #define XER_OV32 19
1408 #define XER_CA32 18
1409 #define XER_CMP 8
1410 #define XER_BC 0
1411 #define xer_so (env->so)
1412 #define xer_ov (env->ov)
1413 #define xer_ca (env->ca)
1414 #define xer_ov32 (env->ov)
1415 #define xer_ca32 (env->ca)
1416 #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1417 #define xer_bc ((env->xer >> XER_BC) & 0x7F)
1418
1419 /* SPR definitions */
1420 #define SPR_MQ (0x000)
1421 #define SPR_XER (0x001)
1422 #define SPR_601_VRTCU (0x004)
1423 #define SPR_601_VRTCL (0x005)
1424 #define SPR_601_UDECR (0x006)
1425 #define SPR_LR (0x008)
1426 #define SPR_CTR (0x009)
1427 #define SPR_UAMR (0x00D)
1428 #define SPR_DSCR (0x011)
1429 #define SPR_DSISR (0x012)
1430 #define SPR_DAR (0x013) /* DAE for PowerPC 601 */
1431 #define SPR_601_RTCU (0x014)
1432 #define SPR_601_RTCL (0x015)
1433 #define SPR_DECR (0x016)
1434 #define SPR_SDR1 (0x019)
1435 #define SPR_SRR0 (0x01A)
1436 #define SPR_SRR1 (0x01B)
1437 #define SPR_CFAR (0x01C)
1438 #define SPR_AMR (0x01D)
1439 #define SPR_ACOP (0x01F)
1440 #define SPR_BOOKE_PID (0x030)
1441 #define SPR_BOOKS_PID (0x030)
1442 #define SPR_BOOKE_DECAR (0x036)
1443 #define SPR_BOOKE_CSRR0 (0x03A)
1444 #define SPR_BOOKE_CSRR1 (0x03B)
1445 #define SPR_BOOKE_DEAR (0x03D)
1446 #define SPR_IAMR (0x03D)
1447 #define SPR_BOOKE_ESR (0x03E)
1448 #define SPR_BOOKE_IVPR (0x03F)
1449 #define SPR_MPC_EIE (0x050)
1450 #define SPR_MPC_EID (0x051)
1451 #define SPR_MPC_NRI (0x052)
1452 #define SPR_TFHAR (0x080)
1453 #define SPR_TFIAR (0x081)
1454 #define SPR_TEXASR (0x082)
1455 #define SPR_TEXASRU (0x083)
1456 #define SPR_UCTRL (0x088)
1457 #define SPR_TIDR (0x090)
1458 #define SPR_MPC_CMPA (0x090)
1459 #define SPR_MPC_CMPB (0x091)
1460 #define SPR_MPC_CMPC (0x092)
1461 #define SPR_MPC_CMPD (0x093)
1462 #define SPR_MPC_ECR (0x094)
1463 #define SPR_MPC_DER (0x095)
1464 #define SPR_MPC_COUNTA (0x096)
1465 #define SPR_MPC_COUNTB (0x097)
1466 #define SPR_CTRL (0x098)
1467 #define SPR_MPC_CMPE (0x098)
1468 #define SPR_MPC_CMPF (0x099)
1469 #define SPR_FSCR (0x099)
1470 #define SPR_MPC_CMPG (0x09A)
1471 #define SPR_MPC_CMPH (0x09B)
1472 #define SPR_MPC_LCTRL1 (0x09C)
1473 #define SPR_MPC_LCTRL2 (0x09D)
1474 #define SPR_UAMOR (0x09D)
1475 #define SPR_MPC_ICTRL (0x09E)
1476 #define SPR_MPC_BAR (0x09F)
1477 #define SPR_PSPB (0x09F)
1478 #define SPR_DAWR (0x0B4)
1479 #define SPR_RPR (0x0BA)
1480 #define SPR_CIABR (0x0BB)
1481 #define SPR_DAWRX (0x0BC)
1482 #define SPR_HFSCR (0x0BE)
1483 #define SPR_VRSAVE (0x100)
1484 #define SPR_USPRG0 (0x100)
1485 #define SPR_USPRG1 (0x101)
1486 #define SPR_USPRG2 (0x102)
1487 #define SPR_USPRG3 (0x103)
1488 #define SPR_USPRG4 (0x104)
1489 #define SPR_USPRG5 (0x105)
1490 #define SPR_USPRG6 (0x106)
1491 #define SPR_USPRG7 (0x107)
1492 #define SPR_VTBL (0x10C)
1493 #define SPR_VTBU (0x10D)
1494 #define SPR_SPRG0 (0x110)
1495 #define SPR_SPRG1 (0x111)
1496 #define SPR_SPRG2 (0x112)
1497 #define SPR_SPRG3 (0x113)
1498 #define SPR_SPRG4 (0x114)
1499 #define SPR_SCOMC (0x114)
1500 #define SPR_SPRG5 (0x115)
1501 #define SPR_SCOMD (0x115)
1502 #define SPR_SPRG6 (0x116)
1503 #define SPR_SPRG7 (0x117)
1504 #define SPR_ASR (0x118)
1505 #define SPR_EAR (0x11A)
1506 #define SPR_TBL (0x11C)
1507 #define SPR_TBU (0x11D)
1508 #define SPR_TBU40 (0x11E)
1509 #define SPR_SVR (0x11E)
1510 #define SPR_BOOKE_PIR (0x11E)
1511 #define SPR_PVR (0x11F)
1512 #define SPR_HSPRG0 (0x130)
1513 #define SPR_BOOKE_DBSR (0x130)
1514 #define SPR_HSPRG1 (0x131)
1515 #define SPR_HDSISR (0x132)
1516 #define SPR_HDAR (0x133)
1517 #define SPR_BOOKE_EPCR (0x133)
1518 #define SPR_SPURR (0x134)
1519 #define SPR_BOOKE_DBCR0 (0x134)
1520 #define SPR_IBCR (0x135)
1521 #define SPR_PURR (0x135)
1522 #define SPR_BOOKE_DBCR1 (0x135)
1523 #define SPR_DBCR (0x136)
1524 #define SPR_HDEC (0x136)
1525 #define SPR_BOOKE_DBCR2 (0x136)
1526 #define SPR_HIOR (0x137)
1527 #define SPR_MBAR (0x137)
1528 #define SPR_RMOR (0x138)
1529 #define SPR_BOOKE_IAC1 (0x138)
1530 #define SPR_HRMOR (0x139)
1531 #define SPR_BOOKE_IAC2 (0x139)
1532 #define SPR_HSRR0 (0x13A)
1533 #define SPR_BOOKE_IAC3 (0x13A)
1534 #define SPR_HSRR1 (0x13B)
1535 #define SPR_BOOKE_IAC4 (0x13B)
1536 #define SPR_BOOKE_DAC1 (0x13C)
1537 #define SPR_MMCRH (0x13C)
1538 #define SPR_DABR2 (0x13D)
1539 #define SPR_BOOKE_DAC2 (0x13D)
1540 #define SPR_TFMR (0x13D)
1541 #define SPR_BOOKE_DVC1 (0x13E)
1542 #define SPR_LPCR (0x13E)
1543 #define SPR_BOOKE_DVC2 (0x13F)
1544 #define SPR_LPIDR (0x13F)
1545 #define SPR_BOOKE_TSR (0x150)
1546 #define SPR_HMER (0x150)
1547 #define SPR_HMEER (0x151)
1548 #define SPR_PCR (0x152)
1549 #define SPR_BOOKE_LPIDR (0x152)
1550 #define SPR_BOOKE_TCR (0x154)
1551 #define SPR_BOOKE_TLB0PS (0x158)
1552 #define SPR_BOOKE_TLB1PS (0x159)
1553 #define SPR_BOOKE_TLB2PS (0x15A)
1554 #define SPR_BOOKE_TLB3PS (0x15B)
1555 #define SPR_AMOR (0x15D)
1556 #define SPR_BOOKE_MAS7_MAS3 (0x174)
1557 #define SPR_BOOKE_IVOR0 (0x190)
1558 #define SPR_BOOKE_IVOR1 (0x191)
1559 #define SPR_BOOKE_IVOR2 (0x192)
1560 #define SPR_BOOKE_IVOR3 (0x193)
1561 #define SPR_BOOKE_IVOR4 (0x194)
1562 #define SPR_BOOKE_IVOR5 (0x195)
1563 #define SPR_BOOKE_IVOR6 (0x196)
1564 #define SPR_BOOKE_IVOR7 (0x197)
1565 #define SPR_BOOKE_IVOR8 (0x198)
1566 #define SPR_BOOKE_IVOR9 (0x199)
1567 #define SPR_BOOKE_IVOR10 (0x19A)
1568 #define SPR_BOOKE_IVOR11 (0x19B)
1569 #define SPR_BOOKE_IVOR12 (0x19C)
1570 #define SPR_BOOKE_IVOR13 (0x19D)
1571 #define SPR_BOOKE_IVOR14 (0x19E)
1572 #define SPR_BOOKE_IVOR15 (0x19F)
1573 #define SPR_BOOKE_IVOR38 (0x1B0)
1574 #define SPR_BOOKE_IVOR39 (0x1B1)
1575 #define SPR_BOOKE_IVOR40 (0x1B2)
1576 #define SPR_BOOKE_IVOR41 (0x1B3)
1577 #define SPR_BOOKE_IVOR42 (0x1B4)
1578 #define SPR_BOOKE_GIVOR2 (0x1B8)
1579 #define SPR_BOOKE_GIVOR3 (0x1B9)
1580 #define SPR_BOOKE_GIVOR4 (0x1BA)
1581 #define SPR_BOOKE_GIVOR8 (0x1BB)
1582 #define SPR_BOOKE_GIVOR13 (0x1BC)
1583 #define SPR_BOOKE_GIVOR14 (0x1BD)
1584 #define SPR_TIR (0x1BE)
1585 #define SPR_BOOKE_SPEFSCR (0x200)
1586 #define SPR_Exxx_BBEAR (0x201)
1587 #define SPR_Exxx_BBTAR (0x202)
1588 #define SPR_Exxx_L1CFG0 (0x203)
1589 #define SPR_Exxx_L1CFG1 (0x204)
1590 #define SPR_Exxx_NPIDR (0x205)
1591 #define SPR_ATBL (0x20E)
1592 #define SPR_ATBU (0x20F)
1593 #define SPR_IBAT0U (0x210)
1594 #define SPR_BOOKE_IVOR32 (0x210)
1595 #define SPR_RCPU_MI_GRA (0x210)
1596 #define SPR_IBAT0L (0x211)
1597 #define SPR_BOOKE_IVOR33 (0x211)
1598 #define SPR_IBAT1U (0x212)
1599 #define SPR_BOOKE_IVOR34 (0x212)
1600 #define SPR_IBAT1L (0x213)
1601 #define SPR_BOOKE_IVOR35 (0x213)
1602 #define SPR_IBAT2U (0x214)
1603 #define SPR_BOOKE_IVOR36 (0x214)
1604 #define SPR_IBAT2L (0x215)
1605 #define SPR_BOOKE_IVOR37 (0x215)
1606 #define SPR_IBAT3U (0x216)
1607 #define SPR_IBAT3L (0x217)
1608 #define SPR_DBAT0U (0x218)
1609 #define SPR_RCPU_L2U_GRA (0x218)
1610 #define SPR_DBAT0L (0x219)
1611 #define SPR_DBAT1U (0x21A)
1612 #define SPR_DBAT1L (0x21B)
1613 #define SPR_DBAT2U (0x21C)
1614 #define SPR_DBAT2L (0x21D)
1615 #define SPR_DBAT3U (0x21E)
1616 #define SPR_DBAT3L (0x21F)
1617 #define SPR_IBAT4U (0x230)
1618 #define SPR_RPCU_BBCMCR (0x230)
1619 #define SPR_MPC_IC_CST (0x230)
1620 #define SPR_Exxx_CTXCR (0x230)
1621 #define SPR_IBAT4L (0x231)
1622 #define SPR_MPC_IC_ADR (0x231)
1623 #define SPR_Exxx_DBCR3 (0x231)
1624 #define SPR_IBAT5U (0x232)
1625 #define SPR_MPC_IC_DAT (0x232)
1626 #define SPR_Exxx_DBCNT (0x232)
1627 #define SPR_IBAT5L (0x233)
1628 #define SPR_IBAT6U (0x234)
1629 #define SPR_IBAT6L (0x235)
1630 #define SPR_IBAT7U (0x236)
1631 #define SPR_IBAT7L (0x237)
1632 #define SPR_DBAT4U (0x238)
1633 #define SPR_RCPU_L2U_MCR (0x238)
1634 #define SPR_MPC_DC_CST (0x238)
1635 #define SPR_Exxx_ALTCTXCR (0x238)
1636 #define SPR_DBAT4L (0x239)
1637 #define SPR_MPC_DC_ADR (0x239)
1638 #define SPR_DBAT5U (0x23A)
1639 #define SPR_BOOKE_MCSRR0 (0x23A)
1640 #define SPR_MPC_DC_DAT (0x23A)
1641 #define SPR_DBAT5L (0x23B)
1642 #define SPR_BOOKE_MCSRR1 (0x23B)
1643 #define SPR_DBAT6U (0x23C)
1644 #define SPR_BOOKE_MCSR (0x23C)
1645 #define SPR_DBAT6L (0x23D)
1646 #define SPR_Exxx_MCAR (0x23D)
1647 #define SPR_DBAT7U (0x23E)
1648 #define SPR_BOOKE_DSRR0 (0x23E)
1649 #define SPR_DBAT7L (0x23F)
1650 #define SPR_BOOKE_DSRR1 (0x23F)
1651 #define SPR_BOOKE_SPRG8 (0x25C)
1652 #define SPR_BOOKE_SPRG9 (0x25D)
1653 #define SPR_BOOKE_MAS0 (0x270)
1654 #define SPR_BOOKE_MAS1 (0x271)
1655 #define SPR_BOOKE_MAS2 (0x272)
1656 #define SPR_BOOKE_MAS3 (0x273)
1657 #define SPR_BOOKE_MAS4 (0x274)
1658 #define SPR_BOOKE_MAS5 (0x275)
1659 #define SPR_BOOKE_MAS6 (0x276)
1660 #define SPR_BOOKE_PID1 (0x279)
1661 #define SPR_BOOKE_PID2 (0x27A)
1662 #define SPR_MPC_DPDR (0x280)
1663 #define SPR_MPC_IMMR (0x288)
1664 #define SPR_BOOKE_TLB0CFG (0x2B0)
1665 #define SPR_BOOKE_TLB1CFG (0x2B1)
1666 #define SPR_BOOKE_TLB2CFG (0x2B2)
1667 #define SPR_BOOKE_TLB3CFG (0x2B3)
1668 #define SPR_BOOKE_EPR (0x2BE)
1669 #define SPR_PERF0 (0x300)
1670 #define SPR_RCPU_MI_RBA0 (0x300)
1671 #define SPR_MPC_MI_CTR (0x300)
1672 #define SPR_POWER_USIER (0x300)
1673 #define SPR_PERF1 (0x301)
1674 #define SPR_RCPU_MI_RBA1 (0x301)
1675 #define SPR_POWER_UMMCR2 (0x301)
1676 #define SPR_PERF2 (0x302)
1677 #define SPR_RCPU_MI_RBA2 (0x302)
1678 #define SPR_MPC_MI_AP (0x302)
1679 #define SPR_POWER_UMMCRA (0x302)
1680 #define SPR_PERF3 (0x303)
1681 #define SPR_RCPU_MI_RBA3 (0x303)
1682 #define SPR_MPC_MI_EPN (0x303)
1683 #define SPR_POWER_UPMC1 (0x303)
1684 #define SPR_PERF4 (0x304)
1685 #define SPR_POWER_UPMC2 (0x304)
1686 #define SPR_PERF5 (0x305)
1687 #define SPR_MPC_MI_TWC (0x305)
1688 #define SPR_POWER_UPMC3 (0x305)
1689 #define SPR_PERF6 (0x306)
1690 #define SPR_MPC_MI_RPN (0x306)
1691 #define SPR_POWER_UPMC4 (0x306)
1692 #define SPR_PERF7 (0x307)
1693 #define SPR_POWER_UPMC5 (0x307)
1694 #define SPR_PERF8 (0x308)
1695 #define SPR_RCPU_L2U_RBA0 (0x308)
1696 #define SPR_MPC_MD_CTR (0x308)
1697 #define SPR_POWER_UPMC6 (0x308)
1698 #define SPR_PERF9 (0x309)
1699 #define SPR_RCPU_L2U_RBA1 (0x309)
1700 #define SPR_MPC_MD_CASID (0x309)
1701 #define SPR_970_UPMC7 (0X309)
1702 #define SPR_PERFA (0x30A)
1703 #define SPR_RCPU_L2U_RBA2 (0x30A)
1704 #define SPR_MPC_MD_AP (0x30A)
1705 #define SPR_970_UPMC8 (0X30A)
1706 #define SPR_PERFB (0x30B)
1707 #define SPR_RCPU_L2U_RBA3 (0x30B)
1708 #define SPR_MPC_MD_EPN (0x30B)
1709 #define SPR_POWER_UMMCR0 (0X30B)
1710 #define SPR_PERFC (0x30C)
1711 #define SPR_MPC_MD_TWB (0x30C)
1712 #define SPR_POWER_USIAR (0X30C)
1713 #define SPR_PERFD (0x30D)
1714 #define SPR_MPC_MD_TWC (0x30D)
1715 #define SPR_POWER_USDAR (0X30D)
1716 #define SPR_PERFE (0x30E)
1717 #define SPR_MPC_MD_RPN (0x30E)
1718 #define SPR_POWER_UMMCR1 (0X30E)
1719 #define SPR_PERFF (0x30F)
1720 #define SPR_MPC_MD_TW (0x30F)
1721 #define SPR_UPERF0 (0x310)
1722 #define SPR_POWER_SIER (0x310)
1723 #define SPR_UPERF1 (0x311)
1724 #define SPR_POWER_MMCR2 (0x311)
1725 #define SPR_UPERF2 (0x312)
1726 #define SPR_POWER_MMCRA (0X312)
1727 #define SPR_UPERF3 (0x313)
1728 #define SPR_POWER_PMC1 (0X313)
1729 #define SPR_UPERF4 (0x314)
1730 #define SPR_POWER_PMC2 (0X314)
1731 #define SPR_UPERF5 (0x315)
1732 #define SPR_POWER_PMC3 (0X315)
1733 #define SPR_UPERF6 (0x316)
1734 #define SPR_POWER_PMC4 (0X316)
1735 #define SPR_UPERF7 (0x317)
1736 #define SPR_POWER_PMC5 (0X317)
1737 #define SPR_UPERF8 (0x318)
1738 #define SPR_POWER_PMC6 (0X318)
1739 #define SPR_UPERF9 (0x319)
1740 #define SPR_970_PMC7 (0X319)
1741 #define SPR_UPERFA (0x31A)
1742 #define SPR_970_PMC8 (0X31A)
1743 #define SPR_UPERFB (0x31B)
1744 #define SPR_POWER_MMCR0 (0X31B)
1745 #define SPR_UPERFC (0x31C)
1746 #define SPR_POWER_SIAR (0X31C)
1747 #define SPR_UPERFD (0x31D)
1748 #define SPR_POWER_SDAR (0X31D)
1749 #define SPR_UPERFE (0x31E)
1750 #define SPR_POWER_MMCR1 (0X31E)
1751 #define SPR_UPERFF (0x31F)
1752 #define SPR_RCPU_MI_RA0 (0x320)
1753 #define SPR_MPC_MI_DBCAM (0x320)
1754 #define SPR_BESCRS (0x320)
1755 #define SPR_RCPU_MI_RA1 (0x321)
1756 #define SPR_MPC_MI_DBRAM0 (0x321)
1757 #define SPR_BESCRSU (0x321)
1758 #define SPR_RCPU_MI_RA2 (0x322)
1759 #define SPR_MPC_MI_DBRAM1 (0x322)
1760 #define SPR_BESCRR (0x322)
1761 #define SPR_RCPU_MI_RA3 (0x323)
1762 #define SPR_BESCRRU (0x323)
1763 #define SPR_EBBHR (0x324)
1764 #define SPR_EBBRR (0x325)
1765 #define SPR_BESCR (0x326)
1766 #define SPR_RCPU_L2U_RA0 (0x328)
1767 #define SPR_MPC_MD_DBCAM (0x328)
1768 #define SPR_RCPU_L2U_RA1 (0x329)
1769 #define SPR_MPC_MD_DBRAM0 (0x329)
1770 #define SPR_RCPU_L2U_RA2 (0x32A)
1771 #define SPR_MPC_MD_DBRAM1 (0x32A)
1772 #define SPR_RCPU_L2U_RA3 (0x32B)
1773 #define SPR_TAR (0x32F)
1774 #define SPR_IC (0x350)
1775 #define SPR_VTB (0x351)
1776 #define SPR_MMCRC (0x353)
1777 #define SPR_PSSCR (0x357)
1778 #define SPR_440_INV0 (0x370)
1779 #define SPR_440_INV1 (0x371)
1780 #define SPR_440_INV2 (0x372)
1781 #define SPR_440_INV3 (0x373)
1782 #define SPR_440_ITV0 (0x374)
1783 #define SPR_440_ITV1 (0x375)
1784 #define SPR_440_ITV2 (0x376)
1785 #define SPR_440_ITV3 (0x377)
1786 #define SPR_440_CCR1 (0x378)
1787 #define SPR_TACR (0x378)
1788 #define SPR_TCSCR (0x379)
1789 #define SPR_CSIGR (0x37a)
1790 #define SPR_DCRIPR (0x37B)
1791 #define SPR_POWER_SPMC1 (0x37C)
1792 #define SPR_POWER_SPMC2 (0x37D)
1793 #define SPR_POWER_MMCRS (0x37E)
1794 #define SPR_WORT (0x37F)
1795 #define SPR_PPR (0x380)
1796 #define SPR_750_GQR0 (0x390)
1797 #define SPR_440_DNV0 (0x390)
1798 #define SPR_750_GQR1 (0x391)
1799 #define SPR_440_DNV1 (0x391)
1800 #define SPR_750_GQR2 (0x392)
1801 #define SPR_440_DNV2 (0x392)
1802 #define SPR_750_GQR3 (0x393)
1803 #define SPR_440_DNV3 (0x393)
1804 #define SPR_750_GQR4 (0x394)
1805 #define SPR_440_DTV0 (0x394)
1806 #define SPR_750_GQR5 (0x395)
1807 #define SPR_440_DTV1 (0x395)
1808 #define SPR_750_GQR6 (0x396)
1809 #define SPR_440_DTV2 (0x396)
1810 #define SPR_750_GQR7 (0x397)
1811 #define SPR_440_DTV3 (0x397)
1812 #define SPR_750_THRM4 (0x398)
1813 #define SPR_750CL_HID2 (0x398)
1814 #define SPR_440_DVLIM (0x398)
1815 #define SPR_750_WPAR (0x399)
1816 #define SPR_440_IVLIM (0x399)
1817 #define SPR_TSCR (0x399)
1818 #define SPR_750_DMAU (0x39A)
1819 #define SPR_750_DMAL (0x39B)
1820 #define SPR_440_RSTCFG (0x39B)
1821 #define SPR_BOOKE_DCDBTRL (0x39C)
1822 #define SPR_BOOKE_DCDBTRH (0x39D)
1823 #define SPR_BOOKE_ICDBTRL (0x39E)
1824 #define SPR_BOOKE_ICDBTRH (0x39F)
1825 #define SPR_74XX_UMMCR2 (0x3A0)
1826 #define SPR_7XX_UPMC5 (0x3A1)
1827 #define SPR_7XX_UPMC6 (0x3A2)
1828 #define SPR_UBAMR (0x3A7)
1829 #define SPR_7XX_UMMCR0 (0x3A8)
1830 #define SPR_7XX_UPMC1 (0x3A9)
1831 #define SPR_7XX_UPMC2 (0x3AA)
1832 #define SPR_7XX_USIAR (0x3AB)
1833 #define SPR_7XX_UMMCR1 (0x3AC)
1834 #define SPR_7XX_UPMC3 (0x3AD)
1835 #define SPR_7XX_UPMC4 (0x3AE)
1836 #define SPR_USDA (0x3AF)
1837 #define SPR_40x_ZPR (0x3B0)
1838 #define SPR_BOOKE_MAS7 (0x3B0)
1839 #define SPR_74XX_MMCR2 (0x3B0)
1840 #define SPR_7XX_PMC5 (0x3B1)
1841 #define SPR_40x_PID (0x3B1)
1842 #define SPR_7XX_PMC6 (0x3B2)
1843 #define SPR_440_MMUCR (0x3B2)
1844 #define SPR_4xx_CCR0 (0x3B3)
1845 #define SPR_BOOKE_EPLC (0x3B3)
1846 #define SPR_405_IAC3 (0x3B4)
1847 #define SPR_BOOKE_EPSC (0x3B4)
1848 #define SPR_405_IAC4 (0x3B5)
1849 #define SPR_405_DVC1 (0x3B6)
1850 #define SPR_405_DVC2 (0x3B7)
1851 #define SPR_BAMR (0x3B7)
1852 #define SPR_7XX_MMCR0 (0x3B8)
1853 #define SPR_7XX_PMC1 (0x3B9)
1854 #define SPR_40x_SGR (0x3B9)
1855 #define SPR_7XX_PMC2 (0x3BA)
1856 #define SPR_40x_DCWR (0x3BA)
1857 #define SPR_7XX_SIAR (0x3BB)
1858 #define SPR_405_SLER (0x3BB)
1859 #define SPR_7XX_MMCR1 (0x3BC)
1860 #define SPR_405_SU0R (0x3BC)
1861 #define SPR_401_SKR (0x3BC)
1862 #define SPR_7XX_PMC3 (0x3BD)
1863 #define SPR_405_DBCR1 (0x3BD)
1864 #define SPR_7XX_PMC4 (0x3BE)
1865 #define SPR_SDA (0x3BF)
1866 #define SPR_403_VTBL (0x3CC)
1867 #define SPR_403_VTBU (0x3CD)
1868 #define SPR_DMISS (0x3D0)
1869 #define SPR_DCMP (0x3D1)
1870 #define SPR_HASH1 (0x3D2)
1871 #define SPR_HASH2 (0x3D3)
1872 #define SPR_BOOKE_ICDBDR (0x3D3)
1873 #define SPR_TLBMISS (0x3D4)
1874 #define SPR_IMISS (0x3D4)
1875 #define SPR_40x_ESR (0x3D4)
1876 #define SPR_PTEHI (0x3D5)
1877 #define SPR_ICMP (0x3D5)
1878 #define SPR_40x_DEAR (0x3D5)
1879 #define SPR_PTELO (0x3D6)
1880 #define SPR_RPA (0x3D6)
1881 #define SPR_40x_EVPR (0x3D6)
1882 #define SPR_L3PM (0x3D7)
1883 #define SPR_403_CDBCR (0x3D7)
1884 #define SPR_L3ITCR0 (0x3D8)
1885 #define SPR_TCR (0x3D8)
1886 #define SPR_40x_TSR (0x3D8)
1887 #define SPR_IBR (0x3DA)
1888 #define SPR_40x_TCR (0x3DA)
1889 #define SPR_ESASRR (0x3DB)
1890 #define SPR_40x_PIT (0x3DB)
1891 #define SPR_403_TBL (0x3DC)
1892 #define SPR_403_TBU (0x3DD)
1893 #define SPR_SEBR (0x3DE)
1894 #define SPR_40x_SRR2 (0x3DE)
1895 #define SPR_SER (0x3DF)
1896 #define SPR_40x_SRR3 (0x3DF)
1897 #define SPR_L3OHCR (0x3E8)
1898 #define SPR_L3ITCR1 (0x3E9)
1899 #define SPR_L3ITCR2 (0x3EA)
1900 #define SPR_L3ITCR3 (0x3EB)
1901 #define SPR_HID0 (0x3F0)
1902 #define SPR_40x_DBSR (0x3F0)
1903 #define SPR_HID1 (0x3F1)
1904 #define SPR_IABR (0x3F2)
1905 #define SPR_40x_DBCR0 (0x3F2)
1906 #define SPR_601_HID2 (0x3F2)
1907 #define SPR_Exxx_L1CSR0 (0x3F2)
1908 #define SPR_ICTRL (0x3F3)
1909 #define SPR_HID2 (0x3F3)
1910 #define SPR_750CL_HID4 (0x3F3)
1911 #define SPR_Exxx_L1CSR1 (0x3F3)
1912 #define SPR_440_DBDR (0x3F3)
1913 #define SPR_LDSTDB (0x3F4)
1914 #define SPR_750_TDCL (0x3F4)
1915 #define SPR_40x_IAC1 (0x3F4)
1916 #define SPR_MMUCSR0 (0x3F4)
1917 #define SPR_970_HID4 (0x3F4)
1918 #define SPR_DABR (0x3F5)
1919 #define DABR_MASK (~(target_ulong)0x7)
1920 #define SPR_Exxx_BUCSR (0x3F5)
1921 #define SPR_40x_IAC2 (0x3F5)
1922 #define SPR_601_HID5 (0x3F5)
1923 #define SPR_40x_DAC1 (0x3F6)
1924 #define SPR_MSSCR0 (0x3F6)
1925 #define SPR_970_HID5 (0x3F6)
1926 #define SPR_MSSSR0 (0x3F7)
1927 #define SPR_MSSCR1 (0x3F7)
1928 #define SPR_DABRX (0x3F7)
1929 #define SPR_40x_DAC2 (0x3F7)
1930 #define SPR_MMUCFG (0x3F7)
1931 #define SPR_LDSTCR (0x3F8)
1932 #define SPR_L2PMCR (0x3F8)
1933 #define SPR_750FX_HID2 (0x3F8)
1934 #define SPR_Exxx_L1FINV0 (0x3F8)
1935 #define SPR_L2CR (0x3F9)
1936 #define SPR_L3CR (0x3FA)
1937 #define SPR_750_TDCH (0x3FA)
1938 #define SPR_IABR2 (0x3FA)
1939 #define SPR_40x_DCCR (0x3FA)
1940 #define SPR_ICTC (0x3FB)
1941 #define SPR_40x_ICCR (0x3FB)
1942 #define SPR_THRM1 (0x3FC)
1943 #define SPR_403_PBL1 (0x3FC)
1944 #define SPR_SP (0x3FD)
1945 #define SPR_THRM2 (0x3FD)
1946 #define SPR_403_PBU1 (0x3FD)
1947 #define SPR_604_HID13 (0x3FD)
1948 #define SPR_LT (0x3FE)
1949 #define SPR_THRM3 (0x3FE)
1950 #define SPR_RCPU_FPECR (0x3FE)
1951 #define SPR_403_PBL2 (0x3FE)
1952 #define SPR_PIR (0x3FF)
1953 #define SPR_403_PBU2 (0x3FF)
1954 #define SPR_601_HID15 (0x3FF)
1955 #define SPR_604_HID15 (0x3FF)
1956 #define SPR_E500_SVR (0x3FF)
1957
1958 /* Disable MAS Interrupt Updates for Hypervisor */
1959 #define EPCR_DMIUH (1 << 22)
1960 /* Disable Guest TLB Management Instructions */
1961 #define EPCR_DGTMI (1 << 23)
1962 /* Guest Interrupt Computation Mode */
1963 #define EPCR_GICM (1 << 24)
1964 /* Interrupt Computation Mode */
1965 #define EPCR_ICM (1 << 25)
1966 /* Disable Embedded Hypervisor Debug */
1967 #define EPCR_DUVD (1 << 26)
1968 /* Instruction Storage Interrupt Directed to Guest State */
1969 #define EPCR_ISIGS (1 << 27)
1970 /* Data Storage Interrupt Directed to Guest State */
1971 #define EPCR_DSIGS (1 << 28)
1972 /* Instruction TLB Error Interrupt Directed to Guest State */
1973 #define EPCR_ITLBGS (1 << 29)
1974 /* Data TLB Error Interrupt Directed to Guest State */
1975 #define EPCR_DTLBGS (1 << 30)
1976 /* External Input Interrupt Directed to Guest State */
1977 #define EPCR_EXTGS (1 << 31)
1978
1979 #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
1980 #define L1CSR0_CUL 0x00000400 /* (D-)Cache Unable to Lock */
1981 #define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */
1982 #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
1983 #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
1984
1985 #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
1986 #define L1CSR1_ICUL 0x00000400 /* I-Cache Unable to Lock */
1987 #define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */
1988 #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
1989 #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
1990
1991 /* HID0 bits */
1992 #define HID0_DEEPNAP (1 << 24) /* pre-2.06 */
1993 #define HID0_DOZE (1 << 23) /* pre-2.06 */
1994 #define HID0_NAP (1 << 22) /* pre-2.06 */
1995 #define HID0_HILE (1ull << (63 - 19)) /* POWER8 */
1996
1997 /*****************************************************************************/
1998 /* PowerPC Instructions types definitions */
1999 enum {
2000 PPC_NONE = 0x0000000000000000ULL,
2001 /* PowerPC base instructions set */
2002 PPC_INSNS_BASE = 0x0000000000000001ULL,
2003 /* integer operations instructions */
2004 #define PPC_INTEGER PPC_INSNS_BASE
2005 /* flow control instructions */
2006 #define PPC_FLOW PPC_INSNS_BASE
2007 /* virtual memory instructions */
2008 #define PPC_MEM PPC_INSNS_BASE
2009 /* ld/st with reservation instructions */
2010 #define PPC_RES PPC_INSNS_BASE
2011 /* spr/msr access instructions */
2012 #define PPC_MISC PPC_INSNS_BASE
2013 /* Deprecated instruction sets */
2014 /* Original POWER instruction set */
2015 PPC_POWER = 0x0000000000000002ULL,
2016 /* POWER2 instruction set extension */
2017 PPC_POWER2 = 0x0000000000000004ULL,
2018 /* Power RTC support */
2019 PPC_POWER_RTC = 0x0000000000000008ULL,
2020 /* Power-to-PowerPC bridge (601) */
2021 PPC_POWER_BR = 0x0000000000000010ULL,
2022 /* 64 bits PowerPC instruction set */
2023 PPC_64B = 0x0000000000000020ULL,
2024 /* New 64 bits extensions (PowerPC 2.0x) */
2025 PPC_64BX = 0x0000000000000040ULL,
2026 /* 64 bits hypervisor extensions */
2027 PPC_64H = 0x0000000000000080ULL,
2028 /* New wait instruction (PowerPC 2.0x) */
2029 PPC_WAIT = 0x0000000000000100ULL,
2030 /* Time base mftb instruction */
2031 PPC_MFTB = 0x0000000000000200ULL,
2032
2033 /* Fixed-point unit extensions */
2034 /* PowerPC 602 specific */
2035 PPC_602_SPEC = 0x0000000000000400ULL,
2036 /* isel instruction */
2037 PPC_ISEL = 0x0000000000000800ULL,
2038 /* popcntb instruction */
2039 PPC_POPCNTB = 0x0000000000001000ULL,
2040 /* string load / store */
2041 PPC_STRING = 0x0000000000002000ULL,
2042 /* real mode cache inhibited load / store */
2043 PPC_CILDST = 0x0000000000004000ULL,
2044
2045 /* Floating-point unit extensions */
2046 /* Optional floating point instructions */
2047 PPC_FLOAT = 0x0000000000010000ULL,
2048 /* New floating-point extensions (PowerPC 2.0x) */
2049 PPC_FLOAT_EXT = 0x0000000000020000ULL,
2050 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
2051 PPC_FLOAT_FRES = 0x0000000000080000ULL,
2052 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
2053 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
2054 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
2055 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
2056
2057 /* Vector/SIMD extensions */
2058 /* Altivec support */
2059 PPC_ALTIVEC = 0x0000000001000000ULL,
2060 /* PowerPC 2.03 SPE extension */
2061 PPC_SPE = 0x0000000002000000ULL,
2062 /* PowerPC 2.03 SPE single-precision floating-point extension */
2063 PPC_SPE_SINGLE = 0x0000000004000000ULL,
2064 /* PowerPC 2.03 SPE double-precision floating-point extension */
2065 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
2066
2067 /* Optional memory control instructions */
2068 PPC_MEM_TLBIA = 0x0000000010000000ULL,
2069 PPC_MEM_TLBIE = 0x0000000020000000ULL,
2070 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
2071 /* sync instruction */
2072 PPC_MEM_SYNC = 0x0000000080000000ULL,
2073 /* eieio instruction */
2074 PPC_MEM_EIEIO = 0x0000000100000000ULL,
2075
2076 /* Cache control instructions */
2077 PPC_CACHE = 0x0000000200000000ULL,
2078 /* icbi instruction */
2079 PPC_CACHE_ICBI = 0x0000000400000000ULL,
2080 /* dcbz instruction */
2081 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
2082 /* dcba instruction */
2083 PPC_CACHE_DCBA = 0x0000002000000000ULL,
2084 /* Freescale cache locking instructions */
2085 PPC_CACHE_LOCK = 0x0000004000000000ULL,
2086
2087 /* MMU related extensions */
2088 /* external control instructions */
2089 PPC_EXTERN = 0x0000010000000000ULL,
2090 /* segment register access instructions */
2091 PPC_SEGMENT = 0x0000020000000000ULL,
2092 /* PowerPC 6xx TLB management instructions */
2093 PPC_6xx_TLB = 0x0000040000000000ULL,
2094 /* PowerPC 74xx TLB management instructions */
2095 PPC_74xx_TLB = 0x0000080000000000ULL,
2096 /* PowerPC 40x TLB management instructions */
2097 PPC_40x_TLB = 0x0000100000000000ULL,
2098 /* segment register access instructions for PowerPC 64 "bridge" */
2099 PPC_SEGMENT_64B = 0x0000200000000000ULL,
2100 /* SLB management */
2101 PPC_SLBI = 0x0000400000000000ULL,
2102
2103 /* Embedded PowerPC dedicated instructions */
2104 PPC_WRTEE = 0x0001000000000000ULL,
2105 /* PowerPC 40x exception model */
2106 PPC_40x_EXCP = 0x0002000000000000ULL,
2107 /* PowerPC 405 Mac instructions */
2108 PPC_405_MAC = 0x0004000000000000ULL,
2109 /* PowerPC 440 specific instructions */
2110 PPC_440_SPEC = 0x0008000000000000ULL,
2111 /* BookE (embedded) PowerPC specification */
2112 PPC_BOOKE = 0x0010000000000000ULL,
2113 /* mfapidi instruction */
2114 PPC_MFAPIDI = 0x0020000000000000ULL,
2115 /* tlbiva instruction */
2116 PPC_TLBIVA = 0x0040000000000000ULL,
2117 /* tlbivax instruction */
2118 PPC_TLBIVAX = 0x0080000000000000ULL,
2119 /* PowerPC 4xx dedicated instructions */
2120 PPC_4xx_COMMON = 0x0100000000000000ULL,
2121 /* PowerPC 40x ibct instructions */
2122 PPC_40x_ICBT = 0x0200000000000000ULL,
2123 /* rfmci is not implemented in all BookE PowerPC */
2124 PPC_RFMCI = 0x0400000000000000ULL,
2125 /* rfdi instruction */
2126 PPC_RFDI = 0x0800000000000000ULL,
2127 /* DCR accesses */
2128 PPC_DCR = 0x1000000000000000ULL,
2129 /* DCR extended accesse */
2130 PPC_DCRX = 0x2000000000000000ULL,
2131 /* user-mode DCR access, implemented in PowerPC 460 */
2132 PPC_DCRUX = 0x4000000000000000ULL,
2133 /* popcntw and popcntd instructions */
2134 PPC_POPCNTWD = 0x8000000000000000ULL,
2135
2136 #define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
2137 | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
2138 | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
2139 | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
2140 | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
2141 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
2142 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
2143 | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
2144 | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
2145 | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
2146 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
2147 | PPC_MEM_SYNC | PPC_MEM_EIEIO \
2148 | PPC_CACHE | PPC_CACHE_ICBI \
2149 | PPC_CACHE_DCBZ \
2150 | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
2151 | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
2152 | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
2153 | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
2154 | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
2155 | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
2156 | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
2157 | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
2158 | PPC_POPCNTWD | PPC_CILDST)
2159
2160 /* extended type values */
2161
2162 /* BookE 2.06 PowerPC specification */
2163 PPC2_BOOKE206 = 0x0000000000000001ULL,
2164 /* VSX (extensions to Altivec / VMX) */
2165 PPC2_VSX = 0x0000000000000002ULL,
2166 /* Decimal Floating Point (DFP) */
2167 PPC2_DFP = 0x0000000000000004ULL,
2168 /* Embedded.Processor Control */
2169 PPC2_PRCNTL = 0x0000000000000008ULL,
2170 /* Byte-reversed, indexed, double-word load and store */
2171 PPC2_DBRX = 0x0000000000000010ULL,
2172 /* Book I 2.05 PowerPC specification */
2173 PPC2_ISA205 = 0x0000000000000020ULL,
2174 /* VSX additions in ISA 2.07 */
2175 PPC2_VSX207 = 0x0000000000000040ULL,
2176 /* ISA 2.06B bpermd */
2177 PPC2_PERM_ISA206 = 0x0000000000000080ULL,
2178 /* ISA 2.06B divide extended variants */
2179 PPC2_DIVE_ISA206 = 0x0000000000000100ULL,
2180 /* ISA 2.06B larx/stcx. instructions */
2181 PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
2182 /* ISA 2.06B floating point integer conversion */
2183 PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
2184 /* ISA 2.06B floating point test instructions */
2185 PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
2186 /* ISA 2.07 bctar instruction */
2187 PPC2_BCTAR_ISA207 = 0x0000000000001000ULL,
2188 /* ISA 2.07 load/store quadword */
2189 PPC2_LSQ_ISA207 = 0x0000000000002000ULL,
2190 /* ISA 2.07 Altivec */
2191 PPC2_ALTIVEC_207 = 0x0000000000004000ULL,
2192 /* PowerISA 2.07 Book3s specification */
2193 PPC2_ISA207S = 0x0000000000008000ULL,
2194 /* Double precision floating point conversion for signed integer 64 */
2195 PPC2_FP_CVT_S64 = 0x0000000000010000ULL,
2196 /* Transactional Memory (ISA 2.07, Book II) */
2197 PPC2_TM = 0x0000000000020000ULL,
2198 /* Server PM instructgions (ISA 2.06, Book III) */
2199 PPC2_PM_ISA206 = 0x0000000000040000ULL,
2200 /* POWER ISA 3.0 */
2201 PPC2_ISA300 = 0x0000000000080000ULL,
2202
2203 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
2204 PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
2205 PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
2206 PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
2207 PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
2208 PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
2209 PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
2210 PPC2_ISA300)
2211 };
2212
2213 /*****************************************************************************/
2214 /* Memory access type :
2215 * may be needed for precise access rights control and precise exceptions.
2216 */
2217 enum {
2218 /* 1 bit to define user level / supervisor access */
2219 ACCESS_USER = 0x00,
2220 ACCESS_SUPER = 0x01,
2221 /* Type of instruction that generated the access */
2222 ACCESS_CODE = 0x10, /* Code fetch access */
2223 ACCESS_INT = 0x20, /* Integer load/store access */
2224 ACCESS_FLOAT = 0x30, /* floating point load/store access */
2225 ACCESS_RES = 0x40, /* load/store with reservation */
2226 ACCESS_EXT = 0x50, /* external access */
2227 ACCESS_CACHE = 0x60, /* Cache manipulation */
2228 };
2229
2230 /* Hardware interruption sources:
2231 * all those exception can be raised simulteaneously
2232 */
2233 /* Input pins definitions */
2234 enum {
2235 /* 6xx bus input pins */
2236 PPC6xx_INPUT_HRESET = 0,
2237 PPC6xx_INPUT_SRESET = 1,
2238 PPC6xx_INPUT_CKSTP_IN = 2,
2239 PPC6xx_INPUT_MCP = 3,
2240 PPC6xx_INPUT_SMI = 4,
2241 PPC6xx_INPUT_INT = 5,
2242 PPC6xx_INPUT_TBEN = 6,
2243 PPC6xx_INPUT_WAKEUP = 7,
2244 PPC6xx_INPUT_NB,
2245 };
2246
2247 enum {
2248 /* Embedded PowerPC input pins */
2249 PPCBookE_INPUT_HRESET = 0,
2250 PPCBookE_INPUT_SRESET = 1,
2251 PPCBookE_INPUT_CKSTP_IN = 2,
2252 PPCBookE_INPUT_MCP = 3,
2253 PPCBookE_INPUT_SMI = 4,
2254 PPCBookE_INPUT_INT = 5,
2255 PPCBookE_INPUT_CINT = 6,
2256 PPCBookE_INPUT_NB,
2257 };
2258
2259 enum {
2260 /* PowerPC E500 input pins */
2261 PPCE500_INPUT_RESET_CORE = 0,
2262 PPCE500_INPUT_MCK = 1,
2263 PPCE500_INPUT_CINT = 3,
2264 PPCE500_INPUT_INT = 4,
2265 PPCE500_INPUT_DEBUG = 6,
2266 PPCE500_INPUT_NB,
2267 };
2268
2269 enum {
2270 /* PowerPC 40x input pins */
2271 PPC40x_INPUT_RESET_CORE = 0,
2272 PPC40x_INPUT_RESET_CHIP = 1,
2273 PPC40x_INPUT_RESET_SYS = 2,
2274 PPC40x_INPUT_CINT = 3,
2275 PPC40x_INPUT_INT = 4,
2276 PPC40x_INPUT_HALT = 5,
2277 PPC40x_INPUT_DEBUG = 6,
2278 PPC40x_INPUT_NB,
2279 };
2280
2281 enum {
2282 /* RCPU input pins */
2283 PPCRCPU_INPUT_PORESET = 0,
2284 PPCRCPU_INPUT_HRESET = 1,
2285 PPCRCPU_INPUT_SRESET = 2,
2286 PPCRCPU_INPUT_IRQ0 = 3,
2287 PPCRCPU_INPUT_IRQ1 = 4,
2288 PPCRCPU_INPUT_IRQ2 = 5,
2289 PPCRCPU_INPUT_IRQ3 = 6,
2290 PPCRCPU_INPUT_IRQ4 = 7,
2291 PPCRCPU_INPUT_IRQ5 = 8,
2292 PPCRCPU_INPUT_IRQ6 = 9,
2293 PPCRCPU_INPUT_IRQ7 = 10,
2294 PPCRCPU_INPUT_NB,
2295 };
2296
2297 #if defined(TARGET_PPC64)
2298 enum {
2299 /* PowerPC 970 input pins */
2300 PPC970_INPUT_HRESET = 0,
2301 PPC970_INPUT_SRESET = 1,
2302 PPC970_INPUT_CKSTP = 2,
2303 PPC970_INPUT_TBEN = 3,
2304 PPC970_INPUT_MCP = 4,
2305 PPC970_INPUT_INT = 5,
2306 PPC970_INPUT_THINT = 6,
2307 PPC970_INPUT_NB,
2308 };
2309
2310 enum {
2311 /* POWER7 input pins */
2312 POWER7_INPUT_INT = 0,
2313 /* POWER7 probably has other inputs, but we don't care about them
2314 * for any existing machine. We can wire these up when we need
2315 * them */
2316 POWER7_INPUT_NB,
2317 };
2318 #endif
2319
2320 /* Hardware exceptions definitions */
2321 enum {
2322 /* External hardware exception sources */
2323 PPC_INTERRUPT_RESET = 0, /* Reset exception */
2324 PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
2325 PPC_INTERRUPT_MCK, /* Machine check exception */
2326 PPC_INTERRUPT_EXT, /* External interrupt */
2327 PPC_INTERRUPT_SMI, /* System management interrupt */
2328 PPC_INTERRUPT_CEXT, /* Critical external interrupt */
2329 PPC_INTERRUPT_DEBUG, /* External debug exception */
2330 PPC_INTERRUPT_THERM, /* Thermal exception */
2331 /* Internal hardware exception sources */
2332 PPC_INTERRUPT_DECR, /* Decrementer exception */
2333 PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
2334 PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
2335 PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
2336 PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
2337 PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
2338 PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
2339 PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
2340 PPC_INTERRUPT_HMI, /* Hypervisor Maintainance interrupt */
2341 PPC_INTERRUPT_HDOORBELL, /* Hypervisor Doorbell interrupt */
2342 };
2343
2344 /* Processor Compatibility mask (PCR) */
2345 enum {
2346 PCR_COMPAT_2_05 = 1ull << (63-62),
2347 PCR_COMPAT_2_06 = 1ull << (63-61),
2348 PCR_COMPAT_2_07 = 1ull << (63-60),
2349 PCR_COMPAT_3_00 = 1ull << (63-59),
2350 PCR_VEC_DIS = 1ull << (63-0), /* Vec. disable (bit NA since POWER8) */
2351 PCR_VSX_DIS = 1ull << (63-1), /* VSX disable (bit NA since POWER8) */
2352 PCR_TM_DIS = 1ull << (63-2), /* Trans. memory disable (POWER8) */
2353 };
2354
2355 /* HMER/HMEER */
2356 enum {
2357 HMER_MALFUNCTION_ALERT = 1ull << (63 - 0),
2358 HMER_PROC_RECV_DONE = 1ull << (63 - 2),
2359 HMER_PROC_RECV_ERROR_MASKED = 1ull << (63 - 3),
2360 HMER_TFAC_ERROR = 1ull << (63 - 4),
2361 HMER_TFMR_PARITY_ERROR = 1ull << (63 - 5),
2362 HMER_XSCOM_FAIL = 1ull << (63 - 8),
2363 HMER_XSCOM_DONE = 1ull << (63 - 9),
2364 HMER_PROC_RECV_AGAIN = 1ull << (63 - 11),
2365 HMER_WARN_RISE = 1ull << (63 - 14),
2366 HMER_WARN_FALL = 1ull << (63 - 15),
2367 HMER_SCOM_FIR_HMI = 1ull << (63 - 16),
2368 HMER_TRIG_FIR_HMI = 1ull << (63 - 17),
2369 HMER_HYP_RESOURCE_ERR = 1ull << (63 - 20),
2370 HMER_XSCOM_STATUS_MASK = 7ull << (63 - 23),
2371 HMER_XSCOM_STATUS_LSH = (63 - 23),
2372 };
2373
2374 /* Alternate Interrupt Location (AIL) */
2375 enum {
2376 AIL_NONE = 0,
2377 AIL_RESERVED = 1,
2378 AIL_0001_8000 = 2,
2379 AIL_C000_0000_0000_4000 = 3,
2380 };
2381
2382 /*****************************************************************************/
2383
2384 #define is_isa300(ctx) (!!(ctx->insns_flags2 & PPC2_ISA300))
2385 target_ulong cpu_read_xer(CPUPPCState *env);
2386 void cpu_write_xer(CPUPPCState *env, target_ulong xer);
2387
2388 static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
2389 target_ulong *cs_base, uint32_t *flags)
2390 {
2391 *pc = env->nip;
2392 *cs_base = 0;
2393 *flags = env->hflags;
2394 }
2395
2396 void QEMU_NORETURN raise_exception(CPUPPCState *env, uint32_t exception);
2397 void QEMU_NORETURN raise_exception_ra(CPUPPCState *env, uint32_t exception,
2398 uintptr_t raddr);
2399 void QEMU_NORETURN raise_exception_err(CPUPPCState *env, uint32_t exception,
2400 uint32_t error_code);
2401 void QEMU_NORETURN raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
2402 uint32_t error_code, uintptr_t raddr);
2403
2404 #if !defined(CONFIG_USER_ONLY)
2405 static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2406 {
2407 uintptr_t tlbml = (uintptr_t)tlbm;
2408 uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
2409
2410 return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
2411 }
2412
2413 static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
2414 {
2415 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2416 int r = tlbncfg & TLBnCFG_N_ENTRY;
2417 return r;
2418 }
2419
2420 static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
2421 {
2422 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2423 int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2424 return r;
2425 }
2426
2427 static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2428 {
2429 int id = booke206_tlbm_id(env, tlbm);
2430 int end = 0;
2431 int i;
2432
2433 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2434 end += booke206_tlb_size(env, i);
2435 if (id < end) {
2436 return i;
2437 }
2438 }
2439
2440 cpu_abort(CPU(ppc_env_get_cpu(env)), "Unknown TLBe: %d\n", id);
2441 return 0;
2442 }
2443
2444 static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
2445 {
2446 int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2447 int tlbid = booke206_tlbm_id(env, tlb);
2448 return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2449 }
2450
2451 static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
2452 target_ulong ea, int way)
2453 {
2454 int r;
2455 uint32_t ways = booke206_tlb_ways(env, tlbn);
2456 int ways_bits = ctz32(ways);
2457 int tlb_bits = ctz32(booke206_tlb_size(env, tlbn));
2458 int i;
2459
2460 way &= ways - 1;
2461 ea >>= MAS2_EPN_SHIFT;
2462 ea &= (1 << (tlb_bits - ways_bits)) - 1;
2463 r = (ea << ways_bits) | way;
2464
2465 if (r >= booke206_tlb_size(env, tlbn)) {
2466 return NULL;
2467 }
2468
2469 /* bump up to tlbn index */
2470 for (i = 0; i < tlbn; i++) {
2471 r += booke206_tlb_size(env, i);
2472 }
2473
2474 return &env->tlb.tlbm[r];
2475 }
2476
2477 /* returns bitmap of supported page sizes for a given TLB */
2478 static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
2479 {
2480 uint32_t ret = 0;
2481
2482 if ((env->spr[SPR_MMUCFG] & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
2483 /* MAV2 */
2484 ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2485 } else {
2486 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2487 uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2488 uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2489 int i;
2490 for (i = min; i <= max; i++) {
2491 ret |= (1 << (i << 1));
2492 }
2493 }
2494
2495 return ret;
2496 }
2497
2498 static inline void booke206_fixed_size_tlbn(CPUPPCState *env, const int tlbn,
2499 ppcmas_tlb_t *tlb)
2500 {
2501 uint8_t i;
2502 int32_t tsize = -1;
2503
2504 for (i = 0; i < 32; i++) {
2505 if ((env->spr[SPR_BOOKE_TLB0PS + tlbn]) & (1ULL << i)) {
2506 if (tsize == -1) {
2507 tsize = i;
2508 } else {
2509 return;
2510 }
2511 }
2512 }
2513
2514 /* TLBnPS unimplemented? Odd.. */
2515 assert(tsize != -1);
2516 tlb->mas1 &= ~MAS1_TSIZE_MASK;
2517 tlb->mas1 |= ((uint32_t)tsize) << MAS1_TSIZE_SHIFT;
2518 }
2519
2520 #endif
2521
2522 static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2523 {
2524 if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2525 return msr & (1ULL << MSR_CM);
2526 }
2527
2528 return msr & (1ULL << MSR_SF);
2529 }
2530
2531 /**
2532 * Check whether register rx is in the range between start and
2533 * start + nregs (as needed by the LSWX and LSWI instructions)
2534 */
2535 static inline bool lsw_reg_in_range(int start, int nregs, int rx)
2536 {
2537 return (start + nregs <= 32 && rx >= start && rx < start + nregs) ||
2538 (start + nregs > 32 && (rx >= start || rx < start + nregs - 32));
2539 }
2540
2541 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
2542
2543 void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
2544 #endif /* PPC_CPU_H */
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