4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 #include "qemu/osdep.h"
26 #include "monitor/monitor.h"
27 #include "monitor/hmp-target.h"
28 #include "hw/i386/pc.h"
29 #include "sysemu/kvm.h"
33 static void print_pte(Monitor
*mon
, CPUArchState
*env
, hwaddr addr
,
34 hwaddr pte
, hwaddr mask
)
37 if (env
->cr
[4] & CR4_LA57_MASK
) {
38 if (addr
& (1ULL << 56)) {
42 if (addr
& (1ULL << 47)) {
47 monitor_printf(mon
, TARGET_FMT_plx
": " TARGET_FMT_plx
48 " %c%c%c%c%c%c%c%c%c\n",
51 pte
& PG_NX_MASK
? 'X' : '-',
52 pte
& PG_GLOBAL_MASK
? 'G' : '-',
53 pte
& PG_PSE_MASK
? 'P' : '-',
54 pte
& PG_DIRTY_MASK
? 'D' : '-',
55 pte
& PG_ACCESSED_MASK
? 'A' : '-',
56 pte
& PG_PCD_MASK
? 'C' : '-',
57 pte
& PG_PWT_MASK
? 'T' : '-',
58 pte
& PG_USER_MASK
? 'U' : '-',
59 pte
& PG_RW_MASK
? 'W' : '-');
62 static void tlb_info_32(Monitor
*mon
, CPUArchState
*env
)
65 uint32_t pgd
, pde
, pte
;
67 pgd
= env
->cr
[3] & ~0xfff;
68 for(l1
= 0; l1
< 1024; l1
++) {
69 cpu_physical_memory_read(pgd
+ l1
* 4, &pde
, 4);
70 pde
= le32_to_cpu(pde
);
71 if (pde
& PG_PRESENT_MASK
) {
72 if ((pde
& PG_PSE_MASK
) && (env
->cr
[4] & CR4_PSE_MASK
)) {
74 print_pte(mon
, env
, (l1
<< 22), pde
, ~((1 << 21) - 1));
76 for(l2
= 0; l2
< 1024; l2
++) {
77 cpu_physical_memory_read((pde
& ~0xfff) + l2
* 4, &pte
, 4);
78 pte
= le32_to_cpu(pte
);
79 if (pte
& PG_PRESENT_MASK
) {
80 print_pte(mon
, env
, (l1
<< 22) + (l2
<< 12),
90 static void tlb_info_pae32(Monitor
*mon
, CPUArchState
*env
)
92 unsigned int l1
, l2
, l3
;
93 uint64_t pdpe
, pde
, pte
;
94 uint64_t pdp_addr
, pd_addr
, pt_addr
;
96 pdp_addr
= env
->cr
[3] & ~0x1f;
97 for (l1
= 0; l1
< 4; l1
++) {
98 cpu_physical_memory_read(pdp_addr
+ l1
* 8, &pdpe
, 8);
99 pdpe
= le64_to_cpu(pdpe
);
100 if (pdpe
& PG_PRESENT_MASK
) {
101 pd_addr
= pdpe
& 0x3fffffffff000ULL
;
102 for (l2
= 0; l2
< 512; l2
++) {
103 cpu_physical_memory_read(pd_addr
+ l2
* 8, &pde
, 8);
104 pde
= le64_to_cpu(pde
);
105 if (pde
& PG_PRESENT_MASK
) {
106 if (pde
& PG_PSE_MASK
) {
107 /* 2M pages with PAE, CR4.PSE is ignored */
108 print_pte(mon
, env
, (l1
<< 30) + (l2
<< 21), pde
,
109 ~((hwaddr
)(1 << 20) - 1));
111 pt_addr
= pde
& 0x3fffffffff000ULL
;
112 for (l3
= 0; l3
< 512; l3
++) {
113 cpu_physical_memory_read(pt_addr
+ l3
* 8, &pte
, 8);
114 pte
= le64_to_cpu(pte
);
115 if (pte
& PG_PRESENT_MASK
) {
116 print_pte(mon
, env
, (l1
<< 30) + (l2
<< 21)
130 static void tlb_info_la48(Monitor
*mon
, CPUArchState
*env
,
131 uint64_t l0
, uint64_t pml4_addr
)
133 uint64_t l1
, l2
, l3
, l4
;
134 uint64_t pml4e
, pdpe
, pde
, pte
;
135 uint64_t pdp_addr
, pd_addr
, pt_addr
;
137 for (l1
= 0; l1
< 512; l1
++) {
138 cpu_physical_memory_read(pml4_addr
+ l1
* 8, &pml4e
, 8);
139 pml4e
= le64_to_cpu(pml4e
);
140 if (!(pml4e
& PG_PRESENT_MASK
)) {
144 pdp_addr
= pml4e
& 0x3fffffffff000ULL
;
145 for (l2
= 0; l2
< 512; l2
++) {
146 cpu_physical_memory_read(pdp_addr
+ l2
* 8, &pdpe
, 8);
147 pdpe
= le64_to_cpu(pdpe
);
148 if (!(pdpe
& PG_PRESENT_MASK
)) {
152 if (pdpe
& PG_PSE_MASK
) {
153 /* 1G pages, CR4.PSE is ignored */
154 print_pte(mon
, env
, (l0
<< 48) + (l1
<< 39) + (l2
<< 30),
155 pdpe
, 0x3ffffc0000000ULL
);
159 pd_addr
= pdpe
& 0x3fffffffff000ULL
;
160 for (l3
= 0; l3
< 512; l3
++) {
161 cpu_physical_memory_read(pd_addr
+ l3
* 8, &pde
, 8);
162 pde
= le64_to_cpu(pde
);
163 if (!(pde
& PG_PRESENT_MASK
)) {
167 if (pde
& PG_PSE_MASK
) {
168 /* 2M pages, CR4.PSE is ignored */
169 print_pte(mon
, env
, (l0
<< 48) + (l1
<< 39) + (l2
<< 30) +
170 (l3
<< 21), pde
, 0x3ffffffe00000ULL
);
174 pt_addr
= pde
& 0x3fffffffff000ULL
;
175 for (l4
= 0; l4
< 512; l4
++) {
176 cpu_physical_memory_read(pt_addr
179 pte
= le64_to_cpu(pte
);
180 if (pte
& PG_PRESENT_MASK
) {
181 print_pte(mon
, env
, (l0
<< 48) + (l1
<< 39) +
182 (l2
<< 30) + (l3
<< 21) + (l4
<< 12),
183 pte
& ~PG_PSE_MASK
, 0x3fffffffff000ULL
);
191 static void tlb_info_la57(Monitor
*mon
, CPUArchState
*env
)
197 pml5_addr
= env
->cr
[3] & 0x3fffffffff000ULL
;
198 for (l0
= 0; l0
< 512; l0
++) {
199 cpu_physical_memory_read(pml5_addr
+ l0
* 8, &pml5e
, 8);
200 pml5e
= le64_to_cpu(pml5e
);
201 if (pml5e
& PG_PRESENT_MASK
) {
202 tlb_info_la48(mon
, env
, l0
, pml5e
& 0x3fffffffff000ULL
);
206 #endif /* TARGET_X86_64 */
208 void hmp_info_tlb(Monitor
*mon
, const QDict
*qdict
)
212 env
= mon_get_cpu_env();
214 monitor_printf(mon
, "No CPU available\n");
218 if (!(env
->cr
[0] & CR0_PG_MASK
)) {
219 monitor_printf(mon
, "PG disabled\n");
222 if (env
->cr
[4] & CR4_PAE_MASK
) {
224 if (env
->hflags
& HF_LMA_MASK
) {
225 if (env
->cr
[4] & CR4_LA57_MASK
) {
226 tlb_info_la57(mon
, env
);
228 tlb_info_la48(mon
, env
, 0, env
->cr
[3] & 0x3fffffffff000ULL
);
233 tlb_info_pae32(mon
, env
);
236 tlb_info_32(mon
, env
);
240 static void mem_print(Monitor
*mon
, hwaddr
*pstart
,
242 hwaddr end
, int prot
)
248 monitor_printf(mon
, TARGET_FMT_plx
"-" TARGET_FMT_plx
" "
249 TARGET_FMT_plx
" %c%c%c\n",
250 *pstart
, end
, end
- *pstart
,
251 prot1
& PG_USER_MASK
? 'u' : '-',
253 prot1
& PG_RW_MASK
? 'w' : '-');
263 static void mem_info_32(Monitor
*mon
, CPUArchState
*env
)
267 uint32_t pgd
, pde
, pte
;
270 pgd
= env
->cr
[3] & ~0xfff;
273 for(l1
= 0; l1
< 1024; l1
++) {
274 cpu_physical_memory_read(pgd
+ l1
* 4, &pde
, 4);
275 pde
= le32_to_cpu(pde
);
277 if (pde
& PG_PRESENT_MASK
) {
278 if ((pde
& PG_PSE_MASK
) && (env
->cr
[4] & CR4_PSE_MASK
)) {
279 prot
= pde
& (PG_USER_MASK
| PG_RW_MASK
| PG_PRESENT_MASK
);
280 mem_print(mon
, &start
, &last_prot
, end
, prot
);
282 for(l2
= 0; l2
< 1024; l2
++) {
283 cpu_physical_memory_read((pde
& ~0xfff) + l2
* 4, &pte
, 4);
284 pte
= le32_to_cpu(pte
);
285 end
= (l1
<< 22) + (l2
<< 12);
286 if (pte
& PG_PRESENT_MASK
) {
288 (PG_USER_MASK
| PG_RW_MASK
| PG_PRESENT_MASK
);
292 mem_print(mon
, &start
, &last_prot
, end
, prot
);
297 mem_print(mon
, &start
, &last_prot
, end
, prot
);
300 /* Flush last range */
301 mem_print(mon
, &start
, &last_prot
, (hwaddr
)1 << 32, 0);
304 static void mem_info_pae32(Monitor
*mon
, CPUArchState
*env
)
306 unsigned int l1
, l2
, l3
;
308 uint64_t pdpe
, pde
, pte
;
309 uint64_t pdp_addr
, pd_addr
, pt_addr
;
312 pdp_addr
= env
->cr
[3] & ~0x1f;
315 for (l1
= 0; l1
< 4; l1
++) {
316 cpu_physical_memory_read(pdp_addr
+ l1
* 8, &pdpe
, 8);
317 pdpe
= le64_to_cpu(pdpe
);
319 if (pdpe
& PG_PRESENT_MASK
) {
320 pd_addr
= pdpe
& 0x3fffffffff000ULL
;
321 for (l2
= 0; l2
< 512; l2
++) {
322 cpu_physical_memory_read(pd_addr
+ l2
* 8, &pde
, 8);
323 pde
= le64_to_cpu(pde
);
324 end
= (l1
<< 30) + (l2
<< 21);
325 if (pde
& PG_PRESENT_MASK
) {
326 if (pde
& PG_PSE_MASK
) {
327 prot
= pde
& (PG_USER_MASK
| PG_RW_MASK
|
329 mem_print(mon
, &start
, &last_prot
, end
, prot
);
331 pt_addr
= pde
& 0x3fffffffff000ULL
;
332 for (l3
= 0; l3
< 512; l3
++) {
333 cpu_physical_memory_read(pt_addr
+ l3
* 8, &pte
, 8);
334 pte
= le64_to_cpu(pte
);
335 end
= (l1
<< 30) + (l2
<< 21) + (l3
<< 12);
336 if (pte
& PG_PRESENT_MASK
) {
337 prot
= pte
& pde
& (PG_USER_MASK
| PG_RW_MASK
|
342 mem_print(mon
, &start
, &last_prot
, end
, prot
);
347 mem_print(mon
, &start
, &last_prot
, end
, prot
);
352 mem_print(mon
, &start
, &last_prot
, end
, prot
);
355 /* Flush last range */
356 mem_print(mon
, &start
, &last_prot
, (hwaddr
)1 << 32, 0);
361 static void mem_info_la48(Monitor
*mon
, CPUArchState
*env
)
364 uint64_t l1
, l2
, l3
, l4
;
365 uint64_t pml4e
, pdpe
, pde
, pte
;
366 uint64_t pml4_addr
, pdp_addr
, pd_addr
, pt_addr
, start
, end
;
368 pml4_addr
= env
->cr
[3] & 0x3fffffffff000ULL
;
371 for (l1
= 0; l1
< 512; l1
++) {
372 cpu_physical_memory_read(pml4_addr
+ l1
* 8, &pml4e
, 8);
373 pml4e
= le64_to_cpu(pml4e
);
375 if (pml4e
& PG_PRESENT_MASK
) {
376 pdp_addr
= pml4e
& 0x3fffffffff000ULL
;
377 for (l2
= 0; l2
< 512; l2
++) {
378 cpu_physical_memory_read(pdp_addr
+ l2
* 8, &pdpe
, 8);
379 pdpe
= le64_to_cpu(pdpe
);
380 end
= (l1
<< 39) + (l2
<< 30);
381 if (pdpe
& PG_PRESENT_MASK
) {
382 if (pdpe
& PG_PSE_MASK
) {
383 prot
= pdpe
& (PG_USER_MASK
| PG_RW_MASK
|
386 mem_print(mon
, &start
, &last_prot
, end
, prot
);
388 pd_addr
= pdpe
& 0x3fffffffff000ULL
;
389 for (l3
= 0; l3
< 512; l3
++) {
390 cpu_physical_memory_read(pd_addr
+ l3
* 8, &pde
, 8);
391 pde
= le64_to_cpu(pde
);
392 end
= (l1
<< 39) + (l2
<< 30) + (l3
<< 21);
393 if (pde
& PG_PRESENT_MASK
) {
394 if (pde
& PG_PSE_MASK
) {
395 prot
= pde
& (PG_USER_MASK
| PG_RW_MASK
|
397 prot
&= pml4e
& pdpe
;
398 mem_print(mon
, &start
, &last_prot
, end
, prot
);
400 pt_addr
= pde
& 0x3fffffffff000ULL
;
401 for (l4
= 0; l4
< 512; l4
++) {
402 cpu_physical_memory_read(pt_addr
405 pte
= le64_to_cpu(pte
);
406 end
= (l1
<< 39) + (l2
<< 30) +
407 (l3
<< 21) + (l4
<< 12);
408 if (pte
& PG_PRESENT_MASK
) {
409 prot
= pte
& (PG_USER_MASK
| PG_RW_MASK
|
411 prot
&= pml4e
& pdpe
& pde
;
415 mem_print(mon
, &start
, &last_prot
, end
, prot
);
420 mem_print(mon
, &start
, &last_prot
, end
, prot
);
426 mem_print(mon
, &start
, &last_prot
, end
, prot
);
431 mem_print(mon
, &start
, &last_prot
, end
, prot
);
434 /* Flush last range */
435 mem_print(mon
, &start
, &last_prot
, (hwaddr
)1 << 48, 0);
438 static void mem_info_la57(Monitor
*mon
, CPUArchState
*env
)
441 uint64_t l0
, l1
, l2
, l3
, l4
;
442 uint64_t pml5e
, pml4e
, pdpe
, pde
, pte
;
443 uint64_t pml5_addr
, pml4_addr
, pdp_addr
, pd_addr
, pt_addr
, start
, end
;
445 pml5_addr
= env
->cr
[3] & 0x3fffffffff000ULL
;
448 for (l0
= 0; l0
< 512; l0
++) {
449 cpu_physical_memory_read(pml5_addr
+ l0
* 8, &pml5e
, 8);
450 pml5e
= le64_to_cpu(pml5e
);
452 if (!(pml5e
& PG_PRESENT_MASK
)) {
454 mem_print(mon
, &start
, &last_prot
, end
, prot
);
458 pml4_addr
= pml5e
& 0x3fffffffff000ULL
;
459 for (l1
= 0; l1
< 512; l1
++) {
460 cpu_physical_memory_read(pml4_addr
+ l1
* 8, &pml4e
, 8);
461 pml4e
= le64_to_cpu(pml4e
);
462 end
= (l0
<< 48) + (l1
<< 39);
463 if (!(pml4e
& PG_PRESENT_MASK
)) {
465 mem_print(mon
, &start
, &last_prot
, end
, prot
);
469 pdp_addr
= pml4e
& 0x3fffffffff000ULL
;
470 for (l2
= 0; l2
< 512; l2
++) {
471 cpu_physical_memory_read(pdp_addr
+ l2
* 8, &pdpe
, 8);
472 pdpe
= le64_to_cpu(pdpe
);
473 end
= (l0
<< 48) + (l1
<< 39) + (l2
<< 30);
474 if (pdpe
& PG_PRESENT_MASK
) {
476 mem_print(mon
, &start
, &last_prot
, end
, prot
);
480 if (pdpe
& PG_PSE_MASK
) {
481 prot
= pdpe
& (PG_USER_MASK
| PG_RW_MASK
|
483 prot
&= pml5e
& pml4e
;
484 mem_print(mon
, &start
, &last_prot
, end
, prot
);
488 pd_addr
= pdpe
& 0x3fffffffff000ULL
;
489 for (l3
= 0; l3
< 512; l3
++) {
490 cpu_physical_memory_read(pd_addr
+ l3
* 8, &pde
, 8);
491 pde
= le64_to_cpu(pde
);
492 end
= (l0
<< 48) + (l1
<< 39) + (l2
<< 30) + (l3
<< 21);
493 if (pde
& PG_PRESENT_MASK
) {
495 mem_print(mon
, &start
, &last_prot
, end
, prot
);
499 if (pde
& PG_PSE_MASK
) {
500 prot
= pde
& (PG_USER_MASK
| PG_RW_MASK
|
502 prot
&= pml5e
& pml4e
& pdpe
;
503 mem_print(mon
, &start
, &last_prot
, end
, prot
);
507 pt_addr
= pde
& 0x3fffffffff000ULL
;
508 for (l4
= 0; l4
< 512; l4
++) {
509 cpu_physical_memory_read(pt_addr
+ l4
* 8, &pte
, 8);
510 pte
= le64_to_cpu(pte
);
511 end
= (l0
<< 48) + (l1
<< 39) + (l2
<< 30) +
512 (l3
<< 21) + (l4
<< 12);
513 if (pte
& PG_PRESENT_MASK
) {
514 prot
= pte
& (PG_USER_MASK
| PG_RW_MASK
|
516 prot
&= pml5e
& pml4e
& pdpe
& pde
;
520 mem_print(mon
, &start
, &last_prot
, end
, prot
);
526 /* Flush last range */
527 mem_print(mon
, &start
, &last_prot
, (hwaddr
)1 << 57, 0);
529 #endif /* TARGET_X86_64 */
531 void hmp_info_mem(Monitor
*mon
, const QDict
*qdict
)
535 env
= mon_get_cpu_env();
537 monitor_printf(mon
, "No CPU available\n");
541 if (!(env
->cr
[0] & CR0_PG_MASK
)) {
542 monitor_printf(mon
, "PG disabled\n");
545 if (env
->cr
[4] & CR4_PAE_MASK
) {
547 if (env
->hflags
& HF_LMA_MASK
) {
548 if (env
->cr
[4] & CR4_LA57_MASK
) {
549 mem_info_la57(mon
, env
);
551 mem_info_la48(mon
, env
);
556 mem_info_pae32(mon
, env
);
559 mem_info_32(mon
, env
);
563 void hmp_mce(Monitor
*mon
, const QDict
*qdict
)
567 int cpu_index
= qdict_get_int(qdict
, "cpu_index");
568 int bank
= qdict_get_int(qdict
, "bank");
569 uint64_t status
= qdict_get_int(qdict
, "status");
570 uint64_t mcg_status
= qdict_get_int(qdict
, "mcg_status");
571 uint64_t addr
= qdict_get_int(qdict
, "addr");
572 uint64_t misc
= qdict_get_int(qdict
, "misc");
573 int flags
= MCE_INJECT_UNCOND_AO
;
575 if (qdict_get_try_bool(qdict
, "broadcast", false)) {
576 flags
|= MCE_INJECT_BROADCAST
;
578 cs
= qemu_get_cpu(cpu_index
);
581 cpu_x86_inject_mce(mon
, cpu
, bank
, status
, mcg_status
, addr
, misc
,
586 static target_long
monitor_get_pc(const struct MonitorDef
*md
, int val
)
588 CPUArchState
*env
= mon_get_cpu_env();
589 return env
->eip
+ env
->segs
[R_CS
].base
;
592 const MonitorDef monitor_defs
[] = {
593 #define SEG(name, seg) \
594 { name, offsetof(CPUX86State, segs[seg].selector), NULL, MD_I32 },\
595 { name ".base", offsetof(CPUX86State, segs[seg].base) },\
596 { name ".limit", offsetof(CPUX86State, segs[seg].limit), NULL, MD_I32 },
598 { "eax", offsetof(CPUX86State
, regs
[0]) },
599 { "ecx", offsetof(CPUX86State
, regs
[1]) },
600 { "edx", offsetof(CPUX86State
, regs
[2]) },
601 { "ebx", offsetof(CPUX86State
, regs
[3]) },
602 { "esp|sp", offsetof(CPUX86State
, regs
[4]) },
603 { "ebp|fp", offsetof(CPUX86State
, regs
[5]) },
604 { "esi", offsetof(CPUX86State
, regs
[6]) },
605 { "edi", offsetof(CPUX86State
, regs
[7]) },
607 { "r8", offsetof(CPUX86State
, regs
[8]) },
608 { "r9", offsetof(CPUX86State
, regs
[9]) },
609 { "r10", offsetof(CPUX86State
, regs
[10]) },
610 { "r11", offsetof(CPUX86State
, regs
[11]) },
611 { "r12", offsetof(CPUX86State
, regs
[12]) },
612 { "r13", offsetof(CPUX86State
, regs
[13]) },
613 { "r14", offsetof(CPUX86State
, regs
[14]) },
614 { "r15", offsetof(CPUX86State
, regs
[15]) },
616 { "eflags", offsetof(CPUX86State
, eflags
) },
617 { "eip", offsetof(CPUX86State
, eip
) },
624 { "pc", 0, monitor_get_pc
, },
628 const MonitorDef
*target_monitor_defs(void)
633 void hmp_info_local_apic(Monitor
*mon
, const QDict
*qdict
)
637 if (qdict_haskey(qdict
, "apic-id")) {
638 int id
= qdict_get_try_int(qdict
, "apic-id", 0);
639 cs
= cpu_by_arch_id(id
);
646 monitor_printf(mon
, "No CPU available\n");
649 x86_cpu_dump_local_apic_state(cs
, (FILE *)mon
, monitor_fprintf
,
653 void hmp_info_io_apic(Monitor
*mon
, const QDict
*qdict
)
655 if (kvm_irqchip_in_kernel() &&
656 !kvm_irqchip_is_split()) {
657 kvm_ioapic_dump_state(mon
, qdict
);
659 ioapic_dump_state(mon
, qdict
);