hw/xtensa/xtfpga.c

   1 /*
   2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above copyright
  10  *       notice, this list of conditions and the following disclaimer in the
  11  *       documentation and/or other materials provided with the distribution.
  12  *     * Neither the name of the Open Source and Linux Lab nor the
  13  *       names of its contributors may be used to endorse or promote products
  14  *       derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "qemu/units.h"
  30 #include "qapi/error.h"
  31 #include "cpu.h"
  32 #include "sysemu/sysemu.h"
  33 #include "hw/boards.h"
  34 #include "hw/loader.h"
  35 #include "hw/qdev-properties.h"
  36 #include "elf.h"
  37 #include "exec/memory.h"
  38 #include "hw/char/serial.h"
  39 #include "net/net.h"
  40 #include "hw/sysbus.h"
  41 #include "hw/block/flash.h"
  42 #include "chardev/char.h"
  43 #include "sysemu/device_tree.h"
  44 #include "sysemu/reset.h"
  45 #include "sysemu/runstate.h"
  46 #include "qemu/error-report.h"
  47 #include "qemu/option.h"
  48 #include "bootparam.h"
  49 #include "xtensa_memory.h"
  50 #include "hw/xtensa/mx_pic.h"
  51 #include "migration/vmstate.h"
  52
  53 typedef struct XtfpgaFlashDesc {
  54     hwaddr base;
  55     size_t size;
  56     size_t boot_base;
  57     size_t sector_size;
  58 } XtfpgaFlashDesc;
  59
  60 typedef struct XtfpgaBoardDesc {
  61     const XtfpgaFlashDesc *flash;
  62     size_t sram_size;
  63     const hwaddr *io;
  64 } XtfpgaBoardDesc;
  65
  66 typedef struct XtfpgaFpgaState {
  67     MemoryRegion iomem;
  68     uint32_t freq;
  69     uint32_t leds;
  70     uint32_t switches;
  71 } XtfpgaFpgaState;
  72
  73 static void xtfpga_fpga_reset(void *opaque)
  74 {
  75     XtfpgaFpgaState *s = opaque;
  76
  77     s->leds = 0;
  78     s->switches = 0;
  79 }
  80
  81 static uint64_t xtfpga_fpga_read(void *opaque, hwaddr addr,
  82         unsigned size)
  83 {
  84     XtfpgaFpgaState *s = opaque;
  85
  86     switch (addr) {
  87     case 0x0: /*build date code*/
  88         return 0x09272011;
  89
  90     case 0x4: /*processor clock frequency, Hz*/
  91         return s->freq;
  92
  93     case 0x8: /*LEDs (off = 0, on = 1)*/
  94         return s->leds;
  95
  96     case 0xc: /*DIP switches (off = 0, on = 1)*/
  97         return s->switches;
  98     }
  99     return 0;
 100 }
 101
 102 static void xtfpga_fpga_write(void *opaque, hwaddr addr,
 103         uint64_t val, unsigned size)
 104 {
 105     XtfpgaFpgaState *s = opaque;
 106
 107     switch (addr) {
 108     case 0x8: /*LEDs (off = 0, on = 1)*/
 109         s->leds = val;
 110         break;
 111
 112     case 0x10: /*board reset*/
 113         if (val == 0xdead) {
 114             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 115         }
 116         break;
 117     }
 118 }
 119
 120 static const MemoryRegionOps xtfpga_fpga_ops = {
 121     .read = xtfpga_fpga_read,
 122     .write = xtfpga_fpga_write,
 123     .endianness = DEVICE_NATIVE_ENDIAN,
 124 };
 125
 126 static XtfpgaFpgaState *xtfpga_fpga_init(MemoryRegion *address_space,
 127                                          hwaddr base, uint32_t freq)
 128 {
 129     XtfpgaFpgaState *s = g_new(XtfpgaFpgaState, 1);
 130
 131     memory_region_init_io(&s->iomem, NULL, &xtfpga_fpga_ops, s,
 132                           "xtfpga.fpga", 0x10000);
 133     memory_region_add_subregion(address_space, base, &s->iomem);
 134     s->freq = freq;
 135     xtfpga_fpga_reset(s);
 136     qemu_register_reset(xtfpga_fpga_reset, s);
 137     return s;
 138 }
 139
 140 static void xtfpga_net_init(MemoryRegion *address_space,
 141         hwaddr base,
 142         hwaddr descriptors,
 143         hwaddr buffers,
 144         qemu_irq irq, NICInfo *nd)
 145 {
 146     DeviceState *dev;
 147     SysBusDevice *s;
 148     MemoryRegion *ram;
 149
 150     dev = qdev_new("open_eth");
 151     qdev_set_nic_properties(dev, nd);
 152
 153     s = SYS_BUS_DEVICE(dev);
 154     sysbus_realize_and_unref(s, &error_fatal);
 155     sysbus_connect_irq(s, 0, irq);
 156     memory_region_add_subregion(address_space, base,
 157             sysbus_mmio_get_region(s, 0));
 158     memory_region_add_subregion(address_space, descriptors,
 159             sysbus_mmio_get_region(s, 1));
 160
 161     ram = g_malloc(sizeof(*ram));
 162     memory_region_init_ram_nomigrate(ram, OBJECT(s), "open_eth.ram", 16 * KiB,
 163                            &error_fatal);
 164     vmstate_register_ram_global(ram);
 165     memory_region_add_subregion(address_space, buffers, ram);
 166 }
 167
 168 static PFlashCFI01 *xtfpga_flash_init(MemoryRegion *address_space,
 169                                       const XtfpgaBoardDesc *board,
 170                                       DriveInfo *dinfo, int be)
 171 {
 172     SysBusDevice *s;
 173     DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
 174
 175     qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo));
 176     qdev_prop_set_uint32(dev, "num-blocks",
 177                          board->flash->size / board->flash->sector_size);
 178     qdev_prop_set_uint64(dev, "sector-length", board->flash->sector_size);
 179     qdev_prop_set_uint8(dev, "width", 2);
 180     qdev_prop_set_bit(dev, "big-endian", be);
 181     qdev_prop_set_string(dev, "name", "xtfpga.io.flash");
 182     s = SYS_BUS_DEVICE(dev);
 183     sysbus_realize_and_unref(s, &error_fatal);
 184     memory_region_add_subregion(address_space, board->flash->base,
 185                                 sysbus_mmio_get_region(s, 0));
 186     return PFLASH_CFI01(dev);
 187 }
 188
 189 static uint64_t translate_phys_addr(void *opaque, uint64_t addr)
 190 {
 191     XtensaCPU *cpu = opaque;
 192
 193     return cpu_get_phys_page_debug(CPU(cpu), addr);
 194 }
 195
 196 static void xtfpga_reset(void *opaque)
 197 {
 198     XtensaCPU *cpu = opaque;
 199
 200     cpu_reset(CPU(cpu));
 201 }
 202
 203 static uint64_t xtfpga_io_read(void *opaque, hwaddr addr,
 204         unsigned size)
 205 {
 206     return 0;
 207 }
 208
 209 static void xtfpga_io_write(void *opaque, hwaddr addr,
 210         uint64_t val, unsigned size)
 211 {
 212 }
 213
 214 static const MemoryRegionOps xtfpga_io_ops = {
 215     .read = xtfpga_io_read,
 216     .write = xtfpga_io_write,
 217     .endianness = DEVICE_NATIVE_ENDIAN,
 218 };
 219
 220 static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine)
 221 {
 222     MemoryRegion *system_memory = get_system_memory();
 223     XtensaCPU *cpu = NULL;
 224     CPUXtensaState *env = NULL;
 225     MemoryRegion *system_io;
 226     XtensaMxPic *mx_pic = NULL;
 227     qemu_irq *extints;
 228     DriveInfo *dinfo;
 229     PFlashCFI01 *flash = NULL;
 230     const char *kernel_filename = machine->kernel_filename;
 231     const char *kernel_cmdline = machine->kernel_cmdline;
 232     const char *dtb_filename = machine->dtb;
 233     const char *initrd_filename = machine->initrd_filename;
 234     const unsigned system_io_size = 224 * MiB;
 235     uint32_t freq = 10000000;
 236     int n;
 237     unsigned int smp_cpus = machine->smp.cpus;
 238
 239     if (smp_cpus > 1) {
 240         mx_pic = xtensa_mx_pic_init(31);
 241         qemu_register_reset(xtensa_mx_pic_reset, mx_pic);
 242     }
 243     for (n = 0; n < smp_cpus; n++) {
 244         CPUXtensaState *cenv = NULL;
 245
 246         cpu = XTENSA_CPU(cpu_create(machine->cpu_type));
 247         cenv = &cpu->env;
 248         if (!env) {
 249             env = cenv;
 250             freq = env->config->clock_freq_khz * 1000;
 251         }
 252
 253         if (mx_pic) {
 254             MemoryRegion *mx_eri;
 255
 256             mx_eri = xtensa_mx_pic_register_cpu(mx_pic,
 257                                                 xtensa_get_extints(cenv),
 258                                                 xtensa_get_runstall(cenv));
 259             memory_region_add_subregion(xtensa_get_er_region(cenv),
 260                                         0, mx_eri);
 261         }
 262         cenv->sregs[PRID] = n;
 263         xtensa_select_static_vectors(cenv, n != 0);
 264         qemu_register_reset(xtfpga_reset, cpu);
 265         /* Need MMU initialized prior to ELF loading,
 266          * so that ELF gets loaded into virtual addresses
 267          */
 268         cpu_reset(CPU(cpu));
 269     }
 270     if (smp_cpus > 1) {
 271         extints = xtensa_mx_pic_get_extints(mx_pic);
 272     } else {
 273         extints = xtensa_get_extints(env);
 274     }
 275
 276     if (env) {
 277         XtensaMemory sysram = env->config->sysram;
 278
 279         sysram.location[0].size = machine->ram_size;
 280         xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom",
 281                                      system_memory);
 282         xtensa_create_memory_regions(&env->config->instram, "xtensa.instram",
 283                                      system_memory);
 284         xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom",
 285                                      system_memory);
 286         xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram",
 287                                      system_memory);
 288         xtensa_create_memory_regions(&sysram, "xtensa.sysram",
 289                                      system_memory);
 290     }
 291
 292     system_io = g_malloc(sizeof(*system_io));
 293     memory_region_init_io(system_io, NULL, &xtfpga_io_ops, NULL, "xtfpga.io",
 294                           system_io_size);
 295     memory_region_add_subregion(system_memory, board->io[0], system_io);
 296     if (board->io[1]) {
 297         MemoryRegion *io = g_malloc(sizeof(*io));
 298
 299         memory_region_init_alias(io, NULL, "xtfpga.io.cached",
 300                                  system_io, 0, system_io_size);
 301         memory_region_add_subregion(system_memory, board->io[1], io);
 302     }
 303     xtfpga_fpga_init(system_io, 0x0d020000, freq);
 304     if (nd_table[0].used) {
 305         xtfpga_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000,
 306                         extints[1], nd_table);
 307     }
 308
 309     serial_mm_init(system_io, 0x0d050020, 2, extints[0],
 310                    115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
 311
 312     dinfo = drive_get(IF_PFLASH, 0, 0);
 313     if (dinfo) {
 314         flash = xtfpga_flash_init(system_io, board, dinfo, TARGET_BIG_ENDIAN);
 315     }
 316
 317     /* Use presence of kernel file name as 'boot from SRAM' switch. */
 318     if (kernel_filename) {
 319         uint32_t entry_point = env->pc;
 320         size_t bp_size = 3 * get_tag_size(0); /* first/last and memory tags */
 321         uint32_t tagptr = env->config->sysrom.location[0].addr +
 322             board->sram_size;
 323         uint32_t cur_tagptr;
 324         BpMemInfo memory_location = {
 325             .type = tswap32(MEMORY_TYPE_CONVENTIONAL),
 326             .start = tswap32(env->config->sysram.location[0].addr),
 327             .end = tswap32(env->config->sysram.location[0].addr +
 328                            machine->ram_size),
 329         };
 330         uint32_t lowmem_end = machine->ram_size < 0x08000000 ?
 331             machine->ram_size : 0x08000000;
 332         uint32_t cur_lowmem = QEMU_ALIGN_UP(lowmem_end / 2, 4096);
 333
 334         lowmem_end += env->config->sysram.location[0].addr;
 335         cur_lowmem += env->config->sysram.location[0].addr;
 336
 337         xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom",
 338                                      system_memory);
 339
 340         if (kernel_cmdline) {
 341             bp_size += get_tag_size(strlen(kernel_cmdline) + 1);
 342         }
 343         if (dtb_filename) {
 344             bp_size += get_tag_size(sizeof(uint32_t));
 345         }
 346         if (initrd_filename) {
 347             bp_size += get_tag_size(sizeof(BpMemInfo));
 348         }
 349
 350         /* Put kernel bootparameters to the end of that SRAM */
 351         tagptr = (tagptr - bp_size) & ~0xff;
 352         cur_tagptr = put_tag(tagptr, BP_TAG_FIRST, 0, NULL);
 353         cur_tagptr = put_tag(cur_tagptr, BP_TAG_MEMORY,
 354                              sizeof(memory_location), &memory_location);
 355
 356         if (kernel_cmdline) {
 357             cur_tagptr = put_tag(cur_tagptr, BP_TAG_COMMAND_LINE,
 358                                  strlen(kernel_cmdline) + 1, kernel_cmdline);
 359         }
 360 #ifdef CONFIG_FDT
 361         if (dtb_filename) {
 362             int fdt_size;
 363             void *fdt = load_device_tree(dtb_filename, &fdt_size);
 364             uint32_t dtb_addr = tswap32(cur_lowmem);
 365
 366             if (!fdt) {
 367                 error_report("could not load DTB '%s'", dtb_filename);
 368                 exit(EXIT_FAILURE);
 369             }
 370
 371             cpu_physical_memory_write(cur_lowmem, fdt, fdt_size);
 372             cur_tagptr = put_tag(cur_tagptr, BP_TAG_FDT,
 373                                  sizeof(dtb_addr), &dtb_addr);
 374             cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + fdt_size, 4 * KiB);
 375             g_free(fdt);
 376         }
 377 #else
 378         if (dtb_filename) {
 379             error_report("could not load DTB '%s': "
 380                          "FDT support is not configured in QEMU",
 381                          dtb_filename);
 382             exit(EXIT_FAILURE);
 383         }
 384 #endif
 385         if (initrd_filename) {
 386             BpMemInfo initrd_location = { 0 };
 387             int initrd_size = load_ramdisk(initrd_filename, cur_lowmem,
 388                                            lowmem_end - cur_lowmem);
 389
 390             if (initrd_size < 0) {
 391                 initrd_size = load_image_targphys(initrd_filename,
 392                                                   cur_lowmem,
 393                                                   lowmem_end - cur_lowmem);
 394             }
 395             if (initrd_size < 0) {
 396                 error_report("could not load initrd '%s'", initrd_filename);
 397                 exit(EXIT_FAILURE);
 398             }
 399             initrd_location.start = tswap32(cur_lowmem);
 400             initrd_location.end = tswap32(cur_lowmem + initrd_size);
 401             cur_tagptr = put_tag(cur_tagptr, BP_TAG_INITRD,
 402                                  sizeof(initrd_location), &initrd_location);
 403             cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + initrd_size, 4 * KiB);
 404         }
 405         cur_tagptr = put_tag(cur_tagptr, BP_TAG_LAST, 0, NULL);
 406         env->regs[2] = tagptr;
 407
 408         uint64_t elf_entry;
 409         int success = load_elf(kernel_filename, NULL, translate_phys_addr, cpu,
 410                                &elf_entry, NULL, NULL, NULL, TARGET_BIG_ENDIAN,
 411                                EM_XTENSA, 0, 0);
 412         if (success > 0) {
 413             entry_point = elf_entry;
 414         } else {
 415             hwaddr ep;
 416             int is_linux;
 417             success = load_uimage(kernel_filename, &ep, NULL, &is_linux,
 418                                   translate_phys_addr, cpu);
 419             if (success > 0 && is_linux) {
 420                 entry_point = ep;
 421             } else {
 422                 error_report("could not load kernel '%s'",
 423                              kernel_filename);
 424                 exit(EXIT_FAILURE);
 425             }
 426         }
 427         if (entry_point != env->pc) {
 428             uint8_t boot[] = {
 429 #if TARGET_BIG_ENDIAN
 430                 0x60, 0x00, 0x08,       /* j    1f */
 431                 0x00,                   /* .literal_position */
 432                 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */
 433                 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */
 434                                         /* 1: */
 435                 0x10, 0xff, 0xfe,       /* l32r a0, entry_pc */
 436                 0x12, 0xff, 0xfe,       /* l32r a2, entry_a2 */
 437                 0x0a, 0x00, 0x00,       /* jx   a0 */
 438 #else
 439                 0x06, 0x02, 0x00,       /* j    1f */
 440                 0x00,                   /* .literal_position */
 441                 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */
 442                 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */
 443                                         /* 1: */
 444                 0x01, 0xfe, 0xff,       /* l32r a0, entry_pc */
 445                 0x21, 0xfe, 0xff,       /* l32r a2, entry_a2 */
 446                 0xa0, 0x00, 0x00,       /* jx   a0 */
 447 #endif
 448             };
 449             uint32_t entry_pc = tswap32(entry_point);
 450             uint32_t entry_a2 = tswap32(tagptr);
 451
 452             memcpy(boot + 4, &entry_pc, sizeof(entry_pc));
 453             memcpy(boot + 8, &entry_a2, sizeof(entry_a2));
 454             cpu_physical_memory_write(env->pc, boot, sizeof(boot));
 455         }
 456     } else {
 457         if (flash) {
 458             MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash);
 459             MemoryRegion *flash_io = g_malloc(sizeof(*flash_io));
 460             uint32_t size = env->config->sysrom.location[0].size;
 461
 462             if (board->flash->size - board->flash->boot_base < size) {
 463                 size = board->flash->size - board->flash->boot_base;
 464             }
 465
 466             memory_region_init_alias(flash_io, NULL, "xtfpga.flash",
 467                                      flash_mr, board->flash->boot_base, size);
 468             memory_region_add_subregion(system_memory,
 469                                         env->config->sysrom.location[0].addr,
 470                                         flash_io);
 471         } else {
 472             xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom",
 473                                          system_memory);
 474         }
 475     }
 476 }
 477
 478 #define XTFPGA_MMU_RESERVED_MEMORY_SIZE (128 * MiB)
 479
 480 static const hwaddr xtfpga_mmu_io[2] = {
 481     0xf0000000,
 482 };
 483
 484 static const hwaddr xtfpga_nommu_io[2] = {
 485     0x90000000,
 486     0x70000000,
 487 };
 488
 489 static const XtfpgaFlashDesc lx60_flash = {
 490     .base = 0x08000000,
 491     .size = 0x00400000,
 492     .sector_size = 0x10000,
 493 };
 494
 495 static void xtfpga_lx60_init(MachineState *machine)
 496 {
 497     static const XtfpgaBoardDesc lx60_board = {
 498         .flash = &lx60_flash,
 499         .sram_size = 0x20000,
 500         .io = xtfpga_mmu_io,
 501     };
 502     xtfpga_init(&lx60_board, machine);
 503 }
 504
 505 static void xtfpga_lx60_nommu_init(MachineState *machine)
 506 {
 507     static const XtfpgaBoardDesc lx60_board = {
 508         .flash = &lx60_flash,
 509         .sram_size = 0x20000,
 510         .io = xtfpga_nommu_io,
 511     };
 512     xtfpga_init(&lx60_board, machine);
 513 }
 514
 515 static const XtfpgaFlashDesc lx200_flash = {
 516     .base = 0x08000000,
 517     .size = 0x01000000,
 518     .sector_size = 0x20000,
 519 };
 520
 521 static void xtfpga_lx200_init(MachineState *machine)
 522 {
 523     static const XtfpgaBoardDesc lx200_board = {
 524         .flash = &lx200_flash,
 525         .sram_size = 0x2000000,
 526         .io = xtfpga_mmu_io,
 527     };
 528     xtfpga_init(&lx200_board, machine);
 529 }
 530
 531 static void xtfpga_lx200_nommu_init(MachineState *machine)
 532 {
 533     static const XtfpgaBoardDesc lx200_board = {
 534         .flash = &lx200_flash,
 535         .sram_size = 0x2000000,
 536         .io = xtfpga_nommu_io,
 537     };
 538     xtfpga_init(&lx200_board, machine);
 539 }
 540
 541 static const XtfpgaFlashDesc ml605_flash = {
 542     .base = 0x08000000,
 543     .size = 0x01000000,
 544     .sector_size = 0x20000,
 545 };
 546
 547 static void xtfpga_ml605_init(MachineState *machine)
 548 {
 549     static const XtfpgaBoardDesc ml605_board = {
 550         .flash = &ml605_flash,
 551         .sram_size = 0x2000000,
 552         .io = xtfpga_mmu_io,
 553     };
 554     xtfpga_init(&ml605_board, machine);
 555 }
 556
 557 static void xtfpga_ml605_nommu_init(MachineState *machine)
 558 {
 559     static const XtfpgaBoardDesc ml605_board = {
 560         .flash = &ml605_flash,
 561         .sram_size = 0x2000000,
 562         .io = xtfpga_nommu_io,
 563     };
 564     xtfpga_init(&ml605_board, machine);
 565 }
 566
 567 static const XtfpgaFlashDesc kc705_flash = {
 568     .base = 0x00000000,
 569     .size = 0x08000000,
 570     .boot_base = 0x06000000,
 571     .sector_size = 0x20000,
 572 };
 573
 574 static void xtfpga_kc705_init(MachineState *machine)
 575 {
 576     static const XtfpgaBoardDesc kc705_board = {
 577         .flash = &kc705_flash,
 578         .sram_size = 0x2000000,
 579         .io = xtfpga_mmu_io,
 580     };
 581     xtfpga_init(&kc705_board, machine);
 582 }
 583
 584 static void xtfpga_kc705_nommu_init(MachineState *machine)
 585 {
 586     static const XtfpgaBoardDesc kc705_board = {
 587         .flash = &kc705_flash,
 588         .sram_size = 0x2000000,
 589         .io = xtfpga_nommu_io,
 590     };
 591     xtfpga_init(&kc705_board, machine);
 592 }
 593
 594 static void xtfpga_lx60_class_init(ObjectClass *oc, void *data)
 595 {
 596     MachineClass *mc = MACHINE_CLASS(oc);
 597
 598     mc->desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
 599     mc->init = xtfpga_lx60_init;
 600     mc->max_cpus = 32;
 601     mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
 602     mc->default_ram_size = 64 * MiB;
 603 }
 604
 605 static const TypeInfo xtfpga_lx60_type = {
 606     .name = MACHINE_TYPE_NAME("lx60"),
 607     .parent = TYPE_MACHINE,
 608     .class_init = xtfpga_lx60_class_init,
 609 };
 610
 611 static void xtfpga_lx60_nommu_class_init(ObjectClass *oc, void *data)
 612 {
 613     MachineClass *mc = MACHINE_CLASS(oc);
 614
 615     mc->desc = "lx60 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
 616     mc->init = xtfpga_lx60_nommu_init;
 617     mc->max_cpus = 32;
 618     mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
 619     mc->default_ram_size = 64 * MiB;
 620 }
 621
 622 static const TypeInfo xtfpga_lx60_nommu_type = {
 623     .name = MACHINE_TYPE_NAME("lx60-nommu"),
 624     .parent = TYPE_MACHINE,
 625     .class_init = xtfpga_lx60_nommu_class_init,
 626 };
 627
 628 static void xtfpga_lx200_class_init(ObjectClass *oc, void *data)
 629 {
 630     MachineClass *mc = MACHINE_CLASS(oc);
 631
 632     mc->desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
 633     mc->init = xtfpga_lx200_init;
 634     mc->max_cpus = 32;
 635     mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
 636     mc->default_ram_size = 96 * MiB;
 637 }
 638
 639 static const TypeInfo xtfpga_lx200_type = {
 640     .name = MACHINE_TYPE_NAME("lx200"),
 641     .parent = TYPE_MACHINE,
 642     .class_init = xtfpga_lx200_class_init,
 643 };
 644
 645 static void xtfpga_lx200_nommu_class_init(ObjectClass *oc, void *data)
 646 {
 647     MachineClass *mc = MACHINE_CLASS(oc);
 648
 649     mc->desc = "lx200 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
 650     mc->init = xtfpga_lx200_nommu_init;
 651     mc->max_cpus = 32;
 652     mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
 653     mc->default_ram_size = 96 * MiB;
 654 }
 655
 656 static const TypeInfo xtfpga_lx200_nommu_type = {
 657     .name = MACHINE_TYPE_NAME("lx200-nommu"),
 658     .parent = TYPE_MACHINE,
 659     .class_init = xtfpga_lx200_nommu_class_init,
 660 };
 661
 662 static void xtfpga_ml605_class_init(ObjectClass *oc, void *data)
 663 {
 664     MachineClass *mc = MACHINE_CLASS(oc);
 665
 666     mc->desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
 667     mc->init = xtfpga_ml605_init;
 668     mc->max_cpus = 32;
 669     mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
 670     mc->default_ram_size = 512 * MiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE;
 671 }
 672
 673 static const TypeInfo xtfpga_ml605_type = {
 674     .name = MACHINE_TYPE_NAME("ml605"),
 675     .parent = TYPE_MACHINE,
 676     .class_init = xtfpga_ml605_class_init,
 677 };
 678
 679 static void xtfpga_ml605_nommu_class_init(ObjectClass *oc, void *data)
 680 {
 681     MachineClass *mc = MACHINE_CLASS(oc);
 682
 683     mc->desc = "ml605 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
 684     mc->init = xtfpga_ml605_nommu_init;
 685     mc->max_cpus = 32;
 686     mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
 687     mc->default_ram_size = 256 * MiB;
 688 }
 689
 690 static const TypeInfo xtfpga_ml605_nommu_type = {
 691     .name = MACHINE_TYPE_NAME("ml605-nommu"),
 692     .parent = TYPE_MACHINE,
 693     .class_init = xtfpga_ml605_nommu_class_init,
 694 };
 695
 696 static void xtfpga_kc705_class_init(ObjectClass *oc, void *data)
 697 {
 698     MachineClass *mc = MACHINE_CLASS(oc);
 699
 700     mc->desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
 701     mc->init = xtfpga_kc705_init;
 702     mc->max_cpus = 32;
 703     mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
 704     mc->default_ram_size = 1 * GiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE;
 705 }
 706
 707 static const TypeInfo xtfpga_kc705_type = {
 708     .name = MACHINE_TYPE_NAME("kc705"),
 709     .parent = TYPE_MACHINE,
 710     .class_init = xtfpga_kc705_class_init,
 711 };
 712
 713 static void xtfpga_kc705_nommu_class_init(ObjectClass *oc, void *data)
 714 {
 715     MachineClass *mc = MACHINE_CLASS(oc);
 716
 717     mc->desc = "kc705 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
 718     mc->init = xtfpga_kc705_nommu_init;
 719     mc->max_cpus = 32;
 720     mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
 721     mc->default_ram_size = 256 * MiB;
 722 }
 723
 724 static const TypeInfo xtfpga_kc705_nommu_type = {
 725     .name = MACHINE_TYPE_NAME("kc705-nommu"),
 726     .parent = TYPE_MACHINE,
 727     .class_init = xtfpga_kc705_nommu_class_init,
 728 };
 729
 730 static void xtfpga_machines_init(void)
 731 {
 732     type_register_static(&xtfpga_lx60_type);
 733     type_register_static(&xtfpga_lx200_type);
 734     type_register_static(&xtfpga_ml605_type);
 735     type_register_static(&xtfpga_kc705_type);
 736     type_register_static(&xtfpga_lx60_nommu_type);
 737     type_register_static(&xtfpga_lx200_nommu_type);
 738     type_register_static(&xtfpga_ml605_nommu_type);
 739     type_register_static(&xtfpga_kc705_nommu_type);
 740 }
 741
 742 type_init(xtfpga_machines_init)