4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
5 * Feng Gao <gf91597@gmail.com>
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
23 #include "exec/exec-all.h"
24 #include "disas/disas.h"
25 #include "tcg/tcg-op.h"
27 #include "qemu/bitops.h"
28 #include "qemu/qemu-print.h"
29 #include "exec/cpu_ldst.h"
30 #include "exec/translator.h"
32 #include "exec/helper-proto.h"
33 #include "exec/helper-gen.h"
34 #include "exec/gen-icount.h"
36 #include "trace-tcg.h"
39 /* is_jmp field values */
40 #define DISAS_EXIT DISAS_TARGET_0 /* force exit to main loop */
41 #define DISAS_JUMP DISAS_TARGET_1 /* exit via jmp_pc/jmp_pc_imm */
43 typedef struct DisasContext
{
44 DisasContextBase base
;
47 uint32_t delayed_branch
;
51 /* If not -1, jmp_pc contains this value and so is a direct jump. */
52 target_ulong jmp_pc_imm
;
54 /* The temporary corresponding to register 0 for this compilation. */
58 static inline bool is_user(DisasContext
*dc
)
60 #ifdef CONFIG_USER_ONLY
63 return !(dc
->tb_flags
& TB_FLAGS_SM
);
67 /* Include the auto-generated decoder. */
68 #include "decode.inc.c"
71 static TCGv cpu_regs
[32];
73 static TCGv jmp_pc
; /* l.jr/l.jalr temp pc */
75 static TCGv cpu_sr_f
; /* bf/bnf, F flag taken */
76 static TCGv cpu_sr_cy
; /* carry (unsigned overflow) */
77 static TCGv cpu_sr_ov
; /* signed overflow */
78 static TCGv cpu_lock_addr
;
79 static TCGv cpu_lock_value
;
80 static TCGv_i32 fpcsr
;
81 static TCGv_i64 cpu_mac
; /* MACHI:MACLO */
82 static TCGv_i32 cpu_dflag
;
84 void openrisc_translate_init(void)
86 static const char * const regnames
[] = {
87 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
88 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
89 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
90 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
94 cpu_sr
= tcg_global_mem_new(cpu_env
,
95 offsetof(CPUOpenRISCState
, sr
), "sr");
96 cpu_dflag
= tcg_global_mem_new_i32(cpu_env
,
97 offsetof(CPUOpenRISCState
, dflag
),
99 cpu_pc
= tcg_global_mem_new(cpu_env
,
100 offsetof(CPUOpenRISCState
, pc
), "pc");
101 cpu_ppc
= tcg_global_mem_new(cpu_env
,
102 offsetof(CPUOpenRISCState
, ppc
), "ppc");
103 jmp_pc
= tcg_global_mem_new(cpu_env
,
104 offsetof(CPUOpenRISCState
, jmp_pc
), "jmp_pc");
105 cpu_sr_f
= tcg_global_mem_new(cpu_env
,
106 offsetof(CPUOpenRISCState
, sr_f
), "sr_f");
107 cpu_sr_cy
= tcg_global_mem_new(cpu_env
,
108 offsetof(CPUOpenRISCState
, sr_cy
), "sr_cy");
109 cpu_sr_ov
= tcg_global_mem_new(cpu_env
,
110 offsetof(CPUOpenRISCState
, sr_ov
), "sr_ov");
111 cpu_lock_addr
= tcg_global_mem_new(cpu_env
,
112 offsetof(CPUOpenRISCState
, lock_addr
),
114 cpu_lock_value
= tcg_global_mem_new(cpu_env
,
115 offsetof(CPUOpenRISCState
, lock_value
),
117 fpcsr
= tcg_global_mem_new_i32(cpu_env
,
118 offsetof(CPUOpenRISCState
, fpcsr
),
120 cpu_mac
= tcg_global_mem_new_i64(cpu_env
,
121 offsetof(CPUOpenRISCState
, mac
),
123 for (i
= 0; i
< 32; i
++) {
124 cpu_regs
[i
] = tcg_global_mem_new(cpu_env
,
125 offsetof(CPUOpenRISCState
,
131 static void gen_exception(DisasContext
*dc
, unsigned int excp
)
133 TCGv_i32 tmp
= tcg_const_i32(excp
);
134 gen_helper_exception(cpu_env
, tmp
);
135 tcg_temp_free_i32(tmp
);
138 static void gen_illegal_exception(DisasContext
*dc
)
140 tcg_gen_movi_tl(cpu_pc
, dc
->base
.pc_next
);
141 gen_exception(dc
, EXCP_ILLEGAL
);
142 dc
->base
.is_jmp
= DISAS_NORETURN
;
145 static bool check_v1_3(DisasContext
*dc
)
147 return dc
->avr
>= 0x01030000;
150 static bool check_of32s(DisasContext
*dc
)
152 return dc
->cpucfgr
& CPUCFGR_OF32S
;
155 static bool check_of64a32s(DisasContext
*dc
)
157 return dc
->cpucfgr
& CPUCFGR_OF64A32S
;
160 static TCGv
cpu_R(DisasContext
*dc
, int reg
)
165 return cpu_regs
[reg
];
170 * We're about to write to REG. On the off-chance that the user is
171 * writing to R0, re-instate the architectural register.
173 static void check_r0_write(DisasContext
*dc
, int reg
)
175 if (unlikely(reg
== 0)) {
176 dc
->R0
= cpu_regs
[0];
180 static void gen_ove_cy(DisasContext
*dc
)
182 if (dc
->tb_flags
& SR_OVE
) {
183 gen_helper_ove_cy(cpu_env
);
187 static void gen_ove_ov(DisasContext
*dc
)
189 if (dc
->tb_flags
& SR_OVE
) {
190 gen_helper_ove_ov(cpu_env
);
194 static void gen_ove_cyov(DisasContext
*dc
)
196 if (dc
->tb_flags
& SR_OVE
) {
197 gen_helper_ove_cyov(cpu_env
);
201 static void gen_add(DisasContext
*dc
, TCGv dest
, TCGv srca
, TCGv srcb
)
203 TCGv t0
= tcg_const_tl(0);
204 TCGv res
= tcg_temp_new();
206 tcg_gen_add2_tl(res
, cpu_sr_cy
, srca
, t0
, srcb
, t0
);
207 tcg_gen_xor_tl(cpu_sr_ov
, srca
, srcb
);
208 tcg_gen_xor_tl(t0
, res
, srcb
);
209 tcg_gen_andc_tl(cpu_sr_ov
, t0
, cpu_sr_ov
);
212 tcg_gen_mov_tl(dest
, res
);
218 static void gen_addc(DisasContext
*dc
, TCGv dest
, TCGv srca
, TCGv srcb
)
220 TCGv t0
= tcg_const_tl(0);
221 TCGv res
= tcg_temp_new();
223 tcg_gen_add2_tl(res
, cpu_sr_cy
, srca
, t0
, cpu_sr_cy
, t0
);
224 tcg_gen_add2_tl(res
, cpu_sr_cy
, res
, cpu_sr_cy
, srcb
, t0
);
225 tcg_gen_xor_tl(cpu_sr_ov
, srca
, srcb
);
226 tcg_gen_xor_tl(t0
, res
, srcb
);
227 tcg_gen_andc_tl(cpu_sr_ov
, t0
, cpu_sr_ov
);
230 tcg_gen_mov_tl(dest
, res
);
236 static void gen_sub(DisasContext
*dc
, TCGv dest
, TCGv srca
, TCGv srcb
)
238 TCGv res
= tcg_temp_new();
240 tcg_gen_sub_tl(res
, srca
, srcb
);
241 tcg_gen_xor_tl(cpu_sr_cy
, srca
, srcb
);
242 tcg_gen_xor_tl(cpu_sr_ov
, res
, srcb
);
243 tcg_gen_and_tl(cpu_sr_ov
, cpu_sr_ov
, cpu_sr_cy
);
244 tcg_gen_setcond_tl(TCG_COND_LTU
, cpu_sr_cy
, srca
, srcb
);
246 tcg_gen_mov_tl(dest
, res
);
252 static void gen_mul(DisasContext
*dc
, TCGv dest
, TCGv srca
, TCGv srcb
)
254 TCGv t0
= tcg_temp_new();
256 tcg_gen_muls2_tl(dest
, cpu_sr_ov
, srca
, srcb
);
257 tcg_gen_sari_tl(t0
, dest
, TARGET_LONG_BITS
- 1);
258 tcg_gen_setcond_tl(TCG_COND_NE
, cpu_sr_ov
, cpu_sr_ov
, t0
);
261 tcg_gen_neg_tl(cpu_sr_ov
, cpu_sr_ov
);
265 static void gen_mulu(DisasContext
*dc
, TCGv dest
, TCGv srca
, TCGv srcb
)
267 tcg_gen_muls2_tl(dest
, cpu_sr_cy
, srca
, srcb
);
268 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_sr_cy
, cpu_sr_cy
, 0);
273 static void gen_div(DisasContext
*dc
, TCGv dest
, TCGv srca
, TCGv srcb
)
275 TCGv t0
= tcg_temp_new();
277 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_sr_ov
, srcb
, 0);
278 /* The result of divide-by-zero is undefined.
279 Supress the host-side exception by dividing by 1. */
280 tcg_gen_or_tl(t0
, srcb
, cpu_sr_ov
);
281 tcg_gen_div_tl(dest
, srca
, t0
);
284 tcg_gen_neg_tl(cpu_sr_ov
, cpu_sr_ov
);
288 static void gen_divu(DisasContext
*dc
, TCGv dest
, TCGv srca
, TCGv srcb
)
290 TCGv t0
= tcg_temp_new();
292 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_sr_cy
, srcb
, 0);
293 /* The result of divide-by-zero is undefined.
294 Supress the host-side exception by dividing by 1. */
295 tcg_gen_or_tl(t0
, srcb
, cpu_sr_cy
);
296 tcg_gen_divu_tl(dest
, srca
, t0
);
302 static void gen_muld(DisasContext
*dc
, TCGv srca
, TCGv srcb
)
304 TCGv_i64 t1
= tcg_temp_new_i64();
305 TCGv_i64 t2
= tcg_temp_new_i64();
307 tcg_gen_ext_tl_i64(t1
, srca
);
308 tcg_gen_ext_tl_i64(t2
, srcb
);
309 if (TARGET_LONG_BITS
== 32) {
310 tcg_gen_mul_i64(cpu_mac
, t1
, t2
);
311 tcg_gen_movi_tl(cpu_sr_ov
, 0);
313 TCGv_i64 high
= tcg_temp_new_i64();
315 tcg_gen_muls2_i64(cpu_mac
, high
, t1
, t2
);
316 tcg_gen_sari_i64(t1
, cpu_mac
, 63);
317 tcg_gen_setcond_i64(TCG_COND_NE
, t1
, t1
, high
);
318 tcg_temp_free_i64(high
);
319 tcg_gen_trunc_i64_tl(cpu_sr_ov
, t1
);
320 tcg_gen_neg_tl(cpu_sr_ov
, cpu_sr_ov
);
324 tcg_temp_free_i64(t1
);
325 tcg_temp_free_i64(t2
);
328 static void gen_muldu(DisasContext
*dc
, TCGv srca
, TCGv srcb
)
330 TCGv_i64 t1
= tcg_temp_new_i64();
331 TCGv_i64 t2
= tcg_temp_new_i64();
333 tcg_gen_extu_tl_i64(t1
, srca
);
334 tcg_gen_extu_tl_i64(t2
, srcb
);
335 if (TARGET_LONG_BITS
== 32) {
336 tcg_gen_mul_i64(cpu_mac
, t1
, t2
);
337 tcg_gen_movi_tl(cpu_sr_cy
, 0);
339 TCGv_i64 high
= tcg_temp_new_i64();
341 tcg_gen_mulu2_i64(cpu_mac
, high
, t1
, t2
);
342 tcg_gen_setcondi_i64(TCG_COND_NE
, high
, high
, 0);
343 tcg_gen_trunc_i64_tl(cpu_sr_cy
, high
);
344 tcg_temp_free_i64(high
);
348 tcg_temp_free_i64(t1
);
349 tcg_temp_free_i64(t2
);
352 static void gen_mac(DisasContext
*dc
, TCGv srca
, TCGv srcb
)
354 TCGv_i64 t1
= tcg_temp_new_i64();
355 TCGv_i64 t2
= tcg_temp_new_i64();
357 tcg_gen_ext_tl_i64(t1
, srca
);
358 tcg_gen_ext_tl_i64(t2
, srcb
);
359 tcg_gen_mul_i64(t1
, t1
, t2
);
361 /* Note that overflow is only computed during addition stage. */
362 tcg_gen_xor_i64(t2
, cpu_mac
, t1
);
363 tcg_gen_add_i64(cpu_mac
, cpu_mac
, t1
);
364 tcg_gen_xor_i64(t1
, t1
, cpu_mac
);
365 tcg_gen_andc_i64(t1
, t1
, t2
);
366 tcg_temp_free_i64(t2
);
368 #if TARGET_LONG_BITS == 32
369 tcg_gen_extrh_i64_i32(cpu_sr_ov
, t1
);
371 tcg_gen_mov_i64(cpu_sr_ov
, t1
);
373 tcg_temp_free_i64(t1
);
378 static void gen_macu(DisasContext
*dc
, TCGv srca
, TCGv srcb
)
380 TCGv_i64 t1
= tcg_temp_new_i64();
381 TCGv_i64 t2
= tcg_temp_new_i64();
383 tcg_gen_extu_tl_i64(t1
, srca
);
384 tcg_gen_extu_tl_i64(t2
, srcb
);
385 tcg_gen_mul_i64(t1
, t1
, t2
);
386 tcg_temp_free_i64(t2
);
388 /* Note that overflow is only computed during addition stage. */
389 tcg_gen_add_i64(cpu_mac
, cpu_mac
, t1
);
390 tcg_gen_setcond_i64(TCG_COND_LTU
, t1
, cpu_mac
, t1
);
391 tcg_gen_trunc_i64_tl(cpu_sr_cy
, t1
);
392 tcg_temp_free_i64(t1
);
397 static void gen_msb(DisasContext
*dc
, TCGv srca
, TCGv srcb
)
399 TCGv_i64 t1
= tcg_temp_new_i64();
400 TCGv_i64 t2
= tcg_temp_new_i64();
402 tcg_gen_ext_tl_i64(t1
, srca
);
403 tcg_gen_ext_tl_i64(t2
, srcb
);
404 tcg_gen_mul_i64(t1
, t1
, t2
);
406 /* Note that overflow is only computed during subtraction stage. */
407 tcg_gen_xor_i64(t2
, cpu_mac
, t1
);
408 tcg_gen_sub_i64(cpu_mac
, cpu_mac
, t1
);
409 tcg_gen_xor_i64(t1
, t1
, cpu_mac
);
410 tcg_gen_and_i64(t1
, t1
, t2
);
411 tcg_temp_free_i64(t2
);
413 #if TARGET_LONG_BITS == 32
414 tcg_gen_extrh_i64_i32(cpu_sr_ov
, t1
);
416 tcg_gen_mov_i64(cpu_sr_ov
, t1
);
418 tcg_temp_free_i64(t1
);
423 static void gen_msbu(DisasContext
*dc
, TCGv srca
, TCGv srcb
)
425 TCGv_i64 t1
= tcg_temp_new_i64();
426 TCGv_i64 t2
= tcg_temp_new_i64();
428 tcg_gen_extu_tl_i64(t1
, srca
);
429 tcg_gen_extu_tl_i64(t2
, srcb
);
430 tcg_gen_mul_i64(t1
, t1
, t2
);
432 /* Note that overflow is only computed during subtraction stage. */
433 tcg_gen_setcond_i64(TCG_COND_LTU
, t2
, cpu_mac
, t1
);
434 tcg_gen_sub_i64(cpu_mac
, cpu_mac
, t1
);
435 tcg_gen_trunc_i64_tl(cpu_sr_cy
, t2
);
436 tcg_temp_free_i64(t2
);
437 tcg_temp_free_i64(t1
);
442 static bool trans_l_add(DisasContext
*dc
, arg_dab
*a
)
444 check_r0_write(dc
, a
->d
);
445 gen_add(dc
, cpu_R(dc
, a
->d
), cpu_R(dc
, a
->a
), cpu_R(dc
, a
->b
));
449 static bool trans_l_addc(DisasContext
*dc
, arg_dab
*a
)
451 check_r0_write(dc
, a
->d
);
452 gen_addc(dc
, cpu_R(dc
, a
->d
), cpu_R(dc
, a
->a
), cpu_R(dc
, a
->b
));
456 static bool trans_l_sub(DisasContext
*dc
, arg_dab
*a
)
458 check_r0_write(dc
, a
->d
);
459 gen_sub(dc
, cpu_R(dc
, a
->d
), cpu_R(dc
, a
->a
), cpu_R(dc
, a
->b
));
463 static bool trans_l_and(DisasContext
*dc
, arg_dab
*a
)
465 check_r0_write(dc
, a
->d
);
466 tcg_gen_and_tl(cpu_R(dc
, a
->d
), cpu_R(dc
, a
->a
), cpu_R(dc
, a
->b
));
470 static bool trans_l_or(DisasContext
*dc
, arg_dab
*a
)
472 check_r0_write(dc
, a
->d
);
473 tcg_gen_or_tl(cpu_R(dc
, a
->d
), cpu_R(dc
, a
->a
), cpu_R(dc
, a
->b
));
477 static bool trans_l_xor(DisasContext
*dc
, arg_dab
*a
)
479 check_r0_write(dc
, a
->d
);
480 tcg_gen_xor_tl(cpu_R(dc
, a
->d
), cpu_R(dc
, a
->a
), cpu_R(dc
, a
->b
));
484 static bool trans_l_sll(DisasContext
*dc
, arg_dab
*a
)
486 check_r0_write(dc
, a
->d
);
487 tcg_gen_shl_tl(cpu_R(dc
, a
->d
), cpu_R(dc
, a
->a
), cpu_R(dc
, a
->b
));
491 static bool trans_l_srl(DisasContext
*dc
, arg_dab
*a
)
493 check_r0_write(dc
, a
->d
);
494 tcg_gen_shr_tl(cpu_R(dc
, a
->d
), cpu_R(dc
, a
->a
), cpu_R(dc
, a
->b
));
498 static bool trans_l_sra(DisasContext
*dc
, arg_dab
*a
)
500 check_r0_write(dc
, a
->d
);
501 tcg_gen_sar_tl(cpu_R(dc
, a
->d
), cpu_R(dc
, a
->a
), cpu_R(dc
, a
->b
));
505 static bool trans_l_ror(DisasContext
*dc
, arg_dab
*a
)
507 check_r0_write(dc
, a
->d
);
508 tcg_gen_rotr_tl(cpu_R(dc
, a
->d
), cpu_R(dc
, a
->a
), cpu_R(dc
, a
->b
));
512 static bool trans_l_exths(DisasContext
*dc
, arg_da
*a
)
514 check_r0_write(dc
, a
->d
);
515 tcg_gen_ext16s_tl(cpu_R(dc
, a
->d
), cpu_R(dc
, a
->a
));
519 static bool trans_l_extbs(DisasContext
*dc
, arg_da
*a
)
521 check_r0_write(dc
, a
->d
);
522 tcg_gen_ext8s_tl(cpu_R(dc
, a
->d
), cpu_R(dc
, a
->a
));
526 static bool trans_l_exthz(DisasContext
*dc
, arg_da
*a
)
528 check_r0_write(dc
, a
->d
);
529 tcg_gen_ext16u_tl(cpu_R(dc
, a
->d
), cpu_R(dc
, a
->a
));
533 static bool trans_l_extbz(DisasContext
*dc
, arg_da
*a
)
535 check_r0_write(dc
, a
->d
);
536 tcg_gen_ext8u_tl(cpu_R(dc
, a
->d
), cpu_R(dc
, a
->a
));
540 static bool trans_l_cmov(DisasContext
*dc
, arg_dab
*a
)
544 check_r0_write(dc
, a
->d
);
545 zero
= tcg_const_tl(0);
546 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_R(dc
, a
->d
), cpu_sr_f
, zero
,
547 cpu_R(dc
, a
->a
), cpu_R(dc
, a
->b
));
552 static bool trans_l_ff1(DisasContext
*dc
, arg_da
*a
)
554 check_r0_write(dc
, a
->d
);
555 tcg_gen_ctzi_tl(cpu_R(dc
, a
->d
), cpu_R(dc
, a
->a
), -1);
556 tcg_gen_addi_tl(cpu_R(dc
, a
->d
), cpu_R(dc
, a
->d
), 1);
560 static bool trans_l_fl1(DisasContext
*dc
, arg_da
*a
)
562 check_r0_write(dc
, a
->d
);
563 tcg_gen_clzi_tl(cpu_R(dc
, a
->d
), cpu_R(dc
, a
->a
), TARGET_LONG_BITS
);
564 tcg_gen_subfi_tl(cpu_R(dc
, a
->d
), TARGET_LONG_BITS
, cpu_R(dc
, a
->d
));
568 static bool trans_l_mul(DisasContext
*dc
, arg_dab
*a
)
570 check_r0_write(dc
, a
->d
);
571 gen_mul(dc
, cpu_R(dc
, a
->d
), cpu_R(dc
, a
->a
), cpu_R(dc
, a
->b
));
575 static bool trans_l_mulu(DisasContext
*dc
, arg_dab
*a
)
577 check_r0_write(dc
, a
->d
);
578 gen_mulu(dc
, cpu_R(dc
, a
->d
), cpu_R(dc
, a
->a
), cpu_R(dc
, a
->b
));
582 static bool trans_l_div(DisasContext
*dc
, arg_dab
*a
)
584 check_r0_write(dc
, a
->d
);
585 gen_div(dc
, cpu_R(dc
, a
->d
), cpu_R(dc
, a
->a
), cpu_R(dc
, a
->b
));
589 static bool trans_l_divu(DisasContext
*dc
, arg_dab
*a
)
591 check_r0_write(dc
, a
->d
);
592 gen_divu(dc
, cpu_R(dc
, a
->d
), cpu_R(dc
, a
->a
), cpu_R(dc
, a
->b
));
596 static bool trans_l_muld(DisasContext
*dc
, arg_ab
*a
)
598 gen_muld(dc
, cpu_R(dc
, a
->a
), cpu_R(dc
, a
->b
));
602 static bool trans_l_muldu(DisasContext
*dc
, arg_ab
*a
)
604 gen_muldu(dc
, cpu_R(dc
, a
->a
), cpu_R(dc
, a
->b
));
608 static bool trans_l_j(DisasContext
*dc
, arg_l_j
*a
)
610 target_ulong tmp_pc
= dc
->base
.pc_next
+ a
->n
* 4;
612 tcg_gen_movi_tl(jmp_pc
, tmp_pc
);
613 dc
->jmp_pc_imm
= tmp_pc
;
614 dc
->delayed_branch
= 2;
618 static bool trans_l_jal(DisasContext
*dc
, arg_l_jal
*a
)
620 target_ulong tmp_pc
= dc
->base
.pc_next
+ a
->n
* 4;
621 target_ulong ret_pc
= dc
->base
.pc_next
+ 8;
623 tcg_gen_movi_tl(cpu_regs
[9], ret_pc
);
624 /* Optimize jal being used to load the PC for PIC. */
625 if (tmp_pc
!= ret_pc
) {
626 tcg_gen_movi_tl(jmp_pc
, tmp_pc
);
627 dc
->jmp_pc_imm
= tmp_pc
;
628 dc
->delayed_branch
= 2;
633 static void do_bf(DisasContext
*dc
, arg_l_bf
*a
, TCGCond cond
)
635 target_ulong tmp_pc
= dc
->base
.pc_next
+ a
->n
* 4;
636 TCGv t_next
= tcg_const_tl(dc
->base
.pc_next
+ 8);
637 TCGv t_true
= tcg_const_tl(tmp_pc
);
638 TCGv t_zero
= tcg_const_tl(0);
640 tcg_gen_movcond_tl(cond
, jmp_pc
, cpu_sr_f
, t_zero
, t_true
, t_next
);
642 tcg_temp_free(t_next
);
643 tcg_temp_free(t_true
);
644 tcg_temp_free(t_zero
);
645 dc
->delayed_branch
= 2;
648 static bool trans_l_bf(DisasContext
*dc
, arg_l_bf
*a
)
650 do_bf(dc
, a
, TCG_COND_NE
);
654 static bool trans_l_bnf(DisasContext
*dc
, arg_l_bf
*a
)
656 do_bf(dc
, a
, TCG_COND_EQ
);
660 static bool trans_l_jr(DisasContext
*dc
, arg_l_jr
*a
)
662 tcg_gen_mov_tl(jmp_pc
, cpu_R(dc
, a
->b
));
663 dc
->delayed_branch
= 2;
667 static bool trans_l_jalr(DisasContext
*dc
, arg_l_jalr
*a
)
669 tcg_gen_mov_tl(jmp_pc
, cpu_R(dc
, a
->b
));
670 tcg_gen_movi_tl(cpu_regs
[9], dc
->base
.pc_next
+ 8);
671 dc
->delayed_branch
= 2;
675 static bool trans_l_lwa(DisasContext
*dc
, arg_load
*a
)
679 check_r0_write(dc
, a
->d
);
681 tcg_gen_addi_tl(ea
, cpu_R(dc
, a
->a
), a
->i
);
682 tcg_gen_qemu_ld_tl(cpu_R(dc
, a
->d
), ea
, dc
->mem_idx
, MO_TEUL
);
683 tcg_gen_mov_tl(cpu_lock_addr
, ea
);
684 tcg_gen_mov_tl(cpu_lock_value
, cpu_R(dc
, a
->d
));
689 static void do_load(DisasContext
*dc
, arg_load
*a
, MemOp mop
)
693 check_r0_write(dc
, a
->d
);
695 tcg_gen_addi_tl(ea
, cpu_R(dc
, a
->a
), a
->i
);
696 tcg_gen_qemu_ld_tl(cpu_R(dc
, a
->d
), ea
, dc
->mem_idx
, mop
);
700 static bool trans_l_lwz(DisasContext
*dc
, arg_load
*a
)
702 do_load(dc
, a
, MO_TEUL
);
706 static bool trans_l_lws(DisasContext
*dc
, arg_load
*a
)
708 do_load(dc
, a
, MO_TESL
);
712 static bool trans_l_lbz(DisasContext
*dc
, arg_load
*a
)
714 do_load(dc
, a
, MO_UB
);
718 static bool trans_l_lbs(DisasContext
*dc
, arg_load
*a
)
720 do_load(dc
, a
, MO_SB
);
724 static bool trans_l_lhz(DisasContext
*dc
, arg_load
*a
)
726 do_load(dc
, a
, MO_TEUW
);
730 static bool trans_l_lhs(DisasContext
*dc
, arg_load
*a
)
732 do_load(dc
, a
, MO_TESW
);
736 static bool trans_l_swa(DisasContext
*dc
, arg_store
*a
)
739 TCGLabel
*lab_fail
, *lab_done
;
742 tcg_gen_addi_tl(ea
, cpu_R(dc
, a
->a
), a
->i
);
744 /* For TB_FLAGS_R0_0, the branch below invalidates the temporary assigned
745 to cpu_regs[0]. Since l.swa is quite often immediately followed by a
746 branch, don't bother reallocating; finish the TB using the "real" R0.
747 This also takes care of RB input across the branch. */
748 dc
->R0
= cpu_regs
[0];
750 lab_fail
= gen_new_label();
751 lab_done
= gen_new_label();
752 tcg_gen_brcond_tl(TCG_COND_NE
, ea
, cpu_lock_addr
, lab_fail
);
755 val
= tcg_temp_new();
756 tcg_gen_atomic_cmpxchg_tl(val
, cpu_lock_addr
, cpu_lock_value
,
757 cpu_regs
[a
->b
], dc
->mem_idx
, MO_TEUL
);
758 tcg_gen_setcond_tl(TCG_COND_EQ
, cpu_sr_f
, val
, cpu_lock_value
);
761 tcg_gen_br(lab_done
);
763 gen_set_label(lab_fail
);
764 tcg_gen_movi_tl(cpu_sr_f
, 0);
766 gen_set_label(lab_done
);
767 tcg_gen_movi_tl(cpu_lock_addr
, -1);
771 static void do_store(DisasContext
*dc
, arg_store
*a
, MemOp mop
)
773 TCGv t0
= tcg_temp_new();
774 tcg_gen_addi_tl(t0
, cpu_R(dc
, a
->a
), a
->i
);
775 tcg_gen_qemu_st_tl(cpu_R(dc
, a
->b
), t0
, dc
->mem_idx
, mop
);
779 static bool trans_l_sw(DisasContext
*dc
, arg_store
*a
)
781 do_store(dc
, a
, MO_TEUL
);
785 static bool trans_l_sb(DisasContext
*dc
, arg_store
*a
)
787 do_store(dc
, a
, MO_UB
);
791 static bool trans_l_sh(DisasContext
*dc
, arg_store
*a
)
793 do_store(dc
, a
, MO_TEUW
);
797 static bool trans_l_nop(DisasContext
*dc
, arg_l_nop
*a
)
802 static bool trans_l_adrp(DisasContext
*dc
, arg_l_adrp
*a
)
804 if (!check_v1_3(dc
)) {
807 check_r0_write(dc
, a
->d
);
809 tcg_gen_movi_i32(cpu_R(dc
, a
->d
),
810 (dc
->base
.pc_next
& TARGET_PAGE_MASK
) +
811 ((target_long
)a
->i
<< TARGET_PAGE_BITS
));
815 static bool trans_l_addi(DisasContext
*dc
, arg_rri
*a
)
819 check_r0_write(dc
, a
->d
);
820 t0
= tcg_const_tl(a
->i
);
821 gen_add(dc
, cpu_R(dc
, a
->d
), cpu_R(dc
, a
->a
), t0
);
826 static bool trans_l_addic(DisasContext
*dc
, arg_rri
*a
)
830 check_r0_write(dc
, a
->d
);
831 t0
= tcg_const_tl(a
->i
);
832 gen_addc(dc
, cpu_R(dc
, a
->d
), cpu_R(dc
, a
->a
), t0
);
837 static bool trans_l_muli(DisasContext
*dc
, arg_rri
*a
)
841 check_r0_write(dc
, a
->d
);
842 t0
= tcg_const_tl(a
->i
);
843 gen_mul(dc
, cpu_R(dc
, a
->d
), cpu_R(dc
, a
->a
), t0
);
848 static bool trans_l_maci(DisasContext
*dc
, arg_l_maci
*a
)
852 t0
= tcg_const_tl(a
->i
);
853 gen_mac(dc
, cpu_R(dc
, a
->a
), t0
);
858 static bool trans_l_andi(DisasContext
*dc
, arg_rrk
*a
)
860 check_r0_write(dc
, a
->d
);
861 tcg_gen_andi_tl(cpu_R(dc
, a
->d
), cpu_R(dc
, a
->a
), a
->k
);
865 static bool trans_l_ori(DisasContext
*dc
, arg_rrk
*a
)
867 check_r0_write(dc
, a
->d
);
868 tcg_gen_ori_tl(cpu_R(dc
, a
->d
), cpu_R(dc
, a
->a
), a
->k
);
872 static bool trans_l_xori(DisasContext
*dc
, arg_rri
*a
)
874 check_r0_write(dc
, a
->d
);
875 tcg_gen_xori_tl(cpu_R(dc
, a
->d
), cpu_R(dc
, a
->a
), a
->i
);
879 static bool trans_l_mfspr(DisasContext
*dc
, arg_l_mfspr
*a
)
881 check_r0_write(dc
, a
->d
);
884 gen_illegal_exception(dc
);
886 TCGv spr
= tcg_temp_new();
887 tcg_gen_ori_tl(spr
, cpu_R(dc
, a
->a
), a
->k
);
888 gen_helper_mfspr(cpu_R(dc
, a
->d
), cpu_env
, cpu_R(dc
, a
->d
), spr
);
894 static bool trans_l_mtspr(DisasContext
*dc
, arg_l_mtspr
*a
)
897 gen_illegal_exception(dc
);
901 /* For SR, we will need to exit the TB to recognize the new
902 * exception state. For NPC, in theory this counts as a branch
903 * (although the SPR only exists for use by an ICE). Save all
904 * of the cpu state first, allowing it to be overwritten.
906 if (dc
->delayed_branch
) {
907 tcg_gen_mov_tl(cpu_pc
, jmp_pc
);
908 tcg_gen_discard_tl(jmp_pc
);
910 tcg_gen_movi_tl(cpu_pc
, dc
->base
.pc_next
+ 4);
912 dc
->base
.is_jmp
= DISAS_EXIT
;
914 spr
= tcg_temp_new();
915 tcg_gen_ori_tl(spr
, cpu_R(dc
, a
->a
), a
->k
);
916 gen_helper_mtspr(cpu_env
, spr
, cpu_R(dc
, a
->b
));
922 static bool trans_l_mac(DisasContext
*dc
, arg_ab
*a
)
924 gen_mac(dc
, cpu_R(dc
, a
->a
), cpu_R(dc
, a
->b
));
928 static bool trans_l_msb(DisasContext
*dc
, arg_ab
*a
)
930 gen_msb(dc
, cpu_R(dc
, a
->a
), cpu_R(dc
, a
->b
));
934 static bool trans_l_macu(DisasContext
*dc
, arg_ab
*a
)
936 gen_macu(dc
, cpu_R(dc
, a
->a
), cpu_R(dc
, a
->b
));
940 static bool trans_l_msbu(DisasContext
*dc
, arg_ab
*a
)
942 gen_msbu(dc
, cpu_R(dc
, a
->a
), cpu_R(dc
, a
->b
));
946 static bool trans_l_slli(DisasContext
*dc
, arg_dal
*a
)
948 check_r0_write(dc
, a
->d
);
949 tcg_gen_shli_tl(cpu_R(dc
, a
->d
), cpu_R(dc
, a
->a
),
950 a
->l
& (TARGET_LONG_BITS
- 1));
954 static bool trans_l_srli(DisasContext
*dc
, arg_dal
*a
)
956 check_r0_write(dc
, a
->d
);
957 tcg_gen_shri_tl(cpu_R(dc
, a
->d
), cpu_R(dc
, a
->a
),
958 a
->l
& (TARGET_LONG_BITS
- 1));
962 static bool trans_l_srai(DisasContext
*dc
, arg_dal
*a
)
964 check_r0_write(dc
, a
->d
);
965 tcg_gen_sari_tl(cpu_R(dc
, a
->d
), cpu_R(dc
, a
->a
),
966 a
->l
& (TARGET_LONG_BITS
- 1));
970 static bool trans_l_rori(DisasContext
*dc
, arg_dal
*a
)
972 check_r0_write(dc
, a
->d
);
973 tcg_gen_rotri_tl(cpu_R(dc
, a
->d
), cpu_R(dc
, a
->a
),
974 a
->l
& (TARGET_LONG_BITS
- 1));
978 static bool trans_l_movhi(DisasContext
*dc
, arg_l_movhi
*a
)
980 check_r0_write(dc
, a
->d
);
981 tcg_gen_movi_tl(cpu_R(dc
, a
->d
), a
->k
<< 16);
985 static bool trans_l_macrc(DisasContext
*dc
, arg_l_macrc
*a
)
987 check_r0_write(dc
, a
->d
);
988 tcg_gen_trunc_i64_tl(cpu_R(dc
, a
->d
), cpu_mac
);
989 tcg_gen_movi_i64(cpu_mac
, 0);
993 static bool trans_l_sfeq(DisasContext
*dc
, arg_ab
*a
)
995 tcg_gen_setcond_tl(TCG_COND_EQ
, cpu_sr_f
,
996 cpu_R(dc
, a
->a
), cpu_R(dc
, a
->b
));
1000 static bool trans_l_sfne(DisasContext
*dc
, arg_ab
*a
)
1002 tcg_gen_setcond_tl(TCG_COND_NE
, cpu_sr_f
,
1003 cpu_R(dc
, a
->a
), cpu_R(dc
, a
->b
));
1007 static bool trans_l_sfgtu(DisasContext
*dc
, arg_ab
*a
)
1009 tcg_gen_setcond_tl(TCG_COND_GTU
, cpu_sr_f
,
1010 cpu_R(dc
, a
->a
), cpu_R(dc
, a
->b
));
1014 static bool trans_l_sfgeu(DisasContext
*dc
, arg_ab
*a
)
1016 tcg_gen_setcond_tl(TCG_COND_GEU
, cpu_sr_f
,
1017 cpu_R(dc
, a
->a
), cpu_R(dc
, a
->b
));
1021 static bool trans_l_sfltu(DisasContext
*dc
, arg_ab
*a
)
1023 tcg_gen_setcond_tl(TCG_COND_LTU
, cpu_sr_f
,
1024 cpu_R(dc
, a
->a
), cpu_R(dc
, a
->b
));
1028 static bool trans_l_sfleu(DisasContext
*dc
, arg_ab
*a
)
1030 tcg_gen_setcond_tl(TCG_COND_LEU
, cpu_sr_f
,
1031 cpu_R(dc
, a
->a
), cpu_R(dc
, a
->b
));
1035 static bool trans_l_sfgts(DisasContext
*dc
, arg_ab
*a
)
1037 tcg_gen_setcond_tl(TCG_COND_GT
, cpu_sr_f
,
1038 cpu_R(dc
, a
->a
), cpu_R(dc
, a
->b
));
1042 static bool trans_l_sfges(DisasContext
*dc
, arg_ab
*a
)
1044 tcg_gen_setcond_tl(TCG_COND_GE
, cpu_sr_f
,
1045 cpu_R(dc
, a
->a
), cpu_R(dc
, a
->b
));
1049 static bool trans_l_sflts(DisasContext
*dc
, arg_ab
*a
)
1051 tcg_gen_setcond_tl(TCG_COND_LT
, cpu_sr_f
,
1052 cpu_R(dc
, a
->a
), cpu_R(dc
, a
->b
));
1056 static bool trans_l_sfles(DisasContext
*dc
, arg_ab
*a
)
1058 tcg_gen_setcond_tl(TCG_COND_LE
,
1059 cpu_sr_f
, cpu_R(dc
, a
->a
), cpu_R(dc
, a
->b
));
1063 static bool trans_l_sfeqi(DisasContext
*dc
, arg_ai
*a
)
1065 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_sr_f
, cpu_R(dc
, a
->a
), a
->i
);
1069 static bool trans_l_sfnei(DisasContext
*dc
, arg_ai
*a
)
1071 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_sr_f
, cpu_R(dc
, a
->a
), a
->i
);
1075 static bool trans_l_sfgtui(DisasContext
*dc
, arg_ai
*a
)
1077 tcg_gen_setcondi_tl(TCG_COND_GTU
, cpu_sr_f
, cpu_R(dc
, a
->a
), a
->i
);
1081 static bool trans_l_sfgeui(DisasContext
*dc
, arg_ai
*a
)
1083 tcg_gen_setcondi_tl(TCG_COND_GEU
, cpu_sr_f
, cpu_R(dc
, a
->a
), a
->i
);
1087 static bool trans_l_sfltui(DisasContext
*dc
, arg_ai
*a
)
1089 tcg_gen_setcondi_tl(TCG_COND_LTU
, cpu_sr_f
, cpu_R(dc
, a
->a
), a
->i
);
1093 static bool trans_l_sfleui(DisasContext
*dc
, arg_ai
*a
)
1095 tcg_gen_setcondi_tl(TCG_COND_LEU
, cpu_sr_f
, cpu_R(dc
, a
->a
), a
->i
);
1099 static bool trans_l_sfgtsi(DisasContext
*dc
, arg_ai
*a
)
1101 tcg_gen_setcondi_tl(TCG_COND_GT
, cpu_sr_f
, cpu_R(dc
, a
->a
), a
->i
);
1105 static bool trans_l_sfgesi(DisasContext
*dc
, arg_ai
*a
)
1107 tcg_gen_setcondi_tl(TCG_COND_GE
, cpu_sr_f
, cpu_R(dc
, a
->a
), a
->i
);
1111 static bool trans_l_sfltsi(DisasContext
*dc
, arg_ai
*a
)
1113 tcg_gen_setcondi_tl(TCG_COND_LT
, cpu_sr_f
, cpu_R(dc
, a
->a
), a
->i
);
1117 static bool trans_l_sflesi(DisasContext
*dc
, arg_ai
*a
)
1119 tcg_gen_setcondi_tl(TCG_COND_LE
, cpu_sr_f
, cpu_R(dc
, a
->a
), a
->i
);
1123 static bool trans_l_sys(DisasContext
*dc
, arg_l_sys
*a
)
1125 tcg_gen_movi_tl(cpu_pc
, dc
->base
.pc_next
);
1126 gen_exception(dc
, EXCP_SYSCALL
);
1127 dc
->base
.is_jmp
= DISAS_NORETURN
;
1131 static bool trans_l_trap(DisasContext
*dc
, arg_l_trap
*a
)
1133 tcg_gen_movi_tl(cpu_pc
, dc
->base
.pc_next
);
1134 gen_exception(dc
, EXCP_TRAP
);
1135 dc
->base
.is_jmp
= DISAS_NORETURN
;
1139 static bool trans_l_msync(DisasContext
*dc
, arg_l_msync
*a
)
1141 tcg_gen_mb(TCG_MO_ALL
);
1145 static bool trans_l_psync(DisasContext
*dc
, arg_l_psync
*a
)
1150 static bool trans_l_csync(DisasContext
*dc
, arg_l_csync
*a
)
1155 static bool trans_l_rfe(DisasContext
*dc
, arg_l_rfe
*a
)
1158 gen_illegal_exception(dc
);
1160 gen_helper_rfe(cpu_env
);
1161 dc
->base
.is_jmp
= DISAS_EXIT
;
1166 static bool do_fp2(DisasContext
*dc
, arg_da
*a
,
1167 void (*fn
)(TCGv
, TCGv_env
, TCGv
))
1169 if (!check_of32s(dc
)) {
1172 check_r0_write(dc
, a
->d
);
1173 fn(cpu_R(dc
, a
->d
), cpu_env
, cpu_R(dc
, a
->a
));
1174 gen_helper_update_fpcsr(cpu_env
);
1178 static bool do_fp3(DisasContext
*dc
, arg_dab
*a
,
1179 void (*fn
)(TCGv
, TCGv_env
, TCGv
, TCGv
))
1181 if (!check_of32s(dc
)) {
1184 check_r0_write(dc
, a
->d
);
1185 fn(cpu_R(dc
, a
->d
), cpu_env
, cpu_R(dc
, a
->a
), cpu_R(dc
, a
->b
));
1186 gen_helper_update_fpcsr(cpu_env
);
1190 static bool do_fpcmp(DisasContext
*dc
, arg_ab
*a
,
1191 void (*fn
)(TCGv
, TCGv_env
, TCGv
, TCGv
),
1192 bool inv
, bool swap
)
1194 if (!check_of32s(dc
)) {
1198 fn(cpu_sr_f
, cpu_env
, cpu_R(dc
, a
->b
), cpu_R(dc
, a
->a
));
1200 fn(cpu_sr_f
, cpu_env
, cpu_R(dc
, a
->a
), cpu_R(dc
, a
->b
));
1203 tcg_gen_xori_tl(cpu_sr_f
, cpu_sr_f
, 1);
1205 gen_helper_update_fpcsr(cpu_env
);
1209 static bool trans_lf_add_s(DisasContext
*dc
, arg_dab
*a
)
1211 return do_fp3(dc
, a
, gen_helper_float_add_s
);
1214 static bool trans_lf_sub_s(DisasContext
*dc
, arg_dab
*a
)
1216 return do_fp3(dc
, a
, gen_helper_float_sub_s
);
1219 static bool trans_lf_mul_s(DisasContext
*dc
, arg_dab
*a
)
1221 return do_fp3(dc
, a
, gen_helper_float_mul_s
);
1224 static bool trans_lf_div_s(DisasContext
*dc
, arg_dab
*a
)
1226 return do_fp3(dc
, a
, gen_helper_float_div_s
);
1229 static bool trans_lf_rem_s(DisasContext
*dc
, arg_dab
*a
)
1231 return do_fp3(dc
, a
, gen_helper_float_rem_s
);
1235 static bool trans_lf_itof_s(DisasContext
*dc
, arg_da
*a
)
1237 return do_fp2(dc
, a
, gen_helper_itofs
);
1240 static bool trans_lf_ftoi_s(DisasContext
*dc
, arg_da
*a
)
1242 return do_fp2(dc
, a
, gen_helper_ftois
);
1245 static bool trans_lf_madd_s(DisasContext
*dc
, arg_dab
*a
)
1247 if (!check_of32s(dc
)) {
1250 check_r0_write(dc
, a
->d
);
1251 gen_helper_float_madd_s(cpu_R(dc
, a
->d
), cpu_env
, cpu_R(dc
, a
->d
),
1252 cpu_R(dc
, a
->a
), cpu_R(dc
, a
->b
));
1253 gen_helper_update_fpcsr(cpu_env
);
1257 static bool trans_lf_sfeq_s(DisasContext
*dc
, arg_ab
*a
)
1259 return do_fpcmp(dc
, a
, gen_helper_float_eq_s
, false, false);
1262 static bool trans_lf_sfne_s(DisasContext
*dc
, arg_ab
*a
)
1264 return do_fpcmp(dc
, a
, gen_helper_float_eq_s
, true, false);
1267 static bool trans_lf_sfgt_s(DisasContext
*dc
, arg_ab
*a
)
1269 return do_fpcmp(dc
, a
, gen_helper_float_lt_s
, false, true);
1272 static bool trans_lf_sfge_s(DisasContext
*dc
, arg_ab
*a
)
1274 return do_fpcmp(dc
, a
, gen_helper_float_le_s
, false, true);
1277 static bool trans_lf_sflt_s(DisasContext
*dc
, arg_ab
*a
)
1279 return do_fpcmp(dc
, a
, gen_helper_float_lt_s
, false, false);
1282 static bool trans_lf_sfle_s(DisasContext
*dc
, arg_ab
*a
)
1284 return do_fpcmp(dc
, a
, gen_helper_float_le_s
, false, false);
1287 static bool trans_lf_sfueq_s(DisasContext
*dc
, arg_ab
*a
)
1289 if (!check_v1_3(dc
)) {
1292 return do_fpcmp(dc
, a
, gen_helper_float_ueq_s
, false, false);
1295 static bool trans_lf_sfult_s(DisasContext
*dc
, arg_ab
*a
)
1297 if (!check_v1_3(dc
)) {
1300 return do_fpcmp(dc
, a
, gen_helper_float_ult_s
, false, false);
1303 static bool trans_lf_sfugt_s(DisasContext
*dc
, arg_ab
*a
)
1305 if (!check_v1_3(dc
)) {
1308 return do_fpcmp(dc
, a
, gen_helper_float_ult_s
, false, true);
1311 static bool trans_lf_sfule_s(DisasContext
*dc
, arg_ab
*a
)
1313 if (!check_v1_3(dc
)) {
1316 return do_fpcmp(dc
, a
, gen_helper_float_ule_s
, false, false);
1319 static bool trans_lf_sfuge_s(DisasContext
*dc
, arg_ab
*a
)
1321 if (!check_v1_3(dc
)) {
1324 return do_fpcmp(dc
, a
, gen_helper_float_ule_s
, false, true);
1327 static bool trans_lf_sfun_s(DisasContext
*dc
, arg_ab
*a
)
1329 if (!check_v1_3(dc
)) {
1332 return do_fpcmp(dc
, a
, gen_helper_float_un_s
, false, false);
1335 static bool check_pair(DisasContext
*dc
, int r
, int p
)
1337 return r
+ 1 + p
< 32;
1340 static void load_pair(DisasContext
*dc
, TCGv_i64 t
, int r
, int p
)
1342 tcg_gen_concat_i32_i64(t
, cpu_R(dc
, r
+ 1 + p
), cpu_R(dc
, r
));
1345 static void save_pair(DisasContext
*dc
, TCGv_i64 t
, int r
, int p
)
1347 tcg_gen_extr_i64_i32(cpu_R(dc
, r
+ 1 + p
), cpu_R(dc
, r
), t
);
1350 static bool do_dp3(DisasContext
*dc
, arg_dab_pair
*a
,
1351 void (*fn
)(TCGv_i64
, TCGv_env
, TCGv_i64
, TCGv_i64
))
1355 if (!check_of64a32s(dc
) ||
1356 !check_pair(dc
, a
->a
, a
->ap
) ||
1357 !check_pair(dc
, a
->b
, a
->bp
) ||
1358 !check_pair(dc
, a
->d
, a
->dp
)) {
1361 check_r0_write(dc
, a
->d
);
1363 t0
= tcg_temp_new_i64();
1364 t1
= tcg_temp_new_i64();
1365 load_pair(dc
, t0
, a
->a
, a
->ap
);
1366 load_pair(dc
, t1
, a
->b
, a
->bp
);
1367 fn(t0
, cpu_env
, t0
, t1
);
1368 save_pair(dc
, t0
, a
->d
, a
->dp
);
1369 tcg_temp_free_i64(t0
);
1370 tcg_temp_free_i64(t1
);
1372 gen_helper_update_fpcsr(cpu_env
);
1376 static bool do_dp2(DisasContext
*dc
, arg_da_pair
*a
,
1377 void (*fn
)(TCGv_i64
, TCGv_env
, TCGv_i64
))
1381 if (!check_of64a32s(dc
) ||
1382 !check_pair(dc
, a
->a
, a
->ap
) ||
1383 !check_pair(dc
, a
->d
, a
->dp
)) {
1386 check_r0_write(dc
, a
->d
);
1388 t0
= tcg_temp_new_i64();
1389 load_pair(dc
, t0
, a
->a
, a
->ap
);
1390 fn(t0
, cpu_env
, t0
);
1391 save_pair(dc
, t0
, a
->d
, a
->dp
);
1392 tcg_temp_free_i64(t0
);
1394 gen_helper_update_fpcsr(cpu_env
);
1398 static bool do_dpcmp(DisasContext
*dc
, arg_ab_pair
*a
,
1399 void (*fn
)(TCGv
, TCGv_env
, TCGv_i64
, TCGv_i64
),
1400 bool inv
, bool swap
)
1404 if (!check_of64a32s(dc
) ||
1405 !check_pair(dc
, a
->a
, a
->ap
) ||
1406 !check_pair(dc
, a
->b
, a
->bp
)) {
1410 t0
= tcg_temp_new_i64();
1411 t1
= tcg_temp_new_i64();
1412 load_pair(dc
, t0
, a
->a
, a
->ap
);
1413 load_pair(dc
, t1
, a
->b
, a
->bp
);
1415 fn(cpu_sr_f
, cpu_env
, t1
, t0
);
1417 fn(cpu_sr_f
, cpu_env
, t0
, t1
);
1419 tcg_temp_free_i64(t0
);
1420 tcg_temp_free_i64(t1
);
1423 tcg_gen_xori_tl(cpu_sr_f
, cpu_sr_f
, 1);
1425 gen_helper_update_fpcsr(cpu_env
);
1429 static bool trans_lf_add_d(DisasContext
*dc
, arg_dab_pair
*a
)
1431 return do_dp3(dc
, a
, gen_helper_float_add_d
);
1434 static bool trans_lf_sub_d(DisasContext
*dc
, arg_dab_pair
*a
)
1436 return do_dp3(dc
, a
, gen_helper_float_sub_d
);
1439 static bool trans_lf_mul_d(DisasContext
*dc
, arg_dab_pair
*a
)
1441 return do_dp3(dc
, a
, gen_helper_float_mul_d
);
1444 static bool trans_lf_div_d(DisasContext
*dc
, arg_dab_pair
*a
)
1446 return do_dp3(dc
, a
, gen_helper_float_div_d
);
1449 static bool trans_lf_rem_d(DisasContext
*dc
, arg_dab_pair
*a
)
1451 return do_dp3(dc
, a
, gen_helper_float_rem_d
);
1454 static bool trans_lf_itof_d(DisasContext
*dc
, arg_da_pair
*a
)
1456 return do_dp2(dc
, a
, gen_helper_itofd
);
1459 static bool trans_lf_ftoi_d(DisasContext
*dc
, arg_da_pair
*a
)
1461 return do_dp2(dc
, a
, gen_helper_ftoid
);
1464 static bool trans_lf_stod_d(DisasContext
*dc
, arg_lf_stod_d
*a
)
1468 if (!check_of64a32s(dc
) ||
1469 !check_pair(dc
, a
->d
, a
->dp
)) {
1472 check_r0_write(dc
, a
->d
);
1474 t0
= tcg_temp_new_i64();
1475 gen_helper_stod(t0
, cpu_env
, cpu_R(dc
, a
->a
));
1476 save_pair(dc
, t0
, a
->d
, a
->dp
);
1477 tcg_temp_free_i64(t0
);
1479 gen_helper_update_fpcsr(cpu_env
);
1483 static bool trans_lf_dtos_d(DisasContext
*dc
, arg_lf_dtos_d
*a
)
1487 if (!check_of64a32s(dc
) ||
1488 !check_pair(dc
, a
->a
, a
->ap
)) {
1491 check_r0_write(dc
, a
->d
);
1493 t0
= tcg_temp_new_i64();
1494 load_pair(dc
, t0
, a
->a
, a
->ap
);
1495 gen_helper_dtos(cpu_R(dc
, a
->d
), cpu_env
, t0
);
1496 tcg_temp_free_i64(t0
);
1498 gen_helper_update_fpcsr(cpu_env
);
1502 static bool trans_lf_madd_d(DisasContext
*dc
, arg_dab_pair
*a
)
1504 TCGv_i64 t0
, t1
, t2
;
1506 if (!check_of64a32s(dc
) ||
1507 !check_pair(dc
, a
->a
, a
->ap
) ||
1508 !check_pair(dc
, a
->b
, a
->bp
) ||
1509 !check_pair(dc
, a
->d
, a
->dp
)) {
1512 check_r0_write(dc
, a
->d
);
1514 t0
= tcg_temp_new_i64();
1515 t1
= tcg_temp_new_i64();
1516 t2
= tcg_temp_new_i64();
1517 load_pair(dc
, t0
, a
->d
, a
->dp
);
1518 load_pair(dc
, t1
, a
->a
, a
->ap
);
1519 load_pair(dc
, t2
, a
->b
, a
->bp
);
1520 gen_helper_float_madd_d(t0
, cpu_env
, t0
, t1
, t2
);
1521 save_pair(dc
, t0
, a
->d
, a
->dp
);
1522 tcg_temp_free_i64(t0
);
1523 tcg_temp_free_i64(t1
);
1524 tcg_temp_free_i64(t2
);
1526 gen_helper_update_fpcsr(cpu_env
);
1530 static bool trans_lf_sfeq_d(DisasContext
*dc
, arg_ab_pair
*a
)
1532 return do_dpcmp(dc
, a
, gen_helper_float_eq_d
, false, false);
1535 static bool trans_lf_sfne_d(DisasContext
*dc
, arg_ab_pair
*a
)
1537 return do_dpcmp(dc
, a
, gen_helper_float_eq_d
, true, false);
1540 static bool trans_lf_sfgt_d(DisasContext
*dc
, arg_ab_pair
*a
)
1542 return do_dpcmp(dc
, a
, gen_helper_float_lt_d
, false, true);
1545 static bool trans_lf_sfge_d(DisasContext
*dc
, arg_ab_pair
*a
)
1547 return do_dpcmp(dc
, a
, gen_helper_float_le_d
, false, true);
1550 static bool trans_lf_sflt_d(DisasContext
*dc
, arg_ab_pair
*a
)
1552 return do_dpcmp(dc
, a
, gen_helper_float_lt_d
, false, false);
1555 static bool trans_lf_sfle_d(DisasContext
*dc
, arg_ab_pair
*a
)
1557 return do_dpcmp(dc
, a
, gen_helper_float_le_d
, false, false);
1560 static bool trans_lf_sfueq_d(DisasContext
*dc
, arg_ab_pair
*a
)
1562 return do_dpcmp(dc
, a
, gen_helper_float_ueq_d
, false, false);
1565 static bool trans_lf_sfule_d(DisasContext
*dc
, arg_ab_pair
*a
)
1567 return do_dpcmp(dc
, a
, gen_helper_float_ule_d
, false, false);
1570 static bool trans_lf_sfuge_d(DisasContext
*dc
, arg_ab_pair
*a
)
1572 return do_dpcmp(dc
, a
, gen_helper_float_ule_d
, false, true);
1575 static bool trans_lf_sfult_d(DisasContext
*dc
, arg_ab_pair
*a
)
1577 return do_dpcmp(dc
, a
, gen_helper_float_ult_d
, false, false);
1580 static bool trans_lf_sfugt_d(DisasContext
*dc
, arg_ab_pair
*a
)
1582 return do_dpcmp(dc
, a
, gen_helper_float_ult_d
, false, true);
1585 static bool trans_lf_sfun_d(DisasContext
*dc
, arg_ab_pair
*a
)
1587 return do_dpcmp(dc
, a
, gen_helper_float_un_d
, false, false);
1590 static void openrisc_tr_init_disas_context(DisasContextBase
*dcb
, CPUState
*cs
)
1592 DisasContext
*dc
= container_of(dcb
, DisasContext
, base
);
1593 CPUOpenRISCState
*env
= cs
->env_ptr
;
1596 dc
->mem_idx
= cpu_mmu_index(env
, false);
1597 dc
->tb_flags
= dc
->base
.tb
->flags
;
1598 dc
->delayed_branch
= (dc
->tb_flags
& TB_FLAGS_DFLAG
) != 0;
1599 dc
->cpucfgr
= env
->cpucfgr
;
1601 dc
->jmp_pc_imm
= -1;
1603 bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
1604 dc
->base
.max_insns
= MIN(dc
->base
.max_insns
, bound
);
1607 static void openrisc_tr_tb_start(DisasContextBase
*db
, CPUState
*cs
)
1609 DisasContext
*dc
= container_of(db
, DisasContext
, base
);
1611 /* Allow the TCG optimizer to see that R0 == 0,
1612 when it's true, which is the common case. */
1613 if (dc
->tb_flags
& TB_FLAGS_R0_0
) {
1614 dc
->R0
= tcg_const_tl(0);
1616 dc
->R0
= cpu_regs
[0];
1620 static void openrisc_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cs
)
1622 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
1624 tcg_gen_insn_start(dc
->base
.pc_next
, (dc
->delayed_branch
? 1 : 0)
1625 | (dc
->base
.num_insns
> 1 ? 2 : 0));
1628 static bool openrisc_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cs
,
1629 const CPUBreakpoint
*bp
)
1631 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
1633 tcg_gen_movi_tl(cpu_pc
, dc
->base
.pc_next
);
1634 gen_exception(dc
, EXCP_DEBUG
);
1635 dc
->base
.is_jmp
= DISAS_NORETURN
;
1636 /* The address covered by the breakpoint must be included in
1637 [tb->pc, tb->pc + tb->size) in order to for it to be
1638 properly cleared -- thus we increment the PC here so that
1639 the logic setting tb->size below does the right thing. */
1640 dc
->base
.pc_next
+= 4;
1644 static void openrisc_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cs
)
1646 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
1647 OpenRISCCPU
*cpu
= OPENRISC_CPU(cs
);
1648 uint32_t insn
= translator_ldl(&cpu
->env
, dc
->base
.pc_next
);
1650 if (!decode(dc
, insn
)) {
1651 gen_illegal_exception(dc
);
1653 dc
->base
.pc_next
+= 4;
1655 /* When exiting the delay slot normally, exit via jmp_pc.
1656 * For DISAS_NORETURN, we have raised an exception and already exited.
1657 * For DISAS_EXIT, we found l.rfe in a delay slot. There's nothing
1658 * in the manual saying this is illegal, but it surely it should.
1659 * At least or1ksim overrides pcnext and ignores the branch.
1661 if (dc
->delayed_branch
1662 && --dc
->delayed_branch
== 0
1663 && dc
->base
.is_jmp
== DISAS_NEXT
) {
1664 dc
->base
.is_jmp
= DISAS_JUMP
;
1668 static void openrisc_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cs
)
1670 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
1671 target_ulong jmp_dest
;
1673 /* If we have already exited the TB, nothing following has effect. */
1674 if (dc
->base
.is_jmp
== DISAS_NORETURN
) {
1678 /* Adjust the delayed branch state for the next TB. */
1679 if ((dc
->tb_flags
& TB_FLAGS_DFLAG
? 1 : 0) != (dc
->delayed_branch
!= 0)) {
1680 tcg_gen_movi_i32(cpu_dflag
, dc
->delayed_branch
!= 0);
1683 /* For DISAS_TOO_MANY, jump to the next insn. */
1684 jmp_dest
= dc
->base
.pc_next
;
1685 tcg_gen_movi_tl(cpu_ppc
, jmp_dest
- 4);
1687 switch (dc
->base
.is_jmp
) {
1689 jmp_dest
= dc
->jmp_pc_imm
;
1690 if (jmp_dest
== -1) {
1691 /* The jump destination is indirect/computed; use jmp_pc. */
1692 tcg_gen_mov_tl(cpu_pc
, jmp_pc
);
1693 tcg_gen_discard_tl(jmp_pc
);
1694 if (unlikely(dc
->base
.singlestep_enabled
)) {
1695 gen_exception(dc
, EXCP_DEBUG
);
1697 tcg_gen_lookup_and_goto_ptr();
1701 /* The jump destination is direct; use jmp_pc_imm.
1702 However, we will have stored into jmp_pc as well;
1703 we know now that it wasn't needed. */
1704 tcg_gen_discard_tl(jmp_pc
);
1707 case DISAS_TOO_MANY
:
1708 if (unlikely(dc
->base
.singlestep_enabled
)) {
1709 tcg_gen_movi_tl(cpu_pc
, jmp_dest
);
1710 gen_exception(dc
, EXCP_DEBUG
);
1711 } else if ((dc
->base
.pc_first
^ jmp_dest
) & TARGET_PAGE_MASK
) {
1712 tcg_gen_movi_tl(cpu_pc
, jmp_dest
);
1713 tcg_gen_lookup_and_goto_ptr();
1716 tcg_gen_movi_tl(cpu_pc
, jmp_dest
);
1717 tcg_gen_exit_tb(dc
->base
.tb
, 0);
1722 if (unlikely(dc
->base
.singlestep_enabled
)) {
1723 gen_exception(dc
, EXCP_DEBUG
);
1725 tcg_gen_exit_tb(NULL
, 0);
1729 g_assert_not_reached();
1733 static void openrisc_tr_disas_log(const DisasContextBase
*dcbase
, CPUState
*cs
)
1735 DisasContext
*s
= container_of(dcbase
, DisasContext
, base
);
1737 qemu_log("IN: %s\n", lookup_symbol(s
->base
.pc_first
));
1738 log_target_disas(cs
, s
->base
.pc_first
, s
->base
.tb
->size
);
1741 static const TranslatorOps openrisc_tr_ops
= {
1742 .init_disas_context
= openrisc_tr_init_disas_context
,
1743 .tb_start
= openrisc_tr_tb_start
,
1744 .insn_start
= openrisc_tr_insn_start
,
1745 .breakpoint_check
= openrisc_tr_breakpoint_check
,
1746 .translate_insn
= openrisc_tr_translate_insn
,
1747 .tb_stop
= openrisc_tr_tb_stop
,
1748 .disas_log
= openrisc_tr_disas_log
,
1751 void gen_intermediate_code(CPUState
*cs
, TranslationBlock
*tb
, int max_insns
)
1755 translator_loop(&openrisc_tr_ops
, &ctx
.base
, cs
, tb
, max_insns
);
1758 void openrisc_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
1760 OpenRISCCPU
*cpu
= OPENRISC_CPU(cs
);
1761 CPUOpenRISCState
*env
= &cpu
->env
;
1764 qemu_fprintf(f
, "PC=%08x\n", env
->pc
);
1765 for (i
= 0; i
< 32; ++i
) {
1766 qemu_fprintf(f
, "R%02d=%08x%c", i
, cpu_get_gpr(env
, i
),
1767 (i
% 4) == 3 ? '\n' : ' ');
1771 void restore_state_to_opc(CPUOpenRISCState
*env
, TranslationBlock
*tb
,
1775 env
->dflag
= data
[1] & 1;
1777 env
->ppc
= env
->pc
- 4;