target-arm/kvm64.c

   1 /*
   2  * ARM implementation of KVM hooks, 64 bit specific code
   3  *
   4  * Copyright Mian-M. Hamayun 2013, Virtual Open Systems
   5  *
   6  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   7  * See the COPYING file in the top-level directory.
   8  *
   9  */
  10
  11 #include <stdio.h>
  12 #include <sys/types.h>
  13 #include <sys/ioctl.h>
  14 #include <sys/mman.h>
  15
  16 #include <linux/kvm.h>
  17
  18 #include "qemu-common.h"
  19 #include "qemu/timer.h"
  20 #include "sysemu/sysemu.h"
  21 #include "sysemu/kvm.h"
  22 #include "kvm_arm.h"
  23 #include "cpu.h"
  24 #include "internals.h"
  25 #include "hw/arm/arm.h"
  26
  27 static inline void set_feature(uint64_t *features, int feature)
  28 {
  29     *features |= 1ULL << feature;
  30 }
  31
  32 bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc)
  33 {
  34     /* Identify the feature bits corresponding to the host CPU, and
  35      * fill out the ARMHostCPUClass fields accordingly. To do this
  36      * we have to create a scratch VM, create a single CPU inside it,
  37      * and then query that CPU for the relevant ID registers.
  38      * For AArch64 we currently don't care about ID registers at
  39      * all; we just want to know the CPU type.
  40      */
  41     int fdarray[3];
  42     uint64_t features = 0;
  43     /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
  44      * we know these will only support creating one kind of guest CPU,
  45      * which is its preferred CPU type. Fortunately these old kernels
  46      * support only a very limited number of CPUs.
  47      */
  48     static const uint32_t cpus_to_try[] = {
  49         KVM_ARM_TARGET_AEM_V8,
  50         KVM_ARM_TARGET_FOUNDATION_V8,
  51         KVM_ARM_TARGET_CORTEX_A57,
  52         QEMU_KVM_ARM_TARGET_NONE
  53     };
  54     struct kvm_vcpu_init init;
  55
  56     if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
  57         return false;
  58     }
  59
  60     ahcc->target = init.target;
  61     ahcc->dtb_compatible = "arm,arm-v8";
  62
  63     kvm_arm_destroy_scratch_host_vcpu(fdarray);
  64
  65    /* We can assume any KVM supporting CPU is at least a v8
  66      * with VFPv4+Neon; this in turn implies most of the other
  67      * feature bits.
  68      */
  69     set_feature(&features, ARM_FEATURE_V8);
  70     set_feature(&features, ARM_FEATURE_VFP4);
  71     set_feature(&features, ARM_FEATURE_NEON);
  72     set_feature(&features, ARM_FEATURE_AARCH64);
  73
  74     ahcc->features = features;
  75
  76     return true;
  77 }
  78
  79 int kvm_arch_init_vcpu(CPUState *cs)
  80 {
  81     int ret;
  82     ARMCPU *cpu = ARM_CPU(cs);
  83
  84     if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE ||
  85         !object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) {
  86         fprintf(stderr, "KVM is not supported for this guest CPU type\n");
  87         return -EINVAL;
  88     }
  89
  90     /* Determine init features for this CPU */
  91     memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features));
  92     if (cpu->start_powered_off) {
  93         cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_POWER_OFF;
  94     }
  95     if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PSCI_0_2)) {
  96         cpu->psci_version = 2;
  97         cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2;
  98     }
  99     if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 100         cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_EL1_32BIT;
 101     }
 102
 103     /* Do KVM_ARM_VCPU_INIT ioctl */
 104     ret = kvm_arm_vcpu_init(cs);
 105     if (ret) {
 106         return ret;
 107     }
 108
 109     return kvm_arm_init_cpreg_list(cpu);
 110 }
 111
 112 bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx)
 113 {
 114     /* Return true if the regidx is a register we should synchronize
 115      * via the cpreg_tuples array (ie is not a core reg we sync by
 116      * hand in kvm_arch_get/put_registers())
 117      */
 118     switch (regidx & KVM_REG_ARM_COPROC_MASK) {
 119     case KVM_REG_ARM_CORE:
 120         return false;
 121     default:
 122         return true;
 123     }
 124 }
 125
 126 #define AARCH64_CORE_REG(x)   (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
 127                  KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
 128
 129 int kvm_arch_put_registers(CPUState *cs, int level)
 130 {
 131     struct kvm_one_reg reg;
 132     uint64_t val;
 133     int i;
 134     int ret;
 135
 136     ARMCPU *cpu = ARM_CPU(cs);
 137     CPUARMState *env = &cpu->env;
 138
 139     /* If we are in AArch32 mode then we need to copy the AArch32 regs to the
 140      * AArch64 registers before pushing them out to 64-bit KVM.
 141      */
 142     if (!is_a64(env)) {
 143         aarch64_sync_32_to_64(env);
 144     }
 145
 146     for (i = 0; i < 31; i++) {
 147         reg.id = AARCH64_CORE_REG(regs.regs[i]);
 148         reg.addr = (uintptr_t) &env->xregs[i];
 149         ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 150         if (ret) {
 151             return ret;
 152         }
 153     }
 154
 155     /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the
 156      * QEMU side we keep the current SP in xregs[31] as well.
 157      */
 158     aarch64_save_sp(env, 1);
 159
 160     reg.id = AARCH64_CORE_REG(regs.sp);
 161     reg.addr = (uintptr_t) &env->sp_el[0];
 162     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 163     if (ret) {
 164         return ret;
 165     }
 166
 167     reg.id = AARCH64_CORE_REG(sp_el1);
 168     reg.addr = (uintptr_t) &env->sp_el[1];
 169     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 170     if (ret) {
 171         return ret;
 172     }
 173
 174     /* Note that KVM thinks pstate is 64 bit but we use a uint32_t */
 175     if (is_a64(env)) {
 176         val = pstate_read(env);
 177     } else {
 178         val = cpsr_read(env);
 179     }
 180     reg.id = AARCH64_CORE_REG(regs.pstate);
 181     reg.addr = (uintptr_t) &val;
 182     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 183     if (ret) {
 184         return ret;
 185     }
 186
 187     reg.id = AARCH64_CORE_REG(regs.pc);
 188     reg.addr = (uintptr_t) &env->pc;
 189     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 190     if (ret) {
 191         return ret;
 192     }
 193
 194     reg.id = AARCH64_CORE_REG(elr_el1);
 195     reg.addr = (uintptr_t) &env->elr_el[1];
 196     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 197     if (ret) {
 198         return ret;
 199     }
 200
 201     for (i = 0; i < KVM_NR_SPSR; i++) {
 202         reg.id = AARCH64_CORE_REG(spsr[i]);
 203         reg.addr = (uintptr_t) &env->banked_spsr[i - 1];
 204         ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 205         if (ret) {
 206             return ret;
 207         }
 208     }
 209
 210     if (!write_list_to_kvmstate(cpu)) {
 211         return EINVAL;
 212     }
 213
 214     /* TODO:
 215      * FP state
 216      */
 217     return ret;
 218 }
 219
 220 int kvm_arch_get_registers(CPUState *cs)
 221 {
 222     struct kvm_one_reg reg;
 223     uint64_t val;
 224     int i;
 225     int ret;
 226
 227     ARMCPU *cpu = ARM_CPU(cs);
 228     CPUARMState *env = &cpu->env;
 229
 230     for (i = 0; i < 31; i++) {
 231         reg.id = AARCH64_CORE_REG(regs.regs[i]);
 232         reg.addr = (uintptr_t) &env->xregs[i];
 233         ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 234         if (ret) {
 235             return ret;
 236         }
 237     }
 238
 239     reg.id = AARCH64_CORE_REG(regs.sp);
 240     reg.addr = (uintptr_t) &env->sp_el[0];
 241     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 242     if (ret) {
 243         return ret;
 244     }
 245
 246     reg.id = AARCH64_CORE_REG(sp_el1);
 247     reg.addr = (uintptr_t) &env->sp_el[1];
 248     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 249     if (ret) {
 250         return ret;
 251     }
 252
 253     reg.id = AARCH64_CORE_REG(regs.pstate);
 254     reg.addr = (uintptr_t) &val;
 255     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 256     if (ret) {
 257         return ret;
 258     }
 259
 260     env->aarch64 = ((val & PSTATE_nRW) == 0);
 261     if (is_a64(env)) {
 262         pstate_write(env, val);
 263     } else {
 264         env->uncached_cpsr = val & CPSR_M;
 265         cpsr_write(env, val, 0xffffffff);
 266     }
 267
 268     /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the
 269      * QEMU side we keep the current SP in xregs[31] as well.
 270      */
 271     aarch64_restore_sp(env, 1);
 272
 273     reg.id = AARCH64_CORE_REG(regs.pc);
 274     reg.addr = (uintptr_t) &env->pc;
 275     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 276     if (ret) {
 277         return ret;
 278     }
 279
 280     /* If we are in AArch32 mode then we need to sync the AArch32 regs with the
 281      * incoming AArch64 regs received from 64-bit KVM.
 282      * We must perform this after all of the registers have been acquired from
 283      * the kernel.
 284      */
 285     if (!is_a64(env)) {
 286         aarch64_sync_64_to_32(env);
 287     }
 288
 289     reg.id = AARCH64_CORE_REG(elr_el1);
 290     reg.addr = (uintptr_t) &env->elr_el[1];
 291     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 292     if (ret) {
 293         return ret;
 294     }
 295
 296     for (i = 0; i < KVM_NR_SPSR; i++) {
 297         reg.id = AARCH64_CORE_REG(spsr[i]);
 298         reg.addr = (uintptr_t) &env->banked_spsr[i - 1];
 299         ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 300         if (ret) {
 301             return ret;
 302         }
 303     }
 304
 305     if (!write_kvmstate_to_list(cpu)) {
 306         return EINVAL;
 307     }
 308     /* Note that it's OK to have registers which aren't in CPUState,
 309      * so we can ignore a failure return here.
 310      */
 311     write_list_to_cpustate(cpu);
 312
 313     /* TODO: other registers */
 314     return ret;
 315 }