target-arm/kvm32.c

   1 /*
   2  * ARM implementation of KVM hooks, 32 bit specific code.
   3  *
   4  * Copyright Christoffer Dall 2009-2010
   5  *
   6  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   7  * See the COPYING file in the top-level directory.
   8  *
   9  */
  10
  11 #include <stdio.h>
  12 #include <sys/types.h>
  13 #include <sys/ioctl.h>
  14 #include <sys/mman.h>
  15
  16 #include <linux/kvm.h>
  17
  18 #include "qemu-common.h"
  19 #include "qemu/timer.h"
  20 #include "sysemu/sysemu.h"
  21 #include "sysemu/kvm.h"
  22 #include "kvm_arm.h"
  23 #include "cpu.h"
  24 #include "internals.h"
  25 #include "hw/arm/arm.h"
  26
  27 static inline void set_feature(uint64_t *features, int feature)
  28 {
  29     *features |= 1ULL << feature;
  30 }
  31
  32 bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc)
  33 {
  34     /* Identify the feature bits corresponding to the host CPU, and
  35      * fill out the ARMHostCPUClass fields accordingly. To do this
  36      * we have to create a scratch VM, create a single CPU inside it,
  37      * and then query that CPU for the relevant ID registers.
  38      */
  39     int i, ret, fdarray[3];
  40     uint32_t midr, id_pfr0, id_isar0, mvfr1;
  41     uint64_t features = 0;
  42     /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
  43      * we know these will only support creating one kind of guest CPU,
  44      * which is its preferred CPU type.
  45      */
  46     static const uint32_t cpus_to_try[] = {
  47         QEMU_KVM_ARM_TARGET_CORTEX_A15,
  48         QEMU_KVM_ARM_TARGET_NONE
  49     };
  50     struct kvm_vcpu_init init;
  51     struct kvm_one_reg idregs[] = {
  52         {
  53             .id = KVM_REG_ARM | KVM_REG_SIZE_U32
  54             | ENCODE_CP_REG(15, 0, 0, 0, 0, 0, 0),
  55             .addr = (uintptr_t)&midr,
  56         },
  57         {
  58             .id = KVM_REG_ARM | KVM_REG_SIZE_U32
  59             | ENCODE_CP_REG(15, 0, 0, 0, 1, 0, 0),
  60             .addr = (uintptr_t)&id_pfr0,
  61         },
  62         {
  63             .id = KVM_REG_ARM | KVM_REG_SIZE_U32
  64             | ENCODE_CP_REG(15, 0, 0, 0, 2, 0, 0),
  65             .addr = (uintptr_t)&id_isar0,
  66         },
  67         {
  68             .id = KVM_REG_ARM | KVM_REG_SIZE_U32
  69             | KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1,
  70             .addr = (uintptr_t)&mvfr1,
  71         },
  72     };
  73
  74     if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
  75         return false;
  76     }
  77
  78     ahcc->target = init.target;
  79
  80     /* This is not strictly blessed by the device tree binding docs yet,
  81      * but in practice the kernel does not care about this string so
  82      * there is no point maintaining an KVM_ARM_TARGET_* -> string table.
  83      */
  84     ahcc->dtb_compatible = "arm,arm-v7";
  85
  86     for (i = 0; i < ARRAY_SIZE(idregs); i++) {
  87         ret = ioctl(fdarray[2], KVM_GET_ONE_REG, &idregs[i]);
  88         if (ret) {
  89             break;
  90         }
  91     }
  92
  93     kvm_arm_destroy_scratch_host_vcpu(fdarray);
  94
  95     if (ret) {
  96         return false;
  97     }
  98
  99     /* Now we've retrieved all the register information we can
 100      * set the feature bits based on the ID register fields.
 101      * We can assume any KVM supporting CPU is at least a v7
 102      * with VFPv3, LPAE and the generic timers; this in turn implies
 103      * most of the other feature bits, but a few must be tested.
 104      */
 105     set_feature(&features, ARM_FEATURE_V7);
 106     set_feature(&features, ARM_FEATURE_VFP3);
 107     set_feature(&features, ARM_FEATURE_LPAE);
 108     set_feature(&features, ARM_FEATURE_GENERIC_TIMER);
 109
 110     switch (extract32(id_isar0, 24, 4)) {
 111     case 1:
 112         set_feature(&features, ARM_FEATURE_THUMB_DIV);
 113         break;
 114     case 2:
 115         set_feature(&features, ARM_FEATURE_ARM_DIV);
 116         set_feature(&features, ARM_FEATURE_THUMB_DIV);
 117         break;
 118     default:
 119         break;
 120     }
 121
 122     if (extract32(id_pfr0, 12, 4) == 1) {
 123         set_feature(&features, ARM_FEATURE_THUMB2EE);
 124     }
 125     if (extract32(mvfr1, 20, 4) == 1) {
 126         set_feature(&features, ARM_FEATURE_VFP_FP16);
 127     }
 128     if (extract32(mvfr1, 12, 4) == 1) {
 129         set_feature(&features, ARM_FEATURE_NEON);
 130     }
 131     if (extract32(mvfr1, 28, 4) == 1) {
 132         /* FMAC support implies VFPv4 */
 133         set_feature(&features, ARM_FEATURE_VFP4);
 134     }
 135
 136     ahcc->features = features;
 137
 138     return true;
 139 }
 140
 141 bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx)
 142 {
 143     /* Return true if the regidx is a register we should synchronize
 144      * via the cpreg_tuples array (ie is not a core reg we sync by
 145      * hand in kvm_arch_get/put_registers())
 146      */
 147     switch (regidx & KVM_REG_ARM_COPROC_MASK) {
 148     case KVM_REG_ARM_CORE:
 149     case KVM_REG_ARM_VFP:
 150         return false;
 151     default:
 152         return true;
 153     }
 154 }
 155
 156 int kvm_arch_init_vcpu(CPUState *cs)
 157 {
 158     int ret;
 159     uint64_t v;
 160     struct kvm_one_reg r;
 161     ARMCPU *cpu = ARM_CPU(cs);
 162
 163     if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE) {
 164         fprintf(stderr, "KVM is not supported for this guest CPU type\n");
 165         return -EINVAL;
 166     }
 167
 168     /* Determine init features for this CPU */
 169     memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features));
 170     if (cpu->start_powered_off) {
 171         cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_POWER_OFF;
 172     }
 173     if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PSCI_0_2)) {
 174         cpu->psci_version = 2;
 175         cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2;
 176     }
 177
 178     /* Do KVM_ARM_VCPU_INIT ioctl */
 179     ret = kvm_arm_vcpu_init(cs);
 180     if (ret) {
 181         return ret;
 182     }
 183
 184     /* Query the kernel to make sure it supports 32 VFP
 185      * registers: QEMU's "cortex-a15" CPU is always a
 186      * VFP-D32 core. The simplest way to do this is just
 187      * to attempt to read register d31.
 188      */
 189     r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP | 31;
 190     r.addr = (uintptr_t)(&v);
 191     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 192     if (ret == -ENOENT) {
 193         return -EINVAL;
 194     }
 195
 196     return kvm_arm_init_cpreg_list(cpu);
 197 }
 198
 199 typedef struct Reg {
 200     uint64_t id;
 201     int offset;
 202 } Reg;
 203
 204 #define COREREG(KERNELNAME, QEMUFIELD)                       \
 205     {                                                        \
 206         KVM_REG_ARM | KVM_REG_SIZE_U32 |                     \
 207         KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(KERNELNAME), \
 208         offsetof(CPUARMState, QEMUFIELD)                     \
 209     }
 210
 211 #define VFPSYSREG(R)                                       \
 212     {                                                      \
 213         KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | \
 214         KVM_REG_ARM_VFP_##R,                               \
 215         offsetof(CPUARMState, vfp.xregs[ARM_VFP_##R])      \
 216     }
 217
 218 /* Like COREREG, but handle fields which are in a uint64_t in CPUARMState. */
 219 #define COREREG64(KERNELNAME, QEMUFIELD)                     \
 220     {                                                        \
 221         KVM_REG_ARM | KVM_REG_SIZE_U32 |                     \
 222         KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(KERNELNAME), \
 223         offsetoflow32(CPUARMState, QEMUFIELD)                \
 224     }
 225
 226 static const Reg regs[] = {
 227     /* R0_usr .. R14_usr */
 228     COREREG(usr_regs.uregs[0], regs[0]),
 229     COREREG(usr_regs.uregs[1], regs[1]),
 230     COREREG(usr_regs.uregs[2], regs[2]),
 231     COREREG(usr_regs.uregs[3], regs[3]),
 232     COREREG(usr_regs.uregs[4], regs[4]),
 233     COREREG(usr_regs.uregs[5], regs[5]),
 234     COREREG(usr_regs.uregs[6], regs[6]),
 235     COREREG(usr_regs.uregs[7], regs[7]),
 236     COREREG(usr_regs.uregs[8], usr_regs[0]),
 237     COREREG(usr_regs.uregs[9], usr_regs[1]),
 238     COREREG(usr_regs.uregs[10], usr_regs[2]),
 239     COREREG(usr_regs.uregs[11], usr_regs[3]),
 240     COREREG(usr_regs.uregs[12], usr_regs[4]),
 241     COREREG(usr_regs.uregs[13], banked_r13[0]),
 242     COREREG(usr_regs.uregs[14], banked_r14[0]),
 243     /* R13, R14, SPSR for SVC, ABT, UND, IRQ banks */
 244     COREREG(svc_regs[0], banked_r13[1]),
 245     COREREG(svc_regs[1], banked_r14[1]),
 246     COREREG64(svc_regs[2], banked_spsr[1]),
 247     COREREG(abt_regs[0], banked_r13[2]),
 248     COREREG(abt_regs[1], banked_r14[2]),
 249     COREREG64(abt_regs[2], banked_spsr[2]),
 250     COREREG(und_regs[0], banked_r13[3]),
 251     COREREG(und_regs[1], banked_r14[3]),
 252     COREREG64(und_regs[2], banked_spsr[3]),
 253     COREREG(irq_regs[0], banked_r13[4]),
 254     COREREG(irq_regs[1], banked_r14[4]),
 255     COREREG64(irq_regs[2], banked_spsr[4]),
 256     /* R8_fiq .. R14_fiq and SPSR_fiq */
 257     COREREG(fiq_regs[0], fiq_regs[0]),
 258     COREREG(fiq_regs[1], fiq_regs[1]),
 259     COREREG(fiq_regs[2], fiq_regs[2]),
 260     COREREG(fiq_regs[3], fiq_regs[3]),
 261     COREREG(fiq_regs[4], fiq_regs[4]),
 262     COREREG(fiq_regs[5], banked_r13[5]),
 263     COREREG(fiq_regs[6], banked_r14[5]),
 264     COREREG64(fiq_regs[7], banked_spsr[5]),
 265     /* R15 */
 266     COREREG(usr_regs.uregs[15], regs[15]),
 267     /* VFP system registers */
 268     VFPSYSREG(FPSID),
 269     VFPSYSREG(MVFR1),
 270     VFPSYSREG(MVFR0),
 271     VFPSYSREG(FPEXC),
 272     VFPSYSREG(FPINST),
 273     VFPSYSREG(FPINST2),
 274 };
 275
 276 int kvm_arch_put_registers(CPUState *cs, int level)
 277 {
 278     ARMCPU *cpu = ARM_CPU(cs);
 279     CPUARMState *env = &cpu->env;
 280     struct kvm_one_reg r;
 281     int mode, bn;
 282     int ret, i;
 283     uint32_t cpsr, fpscr;
 284
 285     /* Make sure the banked regs are properly set */
 286     mode = env->uncached_cpsr & CPSR_M;
 287     bn = bank_number(mode);
 288     if (mode == ARM_CPU_MODE_FIQ) {
 289         memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
 290     } else {
 291         memcpy(env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
 292     }
 293     env->banked_r13[bn] = env->regs[13];
 294     env->banked_r14[bn] = env->regs[14];
 295     env->banked_spsr[bn] = env->spsr;
 296
 297     /* Now we can safely copy stuff down to the kernel */
 298     for (i = 0; i < ARRAY_SIZE(regs); i++) {
 299         r.id = regs[i].id;
 300         r.addr = (uintptr_t)(env) + regs[i].offset;
 301         ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 302         if (ret) {
 303             return ret;
 304         }
 305     }
 306
 307     /* Special cases which aren't a single CPUARMState field */
 308     cpsr = cpsr_read(env);
 309     r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 |
 310         KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr);
 311     r.addr = (uintptr_t)(&cpsr);
 312     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 313     if (ret) {
 314         return ret;
 315     }
 316
 317     /* VFP registers */
 318     r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
 319     for (i = 0; i < 32; i++) {
 320         r.addr = (uintptr_t)(&env->vfp.regs[i]);
 321         ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 322         if (ret) {
 323             return ret;
 324         }
 325         r.id++;
 326     }
 327
 328     r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP |
 329         KVM_REG_ARM_VFP_FPSCR;
 330     fpscr = vfp_get_fpscr(env);
 331     r.addr = (uintptr_t)&fpscr;
 332     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 333     if (ret) {
 334         return ret;
 335     }
 336
 337     /* Note that we do not call write_cpustate_to_list()
 338      * here, so we are only writing the tuple list back to
 339      * KVM. This is safe because nothing can change the
 340      * CPUARMState cp15 fields (in particular gdb accesses cannot)
 341      * and so there are no changes to sync. In fact syncing would
 342      * be wrong at this point: for a constant register where TCG and
 343      * KVM disagree about its value, the preceding write_list_to_cpustate()
 344      * would not have had any effect on the CPUARMState value (since the
 345      * register is read-only), and a write_cpustate_to_list() here would
 346      * then try to write the TCG value back into KVM -- this would either
 347      * fail or incorrectly change the value the guest sees.
 348      *
 349      * If we ever want to allow the user to modify cp15 registers via
 350      * the gdb stub, we would need to be more clever here (for instance
 351      * tracking the set of registers kvm_arch_get_registers() successfully
 352      * managed to update the CPUARMState with, and only allowing those
 353      * to be written back up into the kernel).
 354      */
 355     if (!write_list_to_kvmstate(cpu)) {
 356         return EINVAL;
 357     }
 358
 359     return ret;
 360 }
 361
 362 int kvm_arch_get_registers(CPUState *cs)
 363 {
 364     ARMCPU *cpu = ARM_CPU(cs);
 365     CPUARMState *env = &cpu->env;
 366     struct kvm_one_reg r;
 367     int mode, bn;
 368     int ret, i;
 369     uint32_t cpsr, fpscr;
 370
 371     for (i = 0; i < ARRAY_SIZE(regs); i++) {
 372         r.id = regs[i].id;
 373         r.addr = (uintptr_t)(env) + regs[i].offset;
 374         ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 375         if (ret) {
 376             return ret;
 377         }
 378     }
 379
 380     /* Special cases which aren't a single CPUARMState field */
 381     r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 |
 382         KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr);
 383     r.addr = (uintptr_t)(&cpsr);
 384     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 385     if (ret) {
 386         return ret;
 387     }
 388     cpsr_write(env, cpsr, 0xffffffff);
 389
 390     /* Make sure the current mode regs are properly set */
 391     mode = env->uncached_cpsr & CPSR_M;
 392     bn = bank_number(mode);
 393     if (mode == ARM_CPU_MODE_FIQ) {
 394         memcpy(env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
 395     } else {
 396         memcpy(env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
 397     }
 398     env->regs[13] = env->banked_r13[bn];
 399     env->regs[14] = env->banked_r14[bn];
 400     env->spsr = env->banked_spsr[bn];
 401
 402     /* VFP registers */
 403     r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
 404     for (i = 0; i < 32; i++) {
 405         r.addr = (uintptr_t)(&env->vfp.regs[i]);
 406         ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 407         if (ret) {
 408             return ret;
 409         }
 410         r.id++;
 411     }
 412
 413     r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP |
 414         KVM_REG_ARM_VFP_FPSCR;
 415     r.addr = (uintptr_t)&fpscr;
 416     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 417     if (ret) {
 418         return ret;
 419     }
 420     vfp_set_fpscr(env, fpscr);
 421
 422     if (!write_kvmstate_to_list(cpu)) {
 423         return EINVAL;
 424     }
 425     /* Note that it's OK to have registers which aren't in CPUState,
 426      * so we can ignore a failure return here.
 427      */
 428     write_list_to_cpustate(cpu);
 429
 430     return 0;
 431 }