hw/dma/i8257.c

   1 /*
   2  * QEMU DMA emulation
   3  *
   4  * Copyright (c) 2003-2004 Vassili Karpov (malc)
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "qemu/osdep.h"
  25 #include "hw/hw.h"
  26 #include "hw/isa/isa.h"
  27 #include "qemu/main-loop.h"
  28 #include "trace.h"
  29
  30 /* #define DEBUG_DMA */
  31
  32 #define dolog(...) fprintf (stderr, "dma: " __VA_ARGS__)
  33 #ifdef DEBUG_DMA
  34 #define linfo(...) fprintf (stderr, "dma: " __VA_ARGS__)
  35 #define ldebug(...) fprintf (stderr, "dma: " __VA_ARGS__)
  36 #else
  37 #define linfo(...)
  38 #define ldebug(...)
  39 #endif
  40
  41 typedef struct I8257Regs {
  42     int now[2];
  43     uint16_t base[2];
  44     uint8_t mode;
  45     uint8_t page;
  46     uint8_t pageh;
  47     uint8_t dack;
  48     uint8_t eop;
  49     DMA_transfer_handler transfer_handler;
  50     void *opaque;
  51 } I8257Regs;
  52
  53 #define ADDR 0
  54 #define COUNT 1
  55
  56 typedef struct I8257State {
  57     uint8_t status;
  58     uint8_t command;
  59     uint8_t mask;
  60     uint8_t flip_flop;
  61     int dshift;
  62     I8257Regs regs[4];
  63     MemoryRegion channel_io;
  64     MemoryRegion cont_io;
  65
  66     QEMUBH *dma_bh;
  67     bool dma_bh_scheduled;
  68     int running;
  69 } I8257State;
  70
  71 static I8257State dma_controllers[2];
  72
  73 enum {
  74     CMD_MEMORY_TO_MEMORY = 0x01,
  75     CMD_FIXED_ADDRESS    = 0x02,
  76     CMD_BLOCK_CONTROLLER = 0x04,
  77     CMD_COMPRESSED_TIME  = 0x08,
  78     CMD_CYCLIC_PRIORITY  = 0x10,
  79     CMD_EXTENDED_WRITE   = 0x20,
  80     CMD_LOW_DREQ         = 0x40,
  81     CMD_LOW_DACK         = 0x80,
  82     CMD_NOT_SUPPORTED    = CMD_MEMORY_TO_MEMORY | CMD_FIXED_ADDRESS
  83     | CMD_COMPRESSED_TIME | CMD_CYCLIC_PRIORITY | CMD_EXTENDED_WRITE
  84     | CMD_LOW_DREQ | CMD_LOW_DACK
  85
  86 };
  87
  88 static void i8257_dma_run(void *opaque);
  89
  90 static const int channels[8] = {-1, 2, 3, 1, -1, -1, -1, 0};
  91
  92 static void i8257_write_page(void *opaque, uint32_t nport, uint32_t data)
  93 {
  94     I8257State *d = opaque;
  95     int ichan;
  96
  97     ichan = channels[nport & 7];
  98     if (-1 == ichan) {
  99         dolog ("invalid channel %#x %#x\n", nport, data);
 100         return;
 101     }
 102     d->regs[ichan].page = data;
 103 }
 104
 105 static void i8257_write_pageh(void *opaque, uint32_t nport, uint32_t data)
 106 {
 107     I8257State *d = opaque;
 108     int ichan;
 109
 110     ichan = channels[nport & 7];
 111     if (-1 == ichan) {
 112         dolog ("invalid channel %#x %#x\n", nport, data);
 113         return;
 114     }
 115     d->regs[ichan].pageh = data;
 116 }
 117
 118 static uint32_t i8257_read_page(void *opaque, uint32_t nport)
 119 {
 120     I8257State *d = opaque;
 121     int ichan;
 122
 123     ichan = channels[nport & 7];
 124     if (-1 == ichan) {
 125         dolog ("invalid channel read %#x\n", nport);
 126         return 0;
 127     }
 128     return d->regs[ichan].page;
 129 }
 130
 131 static uint32_t i8257_read_pageh(void *opaque, uint32_t nport)
 132 {
 133     I8257State *d = opaque;
 134     int ichan;
 135
 136     ichan = channels[nport & 7];
 137     if (-1 == ichan) {
 138         dolog ("invalid channel read %#x\n", nport);
 139         return 0;
 140     }
 141     return d->regs[ichan].pageh;
 142 }
 143
 144 static inline void i8257_init_chan(I8257State *d, int ichan)
 145 {
 146     I8257Regs *r;
 147
 148     r = d->regs + ichan;
 149     r->now[ADDR] = r->base[ADDR] << d->dshift;
 150     r->now[COUNT] = 0;
 151 }
 152
 153 static inline int i8257_getff(I8257State *d)
 154 {
 155     int ff;
 156
 157     ff = d->flip_flop;
 158     d->flip_flop = !ff;
 159     return ff;
 160 }
 161
 162 static uint64_t i8257_read_chan(void *opaque, hwaddr nport, unsigned size)
 163 {
 164     I8257State *d = opaque;
 165     int ichan, nreg, iport, ff, val, dir;
 166     I8257Regs *r;
 167
 168     iport = (nport >> d->dshift) & 0x0f;
 169     ichan = iport >> 1;
 170     nreg = iport & 1;
 171     r = d->regs + ichan;
 172
 173     dir = ((r->mode >> 5) & 1) ? -1 : 1;
 174     ff = i8257_getff(d);
 175     if (nreg)
 176         val = (r->base[COUNT] << d->dshift) - r->now[COUNT];
 177     else
 178         val = r->now[ADDR] + r->now[COUNT] * dir;
 179
 180     ldebug ("read_chan %#x -> %d\n", iport, val);
 181     return (val >> (d->dshift + (ff << 3))) & 0xff;
 182 }
 183
 184 static void i8257_write_chan(void *opaque, hwaddr nport, uint64_t data,
 185                              unsigned int size)
 186 {
 187     I8257State *d = opaque;
 188     int iport, ichan, nreg;
 189     I8257Regs *r;
 190
 191     iport = (nport >> d->dshift) & 0x0f;
 192     ichan = iport >> 1;
 193     nreg = iport & 1;
 194     r = d->regs + ichan;
 195     if (i8257_getff(d)) {
 196         r->base[nreg] = (r->base[nreg] & 0xff) | ((data << 8) & 0xff00);
 197         i8257_init_chan(d, ichan);
 198     } else {
 199         r->base[nreg] = (r->base[nreg] & 0xff00) | (data & 0xff);
 200     }
 201 }
 202
 203 static void i8257_write_cont(void *opaque, hwaddr nport, uint64_t data,
 204                              unsigned int size)
 205 {
 206     I8257State *d = opaque;
 207     int iport, ichan = 0;
 208
 209     iport = (nport >> d->dshift) & 0x0f;
 210     switch (iport) {
 211     case 0x00:                  /* command */
 212         if ((data != 0) && (data & CMD_NOT_SUPPORTED)) {
 213             dolog("command %"PRIx64" not supported\n", data);
 214             return;
 215         }
 216         d->command = data;
 217         break;
 218
 219     case 0x01:
 220         ichan = data & 3;
 221         if (data & 4) {
 222             d->status |= 1 << (ichan + 4);
 223         }
 224         else {
 225             d->status &= ~(1 << (ichan + 4));
 226         }
 227         d->status &= ~(1 << ichan);
 228         i8257_dma_run(d);
 229         break;
 230
 231     case 0x02:                  /* single mask */
 232         if (data & 4)
 233             d->mask |= 1 << (data & 3);
 234         else
 235             d->mask &= ~(1 << (data & 3));
 236         i8257_dma_run(d);
 237         break;
 238
 239     case 0x03:                  /* mode */
 240         {
 241             ichan = data & 3;
 242 #ifdef DEBUG_DMA
 243             {
 244                 int op, ai, dir, opmode;
 245                 op = (data >> 2) & 3;
 246                 ai = (data >> 4) & 1;
 247                 dir = (data >> 5) & 1;
 248                 opmode = (data >> 6) & 3;
 249
 250                 linfo ("ichan %d, op %d, ai %d, dir %d, opmode %d\n",
 251                        ichan, op, ai, dir, opmode);
 252             }
 253 #endif
 254             d->regs[ichan].mode = data;
 255             break;
 256         }
 257
 258     case 0x04:                  /* clear flip flop */
 259         d->flip_flop = 0;
 260         break;
 261
 262     case 0x05:                  /* reset */
 263         d->flip_flop = 0;
 264         d->mask = ~0;
 265         d->status = 0;
 266         d->command = 0;
 267         break;
 268
 269     case 0x06:                  /* clear mask for all channels */
 270         d->mask = 0;
 271         i8257_dma_run(d);
 272         break;
 273
 274     case 0x07:                  /* write mask for all channels */
 275         d->mask = data;
 276         i8257_dma_run(d);
 277         break;
 278
 279     default:
 280         dolog ("unknown iport %#x\n", iport);
 281         break;
 282     }
 283
 284 #ifdef DEBUG_DMA
 285     if (0xc != iport) {
 286         linfo ("write_cont: nport %#06x, ichan % 2d, val %#06x\n",
 287                nport, ichan, data);
 288     }
 289 #endif
 290 }
 291
 292 static uint64_t i8257_read_cont(void *opaque, hwaddr nport, unsigned size)
 293 {
 294     I8257State *d = opaque;
 295     int iport, val;
 296
 297     iport = (nport >> d->dshift) & 0x0f;
 298     switch (iport) {
 299     case 0x00:                  /* status */
 300         val = d->status;
 301         d->status &= 0xf0;
 302         break;
 303     case 0x01:                  /* mask */
 304         val = d->mask;
 305         break;
 306     default:
 307         val = 0;
 308         break;
 309     }
 310
 311     ldebug ("read_cont: nport %#06x, iport %#04x val %#x\n", nport, iport, val);
 312     return val;
 313 }
 314
 315 int DMA_get_channel_mode (int nchan)
 316 {
 317     return dma_controllers[nchan > 3].regs[nchan & 3].mode;
 318 }
 319
 320 void DMA_hold_DREQ (int nchan)
 321 {
 322     int ncont, ichan;
 323
 324     ncont = nchan > 3;
 325     ichan = nchan & 3;
 326     linfo ("held cont=%d chan=%d\n", ncont, ichan);
 327     dma_controllers[ncont].status |= 1 << (ichan + 4);
 328     i8257_dma_run(&dma_controllers[ncont]);
 329 }
 330
 331 void DMA_release_DREQ (int nchan)
 332 {
 333     int ncont, ichan;
 334
 335     ncont = nchan > 3;
 336     ichan = nchan & 3;
 337     linfo ("released cont=%d chan=%d\n", ncont, ichan);
 338     dma_controllers[ncont].status &= ~(1 << (ichan + 4));
 339     i8257_dma_run(&dma_controllers[ncont]);
 340 }
 341
 342 static void i8257_channel_run(I8257State *d, int ichan)
 343 {
 344     int ncont = d->dshift;
 345     int n;
 346     I8257Regs *r = &d->regs[ichan];
 347 #ifdef DEBUG_DMA
 348     int dir, opmode;
 349
 350     dir = (r->mode >> 5) & 1;
 351     opmode = (r->mode >> 6) & 3;
 352
 353     if (dir) {
 354         dolog ("DMA in address decrement mode\n");
 355     }
 356     if (opmode != 1) {
 357         dolog ("DMA not in single mode select %#x\n", opmode);
 358     }
 359 #endif
 360
 361     n = r->transfer_handler (r->opaque, ichan + (ncont << 2),
 362                              r->now[COUNT], (r->base[COUNT] + 1) << ncont);
 363     r->now[COUNT] = n;
 364     ldebug ("dma_pos %d size %d\n", n, (r->base[COUNT] + 1) << ncont);
 365 }
 366
 367 static void i8257_dma_run(void *opaque)
 368 {
 369     I8257State *d = opaque;
 370     int ichan;
 371     int rearm = 0;
 372
 373     if (d->running) {
 374         rearm = 1;
 375         goto out;
 376     } else {
 377         d->running = 1;
 378     }
 379
 380     for (ichan = 0; ichan < 4; ichan++) {
 381         int mask;
 382
 383         mask = 1 << ichan;
 384
 385         if ((0 == (d->mask & mask)) && (0 != (d->status & (mask << 4)))) {
 386             i8257_channel_run(d, ichan);
 387             rearm = 1;
 388         }
 389     }
 390
 391     d->running = 0;
 392 out:
 393     if (rearm) {
 394         qemu_bh_schedule_idle(d->dma_bh);
 395         d->dma_bh_scheduled = true;
 396     }
 397 }
 398
 399 void DMA_register_channel (int nchan,
 400                            DMA_transfer_handler transfer_handler,
 401                            void *opaque)
 402 {
 403     I8257Regs *r;
 404     int ichan, ncont;
 405
 406     ncont = nchan > 3;
 407     ichan = nchan & 3;
 408
 409     r = dma_controllers[ncont].regs + ichan;
 410     r->transfer_handler = transfer_handler;
 411     r->opaque = opaque;
 412 }
 413
 414 int DMA_read_memory (int nchan, void *buf, int pos, int len)
 415 {
 416     I8257Regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
 417     hwaddr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
 418
 419     if (r->mode & 0x20) {
 420         int i;
 421         uint8_t *p = buf;
 422
 423         cpu_physical_memory_read (addr - pos - len, buf, len);
 424         /* What about 16bit transfers? */
 425         for (i = 0; i < len >> 1; i++) {
 426             uint8_t b = p[len - i - 1];
 427             p[i] = b;
 428         }
 429     }
 430     else
 431         cpu_physical_memory_read (addr + pos, buf, len);
 432
 433     return len;
 434 }
 435
 436 int DMA_write_memory (int nchan, void *buf, int pos, int len)
 437 {
 438     I8257Regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
 439     hwaddr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
 440
 441     if (r->mode & 0x20) {
 442         int i;
 443         uint8_t *p = buf;
 444
 445         cpu_physical_memory_write (addr - pos - len, buf, len);
 446         /* What about 16bit transfers? */
 447         for (i = 0; i < len; i++) {
 448             uint8_t b = p[len - i - 1];
 449             p[i] = b;
 450         }
 451     }
 452     else
 453         cpu_physical_memory_write (addr + pos, buf, len);
 454
 455     return len;
 456 }
 457
 458 /* request the emulator to transfer a new DMA memory block ASAP (even
 459  * if the idle bottom half would not have exited the iothread yet).
 460  */
 461 void DMA_schedule(void)
 462 {
 463     if (dma_controllers[0].dma_bh_scheduled ||
 464         dma_controllers[1].dma_bh_scheduled) {
 465         qemu_notify_event();
 466     }
 467 }
 468
 469 static void i8257_reset(void *opaque)
 470 {
 471     I8257State *d = opaque;
 472     i8257_write_cont(d, (0x05 << d->dshift), 0, 1);
 473 }
 474
 475 static int i8257_phony_handler(void *opaque, int nchan, int dma_pos,
 476                                int dma_len)
 477 {
 478     trace_i8257_unregistered_dma(nchan, dma_pos, dma_len);
 479     return dma_pos;
 480 }
 481
 482
 483 static const MemoryRegionOps channel_io_ops = {
 484     .read = i8257_read_chan,
 485     .write = i8257_write_chan,
 486     .endianness = DEVICE_NATIVE_ENDIAN,
 487     .impl = {
 488         .min_access_size = 1,
 489         .max_access_size = 1,
 490     },
 491 };
 492
 493 /* IOport from page_base */
 494 static const MemoryRegionPortio page_portio_list[] = {
 495     { 0x01, 3, 1, .write = i8257_write_page, .read = i8257_read_page, },
 496     { 0x07, 1, 1, .write = i8257_write_page, .read = i8257_read_page, },
 497     PORTIO_END_OF_LIST(),
 498 };
 499
 500 /* IOport from pageh_base */
 501 static const MemoryRegionPortio pageh_portio_list[] = {
 502     { 0x01, 3, 1, .write = i8257_write_pageh, .read = i8257_read_pageh, },
 503     { 0x07, 3, 1, .write = i8257_write_pageh, .read = i8257_read_pageh, },
 504     PORTIO_END_OF_LIST(),
 505 };
 506
 507 static const MemoryRegionOps cont_io_ops = {
 508     .read = i8257_read_cont,
 509     .write = i8257_write_cont,
 510     .endianness = DEVICE_NATIVE_ENDIAN,
 511     .impl = {
 512         .min_access_size = 1,
 513         .max_access_size = 1,
 514     },
 515 };
 516
 517 /* dshift = 0: 8 bit DMA, 1 = 16 bit DMA */
 518 static void dma_init2(I8257State *d, int base, int dshift,
 519                       int page_base, int pageh_base)
 520 {
 521     int i;
 522
 523     d->dshift = dshift;
 524
 525     memory_region_init_io(&d->channel_io, NULL, &channel_io_ops, d,
 526                           "dma-chan", 8 << d->dshift);
 527     memory_region_add_subregion(isa_address_space_io(NULL),
 528                                 base, &d->channel_io);
 529
 530     isa_register_portio_list(NULL, page_base, page_portio_list, d,
 531                              "dma-page");
 532     if (pageh_base >= 0) {
 533         isa_register_portio_list(NULL, pageh_base, pageh_portio_list, d,
 534                                  "dma-pageh");
 535     }
 536
 537     memory_region_init_io(&d->cont_io, NULL, &cont_io_ops, d, "dma-cont",
 538                           8 << d->dshift);
 539     memory_region_add_subregion(isa_address_space_io(NULL),
 540                                 base + (8 << d->dshift), &d->cont_io);
 541
 542     qemu_register_reset(i8257_reset, d);
 543     i8257_reset(d);
 544     for (i = 0; i < ARRAY_SIZE (d->regs); ++i) {
 545         d->regs[i].transfer_handler = i8257_phony_handler;
 546     }
 547
 548     d->dma_bh = qemu_bh_new(i8257_dma_run, d);
 549 }
 550
 551 static const VMStateDescription vmstate_i8257_regs = {
 552     .name = "dma_regs",
 553     .version_id = 1,
 554     .minimum_version_id = 1,
 555     .fields = (VMStateField[]) {
 556         VMSTATE_INT32_ARRAY(now, I8257Regs, 2),
 557         VMSTATE_UINT16_ARRAY(base, I8257Regs, 2),
 558         VMSTATE_UINT8(mode, I8257Regs),
 559         VMSTATE_UINT8(page, I8257Regs),
 560         VMSTATE_UINT8(pageh, I8257Regs),
 561         VMSTATE_UINT8(dack, I8257Regs),
 562         VMSTATE_UINT8(eop, I8257Regs),
 563         VMSTATE_END_OF_LIST()
 564     }
 565 };
 566
 567 static int i8257_post_load(void *opaque, int version_id)
 568 {
 569     I8257State *d = opaque;
 570     i8257_dma_run(d);
 571
 572     return 0;
 573 }
 574
 575 static const VMStateDescription vmstate_dma = {
 576     .name = "dma",
 577     .version_id = 1,
 578     .minimum_version_id = 1,
 579     .post_load = i8257_post_load,
 580     .fields = (VMStateField[]) {
 581         VMSTATE_UINT8(command, I8257State),
 582         VMSTATE_UINT8(mask, I8257State),
 583         VMSTATE_UINT8(flip_flop, I8257State),
 584         VMSTATE_INT32(dshift, I8257State),
 585         VMSTATE_STRUCT_ARRAY(regs, I8257State, 4, 1, vmstate_i8257_regs,
 586                              I8257Regs),
 587         VMSTATE_END_OF_LIST()
 588     }
 589 };
 590
 591 void DMA_init(ISABus *bus, int high_page_enable)
 592 {
 593     dma_init2(&dma_controllers[0], 0x00, 0, 0x80, high_page_enable ? 0x480 : -1);
 594     dma_init2(&dma_controllers[1], 0xc0, 1, 0x88, high_page_enable ? 0x488 : -1);
 595     vmstate_register (NULL, 0, &vmstate_dma, &dma_controllers[0]);
 596     vmstate_register (NULL, 1, &vmstate_dma, &dma_controllers[1]);
 597 }