target-i386/cpu.h

   1 /*
   2  * i386 virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef CPU_I386_H
  20 #define CPU_I386_H
  21
  22 #include "config.h"
  23 #include "qemu-common.h"
  24
  25 #ifdef TARGET_X86_64
  26 #define TARGET_LONG_BITS 64
  27 #else
  28 #define TARGET_LONG_BITS 32
  29 #endif
  30
  31 /* target supports implicit self modifying code */
  32 #define TARGET_HAS_SMC
  33 /* support for self modifying code even if the modified instruction is
  34    close to the modifying instruction */
  35 #define TARGET_HAS_PRECISE_SMC
  36
  37 #define TARGET_HAS_ICE 1
  38
  39 #ifdef TARGET_X86_64
  40 #define ELF_MACHINE     EM_X86_64
  41 #else
  42 #define ELF_MACHINE     EM_386
  43 #endif
  44
  45 #define CPUArchState struct CPUX86State
  46
  47 #include "exec/cpu-defs.h"
  48
  49 #include "fpu/softfloat.h"
  50
  51 #define R_EAX 0
  52 #define R_ECX 1
  53 #define R_EDX 2
  54 #define R_EBX 3
  55 #define R_ESP 4
  56 #define R_EBP 5
  57 #define R_ESI 6
  58 #define R_EDI 7
  59
  60 #define R_AL 0
  61 #define R_CL 1
  62 #define R_DL 2
  63 #define R_BL 3
  64 #define R_AH 4
  65 #define R_CH 5
  66 #define R_DH 6
  67 #define R_BH 7
  68
  69 #define R_ES 0
  70 #define R_CS 1
  71 #define R_SS 2
  72 #define R_DS 3
  73 #define R_FS 4
  74 #define R_GS 5
  75
  76 /* segment descriptor fields */
  77 #define DESC_G_MASK     (1 << 23)
  78 #define DESC_B_SHIFT    22
  79 #define DESC_B_MASK     (1 << DESC_B_SHIFT)
  80 #define DESC_L_SHIFT    21 /* x86_64 only : 64 bit code segment */
  81 #define DESC_L_MASK     (1 << DESC_L_SHIFT)
  82 #define DESC_AVL_MASK   (1 << 20)
  83 #define DESC_P_MASK     (1 << 15)
  84 #define DESC_DPL_SHIFT  13
  85 #define DESC_DPL_MASK   (3 << DESC_DPL_SHIFT)
  86 #define DESC_S_MASK     (1 << 12)
  87 #define DESC_TYPE_SHIFT 8
  88 #define DESC_TYPE_MASK  (15 << DESC_TYPE_SHIFT)
  89 #define DESC_A_MASK     (1 << 8)
  90
  91 #define DESC_CS_MASK    (1 << 11) /* 1=code segment 0=data segment */
  92 #define DESC_C_MASK     (1 << 10) /* code: conforming */
  93 #define DESC_R_MASK     (1 << 9)  /* code: readable */
  94
  95 #define DESC_E_MASK     (1 << 10) /* data: expansion direction */
  96 #define DESC_W_MASK     (1 << 9)  /* data: writable */
  97
  98 #define DESC_TSS_BUSY_MASK (1 << 9)
  99
 100 /* eflags masks */
 101 #define CC_C    0x0001
 102 #define CC_P    0x0004
 103 #define CC_A    0x0010
 104 #define CC_Z    0x0040
 105 #define CC_S    0x0080
 106 #define CC_O    0x0800
 107
 108 #define TF_SHIFT   8
 109 #define IOPL_SHIFT 12
 110 #define VM_SHIFT   17
 111
 112 #define TF_MASK                 0x00000100
 113 #define IF_MASK                 0x00000200
 114 #define DF_MASK                 0x00000400
 115 #define IOPL_MASK               0x00003000
 116 #define NT_MASK                 0x00004000
 117 #define RF_MASK                 0x00010000
 118 #define VM_MASK                 0x00020000
 119 #define AC_MASK                 0x00040000
 120 #define VIF_MASK                0x00080000
 121 #define VIP_MASK                0x00100000
 122 #define ID_MASK                 0x00200000
 123
 124 /* hidden flags - used internally by qemu to represent additional cpu
 125    states. Only the CPL, INHIBIT_IRQ, SMM and SVMI are not
 126    redundant. We avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK
 127    bit positions to ease oring with eflags. */
 128 /* current cpl */
 129 #define HF_CPL_SHIFT         0
 130 /* true if soft mmu is being used */
 131 #define HF_SOFTMMU_SHIFT     2
 132 /* true if hardware interrupts must be disabled for next instruction */
 133 #define HF_INHIBIT_IRQ_SHIFT 3
 134 /* 16 or 32 segments */
 135 #define HF_CS32_SHIFT        4
 136 #define HF_SS32_SHIFT        5
 137 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
 138 #define HF_ADDSEG_SHIFT      6
 139 /* copy of CR0.PE (protected mode) */
 140 #define HF_PE_SHIFT          7
 141 #define HF_TF_SHIFT          8 /* must be same as eflags */
 142 #define HF_MP_SHIFT          9 /* the order must be MP, EM, TS */
 143 #define HF_EM_SHIFT         10
 144 #define HF_TS_SHIFT         11
 145 #define HF_IOPL_SHIFT       12 /* must be same as eflags */
 146 #define HF_LMA_SHIFT        14 /* only used on x86_64: long mode active */
 147 #define HF_CS64_SHIFT       15 /* only used on x86_64: 64 bit code segment  */
 148 #define HF_RF_SHIFT         16 /* must be same as eflags */
 149 #define HF_VM_SHIFT         17 /* must be same as eflags */
 150 #define HF_AC_SHIFT         18 /* must be same as eflags */
 151 #define HF_SMM_SHIFT        19 /* CPU in SMM mode */
 152 #define HF_SVME_SHIFT       20 /* SVME enabled (copy of EFER.SVME) */
 153 #define HF_SVMI_SHIFT       21 /* SVM intercepts are active */
 154 #define HF_OSFXSR_SHIFT     22 /* CR4.OSFXSR */
 155 #define HF_SMAP_SHIFT       23 /* CR4.SMAP */
 156
 157 #define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
 158 #define HF_SOFTMMU_MASK      (1 << HF_SOFTMMU_SHIFT)
 159 #define HF_INHIBIT_IRQ_MASK  (1 << HF_INHIBIT_IRQ_SHIFT)
 160 #define HF_CS32_MASK         (1 << HF_CS32_SHIFT)
 161 #define HF_SS32_MASK         (1 << HF_SS32_SHIFT)
 162 #define HF_ADDSEG_MASK       (1 << HF_ADDSEG_SHIFT)
 163 #define HF_PE_MASK           (1 << HF_PE_SHIFT)
 164 #define HF_TF_MASK           (1 << HF_TF_SHIFT)
 165 #define HF_MP_MASK           (1 << HF_MP_SHIFT)
 166 #define HF_EM_MASK           (1 << HF_EM_SHIFT)
 167 #define HF_TS_MASK           (1 << HF_TS_SHIFT)
 168 #define HF_IOPL_MASK         (3 << HF_IOPL_SHIFT)
 169 #define HF_LMA_MASK          (1 << HF_LMA_SHIFT)
 170 #define HF_CS64_MASK         (1 << HF_CS64_SHIFT)
 171 #define HF_RF_MASK           (1 << HF_RF_SHIFT)
 172 #define HF_VM_MASK           (1 << HF_VM_SHIFT)
 173 #define HF_AC_MASK           (1 << HF_AC_SHIFT)
 174 #define HF_SMM_MASK          (1 << HF_SMM_SHIFT)
 175 #define HF_SVME_MASK         (1 << HF_SVME_SHIFT)
 176 #define HF_SVMI_MASK         (1 << HF_SVMI_SHIFT)
 177 #define HF_OSFXSR_MASK       (1 << HF_OSFXSR_SHIFT)
 178 #define HF_SMAP_MASK         (1 << HF_SMAP_SHIFT)
 179
 180 /* hflags2 */
 181
 182 #define HF2_GIF_SHIFT        0 /* if set CPU takes interrupts */
 183 #define HF2_HIF_SHIFT        1 /* value of IF_MASK when entering SVM */
 184 #define HF2_NMI_SHIFT        2 /* CPU serving NMI */
 185 #define HF2_VINTR_SHIFT      3 /* value of V_INTR_MASKING bit */
 186
 187 #define HF2_GIF_MASK          (1 << HF2_GIF_SHIFT)
 188 #define HF2_HIF_MASK          (1 << HF2_HIF_SHIFT)
 189 #define HF2_NMI_MASK          (1 << HF2_NMI_SHIFT)
 190 #define HF2_VINTR_MASK        (1 << HF2_VINTR_SHIFT)
 191
 192 #define CR0_PE_SHIFT 0
 193 #define CR0_MP_SHIFT 1
 194
 195 #define CR0_PE_MASK  (1 << 0)
 196 #define CR0_MP_MASK  (1 << 1)
 197 #define CR0_EM_MASK  (1 << 2)
 198 #define CR0_TS_MASK  (1 << 3)
 199 #define CR0_ET_MASK  (1 << 4)
 200 #define CR0_NE_MASK  (1 << 5)
 201 #define CR0_WP_MASK  (1 << 16)
 202 #define CR0_AM_MASK  (1 << 18)
 203 #define CR0_PG_MASK  (1 << 31)
 204
 205 #define CR4_VME_MASK  (1 << 0)
 206 #define CR4_PVI_MASK  (1 << 1)
 207 #define CR4_TSD_MASK  (1 << 2)
 208 #define CR4_DE_MASK   (1 << 3)
 209 #define CR4_PSE_MASK  (1 << 4)
 210 #define CR4_PAE_MASK  (1 << 5)
 211 #define CR4_MCE_MASK  (1 << 6)
 212 #define CR4_PGE_MASK  (1 << 7)
 213 #define CR4_PCE_MASK  (1 << 8)
 214 #define CR4_OSFXSR_SHIFT 9
 215 #define CR4_OSFXSR_MASK (1 << CR4_OSFXSR_SHIFT)
 216 #define CR4_OSXMMEXCPT_MASK  (1 << 10)
 217 #define CR4_VMXE_MASK   (1 << 13)
 218 #define CR4_SMXE_MASK   (1 << 14)
 219 #define CR4_FSGSBASE_MASK (1 << 16)
 220 #define CR4_PCIDE_MASK  (1 << 17)
 221 #define CR4_OSXSAVE_MASK (1 << 18)
 222 #define CR4_SMEP_MASK   (1 << 20)
 223 #define CR4_SMAP_MASK   (1 << 21)
 224
 225 #define DR6_BD          (1 << 13)
 226 #define DR6_BS          (1 << 14)
 227 #define DR6_BT          (1 << 15)
 228 #define DR6_FIXED_1     0xffff0ff0
 229
 230 #define DR7_GD          (1 << 13)
 231 #define DR7_TYPE_SHIFT  16
 232 #define DR7_LEN_SHIFT   18
 233 #define DR7_FIXED_1     0x00000400
 234 #define DR7_LOCAL_BP_MASK    0x55
 235 #define DR7_MAX_BP           4
 236 #define DR7_TYPE_BP_INST     0x0
 237 #define DR7_TYPE_DATA_WR     0x1
 238 #define DR7_TYPE_IO_RW       0x2
 239 #define DR7_TYPE_DATA_RW     0x3
 240
 241 #define PG_PRESENT_BIT  0
 242 #define PG_RW_BIT       1
 243 #define PG_USER_BIT     2
 244 #define PG_PWT_BIT      3
 245 #define PG_PCD_BIT      4
 246 #define PG_ACCESSED_BIT 5
 247 #define PG_DIRTY_BIT    6
 248 #define PG_PSE_BIT      7
 249 #define PG_GLOBAL_BIT   8
 250 #define PG_NX_BIT       63
 251
 252 #define PG_PRESENT_MASK  (1 << PG_PRESENT_BIT)
 253 #define PG_RW_MASK       (1 << PG_RW_BIT)
 254 #define PG_USER_MASK     (1 << PG_USER_BIT)
 255 #define PG_PWT_MASK      (1 << PG_PWT_BIT)
 256 #define PG_PCD_MASK      (1 << PG_PCD_BIT)
 257 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
 258 #define PG_DIRTY_MASK    (1 << PG_DIRTY_BIT)
 259 #define PG_PSE_MASK      (1 << PG_PSE_BIT)
 260 #define PG_GLOBAL_MASK   (1 << PG_GLOBAL_BIT)
 261 #define PG_HI_USER_MASK  0x7ff0000000000000LL
 262 #define PG_NX_MASK       (1LL << PG_NX_BIT)
 263
 264 #define PG_ERROR_W_BIT     1
 265
 266 #define PG_ERROR_P_MASK    0x01
 267 #define PG_ERROR_W_MASK    (1 << PG_ERROR_W_BIT)
 268 #define PG_ERROR_U_MASK    0x04
 269 #define PG_ERROR_RSVD_MASK 0x08
 270 #define PG_ERROR_I_D_MASK  0x10
 271
 272 #define MCG_CTL_P       (1ULL<<8)   /* MCG_CAP register available */
 273 #define MCG_SER_P       (1ULL<<24) /* MCA recovery/new status bits */
 274
 275 #define MCE_CAP_DEF     (MCG_CTL_P|MCG_SER_P)
 276 #define MCE_BANKS_DEF   10
 277
 278 #define MCG_STATUS_RIPV (1ULL<<0)   /* restart ip valid */
 279 #define MCG_STATUS_EIPV (1ULL<<1)   /* ip points to correct instruction */
 280 #define MCG_STATUS_MCIP (1ULL<<2)   /* machine check in progress */
 281
 282 #define MCI_STATUS_VAL   (1ULL<<63)  /* valid error */
 283 #define MCI_STATUS_OVER  (1ULL<<62)  /* previous errors lost */
 284 #define MCI_STATUS_UC    (1ULL<<61)  /* uncorrected error */
 285 #define MCI_STATUS_EN    (1ULL<<60)  /* error enabled */
 286 #define MCI_STATUS_MISCV (1ULL<<59)  /* misc error reg. valid */
 287 #define MCI_STATUS_ADDRV (1ULL<<58)  /* addr reg. valid */
 288 #define MCI_STATUS_PCC   (1ULL<<57)  /* processor context corrupt */
 289 #define MCI_STATUS_S     (1ULL<<56)  /* Signaled machine check */
 290 #define MCI_STATUS_AR    (1ULL<<55)  /* Action required */
 291
 292 /* MISC register defines */
 293 #define MCM_ADDR_SEGOFF  0      /* segment offset */
 294 #define MCM_ADDR_LINEAR  1      /* linear address */
 295 #define MCM_ADDR_PHYS    2      /* physical address */
 296 #define MCM_ADDR_MEM     3      /* memory address */
 297 #define MCM_ADDR_GENERIC 7      /* generic */
 298
 299 #define MSR_IA32_TSC                    0x10
 300 #define MSR_IA32_APICBASE               0x1b
 301 #define MSR_IA32_APICBASE_BSP           (1<<8)
 302 #define MSR_IA32_APICBASE_ENABLE        (1<<11)
 303 #define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
 304 #define MSR_IA32_FEATURE_CONTROL        0x0000003a
 305 #define MSR_TSC_ADJUST                  0x0000003b
 306 #define MSR_IA32_TSCDEADLINE            0x6e0
 307
 308 #define MSR_P6_PERFCTR0                 0xc1
 309
 310 #define MSR_MTRRcap                     0xfe
 311 #define MSR_MTRRcap_VCNT                8
 312 #define MSR_MTRRcap_FIXRANGE_SUPPORT    (1 << 8)
 313 #define MSR_MTRRcap_WC_SUPPORTED        (1 << 10)
 314
 315 #define MSR_IA32_SYSENTER_CS            0x174
 316 #define MSR_IA32_SYSENTER_ESP           0x175
 317 #define MSR_IA32_SYSENTER_EIP           0x176
 318
 319 #define MSR_MCG_CAP                     0x179
 320 #define MSR_MCG_STATUS                  0x17a
 321 #define MSR_MCG_CTL                     0x17b
 322
 323 #define MSR_P6_EVNTSEL0                 0x186
 324
 325 #define MSR_IA32_PERF_STATUS            0x198
 326
 327 #define MSR_IA32_MISC_ENABLE            0x1a0
 328 /* Indicates good rep/movs microcode on some processors: */
 329 #define MSR_IA32_MISC_ENABLE_DEFAULT    1
 330
 331 #define MSR_MTRRphysBase(reg)           (0x200 + 2 * (reg))
 332 #define MSR_MTRRphysMask(reg)           (0x200 + 2 * (reg) + 1)
 333
 334 #define MSR_MTRRfix64K_00000            0x250
 335 #define MSR_MTRRfix16K_80000            0x258
 336 #define MSR_MTRRfix16K_A0000            0x259
 337 #define MSR_MTRRfix4K_C0000             0x268
 338 #define MSR_MTRRfix4K_C8000             0x269
 339 #define MSR_MTRRfix4K_D0000             0x26a
 340 #define MSR_MTRRfix4K_D8000             0x26b
 341 #define MSR_MTRRfix4K_E0000             0x26c
 342 #define MSR_MTRRfix4K_E8000             0x26d
 343 #define MSR_MTRRfix4K_F0000             0x26e
 344 #define MSR_MTRRfix4K_F8000             0x26f
 345
 346 #define MSR_PAT                         0x277
 347
 348 #define MSR_MTRRdefType                 0x2ff
 349
 350 #define MSR_CORE_PERF_FIXED_CTR0        0x309
 351 #define MSR_CORE_PERF_FIXED_CTR1        0x30a
 352 #define MSR_CORE_PERF_FIXED_CTR2        0x30b
 353 #define MSR_CORE_PERF_FIXED_CTR_CTRL    0x38d
 354 #define MSR_CORE_PERF_GLOBAL_STATUS     0x38e
 355 #define MSR_CORE_PERF_GLOBAL_CTRL       0x38f
 356 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL   0x390
 357
 358 #define MSR_MC0_CTL                     0x400
 359 #define MSR_MC0_STATUS                  0x401
 360 #define MSR_MC0_ADDR                    0x402
 361 #define MSR_MC0_MISC                    0x403
 362
 363 #define MSR_EFER                        0xc0000080
 364
 365 #define MSR_EFER_SCE   (1 << 0)
 366 #define MSR_EFER_LME   (1 << 8)
 367 #define MSR_EFER_LMA   (1 << 10)
 368 #define MSR_EFER_NXE   (1 << 11)
 369 #define MSR_EFER_SVME  (1 << 12)
 370 #define MSR_EFER_FFXSR (1 << 14)
 371
 372 #define MSR_STAR                        0xc0000081
 373 #define MSR_LSTAR                       0xc0000082
 374 #define MSR_CSTAR                       0xc0000083
 375 #define MSR_FMASK                       0xc0000084
 376 #define MSR_FSBASE                      0xc0000100
 377 #define MSR_GSBASE                      0xc0000101
 378 #define MSR_KERNELGSBASE                0xc0000102
 379 #define MSR_TSC_AUX                     0xc0000103
 380
 381 #define MSR_VM_HSAVE_PA                 0xc0010117
 382
 383 /* CPUID feature words */
 384 typedef enum FeatureWord {
 385     FEAT_1_EDX,         /* CPUID[1].EDX */
 386     FEAT_1_ECX,         /* CPUID[1].ECX */
 387     FEAT_7_0_EBX,       /* CPUID[EAX=7,ECX=0].EBX */
 388     FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */
 389     FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */
 390     FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */
 391     FEAT_KVM,           /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */
 392     FEAT_SVM,           /* CPUID[8000_000A].EDX */
 393     FEATURE_WORDS,
 394 } FeatureWord;
 395
 396 typedef uint32_t FeatureWordArray[FEATURE_WORDS];
 397
 398 /* cpuid_features bits */
 399 #define CPUID_FP87 (1 << 0)
 400 #define CPUID_VME  (1 << 1)
 401 #define CPUID_DE   (1 << 2)
 402 #define CPUID_PSE  (1 << 3)
 403 #define CPUID_TSC  (1 << 4)
 404 #define CPUID_MSR  (1 << 5)
 405 #define CPUID_PAE  (1 << 6)
 406 #define CPUID_MCE  (1 << 7)
 407 #define CPUID_CX8  (1 << 8)
 408 #define CPUID_APIC (1 << 9)
 409 #define CPUID_SEP  (1 << 11) /* sysenter/sysexit */
 410 #define CPUID_MTRR (1 << 12)
 411 #define CPUID_PGE  (1 << 13)
 412 #define CPUID_MCA  (1 << 14)
 413 #define CPUID_CMOV (1 << 15)
 414 #define CPUID_PAT  (1 << 16)
 415 #define CPUID_PSE36   (1 << 17)
 416 #define CPUID_PN   (1 << 18)
 417 #define CPUID_CLFLUSH (1 << 19)
 418 #define CPUID_DTS (1 << 21)
 419 #define CPUID_ACPI (1 << 22)
 420 #define CPUID_MMX  (1 << 23)
 421 #define CPUID_FXSR (1 << 24)
 422 #define CPUID_SSE  (1 << 25)
 423 #define CPUID_SSE2 (1 << 26)
 424 #define CPUID_SS (1 << 27)
 425 #define CPUID_HT (1 << 28)
 426 #define CPUID_TM (1 << 29)
 427 #define CPUID_IA64 (1 << 30)
 428 #define CPUID_PBE (1 << 31)
 429
 430 #define CPUID_EXT_SSE3     (1 << 0)
 431 #define CPUID_EXT_PCLMULQDQ (1 << 1)
 432 #define CPUID_EXT_DTES64   (1 << 2)
 433 #define CPUID_EXT_MONITOR  (1 << 3)
 434 #define CPUID_EXT_DSCPL    (1 << 4)
 435 #define CPUID_EXT_VMX      (1 << 5)
 436 #define CPUID_EXT_SMX      (1 << 6)
 437 #define CPUID_EXT_EST      (1 << 7)
 438 #define CPUID_EXT_TM2      (1 << 8)
 439 #define CPUID_EXT_SSSE3    (1 << 9)
 440 #define CPUID_EXT_CID      (1 << 10)
 441 #define CPUID_EXT_FMA      (1 << 12)
 442 #define CPUID_EXT_CX16     (1 << 13)
 443 #define CPUID_EXT_XTPR     (1 << 14)
 444 #define CPUID_EXT_PDCM     (1 << 15)
 445 #define CPUID_EXT_PCID     (1 << 17)
 446 #define CPUID_EXT_DCA      (1 << 18)
 447 #define CPUID_EXT_SSE41    (1 << 19)
 448 #define CPUID_EXT_SSE42    (1 << 20)
 449 #define CPUID_EXT_X2APIC   (1 << 21)
 450 #define CPUID_EXT_MOVBE    (1 << 22)
 451 #define CPUID_EXT_POPCNT   (1 << 23)
 452 #define CPUID_EXT_TSC_DEADLINE_TIMER (1 << 24)
 453 #define CPUID_EXT_AES      (1 << 25)
 454 #define CPUID_EXT_XSAVE    (1 << 26)
 455 #define CPUID_EXT_OSXSAVE  (1 << 27)
 456 #define CPUID_EXT_AVX      (1 << 28)
 457 #define CPUID_EXT_F16C     (1 << 29)
 458 #define CPUID_EXT_RDRAND   (1 << 30)
 459 #define CPUID_EXT_HYPERVISOR  (1 << 31)
 460
 461 #define CPUID_EXT2_FPU     (1 << 0)
 462 #define CPUID_EXT2_VME     (1 << 1)
 463 #define CPUID_EXT2_DE      (1 << 2)
 464 #define CPUID_EXT2_PSE     (1 << 3)
 465 #define CPUID_EXT2_TSC     (1 << 4)
 466 #define CPUID_EXT2_MSR     (1 << 5)
 467 #define CPUID_EXT2_PAE     (1 << 6)
 468 #define CPUID_EXT2_MCE     (1 << 7)
 469 #define CPUID_EXT2_CX8     (1 << 8)
 470 #define CPUID_EXT2_APIC    (1 << 9)
 471 #define CPUID_EXT2_SYSCALL (1 << 11)
 472 #define CPUID_EXT2_MTRR    (1 << 12)
 473 #define CPUID_EXT2_PGE     (1 << 13)
 474 #define CPUID_EXT2_MCA     (1 << 14)
 475 #define CPUID_EXT2_CMOV    (1 << 15)
 476 #define CPUID_EXT2_PAT     (1 << 16)
 477 #define CPUID_EXT2_PSE36   (1 << 17)
 478 #define CPUID_EXT2_MP      (1 << 19)
 479 #define CPUID_EXT2_NX      (1 << 20)
 480 #define CPUID_EXT2_MMXEXT  (1 << 22)
 481 #define CPUID_EXT2_MMX     (1 << 23)
 482 #define CPUID_EXT2_FXSR    (1 << 24)
 483 #define CPUID_EXT2_FFXSR   (1 << 25)
 484 #define CPUID_EXT2_PDPE1GB (1 << 26)
 485 #define CPUID_EXT2_RDTSCP  (1 << 27)
 486 #define CPUID_EXT2_LM      (1 << 29)
 487 #define CPUID_EXT2_3DNOWEXT (1 << 30)
 488 #define CPUID_EXT2_3DNOW   (1 << 31)
 489
 490 /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */
 491 #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \
 492                                 CPUID_EXT2_DE | CPUID_EXT2_PSE | \
 493                                 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \
 494                                 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \
 495                                 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \
 496                                 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \
 497                                 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \
 498                                 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \
 499                                 CPUID_EXT2_MMX | CPUID_EXT2_FXSR)
 500
 501 #define CPUID_EXT3_LAHF_LM (1 << 0)
 502 #define CPUID_EXT3_CMP_LEG (1 << 1)
 503 #define CPUID_EXT3_SVM     (1 << 2)
 504 #define CPUID_EXT3_EXTAPIC (1 << 3)
 505 #define CPUID_EXT3_CR8LEG  (1 << 4)
 506 #define CPUID_EXT3_ABM     (1 << 5)
 507 #define CPUID_EXT3_SSE4A   (1 << 6)
 508 #define CPUID_EXT3_MISALIGNSSE (1 << 7)
 509 #define CPUID_EXT3_3DNOWPREFETCH (1 << 8)
 510 #define CPUID_EXT3_OSVW    (1 << 9)
 511 #define CPUID_EXT3_IBS     (1 << 10)
 512 #define CPUID_EXT3_XOP     (1 << 11)
 513 #define CPUID_EXT3_SKINIT  (1 << 12)
 514 #define CPUID_EXT3_WDT     (1 << 13)
 515 #define CPUID_EXT3_LWP     (1 << 15)
 516 #define CPUID_EXT3_FMA4    (1 << 16)
 517 #define CPUID_EXT3_TCE     (1 << 17)
 518 #define CPUID_EXT3_NODEID  (1 << 19)
 519 #define CPUID_EXT3_TBM     (1 << 21)
 520 #define CPUID_EXT3_TOPOEXT (1 << 22)
 521 #define CPUID_EXT3_PERFCORE (1 << 23)
 522 #define CPUID_EXT3_PERFNB  (1 << 24)
 523
 524 #define CPUID_SVM_NPT          (1 << 0)
 525 #define CPUID_SVM_LBRV         (1 << 1)
 526 #define CPUID_SVM_SVMLOCK      (1 << 2)
 527 #define CPUID_SVM_NRIPSAVE     (1 << 3)
 528 #define CPUID_SVM_TSCSCALE     (1 << 4)
 529 #define CPUID_SVM_VMCBCLEAN    (1 << 5)
 530 #define CPUID_SVM_FLUSHASID    (1 << 6)
 531 #define CPUID_SVM_DECODEASSIST (1 << 7)
 532 #define CPUID_SVM_PAUSEFILTER  (1 << 10)
 533 #define CPUID_SVM_PFTHRESHOLD  (1 << 12)
 534
 535 #define CPUID_7_0_EBX_FSGSBASE (1 << 0)
 536 #define CPUID_7_0_EBX_BMI1     (1 << 3)
 537 #define CPUID_7_0_EBX_HLE      (1 << 4)
 538 #define CPUID_7_0_EBX_AVX2     (1 << 5)
 539 #define CPUID_7_0_EBX_SMEP     (1 << 7)
 540 #define CPUID_7_0_EBX_BMI2     (1 << 8)
 541 #define CPUID_7_0_EBX_ERMS     (1 << 9)
 542 #define CPUID_7_0_EBX_INVPCID  (1 << 10)
 543 #define CPUID_7_0_EBX_RTM      (1 << 11)
 544 #define CPUID_7_0_EBX_RDSEED   (1 << 18)
 545 #define CPUID_7_0_EBX_ADX      (1 << 19)
 546 #define CPUID_7_0_EBX_SMAP     (1 << 20)
 547
 548 #define CPUID_VENDOR_SZ      12
 549
 550 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
 551 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
 552 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
 553 #define CPUID_VENDOR_INTEL "GenuineIntel"
 554
 555 #define CPUID_VENDOR_AMD_1   0x68747541 /* "Auth" */
 556 #define CPUID_VENDOR_AMD_2   0x69746e65 /* "enti" */
 557 #define CPUID_VENDOR_AMD_3   0x444d4163 /* "cAMD" */
 558 #define CPUID_VENDOR_AMD   "AuthenticAMD"
 559
 560 #define CPUID_VENDOR_VIA   "CentaurHauls"
 561
 562 #define CPUID_MWAIT_IBE     (1 << 1) /* Interrupts can exit capability */
 563 #define CPUID_MWAIT_EMX     (1 << 0) /* enumeration supported */
 564
 565 #ifndef HYPERV_SPINLOCK_NEVER_RETRY
 566 #define HYPERV_SPINLOCK_NEVER_RETRY             0xFFFFFFFF
 567 #endif
 568
 569 #define EXCP00_DIVZ     0
 570 #define EXCP01_DB       1
 571 #define EXCP02_NMI      2
 572 #define EXCP03_INT3     3
 573 #define EXCP04_INTO     4
 574 #define EXCP05_BOUND    5
 575 #define EXCP06_ILLOP    6
 576 #define EXCP07_PREX     7
 577 #define EXCP08_DBLE     8
 578 #define EXCP09_XERR     9
 579 #define EXCP0A_TSS      10
 580 #define EXCP0B_NOSEG    11
 581 #define EXCP0C_STACK    12
 582 #define EXCP0D_GPF      13
 583 #define EXCP0E_PAGE     14
 584 #define EXCP10_COPR     16
 585 #define EXCP11_ALGN     17
 586 #define EXCP12_MCHK     18
 587
 588 #define EXCP_SYSCALL    0x100 /* only happens in user only emulation
 589                                  for syscall instruction */
 590
 591 /* i386-specific interrupt pending bits.  */
 592 #define CPU_INTERRUPT_POLL      CPU_INTERRUPT_TGT_EXT_1
 593 #define CPU_INTERRUPT_SMI       CPU_INTERRUPT_TGT_EXT_2
 594 #define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3
 595 #define CPU_INTERRUPT_MCE       CPU_INTERRUPT_TGT_EXT_4
 596 #define CPU_INTERRUPT_VIRQ      CPU_INTERRUPT_TGT_INT_0
 597 #define CPU_INTERRUPT_INIT      CPU_INTERRUPT_TGT_INT_1
 598 #define CPU_INTERRUPT_SIPI      CPU_INTERRUPT_TGT_INT_2
 599 #define CPU_INTERRUPT_TPR       CPU_INTERRUPT_TGT_INT_3
 600
 601
 602 typedef enum {
 603     CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
 604     CC_OP_EFLAGS,  /* all cc are explicitly computed, CC_SRC = flags */
 605
 606     CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
 607     CC_OP_MULW,
 608     CC_OP_MULL,
 609     CC_OP_MULQ,
 610
 611     CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 612     CC_OP_ADDW,
 613     CC_OP_ADDL,
 614     CC_OP_ADDQ,
 615
 616     CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 617     CC_OP_ADCW,
 618     CC_OP_ADCL,
 619     CC_OP_ADCQ,
 620
 621     CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 622     CC_OP_SUBW,
 623     CC_OP_SUBL,
 624     CC_OP_SUBQ,
 625
 626     CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 627     CC_OP_SBBW,
 628     CC_OP_SBBL,
 629     CC_OP_SBBQ,
 630
 631     CC_OP_LOGICB, /* modify all flags, CC_DST = res */
 632     CC_OP_LOGICW,
 633     CC_OP_LOGICL,
 634     CC_OP_LOGICQ,
 635
 636     CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
 637     CC_OP_INCW,
 638     CC_OP_INCL,
 639     CC_OP_INCQ,
 640
 641     CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C  */
 642     CC_OP_DECW,
 643     CC_OP_DECL,
 644     CC_OP_DECQ,
 645
 646     CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
 647     CC_OP_SHLW,
 648     CC_OP_SHLL,
 649     CC_OP_SHLQ,
 650
 651     CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
 652     CC_OP_SARW,
 653     CC_OP_SARL,
 654     CC_OP_SARQ,
 655
 656     CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */
 657     CC_OP_BMILGW,
 658     CC_OP_BMILGL,
 659     CC_OP_BMILGQ,
 660
 661     CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest.  */
 662     CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest.  */
 663     CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest.  */
 664
 665     CC_OP_CLR, /* Z set, all other flags clear.  */
 666
 667     CC_OP_NB,
 668 } CCOp;
 669
 670 typedef struct SegmentCache {
 671     uint32_t selector;
 672     target_ulong base;
 673     uint32_t limit;
 674     uint32_t flags;
 675 } SegmentCache;
 676
 677 typedef union {
 678     uint8_t _b[16];
 679     uint16_t _w[8];
 680     uint32_t _l[4];
 681     uint64_t _q[2];
 682     float32 _s[4];
 683     float64 _d[2];
 684 } XMMReg;
 685
 686 typedef union {
 687     uint8_t _b[8];
 688     uint16_t _w[4];
 689     uint32_t _l[2];
 690     float32 _s[2];
 691     uint64_t q;
 692 } MMXReg;
 693
 694 #ifdef HOST_WORDS_BIGENDIAN
 695 #define XMM_B(n) _b[15 - (n)]
 696 #define XMM_W(n) _w[7 - (n)]
 697 #define XMM_L(n) _l[3 - (n)]
 698 #define XMM_S(n) _s[3 - (n)]
 699 #define XMM_Q(n) _q[1 - (n)]
 700 #define XMM_D(n) _d[1 - (n)]
 701
 702 #define MMX_B(n) _b[7 - (n)]
 703 #define MMX_W(n) _w[3 - (n)]
 704 #define MMX_L(n) _l[1 - (n)]
 705 #define MMX_S(n) _s[1 - (n)]
 706 #else
 707 #define XMM_B(n) _b[n]
 708 #define XMM_W(n) _w[n]
 709 #define XMM_L(n) _l[n]
 710 #define XMM_S(n) _s[n]
 711 #define XMM_Q(n) _q[n]
 712 #define XMM_D(n) _d[n]
 713
 714 #define MMX_B(n) _b[n]
 715 #define MMX_W(n) _w[n]
 716 #define MMX_L(n) _l[n]
 717 #define MMX_S(n) _s[n]
 718 #endif
 719 #define MMX_Q(n) q
 720
 721 typedef union {
 722     floatx80 d __attribute__((aligned(16)));
 723     MMXReg mmx;
 724 } FPReg;
 725
 726 typedef struct {
 727     uint64_t base;
 728     uint64_t mask;
 729 } MTRRVar;
 730
 731 #define CPU_NB_REGS64 16
 732 #define CPU_NB_REGS32 8
 733
 734 #ifdef TARGET_X86_64
 735 #define CPU_NB_REGS CPU_NB_REGS64
 736 #else
 737 #define CPU_NB_REGS CPU_NB_REGS32
 738 #endif
 739
 740 #define MAX_FIXED_COUNTERS 3
 741 #define MAX_GP_COUNTERS    (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0)
 742
 743 #define NB_MMU_MODES 3
 744
 745 typedef enum TPRAccess {
 746     TPR_ACCESS_READ,
 747     TPR_ACCESS_WRITE,
 748 } TPRAccess;
 749
 750 typedef struct CPUX86State {
 751     /* standard registers */
 752     target_ulong regs[CPU_NB_REGS];
 753     target_ulong eip;
 754     target_ulong eflags; /* eflags register. During CPU emulation, CC
 755                         flags and DF are set to zero because they are
 756                         stored elsewhere */
 757
 758     /* emulator internal eflags handling */
 759     target_ulong cc_dst;
 760     target_ulong cc_src;
 761     target_ulong cc_src2;
 762     uint32_t cc_op;
 763     int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
 764     uint32_t hflags; /* TB flags, see HF_xxx constants. These flags
 765                         are known at translation time. */
 766     uint32_t hflags2; /* various other flags, see HF2_xxx constants. */
 767
 768     /* segments */
 769     SegmentCache segs[6]; /* selector values */
 770     SegmentCache ldt;
 771     SegmentCache tr;
 772     SegmentCache gdt; /* only base and limit are used */
 773     SegmentCache idt; /* only base and limit are used */
 774
 775     target_ulong cr[5]; /* NOTE: cr1 is unused */
 776     int32_t a20_mask;
 777
 778     /* FPU state */
 779     unsigned int fpstt; /* top of stack index */
 780     uint16_t fpus;
 781     uint16_t fpuc;
 782     uint8_t fptags[8];   /* 0 = valid, 1 = empty */
 783     FPReg fpregs[8];
 784     /* KVM-only so far */
 785     uint16_t fpop;
 786     uint64_t fpip;
 787     uint64_t fpdp;
 788
 789     /* emulator internal variables */
 790     float_status fp_status;
 791     floatx80 ft0;
 792
 793     float_status mmx_status; /* for 3DNow! float ops */
 794     float_status sse_status;
 795     uint32_t mxcsr;
 796     XMMReg xmm_regs[CPU_NB_REGS];
 797     XMMReg xmm_t0;
 798     MMXReg mmx_t0;
 799
 800     /* sysenter registers */
 801     uint32_t sysenter_cs;
 802     target_ulong sysenter_esp;
 803     target_ulong sysenter_eip;
 804     uint64_t efer;
 805     uint64_t star;
 806
 807     uint64_t vm_hsave;
 808     uint64_t vm_vmcb;
 809     uint64_t tsc_offset;
 810     uint64_t intercept;
 811     uint16_t intercept_cr_read;
 812     uint16_t intercept_cr_write;
 813     uint16_t intercept_dr_read;
 814     uint16_t intercept_dr_write;
 815     uint32_t intercept_exceptions;
 816     uint8_t v_tpr;
 817
 818 #ifdef TARGET_X86_64
 819     target_ulong lstar;
 820     target_ulong cstar;
 821     target_ulong fmask;
 822     target_ulong kernelgsbase;
 823 #endif
 824     uint64_t system_time_msr;
 825     uint64_t wall_clock_msr;
 826     uint64_t steal_time_msr;
 827     uint64_t async_pf_en_msr;
 828     uint64_t pv_eoi_en_msr;
 829
 830     uint64_t tsc;
 831     uint64_t tsc_adjust;
 832     uint64_t tsc_deadline;
 833
 834     uint64_t mcg_status;
 835     uint64_t msr_ia32_misc_enable;
 836     uint64_t msr_ia32_feature_control;
 837
 838     uint64_t msr_fixed_ctr_ctrl;
 839     uint64_t msr_global_ctrl;
 840     uint64_t msr_global_status;
 841     uint64_t msr_global_ovf_ctrl;
 842     uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS];
 843     uint64_t msr_gp_counters[MAX_GP_COUNTERS];
 844     uint64_t msr_gp_evtsel[MAX_GP_COUNTERS];
 845
 846     /* exception/interrupt handling */
 847     int error_code;
 848     int exception_is_int;
 849     target_ulong exception_next_eip;
 850     target_ulong dr[8]; /* debug registers */
 851     union {
 852         CPUBreakpoint *cpu_breakpoint[4];
 853         CPUWatchpoint *cpu_watchpoint[4];
 854     }; /* break/watchpoints for dr[0..3] */
 855     uint32_t smbase;
 856     int old_exception;  /* exception in flight */
 857
 858     /* KVM states, automatically cleared on reset */
 859     uint8_t nmi_injected;
 860     uint8_t nmi_pending;
 861
 862     CPU_COMMON
 863
 864     uint64_t pat;
 865
 866     /* processor features (e.g. for CPUID insn) */
 867     uint32_t cpuid_level;
 868     uint32_t cpuid_xlevel;
 869     uint32_t cpuid_xlevel2;
 870     uint32_t cpuid_vendor1;
 871     uint32_t cpuid_vendor2;
 872     uint32_t cpuid_vendor3;
 873     uint32_t cpuid_version;
 874     FeatureWordArray features;
 875     uint32_t cpuid_model[12];
 876     uint32_t cpuid_apic_id;
 877
 878     /* MTRRs */
 879     uint64_t mtrr_fixed[11];
 880     uint64_t mtrr_deftype;
 881     MTRRVar mtrr_var[8];
 882
 883     /* For KVM */
 884     uint32_t mp_state;
 885     int32_t exception_injected;
 886     int32_t interrupt_injected;
 887     uint8_t soft_interrupt;
 888     uint8_t has_error_code;
 889     uint32_t sipi_vector;
 890     bool tsc_valid;
 891     int tsc_khz;
 892     void *kvm_xsave_buf;
 893
 894     /* in order to simplify APIC support, we leave this pointer to the
 895        user */
 896     struct DeviceState *apic_state;
 897
 898     uint64_t mcg_cap;
 899     uint64_t mcg_ctl;
 900     uint64_t mce_banks[MCE_BANKS_DEF*4];
 901
 902     uint64_t tsc_aux;
 903
 904     /* vmstate */
 905     uint16_t fpus_vmstate;
 906     uint16_t fptag_vmstate;
 907     uint16_t fpregs_format_vmstate;
 908
 909     uint64_t xstate_bv;
 910     XMMReg ymmh_regs[CPU_NB_REGS];
 911
 912     uint64_t xcr0;
 913
 914     TPRAccess tpr_access_type;
 915 } CPUX86State;
 916
 917 #include "cpu-qom.h"
 918
 919 X86CPU *cpu_x86_init(const char *cpu_model);
 920 X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
 921                        Error **errp);
 922 int cpu_x86_exec(CPUX86State *s);
 923 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 924 void x86_cpudef_setup(void);
 925 int cpu_x86_support_mca_broadcast(CPUX86State *env);
 926
 927 int cpu_get_pic_interrupt(CPUX86State *s);
 928 /* MSDOS compatibility mode FPU exception support */
 929 void cpu_set_ferr(CPUX86State *s);
 930
 931 /* this function must always be used to load data in the segment
 932    cache: it synchronizes the hflags with the segment cache values */
 933 static inline void cpu_x86_load_seg_cache(CPUX86State *env,
 934                                           int seg_reg, unsigned int selector,
 935                                           target_ulong base,
 936                                           unsigned int limit,
 937                                           unsigned int flags)
 938 {
 939     SegmentCache *sc;
 940     unsigned int new_hflags;
 941
 942     sc = &env->segs[seg_reg];
 943     sc->selector = selector;
 944     sc->base = base;
 945     sc->limit = limit;
 946     sc->flags = flags;
 947
 948     /* update the hidden flags */
 949     {
 950         if (seg_reg == R_CS) {
 951 #ifdef TARGET_X86_64
 952             if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
 953                 /* long mode */
 954                 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 955                 env->hflags &= ~(HF_ADDSEG_MASK);
 956             } else
 957 #endif
 958             {
 959                 /* legacy / compatibility case */
 960                 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
 961                     >> (DESC_B_SHIFT - HF_CS32_SHIFT);
 962                 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
 963                     new_hflags;
 964             }
 965         }
 966         new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
 967             >> (DESC_B_SHIFT - HF_SS32_SHIFT);
 968         if (env->hflags & HF_CS64_MASK) {
 969             /* zero base assumed for DS, ES and SS in long mode */
 970         } else if (!(env->cr[0] & CR0_PE_MASK) ||
 971                    (env->eflags & VM_MASK) ||
 972                    !(env->hflags & HF_CS32_MASK)) {
 973             /* XXX: try to avoid this test. The problem comes from the
 974                fact that is real mode or vm86 mode we only modify the
 975                'base' and 'selector' fields of the segment cache to go
 976                faster. A solution may be to force addseg to one in
 977                translate-i386.c. */
 978             new_hflags |= HF_ADDSEG_MASK;
 979         } else {
 980             new_hflags |= ((env->segs[R_DS].base |
 981                             env->segs[R_ES].base |
 982                             env->segs[R_SS].base) != 0) <<
 983                 HF_ADDSEG_SHIFT;
 984         }
 985         env->hflags = (env->hflags &
 986                        ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
 987     }
 988 }
 989
 990 static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu,
 991                                                int sipi_vector)
 992 {
 993     CPUState *cs = CPU(cpu);
 994     CPUX86State *env = &cpu->env;
 995
 996     env->eip = 0;
 997     cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8,
 998                            sipi_vector << 12,
 999                            env->segs[R_CS].limit,
1000                            env->segs[R_CS].flags);
1001     cs->halted = 0;
1002 }
1003
1004 int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
1005                             target_ulong *base, unsigned int *limit,
1006                             unsigned int *flags);
1007
1008 /* wrapper, just in case memory mappings must be changed */
1009 static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
1010 {
1011 #if HF_CPL_MASK == 3
1012     s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl;
1013 #else
1014 #error HF_CPL_MASK is hardcoded
1015 #endif
1016 }
1017
1018 /* op_helper.c */
1019 /* used for debug or cpu save/restore */
1020 void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, floatx80 f);
1021 floatx80 cpu_set_fp80(uint64_t mant, uint16_t upper);
1022
1023 /* cpu-exec.c */
1024 /* the following helpers are only usable in user mode simulation as
1025    they can trigger unexpected exceptions */
1026 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
1027 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
1028 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
1029
1030 /* you can call this signal handler from your SIGBUS and SIGSEGV
1031    signal handlers to inform the virtual CPU of exceptions. non zero
1032    is returned if the signal was handled by the virtual CPU.  */
1033 int cpu_x86_signal_handler(int host_signum, void *pinfo,
1034                            void *puc);
1035
1036 /* cpuid.c */
1037 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1038                    uint32_t *eax, uint32_t *ebx,
1039                    uint32_t *ecx, uint32_t *edx);
1040 void cpu_clear_apic_feature(CPUX86State *env);
1041 void host_cpuid(uint32_t function, uint32_t count,
1042                 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
1043
1044 /* helper.c */
1045 int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
1046                              int is_write, int mmu_idx);
1047 #define cpu_handle_mmu_fault cpu_x86_handle_mmu_fault
1048 void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
1049
1050 static inline bool hw_local_breakpoint_enabled(unsigned long dr7, int index)
1051 {
1052     return (dr7 >> (index * 2)) & 1;
1053 }
1054
1055 static inline bool hw_global_breakpoint_enabled(unsigned long dr7, int index)
1056 {
1057     return (dr7 >> (index * 2)) & 2;
1058
1059 }
1060 static inline bool hw_breakpoint_enabled(unsigned long dr7, int index)
1061 {
1062     return hw_global_breakpoint_enabled(dr7, index) ||
1063            hw_local_breakpoint_enabled(dr7, index);
1064 }
1065
1066 static inline int hw_breakpoint_type(unsigned long dr7, int index)
1067 {
1068     return (dr7 >> (DR7_TYPE_SHIFT + (index * 4))) & 3;
1069 }
1070
1071 static inline int hw_breakpoint_len(unsigned long dr7, int index)
1072 {
1073     int len = ((dr7 >> (DR7_LEN_SHIFT + (index * 4))) & 3);
1074     return (len == 2) ? 8 : len + 1;
1075 }
1076
1077 void hw_breakpoint_insert(CPUX86State *env, int index);
1078 void hw_breakpoint_remove(CPUX86State *env, int index);
1079 bool check_hw_breakpoints(CPUX86State *env, bool force_dr6_update);
1080 void breakpoint_handler(CPUX86State *env);
1081
1082 /* will be suppressed */
1083 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
1084 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
1085 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
1086
1087 /* hw/pc.c */
1088 void cpu_smm_update(CPUX86State *env);
1089 uint64_t cpu_get_tsc(CPUX86State *env);
1090
1091 #define TARGET_PAGE_BITS 12
1092
1093 #ifdef TARGET_X86_64
1094 #define TARGET_PHYS_ADDR_SPACE_BITS 52
1095 /* ??? This is really 48 bits, sign-extended, but the only thing
1096    accessible to userland with bit 48 set is the VSYSCALL, and that
1097    is handled via other mechanisms.  */
1098 #define TARGET_VIRT_ADDR_SPACE_BITS 47
1099 #else
1100 #define TARGET_PHYS_ADDR_SPACE_BITS 36
1101 #define TARGET_VIRT_ADDR_SPACE_BITS 32
1102 #endif
1103
1104 static inline CPUX86State *cpu_init(const char *cpu_model)
1105 {
1106     X86CPU *cpu = cpu_x86_init(cpu_model);
1107     if (cpu == NULL) {
1108         return NULL;
1109     }
1110     return &cpu->env;
1111 }
1112
1113 #define cpu_exec cpu_x86_exec
1114 #define cpu_gen_code cpu_x86_gen_code
1115 #define cpu_signal_handler cpu_x86_signal_handler
1116 #define cpu_list x86_cpu_list
1117 #define cpudef_setup x86_cpudef_setup
1118
1119 /* MMU modes definitions */
1120 #define MMU_MODE0_SUFFIX _kernel
1121 #define MMU_MODE1_SUFFIX _user
1122 #define MMU_MODE2_SUFFIX _ksmap /* Kernel with SMAP override */
1123 #define MMU_KERNEL_IDX  0
1124 #define MMU_USER_IDX    1
1125 #define MMU_KSMAP_IDX   2
1126 static inline int cpu_mmu_index (CPUX86State *env)
1127 {
1128     return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX :
1129         ((env->hflags & HF_SMAP_MASK) && (env->eflags & AC_MASK))
1130         ? MMU_KSMAP_IDX : MMU_KERNEL_IDX;
1131 }
1132
1133 #define CC_DST  (env->cc_dst)
1134 #define CC_SRC  (env->cc_src)
1135 #define CC_SRC2 (env->cc_src2)
1136 #define CC_OP   (env->cc_op)
1137
1138 /* n must be a constant to be efficient */
1139 static inline target_long lshift(target_long x, int n)
1140 {
1141     if (n >= 0) {
1142         return x << n;
1143     } else {
1144         return x >> (-n);
1145     }
1146 }
1147
1148 /* float macros */
1149 #define FT0    (env->ft0)
1150 #define ST0    (env->fpregs[env->fpstt].d)
1151 #define ST(n)  (env->fpregs[(env->fpstt + (n)) & 7].d)
1152 #define ST1    ST(1)
1153
1154 /* translate.c */
1155 void optimize_flags_init(void);
1156
1157 #include "exec/cpu-all.h"
1158 #include "svm.h"
1159
1160 #if !defined(CONFIG_USER_ONLY)
1161 #include "hw/i386/apic.h"
1162 #endif
1163
1164 static inline bool cpu_has_work(CPUState *cs)
1165 {
1166     X86CPU *cpu = X86_CPU(cs);
1167     CPUX86State *env = &cpu->env;
1168
1169     return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
1170                                       CPU_INTERRUPT_POLL)) &&
1171             (env->eflags & IF_MASK)) ||
1172            (cs->interrupt_request & (CPU_INTERRUPT_NMI |
1173                                      CPU_INTERRUPT_INIT |
1174                                      CPU_INTERRUPT_SIPI |
1175                                      CPU_INTERRUPT_MCE));
1176 }
1177
1178 #include "exec/exec-all.h"
1179
1180 static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc,
1181                                         target_ulong *cs_base, int *flags)
1182 {
1183     *cs_base = env->segs[R_CS].base;
1184     *pc = *cs_base + env->eip;
1185     *flags = env->hflags |
1186         (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK));
1187 }
1188
1189 void do_cpu_init(X86CPU *cpu);
1190 void do_cpu_sipi(X86CPU *cpu);
1191
1192 #define MCE_INJECT_BROADCAST    1
1193 #define MCE_INJECT_UNCOND_AO    2
1194
1195 void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
1196                         uint64_t status, uint64_t mcg_status, uint64_t addr,
1197                         uint64_t misc, int flags);
1198
1199 /* excp_helper.c */
1200 void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index);
1201 void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index,
1202                                        int error_code);
1203 void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int,
1204                                    int error_code, int next_eip_addend);
1205
1206 /* cc_helper.c */
1207 extern const uint8_t parity_table[256];
1208 uint32_t cpu_cc_compute_all(CPUX86State *env1, int op);
1209
1210 static inline uint32_t cpu_compute_eflags(CPUX86State *env)
1211 {
1212     return env->eflags | cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK);
1213 }
1214
1215 /* NOTE: CC_OP must be modified manually to CC_OP_EFLAGS */
1216 static inline void cpu_load_eflags(CPUX86State *env, int eflags,
1217                                    int update_mask)
1218 {
1219     CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
1220     env->df = 1 - (2 * ((eflags >> 10) & 1));
1221     env->eflags = (env->eflags & ~update_mask) |
1222         (eflags & update_mask) | 0x2;
1223 }
1224
1225 /* load efer and update the corresponding hflags. XXX: do consistency
1226    checks with cpuid bits? */
1227 static inline void cpu_load_efer(CPUX86State *env, uint64_t val)
1228 {
1229     env->efer = val;
1230     env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK);
1231     if (env->efer & MSR_EFER_LMA) {
1232         env->hflags |= HF_LMA_MASK;
1233     }
1234     if (env->efer & MSR_EFER_SVME) {
1235         env->hflags |= HF_SVME_MASK;
1236     }
1237 }
1238
1239 /* svm_helper.c */
1240 void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
1241                                    uint64_t param);
1242 void cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, uint64_t exit_info_1);
1243
1244 /* seg_helper.c */
1245 void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw);
1246
1247 void do_smm_enter(X86CPU *cpu);
1248
1249 void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
1250
1251 void disable_kvm_pv_eoi(void);
1252
1253 void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
1254                                  uint32_t feat_add, uint32_t feat_remove);
1255
1256
1257 /* Return name of 32-bit register, from a R_* constant */
1258 const char *get_register_name_32(unsigned int reg);
1259
1260 uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index);
1261 void enable_compat_apic_id_mode(void);
1262
1263 #define APIC_DEFAULT_ADDRESS 0xfee00000
1264 #define APIC_SPACE_SIZE      0x100000
1265
1266 #endif /* CPU_I386_H */