include/hw/i386/pc.h

   1 #ifndef HW_PC_H
   2 #define HW_PC_H
   3
   4 #include "qemu-common.h"
   5 #include "exec/memory.h"
   6 #include "hw/isa/isa.h"
   7 #include "hw/block/fdc.h"
   8 #include "net/net.h"
   9 #include "hw/i386/ioapic.h"
  10
  11 #include "qemu/range.h"
  12 #include "qemu/bitmap.h"
  13 #include "sysemu/sysemu.h"
  14 #include "hw/pci/pci.h"
  15
  16 /* PC-style peripherals (also used by other machines).  */
  17
  18 typedef struct PcPciInfo {
  19     Range w32;
  20     Range w64;
  21 } PcPciInfo;
  22
  23 #define ACPI_PM_PROP_S3_DISABLED "disable_s3"
  24 #define ACPI_PM_PROP_S4_DISABLED "disable_s4"
  25 #define ACPI_PM_PROP_S4_VAL "s4_val"
  26 #define ACPI_PM_PROP_SCI_INT "sci_int"
  27 #define ACPI_PM_PROP_ACPI_ENABLE_CMD "acpi_enable_cmd"
  28 #define ACPI_PM_PROP_ACPI_DISABLE_CMD "acpi_disable_cmd"
  29 #define ACPI_PM_PROP_PM_IO_BASE "pm_io_base"
  30 #define ACPI_PM_PROP_GPE0_BLK "gpe0_blk"
  31 #define ACPI_PM_PROP_GPE0_BLK_LEN "gpe0_blk_len"
  32
  33 struct PcGuestInfo {
  34     bool has_pci_info;
  35     bool isapc_ram_fw;
  36     hwaddr ram_size;
  37     unsigned apic_id_limit;
  38     bool apic_xrupt_override;
  39     uint64_t numa_nodes;
  40     uint64_t *node_mem;
  41     uint64_t *node_cpu;
  42     FWCfgState *fw_cfg;
  43     bool has_acpi_build;
  44 };
  45
  46 /* parallel.c */
  47 static inline bool parallel_init(ISABus *bus, int index, CharDriverState *chr)
  48 {
  49     DeviceState *dev;
  50     ISADevice *isadev;
  51
  52     isadev = isa_try_create(bus, "isa-parallel");
  53     if (!isadev) {
  54         return false;
  55     }
  56     dev = DEVICE(isadev);
  57     qdev_prop_set_uint32(dev, "index", index);
  58     qdev_prop_set_chr(dev, "chardev", chr);
  59     if (qdev_init(dev) < 0) {
  60         return false;
  61     }
  62     return true;
  63 }
  64
  65 bool parallel_mm_init(MemoryRegion *address_space,
  66                       hwaddr base, int it_shift, qemu_irq irq,
  67                       CharDriverState *chr);
  68
  69 /* i8259.c */
  70
  71 extern DeviceState *isa_pic;
  72 qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
  73 qemu_irq *kvm_i8259_init(ISABus *bus);
  74 int pic_read_irq(DeviceState *d);
  75 int pic_get_output(DeviceState *d);
  76 void pic_info(Monitor *mon, const QDict *qdict);
  77 void irq_info(Monitor *mon, const QDict *qdict);
  78
  79 /* Global System Interrupts */
  80
  81 #define GSI_NUM_PINS IOAPIC_NUM_PINS
  82
  83 typedef struct GSIState {
  84     qemu_irq i8259_irq[ISA_NUM_IRQS];
  85     qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
  86 } GSIState;
  87
  88 void gsi_handler(void *opaque, int n, int level);
  89
  90 /* vmport.c */
  91 typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address);
  92
  93 static inline void vmport_init(ISABus *bus)
  94 {
  95     isa_create_simple(bus, "vmport");
  96 }
  97
  98 void vmport_register(unsigned char command, VMPortReadFunc *func, void *opaque);
  99 void vmmouse_get_data(uint32_t *data);
 100 void vmmouse_set_data(const uint32_t *data);
 101
 102 /* pckbd.c */
 103
 104 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
 105 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
 106                    MemoryRegion *region, ram_addr_t size,
 107                    hwaddr mask);
 108 void i8042_isa_mouse_fake_event(void *opaque);
 109 void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out);
 110
 111 /* pc.c */
 112 extern int fd_bootchk;
 113
 114 void pc_register_ferr_irq(qemu_irq irq);
 115 void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
 116
 117 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge);
 118 void pc_hot_add_cpu(const int64_t id, Error **errp);
 119 void pc_acpi_init(const char *default_dsdt);
 120
 121 PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
 122                                 ram_addr_t above_4g_mem_size);
 123
 124 #define PCI_HOST_PROP_PCI_HOLE_START   "pci-hole-start"
 125 #define PCI_HOST_PROP_PCI_HOLE_END     "pci-hole-end"
 126 #define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start"
 127 #define PCI_HOST_PROP_PCI_HOLE64_END   "pci-hole64-end"
 128 #define PCI_HOST_PROP_PCI_HOLE64_SIZE  "pci-hole64-size"
 129 #define DEFAULT_PCI_HOLE64_SIZE (~0x0ULL)
 130
 131 static inline uint64_t pci_host_get_hole64_size(uint64_t pci_hole64_size)
 132 {
 133     if (pci_hole64_size == DEFAULT_PCI_HOLE64_SIZE) {
 134         return 1ULL << 62;
 135     } else {
 136         return pci_hole64_size;
 137     }
 138 }
 139
 140 void pc_init_pci64_hole(PcPciInfo *pci_info, uint64_t pci_hole64_start,
 141                         uint64_t pci_hole64_size);
 142
 143 FWCfgState *pc_memory_init(MemoryRegion *system_memory,
 144                            const char *kernel_filename,
 145                            const char *kernel_cmdline,
 146                            const char *initrd_filename,
 147                            ram_addr_t below_4g_mem_size,
 148                            ram_addr_t above_4g_mem_size,
 149                            MemoryRegion *rom_memory,
 150                            MemoryRegion **ram_memory,
 151                            PcGuestInfo *guest_info);
 152 qemu_irq *pc_allocate_cpu_irq(void);
 153 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus);
 154 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
 155                           ISADevice **rtc_state,
 156                           ISADevice **floppy,
 157                           bool no_vmport);
 158 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd);
 159 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 160                   const char *boot_device,
 161                   ISADevice *floppy, BusState *ide0, BusState *ide1,
 162                   ISADevice *s);
 163 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus);
 164 void pc_pci_device_init(PCIBus *pci_bus);
 165
 166 typedef void (*cpu_set_smm_t)(int smm, void *arg);
 167 void cpu_smm_register(cpu_set_smm_t callback, void *arg);
 168
 169 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);
 170
 171 /* acpi_piix.c */
 172
 173 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 174                        qemu_irq sci_irq, qemu_irq smi_irq,
 175                        int kvm_enabled, FWCfgState *fw_cfg);
 176 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
 177
 178 /* hpet.c */
 179 extern int no_hpet;
 180
 181 /* piix_pci.c */
 182 struct PCII440FXState;
 183 typedef struct PCII440FXState PCII440FXState;
 184
 185 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn,
 186                     ISABus **isa_bus, qemu_irq *pic,
 187                     MemoryRegion *address_space_mem,
 188                     MemoryRegion *address_space_io,
 189                     ram_addr_t ram_size,
 190                     hwaddr pci_hole_start,
 191                     hwaddr pci_hole_size,
 192                     ram_addr_t above_4g_mem_size,
 193                     MemoryRegion *pci_memory,
 194                     MemoryRegion *ram_memory);
 195
 196 PCIBus *find_i440fx(void);
 197 /* piix4.c */
 198 extern PCIDevice *piix4_dev;
 199 int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
 200
 201 /* vga.c */
 202 enum vga_retrace_method {
 203     VGA_RETRACE_DUMB,
 204     VGA_RETRACE_PRECISE
 205 };
 206
 207 extern enum vga_retrace_method vga_retrace_method;
 208
 209 int isa_vga_mm_init(hwaddr vram_base,
 210                     hwaddr ctrl_base, int it_shift,
 211                     MemoryRegion *address_space);
 212
 213 /* ne2000.c */
 214 static inline bool isa_ne2000_init(ISABus *bus, int base, int irq, NICInfo *nd)
 215 {
 216     DeviceState *dev;
 217     ISADevice *isadev;
 218
 219     qemu_check_nic_model(nd, "ne2k_isa");
 220
 221     isadev = isa_try_create(bus, "ne2k_isa");
 222     if (!isadev) {
 223         return false;
 224     }
 225     dev = DEVICE(isadev);
 226     qdev_prop_set_uint32(dev, "iobase", base);
 227     qdev_prop_set_uint32(dev, "irq",    irq);
 228     qdev_set_nic_properties(dev, nd);
 229     qdev_init_nofail(dev);
 230     return true;
 231 }
 232
 233 /* pc_sysfw.c */
 234 void pc_system_firmware_init(MemoryRegion *rom_memory,
 235                              bool isapc_ram_fw);
 236
 237 /* pvpanic.c */
 238 uint16_t pvpanic_port(void);
 239
 240 /* e820 types */
 241 #define E820_RAM        1
 242 #define E820_RESERVED   2
 243 #define E820_ACPI       3
 244 #define E820_NVS        4
 245 #define E820_UNUSABLE   5
 246
 247 int e820_add_entry(uint64_t, uint64_t, uint32_t);
 248
 249 #define PC_COMPAT_1_6 \
 250         {\
 251             .driver   = "e1000",\
 252             .property = "mitigation",\
 253             .value    = "off",\
 254         },{\
 255             .driver   = "qemu64-" TYPE_X86_CPU,\
 256             .property = "model",\
 257             .value    = stringify(2),\
 258         },{\
 259             .driver   = "qemu32-" TYPE_X86_CPU,\
 260             .property = "model",\
 261             .value    = stringify(3),\
 262         },{\
 263             .driver   = "i440FX-pcihost",\
 264             .property = "short_root_bus",\
 265             .value    = stringify(1),\
 266         },{\
 267             .driver   = "q35-pcihost",\
 268             .property = "short_root_bus",\
 269             .value    = stringify(1),\
 270         }
 271
 272 #define PC_COMPAT_1_5 \
 273         PC_COMPAT_1_6, \
 274         {\
 275             .driver   = "Conroe-" TYPE_X86_CPU,\
 276             .property = "model",\
 277             .value    = stringify(2),\
 278         },{\
 279             .driver   = "Conroe-" TYPE_X86_CPU,\
 280             .property = "level",\
 281             .value    = stringify(2),\
 282         },{\
 283             .driver   = "Penryn-" TYPE_X86_CPU,\
 284             .property = "model",\
 285             .value    = stringify(2),\
 286         },{\
 287             .driver   = "Penryn-" TYPE_X86_CPU,\
 288             .property = "level",\
 289             .value    = stringify(2),\
 290         },{\
 291             .driver   = "Nehalem-" TYPE_X86_CPU,\
 292             .property = "model",\
 293             .value    = stringify(2),\
 294         },{\
 295             .driver   = "Nehalem-" TYPE_X86_CPU,\
 296             .property = "level",\
 297             .value    = stringify(2),\
 298         },{\
 299             .driver   = "virtio-net-pci",\
 300             .property = "any_layout",\
 301             .value    = "off",\
 302         },{\
 303             .driver = TYPE_X86_CPU,\
 304             .property = "pmu",\
 305             .value = "on",\
 306         },{\
 307             .driver   = "i440FX-pcihost",\
 308             .property = "short_root_bus",\
 309             .value    = stringify(0),\
 310         },{\
 311             .driver   = "q35-pcihost",\
 312             .property = "short_root_bus",\
 313             .value    = stringify(0),\
 314         }
 315
 316 #define PC_COMPAT_1_4 \
 317         PC_COMPAT_1_5, \
 318         {\
 319             .driver   = "scsi-hd",\
 320             .property = "discard_granularity",\
 321             .value    = stringify(0),\
 322         },{\
 323             .driver   = "scsi-cd",\
 324             .property = "discard_granularity",\
 325             .value    = stringify(0),\
 326         },{\
 327             .driver   = "scsi-disk",\
 328             .property = "discard_granularity",\
 329             .value    = stringify(0),\
 330         },{\
 331             .driver   = "ide-hd",\
 332             .property = "discard_granularity",\
 333             .value    = stringify(0),\
 334         },{\
 335             .driver   = "ide-cd",\
 336             .property = "discard_granularity",\
 337             .value    = stringify(0),\
 338         },{\
 339             .driver   = "ide-drive",\
 340             .property = "discard_granularity",\
 341             .value    = stringify(0),\
 342         },{\
 343             .driver   = "virtio-blk-pci",\
 344             .property = "discard_granularity",\
 345             .value    = stringify(0),\
 346         },{\
 347             .driver   = "virtio-serial-pci",\
 348             .property = "vectors",\
 349             /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string */\
 350             .value    = stringify(0xFFFFFFFF),\
 351         },{ \
 352             .driver   = "virtio-net-pci", \
 353             .property = "ctrl_guest_offloads", \
 354             .value    = "off", \
 355         },{\
 356             .driver   = "e1000",\
 357             .property = "romfile",\
 358             .value    = "pxe-e1000.rom",\
 359         },{\
 360             .driver   = "ne2k_pci",\
 361             .property = "romfile",\
 362             .value    = "pxe-ne2k_pci.rom",\
 363         },{\
 364             .driver   = "pcnet",\
 365             .property = "romfile",\
 366             .value    = "pxe-pcnet.rom",\
 367         },{\
 368             .driver   = "rtl8139",\
 369             .property = "romfile",\
 370             .value    = "pxe-rtl8139.rom",\
 371         },{\
 372             .driver   = "virtio-net-pci",\
 373             .property = "romfile",\
 374             .value    = "pxe-virtio.rom",\
 375         },{\
 376             .driver   = "486-" TYPE_X86_CPU,\
 377             .property = "model",\
 378             .value    = stringify(0),\
 379         }
 380
 381 #define PC_COMMON_MACHINE_OPTIONS \
 382     .default_boot_order = "cad"
 383
 384 #define PC_DEFAULT_MACHINE_OPTIONS \
 385     PC_COMMON_MACHINE_OPTIONS, \
 386     .hot_add_cpu = pc_hot_add_cpu, \
 387     .max_cpus = 255
 388
 389 #endif