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migration: Allow user to specify available switchover bandwidth
[qemu/kevin.git] / hw / net / ftgmac100.c
blob702b001be2ff0c6148f377d0433e15c4f61693c2
1 /*
2 * Faraday FTGMAC100 Gigabit Ethernet
3 *
4 * Copyright (C) 2016-2017, IBM Corporation.
5 *
6 * Based on Coldfire Fast Ethernet Controller emulation.
7 *
8 * Copyright (c) 2007 CodeSourcery.
9 *
10 * This code is licensed under the GPL version 2 or later. See the
11 * COPYING file in the top-level directory.
12 */
13
14 #include "qemu/osdep.h"
15 #include "hw/irq.h"
16 #include "hw/net/ftgmac100.h"
17 #include "sysemu/dma.h"
18 #include "qapi/error.h"
19 #include "qemu/log.h"
20 #include "qemu/module.h"
21 #include "net/checksum.h"
22 #include "net/eth.h"
23 #include "hw/net/mii.h"
24 #include "hw/qdev-properties.h"
25 #include "migration/vmstate.h"
26
27 /* For crc32 */
28 #include <zlib.h>
29
30 /*
31 * FTGMAC100 registers
32 */
33 #define FTGMAC100_ISR 0x00
34 #define FTGMAC100_IER 0x04
35 #define FTGMAC100_MAC_MADR 0x08
36 #define FTGMAC100_MAC_LADR 0x0c
37 #define FTGMAC100_MATH0 0x10
38 #define FTGMAC100_MATH1 0x14
39 #define FTGMAC100_NPTXPD 0x18
40 #define FTGMAC100_RXPD 0x1C
41 #define FTGMAC100_NPTXR_BADR 0x20
42 #define FTGMAC100_RXR_BADR 0x24
43 #define FTGMAC100_HPTXPD 0x28
44 #define FTGMAC100_HPTXR_BADR 0x2c
45 #define FTGMAC100_ITC 0x30
46 #define FTGMAC100_APTC 0x34
47 #define FTGMAC100_DBLAC 0x38
48 #define FTGMAC100_REVR 0x40
49 #define FTGMAC100_FEAR1 0x44
50 #define FTGMAC100_RBSR 0x4c
51 #define FTGMAC100_TPAFCR 0x48
52
53 #define FTGMAC100_MACCR 0x50
54 #define FTGMAC100_MACSR 0x54
55 #define FTGMAC100_PHYCR 0x60
56 #define FTGMAC100_PHYDATA 0x64
57 #define FTGMAC100_FCR 0x68
58
59 /*
60 * Interrupt status register & interrupt enable register
61 */
62 #define FTGMAC100_INT_RPKT_BUF (1 << 0)
63 #define FTGMAC100_INT_RPKT_FIFO (1 << 1)
64 #define FTGMAC100_INT_NO_RXBUF (1 << 2)
65 #define FTGMAC100_INT_RPKT_LOST (1 << 3)
66 #define FTGMAC100_INT_XPKT_ETH (1 << 4)
67 #define FTGMAC100_INT_XPKT_FIFO (1 << 5)
68 #define FTGMAC100_INT_NO_NPTXBUF (1 << 6)
69 #define FTGMAC100_INT_XPKT_LOST (1 << 7)
70 #define FTGMAC100_INT_AHB_ERR (1 << 8)
71 #define FTGMAC100_INT_PHYSTS_CHG (1 << 9)
72 #define FTGMAC100_INT_NO_HPTXBUF (1 << 10)
73
74 /*
75 * Automatic polling timer control register
76 */
77 #define FTGMAC100_APTC_RXPOLL_CNT(x) ((x) & 0xf)
78 #define FTGMAC100_APTC_RXPOLL_TIME_SEL (1 << 4)
79 #define FTGMAC100_APTC_TXPOLL_CNT(x) (((x) >> 8) & 0xf)
80 #define FTGMAC100_APTC_TXPOLL_TIME_SEL (1 << 12)
81
82 /*
83 * DMA burst length and arbitration control register
84 */
85 #define FTGMAC100_DBLAC_RXBURST_SIZE(x) (((x) >> 8) & 0x3)
86 #define FTGMAC100_DBLAC_TXBURST_SIZE(x) (((x) >> 10) & 0x3)
87 #define FTGMAC100_DBLAC_RXDES_SIZE(x) ((((x) >> 12) & 0xf) * 8)
88 #define FTGMAC100_DBLAC_TXDES_SIZE(x) ((((x) >> 16) & 0xf) * 8)
89 #define FTGMAC100_DBLAC_IFG_CNT(x) (((x) >> 20) & 0x7)
90 #define FTGMAC100_DBLAC_IFG_INC (1 << 23)
91
92 /*
93 * PHY control register
94 */
95 #define FTGMAC100_PHYCR_MIIRD (1 << 26)
96 #define FTGMAC100_PHYCR_MIIWR (1 << 27)
97
98 #define FTGMAC100_PHYCR_DEV(x) (((x) >> 16) & 0x1f)
99 #define FTGMAC100_PHYCR_REG(x) (((x) >> 21) & 0x1f)
100
101 /*
102 * PHY data register
103 */
104 #define FTGMAC100_PHYDATA_MIIWDATA(x) ((x) & 0xffff)
105 #define FTGMAC100_PHYDATA_MIIRDATA(x) (((x) >> 16) & 0xffff)
106
107 /*
108 * PHY control register - New MDC/MDIO interface
109 */
110 #define FTGMAC100_PHYCR_NEW_DATA(x) (((x) >> 16) & 0xffff)
111 #define FTGMAC100_PHYCR_NEW_FIRE (1 << 15)
112 #define FTGMAC100_PHYCR_NEW_ST_22 (1 << 12)
113 #define FTGMAC100_PHYCR_NEW_OP(x) (((x) >> 10) & 3)
114 #define FTGMAC100_PHYCR_NEW_OP_WRITE 0x1
115 #define FTGMAC100_PHYCR_NEW_OP_READ 0x2
116 #define FTGMAC100_PHYCR_NEW_DEV(x) (((x) >> 5) & 0x1f)
117 #define FTGMAC100_PHYCR_NEW_REG(x) ((x) & 0x1f)
118
119 /*
120 * Feature Register
121 */
122 #define FTGMAC100_REVR_NEW_MDIO_INTERFACE (1 << 31)
123
124 /*
125 * MAC control register
126 */
127 #define FTGMAC100_MACCR_TXDMA_EN (1 << 0)
128 #define FTGMAC100_MACCR_RXDMA_EN (1 << 1)
129 #define FTGMAC100_MACCR_TXMAC_EN (1 << 2)
130 #define FTGMAC100_MACCR_RXMAC_EN (1 << 3)
131 #define FTGMAC100_MACCR_RM_VLAN (1 << 4)
132 #define FTGMAC100_MACCR_HPTXR_EN (1 << 5)
133 #define FTGMAC100_MACCR_LOOP_EN (1 << 6)
134 #define FTGMAC100_MACCR_ENRX_IN_HALFTX (1 << 7)
135 #define FTGMAC100_MACCR_FULLDUP (1 << 8)
136 #define FTGMAC100_MACCR_GIGA_MODE (1 << 9)
137 #define FTGMAC100_MACCR_CRC_APD (1 << 10) /* not needed */
138 #define FTGMAC100_MACCR_RX_RUNT (1 << 12)
139 #define FTGMAC100_MACCR_JUMBO_LF (1 << 13)
140 #define FTGMAC100_MACCR_RX_ALL (1 << 14)
141 #define FTGMAC100_MACCR_HT_MULTI_EN (1 << 15)
142 #define FTGMAC100_MACCR_RX_MULTIPKT (1 << 16)
143 #define FTGMAC100_MACCR_RX_BROADPKT (1 << 17)
144 #define FTGMAC100_MACCR_DISCARD_CRCERR (1 << 18)
145 #define FTGMAC100_MACCR_FAST_MODE (1 << 19)
146 #define FTGMAC100_MACCR_SW_RST (1 << 31)
147
148 /*
149 * Transmit descriptor
150 */
151 #define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff)
152 #define FTGMAC100_TXDES0_EDOTR (1 << 15)
153 #define FTGMAC100_TXDES0_CRC_ERR (1 << 19)
154 #define FTGMAC100_TXDES0_LTS (1 << 28)
155 #define FTGMAC100_TXDES0_FTS (1 << 29)
156 #define FTGMAC100_TXDES0_EDOTR_ASPEED (1 << 30)
157 #define FTGMAC100_TXDES0_TXDMA_OWN (1 << 31)
158
159 #define FTGMAC100_TXDES1_VLANTAG_CI(x) ((x) & 0xffff)
160 #define FTGMAC100_TXDES1_INS_VLANTAG (1 << 16)
161 #define FTGMAC100_TXDES1_TCP_CHKSUM (1 << 17)
162 #define FTGMAC100_TXDES1_UDP_CHKSUM (1 << 18)
163 #define FTGMAC100_TXDES1_IP_CHKSUM (1 << 19)
164 #define FTGMAC100_TXDES1_LLC (1 << 22)
165 #define FTGMAC100_TXDES1_TX2FIC (1 << 30)
166 #define FTGMAC100_TXDES1_TXIC (1 << 31)
167
168 /*
169 * Receive descriptor
170 */
171 #define FTGMAC100_RXDES0_VDBC 0x3fff
172 #define FTGMAC100_RXDES0_EDORR (1 << 15)
173 #define FTGMAC100_RXDES0_MULTICAST (1 << 16)
174 #define FTGMAC100_RXDES0_BROADCAST (1 << 17)
175 #define FTGMAC100_RXDES0_RX_ERR (1 << 18)
176 #define FTGMAC100_RXDES0_CRC_ERR (1 << 19)
177 #define FTGMAC100_RXDES0_FTL (1 << 20)
178 #define FTGMAC100_RXDES0_RUNT (1 << 21)
179 #define FTGMAC100_RXDES0_RX_ODD_NB (1 << 22)
180 #define FTGMAC100_RXDES0_FIFO_FULL (1 << 23)
181 #define FTGMAC100_RXDES0_PAUSE_OPCODE (1 << 24)
182 #define FTGMAC100_RXDES0_PAUSE_FRAME (1 << 25)
183 #define FTGMAC100_RXDES0_LRS (1 << 28)
184 #define FTGMAC100_RXDES0_FRS (1 << 29)
185 #define FTGMAC100_RXDES0_EDORR_ASPEED (1 << 30)
186 #define FTGMAC100_RXDES0_RXPKT_RDY (1 << 31)
187
188 #define FTGMAC100_RXDES1_VLANTAG_CI 0xffff
189 #define FTGMAC100_RXDES1_PROT_MASK (0x3 << 20)
190 #define FTGMAC100_RXDES1_PROT_NONIP (0x0 << 20)
191 #define FTGMAC100_RXDES1_PROT_IP (0x1 << 20)
192 #define FTGMAC100_RXDES1_PROT_TCPIP (0x2 << 20)
193 #define FTGMAC100_RXDES1_PROT_UDPIP (0x3 << 20)
194 #define FTGMAC100_RXDES1_LLC (1 << 22)
195 #define FTGMAC100_RXDES1_DF (1 << 23)
196 #define FTGMAC100_RXDES1_VLANTAG_AVAIL (1 << 24)
197 #define FTGMAC100_RXDES1_TCP_CHKSUM_ERR (1 << 25)
198 #define FTGMAC100_RXDES1_UDP_CHKSUM_ERR (1 << 26)
199 #define FTGMAC100_RXDES1_IP_CHKSUM_ERR (1 << 27)
200
201 /*
202 * Receive and transmit Buffer Descriptor
203 */
204 typedef struct {
205 uint32_t des0;
206 uint32_t des1;
207 uint32_t des2; /* not used by HW */
208 uint32_t des3;
209 } FTGMAC100Desc;
210
211 #define FTGMAC100_DESC_ALIGNMENT 16
212
213 /*
214 * Specific RTL8211E MII Registers
215 */
216 #define RTL8211E_MII_PHYCR 16 /* PHY Specific Control */
217 #define RTL8211E_MII_PHYSR 17 /* PHY Specific Status */
218 #define RTL8211E_MII_INER 18 /* Interrupt Enable */
219 #define RTL8211E_MII_INSR 19 /* Interrupt Status */
220 #define RTL8211E_MII_RXERC 24 /* Receive Error Counter */
221 #define RTL8211E_MII_LDPSR 27 /* Link Down Power Saving */
222 #define RTL8211E_MII_EPAGSR 30 /* Extension Page Select */
223 #define RTL8211E_MII_PAGSEL 31 /* Page Select */
224
225 /*
226 * RTL8211E Interrupt Status
227 */
228 #define PHY_INT_AUTONEG_ERROR (1 << 15)
229 #define PHY_INT_PAGE_RECV (1 << 12)
230 #define PHY_INT_AUTONEG_COMPLETE (1 << 11)
231 #define PHY_INT_LINK_STATUS (1 << 10)
232 #define PHY_INT_ERROR (1 << 9)
233 #define PHY_INT_DOWN (1 << 8)
234 #define PHY_INT_JABBER (1 << 0)
235
236 /*
237 * Max frame size for the receiving buffer
238 */
239 #define FTGMAC100_MAX_FRAME_SIZE 9220
240
241 /* Limits depending on the type of the frame
242 *
243 * 9216 for Jumbo frames (+ 4 for VLAN)
244 * 1518 for other frames (+ 4 for VLAN)
245 */
246 static int ftgmac100_max_frame_size(FTGMAC100State *s, uint16_t proto)
247 {
248 int max = (s->maccr & FTGMAC100_MACCR_JUMBO_LF ? 9216 : 1518);
249
250 return max + (proto == ETH_P_VLAN ? 4 : 0);
251 }
252
253 static void ftgmac100_update_irq(FTGMAC100State *s)
254 {
255 qemu_set_irq(s->irq, s->isr & s->ier);
256 }
257
258 /*
259 * The MII phy could raise a GPIO to the processor which in turn
260 * could be handled as an interrpt by the OS.
261 * For now we don't handle any GPIO/interrupt line, so the OS will
262 * have to poll for the PHY status.
263 */
264 static void phy_update_irq(FTGMAC100State *s)
265 {
266 ftgmac100_update_irq(s);
267 }
268
269 static void phy_update_link(FTGMAC100State *s)
270 {
271 /* Autonegotiation status mirrors link status. */
272 if (qemu_get_queue(s->nic)->link_down) {
273 s->phy_status &= ~(MII_BMSR_LINK_ST | MII_BMSR_AN_COMP);
274 s->phy_int |= PHY_INT_DOWN;
275 } else {
276 s->phy_status |= (MII_BMSR_LINK_ST | MII_BMSR_AN_COMP);
277 s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
278 }
279 phy_update_irq(s);
280 }
281
282 static void ftgmac100_set_link(NetClientState *nc)
283 {
284 phy_update_link(FTGMAC100(qemu_get_nic_opaque(nc)));
285 }
286
287 static void phy_reset(FTGMAC100State *s)
288 {
289 s->phy_status = (MII_BMSR_100TX_FD | MII_BMSR_100TX_HD | MII_BMSR_10T_FD |
290 MII_BMSR_10T_HD | MII_BMSR_EXTSTAT | MII_BMSR_MFPS |
291 MII_BMSR_AN_COMP | MII_BMSR_AUTONEG | MII_BMSR_LINK_ST |
292 MII_BMSR_EXTCAP);
293 s->phy_control = (MII_BMCR_AUTOEN | MII_BMCR_FD | MII_BMCR_SPEED1000);
294 s->phy_advertise = (MII_ANAR_PAUSE_ASYM | MII_ANAR_PAUSE | MII_ANAR_TXFD |
295 MII_ANAR_TX | MII_ANAR_10FD | MII_ANAR_10 |
296 MII_ANAR_CSMACD);
297 s->phy_int_mask = 0;
298 s->phy_int = 0;
299 }
300
301 static uint16_t do_phy_read(FTGMAC100State *s, uint8_t reg)
302 {
303 uint16_t val;
304
305 switch (reg) {
306 case MII_BMCR: /* Basic Control */
307 val = s->phy_control;
308 break;
309 case MII_BMSR: /* Basic Status */
310 val = s->phy_status;
311 break;
312 case MII_PHYID1: /* ID1 */
313 val = RTL8211E_PHYID1;
314 break;
315 case MII_PHYID2: /* ID2 */
316 val = RTL8211E_PHYID2;
317 break;
318 case MII_ANAR: /* Auto-neg advertisement */
319 val = s->phy_advertise;
320 break;
321 case MII_ANLPAR: /* Auto-neg Link Partner Ability */
322 val = (MII_ANLPAR_ACK | MII_ANLPAR_PAUSE | MII_ANLPAR_TXFD |
323 MII_ANLPAR_TX | MII_ANLPAR_10FD | MII_ANLPAR_10 |
324 MII_ANLPAR_CSMACD);
325 break;
326 case MII_ANER: /* Auto-neg Expansion */
327 val = MII_ANER_NWAY;
328 break;
329 case MII_CTRL1000: /* 1000BASE-T control */
330 val = (MII_CTRL1000_HALF | MII_CTRL1000_FULL);
331 break;
332 case MII_STAT1000: /* 1000BASE-T status */
333 val = MII_STAT1000_FULL;
334 break;
335 case RTL8211E_MII_INSR: /* Interrupt status. */
336 val = s->phy_int;
337 s->phy_int = 0;
338 phy_update_irq(s);
339 break;
340 case RTL8211E_MII_INER: /* Interrupt enable */
341 val = s->phy_int_mask;
342 break;
343 case RTL8211E_MII_PHYCR:
344 case RTL8211E_MII_PHYSR:
345 case RTL8211E_MII_RXERC:
346 case RTL8211E_MII_LDPSR:
347 case RTL8211E_MII_EPAGSR:
348 case RTL8211E_MII_PAGSEL:
349 qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n",
350 __func__, reg);
351 val = 0;
352 break;
353 default:
354 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n",
355 __func__, reg);
356 val = 0;
357 break;
358 }
359
360 return val;
361 }
362
363 #define MII_BMCR_MASK (MII_BMCR_LOOPBACK | MII_BMCR_SPEED100 | \
364 MII_BMCR_SPEED | MII_BMCR_AUTOEN | MII_BMCR_PDOWN | \
365 MII_BMCR_FD | MII_BMCR_CTST)
366 #define MII_ANAR_MASK 0x2d7f
367
368 static void do_phy_write(FTGMAC100State *s, uint8_t reg, uint16_t val)
369 {
370 switch (reg) {
371 case MII_BMCR: /* Basic Control */
372 if (val & MII_BMCR_RESET) {
373 phy_reset(s);
374 } else {
375 s->phy_control = val & MII_BMCR_MASK;
376 /* Complete autonegotiation immediately. */
377 if (val & MII_BMCR_AUTOEN) {
378 s->phy_status |= MII_BMSR_AN_COMP;
379 }
380 }
381 break;
382 case MII_ANAR: /* Auto-neg advertisement */
383 s->phy_advertise = (val & MII_ANAR_MASK) | MII_ANAR_TX;
384 break;
385 case RTL8211E_MII_INER: /* Interrupt enable */
386 s->phy_int_mask = val & 0xff;
387 phy_update_irq(s);
388 break;
389 case RTL8211E_MII_PHYCR:
390 case RTL8211E_MII_PHYSR:
391 case RTL8211E_MII_RXERC:
392 case RTL8211E_MII_LDPSR:
393 case RTL8211E_MII_EPAGSR:
394 case RTL8211E_MII_PAGSEL:
395 qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n",
396 __func__, reg);
397 break;
398 default:
399 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n",
400 __func__, reg);
401 break;
402 }
403 }
404
405 static void do_phy_new_ctl(FTGMAC100State *s)
406 {
407 uint8_t reg;
408 uint16_t data;
409
410 if (!(s->phycr & FTGMAC100_PHYCR_NEW_ST_22)) {
411 qemu_log_mask(LOG_UNIMP, "%s: unsupported ST code\n", __func__);
412 return;
413 }
414
415 /* Nothing to do */
416 if (!(s->phycr & FTGMAC100_PHYCR_NEW_FIRE)) {
417 return;
418 }
419
420 reg = FTGMAC100_PHYCR_NEW_REG(s->phycr);
421 data = FTGMAC100_PHYCR_NEW_DATA(s->phycr);
422
423 switch (FTGMAC100_PHYCR_NEW_OP(s->phycr)) {
424 case FTGMAC100_PHYCR_NEW_OP_WRITE:
425 do_phy_write(s, reg, data);
426 break;
427 case FTGMAC100_PHYCR_NEW_OP_READ:
428 s->phydata = do_phy_read(s, reg) & 0xffff;
429 break;
430 default:
431 qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid OP code %08x\n",
432 __func__, s->phycr);
433 }
434
435 s->phycr &= ~FTGMAC100_PHYCR_NEW_FIRE;
436 }
437
438 static void do_phy_ctl(FTGMAC100State *s)
439 {
440 uint8_t reg = FTGMAC100_PHYCR_REG(s->phycr);
441
442 if (s->phycr & FTGMAC100_PHYCR_MIIWR) {
443 do_phy_write(s, reg, s->phydata & 0xffff);
444 s->phycr &= ~FTGMAC100_PHYCR_MIIWR;
445 } else if (s->phycr & FTGMAC100_PHYCR_MIIRD) {
446 s->phydata = do_phy_read(s, reg) << 16;
447 s->phycr &= ~FTGMAC100_PHYCR_MIIRD;
448 } else {
449 qemu_log_mask(LOG_GUEST_ERROR, "%s: no OP code %08x\n",
450 __func__, s->phycr);
451 }
452 }
453
454 static int ftgmac100_read_bd(FTGMAC100Desc *bd, dma_addr_t addr)
455 {
456 if (dma_memory_read(&address_space_memory, addr,
457 bd, sizeof(*bd), MEMTXATTRS_UNSPECIFIED)) {
458 qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to read descriptor @ 0x%"
459 HWADDR_PRIx "\n", __func__, addr);
460 return -1;
461 }
462 bd->des0 = le32_to_cpu(bd->des0);
463 bd->des1 = le32_to_cpu(bd->des1);
464 bd->des2 = le32_to_cpu(bd->des2);
465 bd->des3 = le32_to_cpu(bd->des3);
466 return 0;
467 }
468
469 static int ftgmac100_write_bd(FTGMAC100Desc *bd, dma_addr_t addr)
470 {
471 FTGMAC100Desc lebd;
472
473 lebd.des0 = cpu_to_le32(bd->des0);
474 lebd.des1 = cpu_to_le32(bd->des1);
475 lebd.des2 = cpu_to_le32(bd->des2);
476 lebd.des3 = cpu_to_le32(bd->des3);
477 if (dma_memory_write(&address_space_memory, addr,
478 &lebd, sizeof(lebd), MEMTXATTRS_UNSPECIFIED)) {
479 qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to write descriptor @ 0x%"
480 HWADDR_PRIx "\n", __func__, addr);
481 return -1;
482 }
483 return 0;
484 }
485
486 static int ftgmac100_insert_vlan(FTGMAC100State *s, int frame_size,
487 uint8_t vlan_tci)
488 {
489 uint8_t *vlan_hdr = s->frame + (ETH_ALEN * 2);
490 uint8_t *payload = vlan_hdr + sizeof(struct vlan_header);
491
492 if (frame_size < sizeof(struct eth_header)) {
493 qemu_log_mask(LOG_GUEST_ERROR,
494 "%s: frame too small for VLAN insertion : %d bytes\n",
495 __func__, frame_size);
496 s->isr |= FTGMAC100_INT_XPKT_LOST;
497 goto out;
498 }
499
500 if (frame_size + sizeof(struct vlan_header) > sizeof(s->frame)) {
501 qemu_log_mask(LOG_GUEST_ERROR,
502 "%s: frame too big : %d bytes\n",
503 __func__, frame_size);
504 s->isr |= FTGMAC100_INT_XPKT_LOST;
505 frame_size -= sizeof(struct vlan_header);
506 }
507
508 memmove(payload, vlan_hdr, frame_size - (ETH_ALEN * 2));
509 stw_be_p(vlan_hdr, ETH_P_VLAN);
510 stw_be_p(vlan_hdr + 2, vlan_tci);
511 frame_size += sizeof(struct vlan_header);
512
513 out:
514 return frame_size;
515 }
516
517 static void ftgmac100_do_tx(FTGMAC100State *s, uint32_t tx_ring,
518 uint32_t tx_descriptor)
519 {
520 int frame_size = 0;
521 uint8_t *ptr = s->frame;
522 uint32_t addr = tx_descriptor;
523 uint32_t flags = 0;
524
525 while (1) {
526 FTGMAC100Desc bd;
527 int len;
528
529 if (ftgmac100_read_bd(&bd, addr) ||
530 ((bd.des0 & FTGMAC100_TXDES0_TXDMA_OWN) == 0)) {
531 /* Run out of descriptors to transmit. */
532 s->isr |= FTGMAC100_INT_NO_NPTXBUF;
533 break;
534 }
535
536 /* record transmit flags as they are valid only on the first
537 * segment */
538 if (bd.des0 & FTGMAC100_TXDES0_FTS) {
539 flags = bd.des1;
540 }
541
542 len = FTGMAC100_TXDES0_TXBUF_SIZE(bd.des0);
543 if (!len) {
544 /*
545 * 0 is an invalid size, however the HW does not raise any
546 * interrupt. Flag an error because the guest is buggy.
547 */
548 qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid segment size\n",
549 __func__);
550 }
551
552 if (frame_size + len > sizeof(s->frame)) {
553 qemu_log_mask(LOG_GUEST_ERROR, "%s: frame too big : %d bytes\n",
554 __func__, len);
555 s->isr |= FTGMAC100_INT_XPKT_LOST;
556 len = sizeof(s->frame) - frame_size;
557 }
558
559 if (dma_memory_read(&address_space_memory, bd.des3,
560 ptr, len, MEMTXATTRS_UNSPECIFIED)) {
561 qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to read packet @ 0x%x\n",
562 __func__, bd.des3);
563 s->isr |= FTGMAC100_INT_AHB_ERR;
564 break;
565 }
566
567 ptr += len;
568 frame_size += len;
569 if (bd.des0 & FTGMAC100_TXDES0_LTS) {
570 int csum = 0;
571
572 /* Check for VLAN */
573 if (flags & FTGMAC100_TXDES1_INS_VLANTAG &&
574 be16_to_cpu(PKT_GET_ETH_HDR(s->frame)->h_proto) != ETH_P_VLAN) {
575 frame_size = ftgmac100_insert_vlan(s, frame_size,
576 FTGMAC100_TXDES1_VLANTAG_CI(flags));
577 }
578
579 if (flags & FTGMAC100_TXDES1_IP_CHKSUM) {
580 csum |= CSUM_IP;
581 }
582 if (flags & FTGMAC100_TXDES1_TCP_CHKSUM) {
583 csum |= CSUM_TCP;
584 }
585 if (flags & FTGMAC100_TXDES1_UDP_CHKSUM) {
586 csum |= CSUM_UDP;
587 }
588 if (csum) {
589 net_checksum_calculate(s->frame, frame_size, csum);
590 }
591
592 /* Last buffer in frame. */
593 qemu_send_packet(qemu_get_queue(s->nic), s->frame, frame_size);
594 ptr = s->frame;
595 frame_size = 0;
596 s->isr |= FTGMAC100_INT_XPKT_ETH;
597 }
598
599 if (flags & FTGMAC100_TXDES1_TX2FIC) {
600 s->isr |= FTGMAC100_INT_XPKT_FIFO;
601 }
602 bd.des0 &= ~FTGMAC100_TXDES0_TXDMA_OWN;
603
604 /* Write back the modified descriptor. */
605 ftgmac100_write_bd(&bd, addr);
606 /* Advance to the next descriptor. */
607 if (bd.des0 & s->txdes0_edotr) {
608 addr = tx_ring;
609 } else {
610 addr += FTGMAC100_DBLAC_TXDES_SIZE(s->dblac);
611 }
612 }
613
614 s->tx_descriptor = addr;
615
616 ftgmac100_update_irq(s);
617 }
618
619 static bool ftgmac100_can_receive(NetClientState *nc)
620 {
621 FTGMAC100State *s = FTGMAC100(qemu_get_nic_opaque(nc));
622 FTGMAC100Desc bd;
623
624 if ((s->maccr & (FTGMAC100_MACCR_RXDMA_EN | FTGMAC100_MACCR_RXMAC_EN))
625 != (FTGMAC100_MACCR_RXDMA_EN | FTGMAC100_MACCR_RXMAC_EN)) {
626 return false;
627 }
628
629 if (ftgmac100_read_bd(&bd, s->rx_descriptor)) {
630 return false;
631 }
632 return !(bd.des0 & FTGMAC100_RXDES0_RXPKT_RDY);
633 }
634
635 /*
636 * This is purely informative. The HW can poll the RW (and RX) ring
637 * buffers for available descriptors but we don't need to trigger a
638 * timer for that in qemu.
639 */
640 static uint32_t ftgmac100_rxpoll(FTGMAC100State *s)
641 {
642 /* Polling times :
643 *
644 * Speed TIME_SEL=0 TIME_SEL=1
645 *
646 * 10 51.2 ms 819.2 ms
647 * 100 5.12 ms 81.92 ms
648 * 1000 1.024 ms 16.384 ms
649 */
650 static const int div[] = { 20, 200, 1000 };
651
652 uint32_t cnt = 1024 * FTGMAC100_APTC_RXPOLL_CNT(s->aptcr);
653 uint32_t speed = (s->maccr & FTGMAC100_MACCR_FAST_MODE) ? 1 : 0;
654
655 if (s->aptcr & FTGMAC100_APTC_RXPOLL_TIME_SEL) {
656 cnt <<= 4;
657 }
658
659 if (s->maccr & FTGMAC100_MACCR_GIGA_MODE) {
660 speed = 2;
661 }
662
663 return cnt / div[speed];
664 }
665
666 static void ftgmac100_do_reset(FTGMAC100State *s, bool sw_reset)
667 {
668 /* Reset the FTGMAC100 */
669 s->isr = 0;
670 s->ier = 0;
671 s->rx_enabled = 0;
672 s->rx_ring = 0;
673 s->rbsr = 0x640;
674 s->rx_descriptor = 0;
675 s->tx_ring = 0;
676 s->tx_descriptor = 0;
677 s->math[0] = 0;
678 s->math[1] = 0;
679 s->itc = 0;
680 s->aptcr = 1;
681 s->dblac = 0x00022f00;
682 s->revr = 0;
683 s->fear1 = 0;
684 s->tpafcr = 0xf1;
685
686 if (sw_reset) {
687 s->maccr &= FTGMAC100_MACCR_GIGA_MODE | FTGMAC100_MACCR_FAST_MODE;
688 } else {
689 s->maccr = 0;
690 }
691
692 s->phycr = 0;
693 s->phydata = 0;
694 s->fcr = 0x400;
695
696 /* and the PHY */
697 phy_reset(s);
698 }
699
700 static void ftgmac100_reset(DeviceState *d)
701 {
702 ftgmac100_do_reset(FTGMAC100(d), false);
703 }
704
705 static uint64_t ftgmac100_read(void *opaque, hwaddr addr, unsigned size)
706 {
707 FTGMAC100State *s = FTGMAC100(opaque);
708
709 switch (addr & 0xff) {
710 case FTGMAC100_ISR:
711 return s->isr;
712 case FTGMAC100_IER:
713 return s->ier;
714 case FTGMAC100_MAC_MADR:
715 return (s->conf.macaddr.a[0] << 8) | s->conf.macaddr.a[1];
716 case FTGMAC100_MAC_LADR:
717 return ((uint32_t) s->conf.macaddr.a[2] << 24) |
718 (s->conf.macaddr.a[3] << 16) | (s->conf.macaddr.a[4] << 8) |
719 s->conf.macaddr.a[5];
720 case FTGMAC100_MATH0:
721 return s->math[0];
722 case FTGMAC100_MATH1:
723 return s->math[1];
724 case FTGMAC100_RXR_BADR:
725 return s->rx_ring;
726 case FTGMAC100_NPTXR_BADR:
727 return s->tx_ring;
728 case FTGMAC100_ITC:
729 return s->itc;
730 case FTGMAC100_DBLAC:
731 return s->dblac;
732 case FTGMAC100_REVR:
733 return s->revr;
734 case FTGMAC100_FEAR1:
735 return s->fear1;
736 case FTGMAC100_TPAFCR:
737 return s->tpafcr;
738 case FTGMAC100_FCR:
739 return s->fcr;
740 case FTGMAC100_MACCR:
741 return s->maccr;
742 case FTGMAC100_PHYCR:
743 return s->phycr;
744 case FTGMAC100_PHYDATA:
745 return s->phydata;
746
747 /* We might want to support these one day */
748 case FTGMAC100_HPTXPD: /* High Priority Transmit Poll Demand */
749 case FTGMAC100_HPTXR_BADR: /* High Priority Transmit Ring Base Address */
750 case FTGMAC100_MACSR: /* MAC Status Register (MACSR) */
751 qemu_log_mask(LOG_UNIMP, "%s: read to unimplemented register 0x%"
752 HWADDR_PRIx "\n", __func__, addr);
753 return 0;
754 default:
755 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset 0x%"
756 HWADDR_PRIx "\n", __func__, addr);
757 return 0;
758 }
759 }
760
761 static void ftgmac100_write(void *opaque, hwaddr addr,
762 uint64_t value, unsigned size)
763 {
764 FTGMAC100State *s = FTGMAC100(opaque);
765
766 switch (addr & 0xff) {
767 case FTGMAC100_ISR: /* Interrupt status */
768 s->isr &= ~value;
769 break;
770 case FTGMAC100_IER: /* Interrupt control */
771 s->ier = value;
772 break;
773 case FTGMAC100_MAC_MADR: /* MAC */
774 s->conf.macaddr.a[0] = value >> 8;
775 s->conf.macaddr.a[1] = value;
776 break;
777 case FTGMAC100_MAC_LADR:
778 s->conf.macaddr.a[2] = value >> 24;
779 s->conf.macaddr.a[3] = value >> 16;
780 s->conf.macaddr.a[4] = value >> 8;
781 s->conf.macaddr.a[5] = value;
782 break;
783 case FTGMAC100_MATH0: /* Multicast Address Hash Table 0 */
784 s->math[0] = value;
785 break;
786 case FTGMAC100_MATH1: /* Multicast Address Hash Table 1 */
787 s->math[1] = value;
788 break;
789 case FTGMAC100_ITC: /* TODO: Interrupt Timer Control */
790 s->itc = value;
791 break;
792 case FTGMAC100_RXR_BADR: /* Ring buffer address */
793 if (!QEMU_IS_ALIGNED(value, FTGMAC100_DESC_ALIGNMENT)) {
794 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad RX buffer alignment 0x%"
795 HWADDR_PRIx "\n", __func__, value);
796 return;
797 }
798
799 s->rx_ring = value;
800 s->rx_descriptor = s->rx_ring;
801 break;
802
803 case FTGMAC100_RBSR: /* DMA buffer size */
804 s->rbsr = value;
805 break;
806
807 case FTGMAC100_NPTXR_BADR: /* Transmit buffer address */
808 if (!QEMU_IS_ALIGNED(value, FTGMAC100_DESC_ALIGNMENT)) {
809 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad TX buffer alignment 0x%"
810 HWADDR_PRIx "\n", __func__, value);
811 return;
812 }
813 s->tx_ring = value;
814 s->tx_descriptor = s->tx_ring;
815 break;
816
817 case FTGMAC100_NPTXPD: /* Trigger transmit */
818 if ((s->maccr & (FTGMAC100_MACCR_TXDMA_EN | FTGMAC100_MACCR_TXMAC_EN))
819 == (FTGMAC100_MACCR_TXDMA_EN | FTGMAC100_MACCR_TXMAC_EN)) {
820 /* TODO: high priority tx ring */
821 ftgmac100_do_tx(s, s->tx_ring, s->tx_descriptor);
822 }
823 if (ftgmac100_can_receive(qemu_get_queue(s->nic))) {
824 qemu_flush_queued_packets(qemu_get_queue(s->nic));
825 }
826 break;
827
828 case FTGMAC100_RXPD: /* Receive Poll Demand Register */
829 if (ftgmac100_can_receive(qemu_get_queue(s->nic))) {
830 qemu_flush_queued_packets(qemu_get_queue(s->nic));
831 }
832 break;
833
834 case FTGMAC100_APTC: /* Automatic polling */
835 s->aptcr = value;
836
837 if (FTGMAC100_APTC_RXPOLL_CNT(s->aptcr)) {
838 ftgmac100_rxpoll(s);
839 }
840
841 if (FTGMAC100_APTC_TXPOLL_CNT(s->aptcr)) {
842 qemu_log_mask(LOG_UNIMP, "%s: no transmit polling\n", __func__);
843 }
844 break;
845
846 case FTGMAC100_MACCR: /* MAC Device control */
847 s->maccr = value;
848 if (value & FTGMAC100_MACCR_SW_RST) {
849 ftgmac100_do_reset(s, true);
850 }
851
852 if (ftgmac100_can_receive(qemu_get_queue(s->nic))) {
853 qemu_flush_queued_packets(qemu_get_queue(s->nic));
854 }
855 break;
856
857 case FTGMAC100_PHYCR: /* PHY Device control */
858 s->phycr = value;
859 if (s->revr & FTGMAC100_REVR_NEW_MDIO_INTERFACE) {
860 do_phy_new_ctl(s);
861 } else {
862 do_phy_ctl(s);
863 }
864 break;
865 case FTGMAC100_PHYDATA:
866 s->phydata = value & 0xffff;
867 break;
868 case FTGMAC100_DBLAC: /* DMA Burst Length and Arbitration Control */
869 if (FTGMAC100_DBLAC_TXDES_SIZE(value) < sizeof(FTGMAC100Desc)) {
870 qemu_log_mask(LOG_GUEST_ERROR,
871 "%s: transmit descriptor too small: %" PRIx64
872 " bytes\n", __func__,
873 FTGMAC100_DBLAC_TXDES_SIZE(value));
874 break;
875 }
876 if (FTGMAC100_DBLAC_RXDES_SIZE(value) < sizeof(FTGMAC100Desc)) {
877 qemu_log_mask(LOG_GUEST_ERROR,
878 "%s: receive descriptor too small : %" PRIx64
879 " bytes\n", __func__,
880 FTGMAC100_DBLAC_RXDES_SIZE(value));
881 break;
882 }
883 s->dblac = value;
884 break;
885 case FTGMAC100_REVR: /* Feature Register */
886 s->revr = value;
887 break;
888 case FTGMAC100_FEAR1: /* Feature Register 1 */
889 s->fear1 = value;
890 break;
891 case FTGMAC100_TPAFCR: /* Transmit Priority Arbitration and FIFO Control */
892 s->tpafcr = value;
893 break;
894 case FTGMAC100_FCR: /* Flow Control */
895 s->fcr = value;
896 break;
897
898 case FTGMAC100_HPTXPD: /* High Priority Transmit Poll Demand */
899 case FTGMAC100_HPTXR_BADR: /* High Priority Transmit Ring Base Address */
900 case FTGMAC100_MACSR: /* MAC Status Register (MACSR) */
901 qemu_log_mask(LOG_UNIMP, "%s: write to unimplemented register 0x%"
902 HWADDR_PRIx "\n", __func__, addr);
903 break;
904 default:
905 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset 0x%"
906 HWADDR_PRIx "\n", __func__, addr);
907 break;
908 }
909
910 ftgmac100_update_irq(s);
911 }
912
913 static int ftgmac100_filter(FTGMAC100State *s, const uint8_t *buf, size_t len)
914 {
915 unsigned mcast_idx;
916
917 if (s->maccr & FTGMAC100_MACCR_RX_ALL) {
918 return 1;
919 }
920
921 switch (get_eth_packet_type(PKT_GET_ETH_HDR(buf))) {
922 case ETH_PKT_BCAST:
923 if (!(s->maccr & FTGMAC100_MACCR_RX_BROADPKT)) {
924 return 0;
925 }
926 break;
927 case ETH_PKT_MCAST:
928 if (!(s->maccr & FTGMAC100_MACCR_RX_MULTIPKT)) {
929 if (!(s->maccr & FTGMAC100_MACCR_HT_MULTI_EN)) {
930 return 0;
931 }
932
933 mcast_idx = net_crc32_le(buf, ETH_ALEN);
934 mcast_idx = (~(mcast_idx >> 2)) & 0x3f;
935 if (!(s->math[mcast_idx / 32] & (1 << (mcast_idx % 32)))) {
936 return 0;
937 }
938 }
939 break;
940 case ETH_PKT_UCAST:
941 if (memcmp(s->conf.macaddr.a, buf, 6)) {
942 return 0;
943 }
944 break;
945 }
946
947 return 1;
948 }
949
950 static ssize_t ftgmac100_receive(NetClientState *nc, const uint8_t *buf,
951 size_t len)
952 {
953 FTGMAC100State *s = FTGMAC100(qemu_get_nic_opaque(nc));
954 FTGMAC100Desc bd;
955 uint32_t flags = 0;
956 uint32_t addr;
957 uint32_t crc;
958 uint32_t buf_addr;
959 uint8_t *crc_ptr;
960 uint32_t buf_len;
961 size_t size = len;
962 uint32_t first = FTGMAC100_RXDES0_FRS;
963 uint16_t proto = be16_to_cpu(PKT_GET_ETH_HDR(buf)->h_proto);
964 int max_frame_size = ftgmac100_max_frame_size(s, proto);
965
966 if ((s->maccr & (FTGMAC100_MACCR_RXDMA_EN | FTGMAC100_MACCR_RXMAC_EN))
967 != (FTGMAC100_MACCR_RXDMA_EN | FTGMAC100_MACCR_RXMAC_EN)) {
968 return -1;
969 }
970
971 if (!ftgmac100_filter(s, buf, size)) {
972 return size;
973 }
974
975 crc = cpu_to_be32(crc32(~0, buf, size));
976 /* Increase size by 4, loop below reads the last 4 bytes from crc_ptr. */
977 size += 4;
978 crc_ptr = (uint8_t *) &crc;
979
980 /* Huge frames are truncated. */
981 if (size > max_frame_size) {
982 qemu_log_mask(LOG_GUEST_ERROR, "%s: frame too big : %zd bytes\n",
983 __func__, size);
984 size = max_frame_size;
985 flags |= FTGMAC100_RXDES0_FTL;
986 }
987
988 switch (get_eth_packet_type(PKT_GET_ETH_HDR(buf))) {
989 case ETH_PKT_BCAST:
990 flags |= FTGMAC100_RXDES0_BROADCAST;
991 break;
992 case ETH_PKT_MCAST:
993 flags |= FTGMAC100_RXDES0_MULTICAST;
994 break;
995 case ETH_PKT_UCAST:
996 break;
997 }
998
999 s->isr |= FTGMAC100_INT_RPKT_FIFO;
1000 addr = s->rx_descriptor;
1001 while (size > 0) {
1002 if (!ftgmac100_can_receive(nc)) {
1003 qemu_log_mask(LOG_GUEST_ERROR, "%s: Unexpected packet\n", __func__);
1004 return -1;
1005 }
1006
1007 if (ftgmac100_read_bd(&bd, addr) ||
1008 (bd.des0 & FTGMAC100_RXDES0_RXPKT_RDY)) {
1009 /* No descriptors available. Bail out. */
1010 qemu_log_mask(LOG_GUEST_ERROR, "%s: Lost end of frame\n",
1011 __func__);
1012 s->isr |= FTGMAC100_INT_NO_RXBUF;
1013 break;
1014 }
1015 buf_len = (size <= s->rbsr) ? size : s->rbsr;
1016 bd.des0 |= buf_len & 0x3fff;
1017 size -= buf_len;
1018
1019 /* The last 4 bytes are the CRC. */
1020 if (size < 4) {
1021 buf_len += size - 4;
1022 }
1023 buf_addr = bd.des3;
1024 if (first && proto == ETH_P_VLAN && buf_len >= 18) {
1025 bd.des1 = lduw_be_p(buf + 14) | FTGMAC100_RXDES1_VLANTAG_AVAIL;
1026
1027 if (s->maccr & FTGMAC100_MACCR_RM_VLAN) {
1028 dma_memory_write(&address_space_memory, buf_addr, buf, 12,
1029 MEMTXATTRS_UNSPECIFIED);
1030 dma_memory_write(&address_space_memory, buf_addr + 12,
1031 buf + 16, buf_len - 16,
1032 MEMTXATTRS_UNSPECIFIED);
1033 } else {
1034 dma_memory_write(&address_space_memory, buf_addr, buf,
1035 buf_len, MEMTXATTRS_UNSPECIFIED);
1036 }
1037 } else {
1038 bd.des1 = 0;
1039 dma_memory_write(&address_space_memory, buf_addr, buf, buf_len,
1040 MEMTXATTRS_UNSPECIFIED);
1041 }
1042 buf += buf_len;
1043 if (size < 4) {
1044 dma_memory_write(&address_space_memory, buf_addr + buf_len,
1045 crc_ptr, 4 - size, MEMTXATTRS_UNSPECIFIED);
1046 crc_ptr += 4 - size;
1047 }
1048
1049 bd.des0 |= first | FTGMAC100_RXDES0_RXPKT_RDY;
1050 first = 0;
1051 if (size == 0) {
1052 /* Last buffer in frame. */
1053 bd.des0 |= flags | FTGMAC100_RXDES0_LRS;
1054 s->isr |= FTGMAC100_INT_RPKT_BUF;
1055 }
1056 ftgmac100_write_bd(&bd, addr);
1057 if (bd.des0 & s->rxdes0_edorr) {
1058 addr = s->rx_ring;
1059 } else {
1060 addr += FTGMAC100_DBLAC_RXDES_SIZE(s->dblac);
1061 }
1062 }
1063 s->rx_descriptor = addr;
1064
1065 ftgmac100_update_irq(s);
1066 return len;
1067 }
1068
1069 static const MemoryRegionOps ftgmac100_ops = {
1070 .read = ftgmac100_read,
1071 .write = ftgmac100_write,
1072 .valid.min_access_size = 4,
1073 .valid.max_access_size = 4,
1074 .endianness = DEVICE_LITTLE_ENDIAN,
1075 };
1076
1077 static void ftgmac100_cleanup(NetClientState *nc)
1078 {
1079 FTGMAC100State *s = FTGMAC100(qemu_get_nic_opaque(nc));
1080
1081 s->nic = NULL;
1082 }
1083
1084 static NetClientInfo net_ftgmac100_info = {
1085 .type = NET_CLIENT_DRIVER_NIC,
1086 .size = sizeof(NICState),
1087 .can_receive = ftgmac100_can_receive,
1088 .receive = ftgmac100_receive,
1089 .cleanup = ftgmac100_cleanup,
1090 .link_status_changed = ftgmac100_set_link,
1091 };
1092
1093 static void ftgmac100_realize(DeviceState *dev, Error **errp)
1094 {
1095 FTGMAC100State *s = FTGMAC100(dev);
1096 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1097
1098 if (s->aspeed) {
1099 s->txdes0_edotr = FTGMAC100_TXDES0_EDOTR_ASPEED;
1100 s->rxdes0_edorr = FTGMAC100_RXDES0_EDORR_ASPEED;
1101 } else {
1102 s->txdes0_edotr = FTGMAC100_TXDES0_EDOTR;
1103 s->rxdes0_edorr = FTGMAC100_RXDES0_EDORR;
1104 }
1105
1106 memory_region_init_io(&s->iomem, OBJECT(dev), &ftgmac100_ops, s,
1107 TYPE_FTGMAC100, 0x2000);
1108 sysbus_init_mmio(sbd, &s->iomem);
1109 sysbus_init_irq(sbd, &s->irq);
1110 qemu_macaddr_default_if_unset(&s->conf.macaddr);
1111
1112 s->nic = qemu_new_nic(&net_ftgmac100_info, &s->conf,
1113 object_get_typename(OBJECT(dev)), dev->id, s);
1114 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
1115 }
1116
1117 static const VMStateDescription vmstate_ftgmac100 = {
1118 .name = TYPE_FTGMAC100,
1119 .version_id = 1,
1120 .minimum_version_id = 1,
1121 .fields = (VMStateField[]) {
1122 VMSTATE_UINT32(irq_state, FTGMAC100State),
1123 VMSTATE_UINT32(isr, FTGMAC100State),
1124 VMSTATE_UINT32(ier, FTGMAC100State),
1125 VMSTATE_UINT32(rx_enabled, FTGMAC100State),
1126 VMSTATE_UINT32(rx_ring, FTGMAC100State),
1127 VMSTATE_UINT32(rbsr, FTGMAC100State),
1128 VMSTATE_UINT32(tx_ring, FTGMAC100State),
1129 VMSTATE_UINT32(rx_descriptor, FTGMAC100State),
1130 VMSTATE_UINT32(tx_descriptor, FTGMAC100State),
1131 VMSTATE_UINT32_ARRAY(math, FTGMAC100State, 2),
1132 VMSTATE_UINT32(itc, FTGMAC100State),
1133 VMSTATE_UINT32(aptcr, FTGMAC100State),
1134 VMSTATE_UINT32(dblac, FTGMAC100State),
1135 VMSTATE_UINT32(revr, FTGMAC100State),
1136 VMSTATE_UINT32(fear1, FTGMAC100State),
1137 VMSTATE_UINT32(tpafcr, FTGMAC100State),
1138 VMSTATE_UINT32(maccr, FTGMAC100State),
1139 VMSTATE_UINT32(phycr, FTGMAC100State),
1140 VMSTATE_UINT32(phydata, FTGMAC100State),
1141 VMSTATE_UINT32(fcr, FTGMAC100State),
1142 VMSTATE_UINT32(phy_status, FTGMAC100State),
1143 VMSTATE_UINT32(phy_control, FTGMAC100State),
1144 VMSTATE_UINT32(phy_advertise, FTGMAC100State),
1145 VMSTATE_UINT32(phy_int, FTGMAC100State),
1146 VMSTATE_UINT32(phy_int_mask, FTGMAC100State),
1147 VMSTATE_UINT32(txdes0_edotr, FTGMAC100State),
1148 VMSTATE_UINT32(rxdes0_edorr, FTGMAC100State),
1149 VMSTATE_END_OF_LIST()
1150 }
1151 };
1152
1153 static Property ftgmac100_properties[] = {
1154 DEFINE_PROP_BOOL("aspeed", FTGMAC100State, aspeed, false),
1155 DEFINE_NIC_PROPERTIES(FTGMAC100State, conf),
1156 DEFINE_PROP_END_OF_LIST(),
1157 };
1158
1159 static void ftgmac100_class_init(ObjectClass *klass, void *data)
1160 {
1161 DeviceClass *dc = DEVICE_CLASS(klass);
1162
1163 dc->vmsd = &vmstate_ftgmac100;
1164 dc->reset = ftgmac100_reset;
1165 device_class_set_props(dc, ftgmac100_properties);
1166 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
1167 dc->realize = ftgmac100_realize;
1168 dc->desc = "Faraday FTGMAC100 Gigabit Ethernet emulation";
1169 }
1170
1171 static const TypeInfo ftgmac100_info = {
1172 .name = TYPE_FTGMAC100,
1173 .parent = TYPE_SYS_BUS_DEVICE,
1174 .instance_size = sizeof(FTGMAC100State),
1175 .class_init = ftgmac100_class_init,
1176 };
1177
1178 /*
1179 * AST2600 MII controller
1180 */
1181 #define ASPEED_MII_PHYCR_FIRE BIT(31)
1182 #define ASPEED_MII_PHYCR_ST_22 BIT(28)
1183 #define ASPEED_MII_PHYCR_OP(x) ((x) & (ASPEED_MII_PHYCR_OP_WRITE | \
1184 ASPEED_MII_PHYCR_OP_READ))
1185 #define ASPEED_MII_PHYCR_OP_WRITE BIT(26)
1186 #define ASPEED_MII_PHYCR_OP_READ BIT(27)
1187 #define ASPEED_MII_PHYCR_DATA(x) (x & 0xffff)
1188 #define ASPEED_MII_PHYCR_PHY(x) (((x) >> 21) & 0x1f)
1189 #define ASPEED_MII_PHYCR_REG(x) (((x) >> 16) & 0x1f)
1190
1191 #define ASPEED_MII_PHYDATA_IDLE BIT(16)
1192
1193 static void aspeed_mii_transition(AspeedMiiState *s, bool fire)
1194 {
1195 if (fire) {
1196 s->phycr |= ASPEED_MII_PHYCR_FIRE;
1197 s->phydata &= ~ASPEED_MII_PHYDATA_IDLE;
1198 } else {
1199 s->phycr &= ~ASPEED_MII_PHYCR_FIRE;
1200 s->phydata |= ASPEED_MII_PHYDATA_IDLE;
1201 }
1202 }
1203
1204 static void aspeed_mii_do_phy_ctl(AspeedMiiState *s)
1205 {
1206 uint8_t reg;
1207 uint16_t data;
1208
1209 if (!(s->phycr & ASPEED_MII_PHYCR_ST_22)) {
1210 aspeed_mii_transition(s, !ASPEED_MII_PHYCR_FIRE);
1211 qemu_log_mask(LOG_UNIMP, "%s: unsupported ST code\n", __func__);
1212 return;
1213 }
1214
1215 /* Nothing to do */
1216 if (!(s->phycr & ASPEED_MII_PHYCR_FIRE)) {
1217 return;
1218 }
1219
1220 reg = ASPEED_MII_PHYCR_REG(s->phycr);
1221 data = ASPEED_MII_PHYCR_DATA(s->phycr);
1222
1223 switch (ASPEED_MII_PHYCR_OP(s->phycr)) {
1224 case ASPEED_MII_PHYCR_OP_WRITE:
1225 do_phy_write(s->nic, reg, data);
1226 break;
1227 case ASPEED_MII_PHYCR_OP_READ:
1228 s->phydata = (s->phydata & ~0xffff) | do_phy_read(s->nic, reg);
1229 break;
1230 default:
1231 qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid OP code %08x\n",
1232 __func__, s->phycr);
1233 }
1234
1235 aspeed_mii_transition(s, !ASPEED_MII_PHYCR_FIRE);
1236 }
1237
1238 static uint64_t aspeed_mii_read(void *opaque, hwaddr addr, unsigned size)
1239 {
1240 AspeedMiiState *s = ASPEED_MII(opaque);
1241
1242 switch (addr) {
1243 case 0x0:
1244 return s->phycr;
1245 case 0x4:
1246 return s->phydata;
1247 default:
1248 g_assert_not_reached();
1249 }
1250 }
1251
1252 static void aspeed_mii_write(void *opaque, hwaddr addr,
1253 uint64_t value, unsigned size)
1254 {
1255 AspeedMiiState *s = ASPEED_MII(opaque);
1256
1257 switch (addr) {
1258 case 0x0:
1259 s->phycr = value & ~(s->phycr & ASPEED_MII_PHYCR_FIRE);
1260 break;
1261 case 0x4:
1262 s->phydata = value & ~(0xffff | ASPEED_MII_PHYDATA_IDLE);
1263 break;
1264 default:
1265 g_assert_not_reached();
1266 }
1267
1268 aspeed_mii_transition(s, !!(s->phycr & ASPEED_MII_PHYCR_FIRE));
1269 aspeed_mii_do_phy_ctl(s);
1270 }
1271
1272 static const MemoryRegionOps aspeed_mii_ops = {
1273 .read = aspeed_mii_read,
1274 .write = aspeed_mii_write,
1275 .valid.min_access_size = 4,
1276 .valid.max_access_size = 4,
1277 .endianness = DEVICE_LITTLE_ENDIAN,
1278 };
1279
1280 static void aspeed_mii_reset(DeviceState *dev)
1281 {
1282 AspeedMiiState *s = ASPEED_MII(dev);
1283
1284 s->phycr = 0;
1285 s->phydata = 0;
1286
1287 aspeed_mii_transition(s, !!(s->phycr & ASPEED_MII_PHYCR_FIRE));
1288 };
1289
1290 static void aspeed_mii_realize(DeviceState *dev, Error **errp)
1291 {
1292 AspeedMiiState *s = ASPEED_MII(dev);
1293 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1294
1295 assert(s->nic);
1296
1297 memory_region_init_io(&s->iomem, OBJECT(dev), &aspeed_mii_ops, s,
1298 TYPE_ASPEED_MII, 0x8);
1299 sysbus_init_mmio(sbd, &s->iomem);
1300 }
1301
1302 static const VMStateDescription vmstate_aspeed_mii = {
1303 .name = TYPE_ASPEED_MII,
1304 .version_id = 1,
1305 .minimum_version_id = 1,
1306 .fields = (VMStateField[]) {
1307 VMSTATE_UINT32(phycr, FTGMAC100State),
1308 VMSTATE_UINT32(phydata, FTGMAC100State),
1309 VMSTATE_END_OF_LIST()
1310 }
1311 };
1312
1313 static Property aspeed_mii_properties[] = {
1314 DEFINE_PROP_LINK("nic", AspeedMiiState, nic, TYPE_FTGMAC100,
1315 FTGMAC100State *),
1316 DEFINE_PROP_END_OF_LIST(),
1317 };
1318
1319 static void aspeed_mii_class_init(ObjectClass *klass, void *data)
1320 {
1321 DeviceClass *dc = DEVICE_CLASS(klass);
1322
1323 dc->vmsd = &vmstate_aspeed_mii;
1324 dc->reset = aspeed_mii_reset;
1325 dc->realize = aspeed_mii_realize;
1326 dc->desc = "Aspeed MII controller";
1327 device_class_set_props(dc, aspeed_mii_properties);
1328 }
1329
1330 static const TypeInfo aspeed_mii_info = {
1331 .name = TYPE_ASPEED_MII,
1332 .parent = TYPE_SYS_BUS_DEVICE,
1333 .instance_size = sizeof(AspeedMiiState),
1334 .class_init = aspeed_mii_class_init,
1335 };
1336
1337 static void ftgmac100_register_types(void)
1338 {
1339 type_register_static(&ftgmac100_info);
1340 type_register_static(&aspeed_mii_info);
1341 }
1342
1343 type_init(ftgmac100_register_types)
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