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migration: Allow user to specify available switchover bandwidth
[qemu/kevin.git] / hw / ide / ahci.c
blobfcc5476e9e88877adeeb68b0929e6048f17cbd18
1 /*
2 * QEMU AHCI Emulation
3 *
4 * Copyright (c) 2010 qiaochong@loongson.cn
5 * Copyright (c) 2010 Roland Elek <elek.roland@gmail.com>
6 * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de>
7 * Copyright (c) 2010 Alexander Graf <agraf@suse.de>
8 *
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2.1 of the License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
18 *
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 *
22 */
23
24 #include "qemu/osdep.h"
25 #include "hw/irq.h"
26 #include "hw/pci/msi.h"
27 #include "hw/pci/pci.h"
28 #include "hw/qdev-properties.h"
29 #include "migration/vmstate.h"
30
31 #include "qemu/error-report.h"
32 #include "qemu/log.h"
33 #include "qemu/main-loop.h"
34 #include "qemu/module.h"
35 #include "sysemu/block-backend.h"
36 #include "sysemu/dma.h"
37 #include "hw/ide/internal.h"
38 #include "hw/ide/pci.h"
39 #include "ahci_internal.h"
40
41 #include "trace.h"
42
43 static void check_cmd(AHCIState *s, int port);
44 static void handle_cmd(AHCIState *s, int port, uint8_t slot);
45 static void ahci_reset_port(AHCIState *s, int port);
46 static bool ahci_write_fis_d2h(AHCIDevice *ad, bool d2h_fis_i);
47 static void ahci_clear_cmd_issue(AHCIDevice *ad, uint8_t slot);
48 static void ahci_init_d2h(AHCIDevice *ad);
49 static int ahci_dma_prepare_buf(const IDEDMA *dma, int32_t limit);
50 static bool ahci_map_clb_address(AHCIDevice *ad);
51 static bool ahci_map_fis_address(AHCIDevice *ad);
52 static void ahci_unmap_clb_address(AHCIDevice *ad);
53 static void ahci_unmap_fis_address(AHCIDevice *ad);
54
55 static const char *AHCIHostReg_lookup[AHCI_HOST_REG__COUNT] = {
56 [AHCI_HOST_REG_CAP] = "CAP",
57 [AHCI_HOST_REG_CTL] = "GHC",
58 [AHCI_HOST_REG_IRQ_STAT] = "IS",
59 [AHCI_HOST_REG_PORTS_IMPL] = "PI",
60 [AHCI_HOST_REG_VERSION] = "VS",
61 [AHCI_HOST_REG_CCC_CTL] = "CCC_CTL",
62 [AHCI_HOST_REG_CCC_PORTS] = "CCC_PORTS",
63 [AHCI_HOST_REG_EM_LOC] = "EM_LOC",
64 [AHCI_HOST_REG_EM_CTL] = "EM_CTL",
65 [AHCI_HOST_REG_CAP2] = "CAP2",
66 [AHCI_HOST_REG_BOHC] = "BOHC",
67 };
68
69 static const char *AHCIPortReg_lookup[AHCI_PORT_REG__COUNT] = {
70 [AHCI_PORT_REG_LST_ADDR] = "PxCLB",
71 [AHCI_PORT_REG_LST_ADDR_HI] = "PxCLBU",
72 [AHCI_PORT_REG_FIS_ADDR] = "PxFB",
73 [AHCI_PORT_REG_FIS_ADDR_HI] = "PxFBU",
74 [AHCI_PORT_REG_IRQ_STAT] = "PxIS",
75 [AHCI_PORT_REG_IRQ_MASK] = "PXIE",
76 [AHCI_PORT_REG_CMD] = "PxCMD",
77 [7] = "Reserved",
78 [AHCI_PORT_REG_TFDATA] = "PxTFD",
79 [AHCI_PORT_REG_SIG] = "PxSIG",
80 [AHCI_PORT_REG_SCR_STAT] = "PxSSTS",
81 [AHCI_PORT_REG_SCR_CTL] = "PxSCTL",
82 [AHCI_PORT_REG_SCR_ERR] = "PxSERR",
83 [AHCI_PORT_REG_SCR_ACT] = "PxSACT",
84 [AHCI_PORT_REG_CMD_ISSUE] = "PxCI",
85 [AHCI_PORT_REG_SCR_NOTIF] = "PxSNTF",
86 [AHCI_PORT_REG_FIS_CTL] = "PxFBS",
87 [AHCI_PORT_REG_DEV_SLEEP] = "PxDEVSLP",
88 [18 ... 27] = "Reserved",
89 [AHCI_PORT_REG_VENDOR_1 ...
90 AHCI_PORT_REG_VENDOR_4] = "PxVS",
91 };
92
93 static const char *AHCIPortIRQ_lookup[AHCI_PORT_IRQ__COUNT] = {
94 [AHCI_PORT_IRQ_BIT_DHRS] = "DHRS",
95 [AHCI_PORT_IRQ_BIT_PSS] = "PSS",
96 [AHCI_PORT_IRQ_BIT_DSS] = "DSS",
97 [AHCI_PORT_IRQ_BIT_SDBS] = "SDBS",
98 [AHCI_PORT_IRQ_BIT_UFS] = "UFS",
99 [AHCI_PORT_IRQ_BIT_DPS] = "DPS",
100 [AHCI_PORT_IRQ_BIT_PCS] = "PCS",
101 [AHCI_PORT_IRQ_BIT_DMPS] = "DMPS",
102 [8 ... 21] = "RESERVED",
103 [AHCI_PORT_IRQ_BIT_PRCS] = "PRCS",
104 [AHCI_PORT_IRQ_BIT_IPMS] = "IPMS",
105 [AHCI_PORT_IRQ_BIT_OFS] = "OFS",
106 [25] = "RESERVED",
107 [AHCI_PORT_IRQ_BIT_INFS] = "INFS",
108 [AHCI_PORT_IRQ_BIT_IFS] = "IFS",
109 [AHCI_PORT_IRQ_BIT_HBDS] = "HBDS",
110 [AHCI_PORT_IRQ_BIT_HBFS] = "HBFS",
111 [AHCI_PORT_IRQ_BIT_TFES] = "TFES",
112 [AHCI_PORT_IRQ_BIT_CPDS] = "CPDS"
113 };
114
115 static uint32_t ahci_port_read(AHCIState *s, int port, int offset)
116 {
117 uint32_t val;
118 AHCIPortRegs *pr = &s->dev[port].port_regs;
119 enum AHCIPortReg regnum = offset / sizeof(uint32_t);
120 assert(regnum < (AHCI_PORT_ADDR_OFFSET_LEN / sizeof(uint32_t)));
121
122 switch (regnum) {
123 case AHCI_PORT_REG_LST_ADDR:
124 val = pr->lst_addr;
125 break;
126 case AHCI_PORT_REG_LST_ADDR_HI:
127 val = pr->lst_addr_hi;
128 break;
129 case AHCI_PORT_REG_FIS_ADDR:
130 val = pr->fis_addr;
131 break;
132 case AHCI_PORT_REG_FIS_ADDR_HI:
133 val = pr->fis_addr_hi;
134 break;
135 case AHCI_PORT_REG_IRQ_STAT:
136 val = pr->irq_stat;
137 break;
138 case AHCI_PORT_REG_IRQ_MASK:
139 val = pr->irq_mask;
140 break;
141 case AHCI_PORT_REG_CMD:
142 val = pr->cmd;
143 break;
144 case AHCI_PORT_REG_TFDATA:
145 val = pr->tfdata;
146 break;
147 case AHCI_PORT_REG_SIG:
148 val = pr->sig;
149 break;
150 case AHCI_PORT_REG_SCR_STAT:
151 if (s->dev[port].port.ifs[0].blk) {
152 val = SATA_SCR_SSTATUS_DET_DEV_PRESENT_PHY_UP |
153 SATA_SCR_SSTATUS_SPD_GEN1 | SATA_SCR_SSTATUS_IPM_ACTIVE;
154 } else {
155 val = SATA_SCR_SSTATUS_DET_NODEV;
156 }
157 break;
158 case AHCI_PORT_REG_SCR_CTL:
159 val = pr->scr_ctl;
160 break;
161 case AHCI_PORT_REG_SCR_ERR:
162 val = pr->scr_err;
163 break;
164 case AHCI_PORT_REG_SCR_ACT:
165 val = pr->scr_act;
166 break;
167 case AHCI_PORT_REG_CMD_ISSUE:
168 val = pr->cmd_issue;
169 break;
170 default:
171 trace_ahci_port_read_default(s, port, AHCIPortReg_lookup[regnum],
172 offset);
173 val = 0;
174 }
175
176 trace_ahci_port_read(s, port, AHCIPortReg_lookup[regnum], offset, val);
177 return val;
178 }
179
180 static void ahci_irq_raise(AHCIState *s)
181 {
182 DeviceState *dev_state = s->container;
183 PCIDevice *pci_dev = (PCIDevice *) object_dynamic_cast(OBJECT(dev_state),
184 TYPE_PCI_DEVICE);
185
186 trace_ahci_irq_raise(s);
187
188 if (pci_dev && msi_enabled(pci_dev)) {
189 msi_notify(pci_dev, 0);
190 } else {
191 qemu_irq_raise(s->irq);
192 }
193 }
194
195 static void ahci_irq_lower(AHCIState *s)
196 {
197 DeviceState *dev_state = s->container;
198 PCIDevice *pci_dev = (PCIDevice *) object_dynamic_cast(OBJECT(dev_state),
199 TYPE_PCI_DEVICE);
200
201 trace_ahci_irq_lower(s);
202
203 if (!pci_dev || !msi_enabled(pci_dev)) {
204 qemu_irq_lower(s->irq);
205 }
206 }
207
208 static void ahci_check_irq(AHCIState *s)
209 {
210 int i;
211 uint32_t old_irq = s->control_regs.irqstatus;
212
213 s->control_regs.irqstatus = 0;
214 for (i = 0; i < s->ports; i++) {
215 AHCIPortRegs *pr = &s->dev[i].port_regs;
216 if (pr->irq_stat & pr->irq_mask) {
217 s->control_regs.irqstatus |= (1 << i);
218 }
219 }
220 trace_ahci_check_irq(s, old_irq, s->control_regs.irqstatus);
221 if (s->control_regs.irqstatus &&
222 (s->control_regs.ghc & HOST_CTL_IRQ_EN)) {
223 ahci_irq_raise(s);
224 } else {
225 ahci_irq_lower(s);
226 }
227 }
228
229 static void ahci_trigger_irq(AHCIState *s, AHCIDevice *d,
230 enum AHCIPortIRQ irqbit)
231 {
232 g_assert((unsigned)irqbit < 32);
233 uint32_t irq = 1U << irqbit;
234 uint32_t irqstat = d->port_regs.irq_stat | irq;
235
236 trace_ahci_trigger_irq(s, d->port_no,
237 AHCIPortIRQ_lookup[irqbit], irq,
238 d->port_regs.irq_stat, irqstat,
239 irqstat & d->port_regs.irq_mask);
240
241 d->port_regs.irq_stat = irqstat;
242 ahci_check_irq(s);
243 }
244
245 static void map_page(AddressSpace *as, uint8_t **ptr, uint64_t addr,
246 uint32_t wanted)
247 {
248 hwaddr len = wanted;
249
250 if (*ptr) {
251 dma_memory_unmap(as, *ptr, len, DMA_DIRECTION_FROM_DEVICE, len);
252 }
253
254 *ptr = dma_memory_map(as, addr, &len, DMA_DIRECTION_FROM_DEVICE,
255 MEMTXATTRS_UNSPECIFIED);
256 if (len < wanted && *ptr) {
257 dma_memory_unmap(as, *ptr, len, DMA_DIRECTION_FROM_DEVICE, len);
258 *ptr = NULL;
259 }
260 }
261
262 /**
263 * Check the cmd register to see if we should start or stop
264 * the DMA or FIS RX engines.
265 *
266 * @ad: Device to dis/engage.
267 *
268 * @return 0 on success, -1 on error.
269 */
270 static int ahci_cond_start_engines(AHCIDevice *ad)
271 {
272 AHCIPortRegs *pr = &ad->port_regs;
273 bool cmd_start = pr->cmd & PORT_CMD_START;
274 bool cmd_on = pr->cmd & PORT_CMD_LIST_ON;
275 bool fis_start = pr->cmd & PORT_CMD_FIS_RX;
276 bool fis_on = pr->cmd & PORT_CMD_FIS_ON;
277
278 if (cmd_start && !cmd_on) {
279 if (!ahci_map_clb_address(ad)) {
280 pr->cmd &= ~PORT_CMD_START;
281 error_report("AHCI: Failed to start DMA engine: "
282 "bad command list buffer address");
283 return -1;
284 }
285 } else if (!cmd_start && cmd_on) {
286 ahci_unmap_clb_address(ad);
287 }
288
289 if (fis_start && !fis_on) {
290 if (!ahci_map_fis_address(ad)) {
291 pr->cmd &= ~PORT_CMD_FIS_RX;
292 error_report("AHCI: Failed to start FIS receive engine: "
293 "bad FIS receive buffer address");
294 return -1;
295 }
296 } else if (!fis_start && fis_on) {
297 ahci_unmap_fis_address(ad);
298 }
299
300 return 0;
301 }
302
303 static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val)
304 {
305 AHCIPortRegs *pr = &s->dev[port].port_regs;
306 enum AHCIPortReg regnum = offset / sizeof(uint32_t);
307 assert(regnum < (AHCI_PORT_ADDR_OFFSET_LEN / sizeof(uint32_t)));
308 trace_ahci_port_write(s, port, AHCIPortReg_lookup[regnum], offset, val);
309
310 switch (regnum) {
311 case AHCI_PORT_REG_LST_ADDR:
312 pr->lst_addr = val;
313 break;
314 case AHCI_PORT_REG_LST_ADDR_HI:
315 pr->lst_addr_hi = val;
316 break;
317 case AHCI_PORT_REG_FIS_ADDR:
318 pr->fis_addr = val;
319 break;
320 case AHCI_PORT_REG_FIS_ADDR_HI:
321 pr->fis_addr_hi = val;
322 break;
323 case AHCI_PORT_REG_IRQ_STAT:
324 pr->irq_stat &= ~val;
325 ahci_check_irq(s);
326 break;
327 case AHCI_PORT_REG_IRQ_MASK:
328 pr->irq_mask = val & 0xfdc000ff;
329 ahci_check_irq(s);
330 break;
331 case AHCI_PORT_REG_CMD:
332 if ((pr->cmd & PORT_CMD_START) && !(val & PORT_CMD_START)) {
333 pr->scr_act = 0;
334 pr->cmd_issue = 0;
335 }
336
337 /* Block any Read-only fields from being set;
338 * including LIST_ON and FIS_ON.
339 * The spec requires to set ICC bits to zero after the ICC change
340 * is done. We don't support ICC state changes, therefore always
341 * force the ICC bits to zero.
342 */
343 pr->cmd = (pr->cmd & PORT_CMD_RO_MASK) |
344 (val & ~(PORT_CMD_RO_MASK | PORT_CMD_ICC_MASK));
345
346 /* Check FIS RX and CLB engines */
347 ahci_cond_start_engines(&s->dev[port]);
348
349 /* XXX usually the FIS would be pending on the bus here and
350 issuing deferred until the OS enables FIS receival.
351 Instead, we only submit it once - which works in most
352 cases, but is a hack. */
353 if ((pr->cmd & PORT_CMD_FIS_ON) &&
354 !s->dev[port].init_d2h_sent) {
355 ahci_init_d2h(&s->dev[port]);
356 }
357
358 check_cmd(s, port);
359 break;
360 case AHCI_PORT_REG_TFDATA:
361 case AHCI_PORT_REG_SIG:
362 case AHCI_PORT_REG_SCR_STAT:
363 /* Read Only */
364 break;
365 case AHCI_PORT_REG_SCR_CTL:
366 if (((pr->scr_ctl & AHCI_SCR_SCTL_DET) == 1) &&
367 ((val & AHCI_SCR_SCTL_DET) == 0)) {
368 ahci_reset_port(s, port);
369 }
370 pr->scr_ctl = val;
371 break;
372 case AHCI_PORT_REG_SCR_ERR:
373 pr->scr_err &= ~val;
374 break;
375 case AHCI_PORT_REG_SCR_ACT:
376 /* RW1 */
377 pr->scr_act |= val;
378 break;
379 case AHCI_PORT_REG_CMD_ISSUE:
380 pr->cmd_issue |= val;
381 check_cmd(s, port);
382 break;
383 default:
384 trace_ahci_port_write_unimpl(s, port, AHCIPortReg_lookup[regnum],
385 offset, val);
386 qemu_log_mask(LOG_UNIMP, "Attempted write to unimplemented register: "
387 "AHCI port %d register %s, offset 0x%x: 0x%"PRIx32,
388 port, AHCIPortReg_lookup[regnum], offset, val);
389 break;
390 }
391 }
392
393 static uint64_t ahci_mem_read_32(void *opaque, hwaddr addr)
394 {
395 AHCIState *s = opaque;
396 uint32_t val = 0;
397
398 if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) {
399 enum AHCIHostReg regnum = addr / 4;
400 assert(regnum < AHCI_HOST_REG__COUNT);
401
402 switch (regnum) {
403 case AHCI_HOST_REG_CAP:
404 val = s->control_regs.cap;
405 break;
406 case AHCI_HOST_REG_CTL:
407 val = s->control_regs.ghc;
408 break;
409 case AHCI_HOST_REG_IRQ_STAT:
410 val = s->control_regs.irqstatus;
411 break;
412 case AHCI_HOST_REG_PORTS_IMPL:
413 val = s->control_regs.impl;
414 break;
415 case AHCI_HOST_REG_VERSION:
416 val = s->control_regs.version;
417 break;
418 default:
419 trace_ahci_mem_read_32_host_default(s, AHCIHostReg_lookup[regnum],
420 addr);
421 }
422 trace_ahci_mem_read_32_host(s, AHCIHostReg_lookup[regnum], addr, val);
423 } else if ((addr >= AHCI_PORT_REGS_START_ADDR) &&
424 (addr < (AHCI_PORT_REGS_START_ADDR +
425 (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) {
426 val = ahci_port_read(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7,
427 addr & AHCI_PORT_ADDR_OFFSET_MASK);
428 } else {
429 trace_ahci_mem_read_32_default(s, addr, val);
430 }
431
432 trace_ahci_mem_read_32(s, addr, val);
433 return val;
434 }
435
436
437 /**
438 * AHCI 1.3 section 3 ("HBA Memory Registers")
439 * Support unaligned 8/16/32 bit reads, and 64 bit aligned reads.
440 * Caller is responsible for masking unwanted higher order bytes.
441 */
442 static uint64_t ahci_mem_read(void *opaque, hwaddr addr, unsigned size)
443 {
444 hwaddr aligned = addr & ~0x3;
445 int ofst = addr - aligned;
446 uint64_t lo = ahci_mem_read_32(opaque, aligned);
447 uint64_t hi;
448 uint64_t val;
449
450 /* if < 8 byte read does not cross 4 byte boundary */
451 if (ofst + size <= 4) {
452 val = lo >> (ofst * 8);
453 } else {
454 g_assert(size > 1);
455
456 /* If the 64bit read is unaligned, we will produce undefined
457 * results. AHCI does not support unaligned 64bit reads. */
458 hi = ahci_mem_read_32(opaque, aligned + 4);
459 val = (hi << 32 | lo) >> (ofst * 8);
460 }
461
462 trace_ahci_mem_read(opaque, size, addr, val);
463 return val;
464 }
465
466
467 static void ahci_mem_write(void *opaque, hwaddr addr,
468 uint64_t val, unsigned size)
469 {
470 AHCIState *s = opaque;
471
472 trace_ahci_mem_write(s, size, addr, val);
473
474 /* Only aligned reads are allowed on AHCI */
475 if (addr & 3) {
476 qemu_log_mask(LOG_GUEST_ERROR,
477 "ahci: Mis-aligned write to addr 0x%03" HWADDR_PRIX "\n",
478 addr);
479 return;
480 }
481
482 if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) {
483 enum AHCIHostReg regnum = addr / 4;
484 assert(regnum < AHCI_HOST_REG__COUNT);
485
486 switch (regnum) {
487 case AHCI_HOST_REG_CAP: /* R/WO, RO */
488 /* FIXME handle R/WO */
489 break;
490 case AHCI_HOST_REG_CTL: /* R/W */
491 if (val & HOST_CTL_RESET) {
492 ahci_reset(s);
493 } else {
494 s->control_regs.ghc = (val & 0x3) | HOST_CTL_AHCI_EN;
495 ahci_check_irq(s);
496 }
497 break;
498 case AHCI_HOST_REG_IRQ_STAT: /* R/WC, RO */
499 s->control_regs.irqstatus &= ~val;
500 ahci_check_irq(s);
501 break;
502 case AHCI_HOST_REG_PORTS_IMPL: /* R/WO, RO */
503 /* FIXME handle R/WO */
504 break;
505 case AHCI_HOST_REG_VERSION: /* RO */
506 /* FIXME report write? */
507 break;
508 default:
509 qemu_log_mask(LOG_UNIMP,
510 "Attempted write to unimplemented register: "
511 "AHCI host register %s, "
512 "offset 0x%"PRIx64": 0x%"PRIx64,
513 AHCIHostReg_lookup[regnum], addr, val);
514 trace_ahci_mem_write_host_unimpl(s, size,
515 AHCIHostReg_lookup[regnum], addr);
516 }
517 trace_ahci_mem_write_host(s, size, AHCIHostReg_lookup[regnum],
518 addr, val);
519 } else if ((addr >= AHCI_PORT_REGS_START_ADDR) &&
520 (addr < (AHCI_PORT_REGS_START_ADDR +
521 (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) {
522 ahci_port_write(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7,
523 addr & AHCI_PORT_ADDR_OFFSET_MASK, val);
524 } else {
525 qemu_log_mask(LOG_UNIMP, "Attempted write to unimplemented register: "
526 "AHCI global register at offset 0x%"PRIx64": 0x%"PRIx64,
527 addr, val);
528 trace_ahci_mem_write_unimpl(s, size, addr, val);
529 }
530 }
531
532 static const MemoryRegionOps ahci_mem_ops = {
533 .read = ahci_mem_read,
534 .write = ahci_mem_write,
535 .endianness = DEVICE_LITTLE_ENDIAN,
536 };
537
538 static uint64_t ahci_idp_read(void *opaque, hwaddr addr,
539 unsigned size)
540 {
541 AHCIState *s = opaque;
542
543 if (addr == s->idp_offset) {
544 /* index register */
545 return s->idp_index;
546 } else if (addr == s->idp_offset + 4) {
547 /* data register - do memory read at location selected by index */
548 return ahci_mem_read(opaque, s->idp_index, size);
549 } else {
550 return 0;
551 }
552 }
553
554 static void ahci_idp_write(void *opaque, hwaddr addr,
555 uint64_t val, unsigned size)
556 {
557 AHCIState *s = opaque;
558
559 if (addr == s->idp_offset) {
560 /* index register - mask off reserved bits */
561 s->idp_index = (uint32_t)val & ((AHCI_MEM_BAR_SIZE - 1) & ~3);
562 } else if (addr == s->idp_offset + 4) {
563 /* data register - do memory write at location selected by index */
564 ahci_mem_write(opaque, s->idp_index, val, size);
565 }
566 }
567
568 static const MemoryRegionOps ahci_idp_ops = {
569 .read = ahci_idp_read,
570 .write = ahci_idp_write,
571 .endianness = DEVICE_LITTLE_ENDIAN,
572 };
573
574
575 static void ahci_reg_init(AHCIState *s)
576 {
577 int i;
578
579 s->control_regs.cap = (s->ports - 1) |
580 (AHCI_NUM_COMMAND_SLOTS << 8) |
581 (AHCI_SUPPORTED_SPEED_GEN1 << AHCI_SUPPORTED_SPEED) |
582 HOST_CAP_NCQ | HOST_CAP_AHCI | HOST_CAP_64;
583
584 s->control_regs.impl = (1 << s->ports) - 1;
585
586 s->control_regs.version = AHCI_VERSION_1_0;
587
588 for (i = 0; i < s->ports; i++) {
589 s->dev[i].port_state = STATE_RUN;
590 }
591 }
592
593 static void check_cmd(AHCIState *s, int port)
594 {
595 AHCIPortRegs *pr = &s->dev[port].port_regs;
596 uint8_t slot;
597
598 if ((pr->cmd & PORT_CMD_START) && pr->cmd_issue) {
599 for (slot = 0; (slot < 32) && pr->cmd_issue; slot++) {
600 if (pr->cmd_issue & (1U << slot)) {
601 handle_cmd(s, port, slot);
602 }
603 }
604 }
605 }
606
607 static void ahci_check_cmd_bh(void *opaque)
608 {
609 AHCIDevice *ad = opaque;
610
611 qemu_bh_delete(ad->check_bh);
612 ad->check_bh = NULL;
613
614 check_cmd(ad->hba, ad->port_no);
615 }
616
617 static void ahci_init_d2h(AHCIDevice *ad)
618 {
619 IDEState *ide_state = &ad->port.ifs[0];
620 AHCIPortRegs *pr = &ad->port_regs;
621
622 if (ad->init_d2h_sent) {
623 return;
624 }
625
626 if (ahci_write_fis_d2h(ad, true)) {
627 ad->init_d2h_sent = true;
628 /* We're emulating receiving the first Reg H2D Fis from the device;
629 * Update the SIG register, but otherwise proceed as normal. */
630 pr->sig = ((uint32_t)ide_state->hcyl << 24) |
631 (ide_state->lcyl << 16) |
632 (ide_state->sector << 8) |
633 (ide_state->nsector & 0xFF);
634 }
635 }
636
637 static void ahci_set_signature(AHCIDevice *ad, uint32_t sig)
638 {
639 IDEState *s = &ad->port.ifs[0];
640 s->hcyl = sig >> 24 & 0xFF;
641 s->lcyl = sig >> 16 & 0xFF;
642 s->sector = sig >> 8 & 0xFF;
643 s->nsector = sig & 0xFF;
644
645 trace_ahci_set_signature(ad->hba, ad->port_no, s->nsector, s->sector,
646 s->lcyl, s->hcyl, sig);
647 }
648
649 static void ahci_reset_port(AHCIState *s, int port)
650 {
651 AHCIDevice *d = &s->dev[port];
652 AHCIPortRegs *pr = &d->port_regs;
653 IDEState *ide_state = &d->port.ifs[0];
654 int i;
655
656 trace_ahci_reset_port(s, port);
657
658 ide_bus_reset(&d->port);
659 ide_state->ncq_queues = AHCI_MAX_CMDS;
660
661 pr->scr_stat = 0;
662 pr->scr_err = 0;
663 pr->scr_act = 0;
664 pr->tfdata = 0x7F;
665 pr->sig = 0xFFFFFFFF;
666 d->busy_slot = -1;
667 d->init_d2h_sent = false;
668
669 ide_state = &s->dev[port].port.ifs[0];
670 if (!ide_state->blk) {
671 return;
672 }
673
674 /* reset ncq queue */
675 for (i = 0; i < AHCI_MAX_CMDS; i++) {
676 NCQTransferState *ncq_tfs = &s->dev[port].ncq_tfs[i];
677 ncq_tfs->halt = false;
678 if (!ncq_tfs->used) {
679 continue;
680 }
681
682 if (ncq_tfs->aiocb) {
683 blk_aio_cancel(ncq_tfs->aiocb);
684 ncq_tfs->aiocb = NULL;
685 }
686
687 /* Maybe we just finished the request thanks to blk_aio_cancel() */
688 if (!ncq_tfs->used) {
689 continue;
690 }
691
692 qemu_sglist_destroy(&ncq_tfs->sglist);
693 ncq_tfs->used = 0;
694 }
695
696 s->dev[port].port_state = STATE_RUN;
697 if (ide_state->drive_kind == IDE_CD) {
698 ahci_set_signature(d, SATA_SIGNATURE_CDROM);
699 ide_state->status = SEEK_STAT | WRERR_STAT | READY_STAT;
700 } else {
701 ahci_set_signature(d, SATA_SIGNATURE_DISK);
702 ide_state->status = SEEK_STAT | WRERR_STAT;
703 }
704
705 ide_state->error = 1;
706 ahci_init_d2h(d);
707 }
708
709 /* Buffer pretty output based on a raw FIS structure. */
710 static char *ahci_pretty_buffer_fis(const uint8_t *fis, int cmd_len)
711 {
712 int i;
713 GString *s = g_string_new("FIS:");
714
715 for (i = 0; i < cmd_len; i++) {
716 if ((i & 0xf) == 0) {
717 g_string_append_printf(s, "\n0x%02x: ", i);
718 }
719 g_string_append_printf(s, "%02x ", fis[i]);
720 }
721 g_string_append_c(s, '\n');
722
723 return g_string_free(s, FALSE);
724 }
725
726 static bool ahci_map_fis_address(AHCIDevice *ad)
727 {
728 AHCIPortRegs *pr = &ad->port_regs;
729 map_page(ad->hba->as, &ad->res_fis,
730 ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256);
731 if (ad->res_fis != NULL) {
732 pr->cmd |= PORT_CMD_FIS_ON;
733 return true;
734 }
735
736 pr->cmd &= ~PORT_CMD_FIS_ON;
737 return false;
738 }
739
740 static void ahci_unmap_fis_address(AHCIDevice *ad)
741 {
742 if (ad->res_fis == NULL) {
743 trace_ahci_unmap_fis_address_null(ad->hba, ad->port_no);
744 return;
745 }
746 ad->port_regs.cmd &= ~PORT_CMD_FIS_ON;
747 dma_memory_unmap(ad->hba->as, ad->res_fis, 256,
748 DMA_DIRECTION_FROM_DEVICE, 256);
749 ad->res_fis = NULL;
750 }
751
752 static bool ahci_map_clb_address(AHCIDevice *ad)
753 {
754 AHCIPortRegs *pr = &ad->port_regs;
755 ad->cur_cmd = NULL;
756 map_page(ad->hba->as, &ad->lst,
757 ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024);
758 if (ad->lst != NULL) {
759 pr->cmd |= PORT_CMD_LIST_ON;
760 return true;
761 }
762
763 pr->cmd &= ~PORT_CMD_LIST_ON;
764 return false;
765 }
766
767 static void ahci_unmap_clb_address(AHCIDevice *ad)
768 {
769 if (ad->lst == NULL) {
770 trace_ahci_unmap_clb_address_null(ad->hba, ad->port_no);
771 return;
772 }
773 ad->port_regs.cmd &= ~PORT_CMD_LIST_ON;
774 dma_memory_unmap(ad->hba->as, ad->lst, 1024,
775 DMA_DIRECTION_FROM_DEVICE, 1024);
776 ad->lst = NULL;
777 }
778
779 static void ahci_write_fis_sdb(AHCIState *s, NCQTransferState *ncq_tfs)
780 {
781 AHCIDevice *ad = ncq_tfs->drive;
782 AHCIPortRegs *pr = &ad->port_regs;
783 IDEState *ide_state;
784 SDBFIS *sdb_fis;
785
786 if (!ad->res_fis ||
787 !(pr->cmd & PORT_CMD_FIS_RX)) {
788 return;
789 }
790
791 sdb_fis = (SDBFIS *)&ad->res_fis[RES_FIS_SDBFIS];
792 ide_state = &ad->port.ifs[0];
793
794 sdb_fis->type = SATA_FIS_TYPE_SDB;
795 /* Interrupt pending & Notification bit */
796 sdb_fis->flags = 0x40; /* Interrupt bit, always 1 for NCQ */
797 sdb_fis->status = ide_state->status & 0x77;
798 sdb_fis->error = ide_state->error;
799 /* update SAct field in SDB_FIS */
800 sdb_fis->payload = cpu_to_le32(ad->finished);
801
802 /* Update shadow registers (except BSY 0x80 and DRQ 0x08) */
803 pr->tfdata = (ad->port.ifs[0].error << 8) |
804 (ad->port.ifs[0].status & 0x77) |
805 (pr->tfdata & 0x88);
806 pr->scr_act &= ~ad->finished;
807 ad->finished = 0;
808
809 /*
810 * TFES IRQ is always raised if ERR_STAT is set, regardless of I bit.
811 * If ERR_STAT is not set, trigger SDBS IRQ if interrupt bit is set
812 * (which currently, it always is).
813 */
814 if (sdb_fis->status & ERR_STAT) {
815 ahci_trigger_irq(s, ad, AHCI_PORT_IRQ_BIT_TFES);
816 } else if (sdb_fis->flags & 0x40) {
817 ahci_trigger_irq(s, ad, AHCI_PORT_IRQ_BIT_SDBS);
818 }
819 }
820
821 static void ahci_write_fis_pio(AHCIDevice *ad, uint16_t len, bool pio_fis_i)
822 {
823 AHCIPortRegs *pr = &ad->port_regs;
824 uint8_t *pio_fis;
825 IDEState *s = &ad->port.ifs[0];
826
827 if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) {
828 return;
829 }
830
831 pio_fis = &ad->res_fis[RES_FIS_PSFIS];
832
833 pio_fis[0] = SATA_FIS_TYPE_PIO_SETUP;
834 pio_fis[1] = (pio_fis_i ? (1 << 6) : 0);
835 pio_fis[2] = s->status;
836 pio_fis[3] = s->error;
837
838 pio_fis[4] = s->sector;
839 pio_fis[5] = s->lcyl;
840 pio_fis[6] = s->hcyl;
841 pio_fis[7] = s->select;
842 pio_fis[8] = s->hob_sector;
843 pio_fis[9] = s->hob_lcyl;
844 pio_fis[10] = s->hob_hcyl;
845 pio_fis[11] = 0;
846 pio_fis[12] = s->nsector & 0xFF;
847 pio_fis[13] = (s->nsector >> 8) & 0xFF;
848 pio_fis[14] = 0;
849 pio_fis[15] = s->status;
850 pio_fis[16] = len & 255;
851 pio_fis[17] = len >> 8;
852 pio_fis[18] = 0;
853 pio_fis[19] = 0;
854
855 /* Update shadow registers: */
856 pr->tfdata = (ad->port.ifs[0].error << 8) |
857 ad->port.ifs[0].status;
858
859 if (pio_fis[2] & ERR_STAT) {
860 ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_TFES);
861 }
862 }
863
864 static bool ahci_write_fis_d2h(AHCIDevice *ad, bool d2h_fis_i)
865 {
866 AHCIPortRegs *pr = &ad->port_regs;
867 uint8_t *d2h_fis;
868 int i;
869 IDEState *s = &ad->port.ifs[0];
870
871 if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) {
872 return false;
873 }
874
875 d2h_fis = &ad->res_fis[RES_FIS_RFIS];
876
877 d2h_fis[0] = SATA_FIS_TYPE_REGISTER_D2H;
878 d2h_fis[1] = d2h_fis_i ? (1 << 6) : 0; /* interrupt bit */
879 d2h_fis[2] = s->status;
880 d2h_fis[3] = s->error;
881
882 d2h_fis[4] = s->sector;
883 d2h_fis[5] = s->lcyl;
884 d2h_fis[6] = s->hcyl;
885 d2h_fis[7] = s->select;
886 d2h_fis[8] = s->hob_sector;
887 d2h_fis[9] = s->hob_lcyl;
888 d2h_fis[10] = s->hob_hcyl;
889 d2h_fis[11] = 0;
890 d2h_fis[12] = s->nsector & 0xFF;
891 d2h_fis[13] = (s->nsector >> 8) & 0xFF;
892 for (i = 14; i < 20; i++) {
893 d2h_fis[i] = 0;
894 }
895
896 /* Update shadow registers: */
897 pr->tfdata = (ad->port.ifs[0].error << 8) |
898 ad->port.ifs[0].status;
899
900 if (d2h_fis[2] & ERR_STAT) {
901 ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_TFES);
902 }
903
904 if (d2h_fis_i) {
905 ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_DHRS);
906 }
907
908 return true;
909 }
910
911 static int prdt_tbl_entry_size(const AHCI_SG *tbl)
912 {
913 /* flags_size is zero-based */
914 return (le32_to_cpu(tbl->flags_size) & AHCI_PRDT_SIZE_MASK) + 1;
915 }
916
917 /**
918 * Fetch entries in a guest-provided PRDT and convert it into a QEMU SGlist.
919 * @ad: The AHCIDevice for whom we are building the SGList.
920 * @sglist: The SGList target to add PRD entries to.
921 * @cmd: The AHCI Command Header that describes where the PRDT is.
922 * @limit: The remaining size of the S/ATA transaction, in bytes.
923 * @offset: The number of bytes already transferred, in bytes.
924 *
925 * The AHCI PRDT can describe up to 256GiB. S/ATA only support transactions of
926 * up to 32MiB as of ATA8-ACS3 rev 1b, assuming a 512 byte sector size. We stop
927 * building the sglist from the PRDT as soon as we hit @limit bytes,
928 * which is <= INT32_MAX/2GiB.
929 */
930 static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist,
931 AHCICmdHdr *cmd, int64_t limit, uint64_t offset)
932 {
933 uint16_t opts = le16_to_cpu(cmd->opts);
934 uint16_t prdtl = le16_to_cpu(cmd->prdtl);
935 uint64_t cfis_addr = le64_to_cpu(cmd->tbl_addr);
936 uint64_t prdt_addr = cfis_addr + 0x80;
937 dma_addr_t prdt_len = (prdtl * sizeof(AHCI_SG));
938 dma_addr_t real_prdt_len = prdt_len;
939 uint8_t *prdt;
940 int i;
941 int r = 0;
942 uint64_t sum = 0;
943 int off_idx = -1;
944 int64_t off_pos = -1;
945 int tbl_entry_size;
946 IDEBus *bus = &ad->port;
947 BusState *qbus = BUS(bus);
948
949 trace_ahci_populate_sglist(ad->hba, ad->port_no);
950
951 if (!prdtl) {
952 trace_ahci_populate_sglist_no_prdtl(ad->hba, ad->port_no, opts);
953 return -1;
954 }
955
956 /* map PRDT */
957 if (!(prdt = dma_memory_map(ad->hba->as, prdt_addr, &prdt_len,
958 DMA_DIRECTION_TO_DEVICE,
959 MEMTXATTRS_UNSPECIFIED))){
960 trace_ahci_populate_sglist_no_map(ad->hba, ad->port_no);
961 return -1;
962 }
963
964 if (prdt_len < real_prdt_len) {
965 trace_ahci_populate_sglist_short_map(ad->hba, ad->port_no);
966 r = -1;
967 goto out;
968 }
969
970 /* Get entries in the PRDT, init a qemu sglist accordingly */
971 if (prdtl > 0) {
972 AHCI_SG *tbl = (AHCI_SG *)prdt;
973 sum = 0;
974 for (i = 0; i < prdtl; i++) {
975 tbl_entry_size = prdt_tbl_entry_size(&tbl[i]);
976 if (offset < (sum + tbl_entry_size)) {
977 off_idx = i;
978 off_pos = offset - sum;
979 break;
980 }
981 sum += tbl_entry_size;
982 }
983 if ((off_idx == -1) || (off_pos < 0) || (off_pos > tbl_entry_size)) {
984 trace_ahci_populate_sglist_bad_offset(ad->hba, ad->port_no,
985 off_idx, off_pos);
986 r = -1;
987 goto out;
988 }
989
990 qemu_sglist_init(sglist, qbus->parent, (prdtl - off_idx),
991 ad->hba->as);
992 qemu_sglist_add(sglist, le64_to_cpu(tbl[off_idx].addr) + off_pos,
993 MIN(prdt_tbl_entry_size(&tbl[off_idx]) - off_pos,
994 limit));
995
996 for (i = off_idx + 1; i < prdtl && sglist->size < limit; i++) {
997 qemu_sglist_add(sglist, le64_to_cpu(tbl[i].addr),
998 MIN(prdt_tbl_entry_size(&tbl[i]),
999 limit - sglist->size));
1000 }
1001 }
1002
1003 out:
1004 dma_memory_unmap(ad->hba->as, prdt, prdt_len,
1005 DMA_DIRECTION_TO_DEVICE, prdt_len);
1006 return r;
1007 }
1008
1009 static void ncq_err(NCQTransferState *ncq_tfs)
1010 {
1011 IDEState *ide_state = &ncq_tfs->drive->port.ifs[0];
1012
1013 ide_state->error = ABRT_ERR;
1014 ide_state->status = READY_STAT | ERR_STAT;
1015 qemu_sglist_destroy(&ncq_tfs->sglist);
1016 ncq_tfs->used = 0;
1017 }
1018
1019 static void ncq_finish(NCQTransferState *ncq_tfs)
1020 {
1021 /* If we didn't error out, set our finished bit. Errored commands
1022 * do not get a bit set for the SDB FIS ACT register, nor do they
1023 * clear the outstanding bit in scr_act (PxSACT). */
1024 if (ncq_tfs->used) {
1025 ncq_tfs->drive->finished |= (1 << ncq_tfs->tag);
1026 }
1027
1028 ahci_write_fis_sdb(ncq_tfs->drive->hba, ncq_tfs);
1029
1030 trace_ncq_finish(ncq_tfs->drive->hba, ncq_tfs->drive->port_no,
1031 ncq_tfs->tag);
1032
1033 block_acct_done(blk_get_stats(ncq_tfs->drive->port.ifs[0].blk),
1034 &ncq_tfs->acct);
1035 qemu_sglist_destroy(&ncq_tfs->sglist);
1036 ncq_tfs->used = 0;
1037 }
1038
1039 static void ncq_cb(void *opaque, int ret)
1040 {
1041 NCQTransferState *ncq_tfs = (NCQTransferState *)opaque;
1042 IDEState *ide_state = &ncq_tfs->drive->port.ifs[0];
1043
1044 ncq_tfs->aiocb = NULL;
1045
1046 if (ret < 0) {
1047 bool is_read = ncq_tfs->cmd == READ_FPDMA_QUEUED;
1048 BlockErrorAction action = blk_get_error_action(ide_state->blk,
1049 is_read, -ret);
1050 if (action == BLOCK_ERROR_ACTION_STOP) {
1051 ncq_tfs->halt = true;
1052 ide_state->bus->error_status = IDE_RETRY_HBA;
1053 } else if (action == BLOCK_ERROR_ACTION_REPORT) {
1054 ncq_err(ncq_tfs);
1055 }
1056 blk_error_action(ide_state->blk, action, is_read, -ret);
1057 } else {
1058 ide_state->status = READY_STAT | SEEK_STAT;
1059 }
1060
1061 if (!ncq_tfs->halt) {
1062 ncq_finish(ncq_tfs);
1063 }
1064 }
1065
1066 static int is_ncq(uint8_t ata_cmd)
1067 {
1068 /* Based on SATA 3.2 section 13.6.3.2 */
1069 switch (ata_cmd) {
1070 case READ_FPDMA_QUEUED:
1071 case WRITE_FPDMA_QUEUED:
1072 case NCQ_NON_DATA:
1073 case RECEIVE_FPDMA_QUEUED:
1074 case SEND_FPDMA_QUEUED:
1075 return 1;
1076 default:
1077 return 0;
1078 }
1079 }
1080
1081 static void execute_ncq_command(NCQTransferState *ncq_tfs)
1082 {
1083 AHCIDevice *ad = ncq_tfs->drive;
1084 IDEState *ide_state = &ad->port.ifs[0];
1085 int port = ad->port_no;
1086
1087 g_assert(is_ncq(ncq_tfs->cmd));
1088 ncq_tfs->halt = false;
1089
1090 switch (ncq_tfs->cmd) {
1091 case READ_FPDMA_QUEUED:
1092 trace_execute_ncq_command_read(ad->hba, port, ncq_tfs->tag,
1093 ncq_tfs->sector_count, ncq_tfs->lba);
1094 dma_acct_start(ide_state->blk, &ncq_tfs->acct,
1095 &ncq_tfs->sglist, BLOCK_ACCT_READ);
1096 ncq_tfs->aiocb = dma_blk_read(ide_state->blk, &ncq_tfs->sglist,
1097 ncq_tfs->lba << BDRV_SECTOR_BITS,
1098 BDRV_SECTOR_SIZE,
1099 ncq_cb, ncq_tfs);
1100 break;
1101 case WRITE_FPDMA_QUEUED:
1102 trace_execute_ncq_command_write(ad->hba, port, ncq_tfs->tag,
1103 ncq_tfs->sector_count, ncq_tfs->lba);
1104 dma_acct_start(ide_state->blk, &ncq_tfs->acct,
1105 &ncq_tfs->sglist, BLOCK_ACCT_WRITE);
1106 ncq_tfs->aiocb = dma_blk_write(ide_state->blk, &ncq_tfs->sglist,
1107 ncq_tfs->lba << BDRV_SECTOR_BITS,
1108 BDRV_SECTOR_SIZE,
1109 ncq_cb, ncq_tfs);
1110 break;
1111 default:
1112 trace_execute_ncq_command_unsup(ad->hba, port,
1113 ncq_tfs->tag, ncq_tfs->cmd);
1114 ncq_err(ncq_tfs);
1115 }
1116 }
1117
1118
1119 static void process_ncq_command(AHCIState *s, int port, const uint8_t *cmd_fis,
1120 uint8_t slot)
1121 {
1122 AHCIDevice *ad = &s->dev[port];
1123 const NCQFrame *ncq_fis = (NCQFrame *)cmd_fis;
1124 uint8_t tag = ncq_fis->tag >> 3;
1125 NCQTransferState *ncq_tfs = &ad->ncq_tfs[tag];
1126 size_t size;
1127
1128 g_assert(is_ncq(ncq_fis->command));
1129 if (ncq_tfs->used) {
1130 /* error - already in use */
1131 qemu_log_mask(LOG_GUEST_ERROR, "%s: tag %d already used\n",
1132 __func__, tag);
1133 return;
1134 }
1135
1136 /*
1137 * A NCQ command clears the bit in PxCI after the command has been QUEUED
1138 * successfully (ERROR not set, BUSY and DRQ cleared).
1139 *
1140 * For NCQ commands, PxCI will always be cleared here.
1141 *
1142 * (Once the NCQ command is COMPLETED, the device will send a SDB FIS with
1143 * the interrupt bit set, which will clear PxSACT and raise an interrupt.)
1144 */
1145 ahci_clear_cmd_issue(ad, slot);
1146
1147 /*
1148 * In reality, for NCQ commands, PxCI is cleared after receiving a D2H FIS
1149 * without the interrupt bit set, but since ahci_write_fis_d2h() can raise
1150 * an IRQ on error, we need to call them in reverse order.
1151 */
1152 ahci_write_fis_d2h(ad, false);
1153
1154 ncq_tfs->used = 1;
1155 ncq_tfs->drive = ad;
1156 ncq_tfs->slot = slot;
1157 ncq_tfs->cmdh = &((AHCICmdHdr *)ad->lst)[slot];
1158 ncq_tfs->cmd = ncq_fis->command;
1159 ncq_tfs->lba = ((uint64_t)ncq_fis->lba5 << 40) |
1160 ((uint64_t)ncq_fis->lba4 << 32) |
1161 ((uint64_t)ncq_fis->lba3 << 24) |
1162 ((uint64_t)ncq_fis->lba2 << 16) |
1163 ((uint64_t)ncq_fis->lba1 << 8) |
1164 (uint64_t)ncq_fis->lba0;
1165 ncq_tfs->tag = tag;
1166
1167 /* Sanity-check the NCQ packet */
1168 if (tag != slot) {
1169 trace_process_ncq_command_mismatch(s, port, tag, slot);
1170 }
1171
1172 if (ncq_fis->aux0 || ncq_fis->aux1 || ncq_fis->aux2 || ncq_fis->aux3) {
1173 trace_process_ncq_command_aux(s, port, tag);
1174 }
1175 if (ncq_fis->prio || ncq_fis->icc) {
1176 trace_process_ncq_command_prioicc(s, port, tag);
1177 }
1178 if (ncq_fis->fua & NCQ_FIS_FUA_MASK) {
1179 trace_process_ncq_command_fua(s, port, tag);
1180 }
1181 if (ncq_fis->tag & NCQ_FIS_RARC_MASK) {
1182 trace_process_ncq_command_rarc(s, port, tag);
1183 }
1184
1185 ncq_tfs->sector_count = ((ncq_fis->sector_count_high << 8) |
1186 ncq_fis->sector_count_low);
1187 if (!ncq_tfs->sector_count) {
1188 ncq_tfs->sector_count = 0x10000;
1189 }
1190 size = ncq_tfs->sector_count * BDRV_SECTOR_SIZE;
1191 ahci_populate_sglist(ad, &ncq_tfs->sglist, ncq_tfs->cmdh, size, 0);
1192
1193 if (ncq_tfs->sglist.size < size) {
1194 error_report("ahci: PRDT length for NCQ command (0x" DMA_ADDR_FMT ") "
1195 "is smaller than the requested size (0x%zx)",
1196 ncq_tfs->sglist.size, size);
1197 ncq_err(ncq_tfs);
1198 ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_OFS);
1199 return;
1200 } else if (ncq_tfs->sglist.size != size) {
1201 trace_process_ncq_command_large(s, port, tag,
1202 ncq_tfs->sglist.size, size);
1203 }
1204
1205 trace_process_ncq_command(s, port, tag,
1206 ncq_fis->command,
1207 ncq_tfs->lba,
1208 ncq_tfs->lba + ncq_tfs->sector_count - 1);
1209 execute_ncq_command(ncq_tfs);
1210 }
1211
1212 static AHCICmdHdr *get_cmd_header(AHCIState *s, uint8_t port, uint8_t slot)
1213 {
1214 if (port >= s->ports || slot >= AHCI_MAX_CMDS) {
1215 return NULL;
1216 }
1217
1218 return s->dev[port].lst ? &((AHCICmdHdr *)s->dev[port].lst)[slot] : NULL;
1219 }
1220
1221 static void handle_reg_h2d_fis(AHCIState *s, int port,
1222 uint8_t slot, const uint8_t *cmd_fis)
1223 {
1224 IDEState *ide_state = &s->dev[port].port.ifs[0];
1225 AHCICmdHdr *cmd = get_cmd_header(s, port, slot);
1226 AHCIDevice *ad = &s->dev[port];
1227 uint16_t opts = le16_to_cpu(cmd->opts);
1228
1229 if (cmd_fis[1] & 0x0F) {
1230 trace_handle_reg_h2d_fis_pmp(s, port, cmd_fis[1],
1231 cmd_fis[2], cmd_fis[3]);
1232 return;
1233 }
1234
1235 if (cmd_fis[1] & 0x70) {
1236 trace_handle_reg_h2d_fis_res(s, port, cmd_fis[1],
1237 cmd_fis[2], cmd_fis[3]);
1238 return;
1239 }
1240
1241 if (!(cmd_fis[1] & SATA_FIS_REG_H2D_UPDATE_COMMAND_REGISTER)) {
1242 switch (s->dev[port].port_state) {
1243 case STATE_RUN:
1244 if (cmd_fis[15] & ATA_SRST) {
1245 s->dev[port].port_state = STATE_RESET;
1246 }
1247 break;
1248 case STATE_RESET:
1249 if (!(cmd_fis[15] & ATA_SRST)) {
1250 ahci_reset_port(s, port);
1251 }
1252 break;
1253 }
1254 return;
1255 }
1256
1257 /* Check for NCQ command */
1258 if (is_ncq(cmd_fis[2])) {
1259 process_ncq_command(s, port, cmd_fis, slot);
1260 return;
1261 }
1262
1263 /* Decompose the FIS:
1264 * AHCI does not interpret FIS packets, it only forwards them.
1265 * SATA 1.0 describes how to decode LBA28 and CHS FIS packets.
1266 * Later specifications, e.g, SATA 3.2, describe LBA48 FIS packets.
1267 *
1268 * ATA4 describes sector number for LBA28/CHS commands.
1269 * ATA6 describes sector number for LBA48 commands.
1270 * ATA8 deprecates CHS fully, describing only LBA28/48.
1271 *
1272 * We dutifully convert the FIS into IDE registers, and allow the
1273 * core layer to interpret them as needed. */
1274 ide_state->feature = cmd_fis[3];
1275 ide_state->sector = cmd_fis[4]; /* LBA 7:0 */
1276 ide_state->lcyl = cmd_fis[5]; /* LBA 15:8 */
1277 ide_state->hcyl = cmd_fis[6]; /* LBA 23:16 */
1278 ide_state->select = cmd_fis[7]; /* LBA 27:24 (LBA28) */
1279 ide_state->hob_sector = cmd_fis[8]; /* LBA 31:24 */
1280 ide_state->hob_lcyl = cmd_fis[9]; /* LBA 39:32 */
1281 ide_state->hob_hcyl = cmd_fis[10]; /* LBA 47:40 */
1282 ide_state->hob_feature = cmd_fis[11];
1283 ide_state->nsector = (int64_t)((cmd_fis[13] << 8) | cmd_fis[12]);
1284 /* 14, 16, 17, 18, 19: Reserved (SATA 1.0) */
1285 /* 15: Only valid when UPDATE_COMMAND not set. */
1286
1287 /* Copy the ACMD field (ATAPI packet, if any) from the AHCI command
1288 * table to ide_state->io_buffer */
1289 if (opts & AHCI_CMD_ATAPI) {
1290 memcpy(ide_state->io_buffer, &cmd_fis[AHCI_COMMAND_TABLE_ACMD], 0x10);
1291 if (trace_event_get_state_backends(TRACE_HANDLE_REG_H2D_FIS_DUMP)) {
1292 char *pretty_fis = ahci_pretty_buffer_fis(ide_state->io_buffer, 0x10);
1293 trace_handle_reg_h2d_fis_dump(s, port, pretty_fis);
1294 g_free(pretty_fis);
1295 }
1296 }
1297
1298 ide_state->error = 0;
1299 s->dev[port].done_first_drq = false;
1300 /* Reset transferred byte counter */
1301 cmd->status = 0;
1302
1303 /*
1304 * A non-NCQ command clears the bit in PxCI after the command has COMPLETED
1305 * successfully (ERROR not set, BUSY and DRQ cleared).
1306 *
1307 * For non-NCQ commands, PxCI will always be cleared by ahci_cmd_done().
1308 */
1309 ad->busy_slot = slot;
1310
1311 /* We're ready to process the command in FIS byte 2. */
1312 ide_bus_exec_cmd(&s->dev[port].port, cmd_fis[2]);
1313 }
1314
1315 static void handle_cmd(AHCIState *s, int port, uint8_t slot)
1316 {
1317 IDEState *ide_state;
1318 uint64_t tbl_addr;
1319 AHCICmdHdr *cmd;
1320 uint8_t *cmd_fis;
1321 dma_addr_t cmd_len;
1322
1323 if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) {
1324 /* Engine currently busy, try again later */
1325 trace_handle_cmd_busy(s, port);
1326 return;
1327 }
1328
1329 if (!s->dev[port].lst) {
1330 trace_handle_cmd_nolist(s, port);
1331 return;
1332 }
1333 cmd = get_cmd_header(s, port, slot);
1334 /* remember current slot handle for later */
1335 s->dev[port].cur_cmd = cmd;
1336
1337 /* The device we are working for */
1338 ide_state = &s->dev[port].port.ifs[0];
1339 if (!ide_state->blk) {
1340 trace_handle_cmd_badport(s, port);
1341 return;
1342 }
1343
1344 tbl_addr = le64_to_cpu(cmd->tbl_addr);
1345 cmd_len = 0x80;
1346 cmd_fis = dma_memory_map(s->as, tbl_addr, &cmd_len,
1347 DMA_DIRECTION_TO_DEVICE, MEMTXATTRS_UNSPECIFIED);
1348 if (!cmd_fis) {
1349 trace_handle_cmd_badfis(s, port);
1350 return;
1351 } else if (cmd_len != 0x80) {
1352 ahci_trigger_irq(s, &s->dev[port], AHCI_PORT_IRQ_BIT_HBFS);
1353 trace_handle_cmd_badmap(s, port, cmd_len);
1354 goto out;
1355 }
1356 if (trace_event_get_state_backends(TRACE_HANDLE_CMD_FIS_DUMP)) {
1357 char *pretty_fis = ahci_pretty_buffer_fis(cmd_fis, 0x80);
1358 trace_handle_cmd_fis_dump(s, port, pretty_fis);
1359 g_free(pretty_fis);
1360 }
1361 switch (cmd_fis[0]) {
1362 case SATA_FIS_TYPE_REGISTER_H2D:
1363 handle_reg_h2d_fis(s, port, slot, cmd_fis);
1364 break;
1365 default:
1366 trace_handle_cmd_unhandled_fis(s, port,
1367 cmd_fis[0], cmd_fis[1], cmd_fis[2]);
1368 break;
1369 }
1370
1371 out:
1372 dma_memory_unmap(s->as, cmd_fis, cmd_len, DMA_DIRECTION_TO_DEVICE,
1373 cmd_len);
1374 }
1375
1376 /* Transfer PIO data between RAM and device */
1377 static void ahci_pio_transfer(const IDEDMA *dma)
1378 {
1379 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1380 IDEState *s = &ad->port.ifs[0];
1381 uint32_t size = (uint32_t)(s->data_end - s->data_ptr);
1382 /* write == ram -> device */
1383 uint16_t opts = le16_to_cpu(ad->cur_cmd->opts);
1384 int is_write = opts & AHCI_CMD_WRITE;
1385 int is_atapi = opts & AHCI_CMD_ATAPI;
1386 int has_sglist = 0;
1387 bool pio_fis_i;
1388
1389 /* The PIO Setup FIS is received prior to transfer, but the interrupt
1390 * is only triggered after data is received.
1391 *
1392 * The device only sets the 'I' bit in the PIO Setup FIS for device->host
1393 * requests (see "DPIOI1" in the SATA spec), or for host->device DRQs after
1394 * the first (see "DPIOO1"). The latter is consistent with the spec's
1395 * description of the PACKET protocol, where the command part of ATAPI requests
1396 * ("DPKT0") has the 'I' bit clear, while the data part of PIO ATAPI requests
1397 * ("DPKT4a" and "DPKT7") has the 'I' bit set for both directions for all DRQs.
1398 */
1399 pio_fis_i = ad->done_first_drq || (!is_atapi && !is_write);
1400 ahci_write_fis_pio(ad, size, pio_fis_i);
1401
1402 if (is_atapi && !ad->done_first_drq) {
1403 /* already prepopulated iobuffer */
1404 goto out;
1405 }
1406
1407 if (ahci_dma_prepare_buf(dma, size)) {
1408 has_sglist = 1;
1409 }
1410
1411 trace_ahci_pio_transfer(ad->hba, ad->port_no, is_write ? "writ" : "read",
1412 size, is_atapi ? "atapi" : "ata",
1413 has_sglist ? "" : "o");
1414
1415 if (has_sglist && size) {
1416 const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
1417
1418 if (is_write) {
1419 dma_buf_write(s->data_ptr, size, NULL, &s->sg, attrs);
1420 } else {
1421 dma_buf_read(s->data_ptr, size, NULL, &s->sg, attrs);
1422 }
1423 }
1424
1425 /* Update number of transferred bytes, destroy sglist */
1426 dma_buf_commit(s, size);
1427
1428 out:
1429 /* declare that we processed everything */
1430 s->data_ptr = s->data_end;
1431
1432 ad->done_first_drq = true;
1433 if (pio_fis_i) {
1434 ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_PSS);
1435 }
1436 }
1437
1438 static void ahci_start_dma(const IDEDMA *dma, IDEState *s,
1439 BlockCompletionFunc *dma_cb)
1440 {
1441 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1442 trace_ahci_start_dma(ad->hba, ad->port_no);
1443 s->io_buffer_offset = 0;
1444 dma_cb(s, 0);
1445 }
1446
1447 static void ahci_restart_dma(const IDEDMA *dma)
1448 {
1449 /* Nothing to do, ahci_start_dma already resets s->io_buffer_offset. */
1450 }
1451
1452 /**
1453 * IDE/PIO restarts are handled by the core layer, but NCQ commands
1454 * need an extra kick from the AHCI HBA.
1455 */
1456 static void ahci_restart(const IDEDMA *dma)
1457 {
1458 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1459 int i;
1460
1461 for (i = 0; i < AHCI_MAX_CMDS; i++) {
1462 NCQTransferState *ncq_tfs = &ad->ncq_tfs[i];
1463 if (ncq_tfs->halt) {
1464 execute_ncq_command(ncq_tfs);
1465 }
1466 }
1467 }
1468
1469 /**
1470 * Called in DMA and PIO R/W chains to read the PRDT.
1471 * Not shared with NCQ pathways.
1472 */
1473 static int32_t ahci_dma_prepare_buf(const IDEDMA *dma, int32_t limit)
1474 {
1475 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1476 IDEState *s = &ad->port.ifs[0];
1477
1478 if (ahci_populate_sglist(ad, &s->sg, ad->cur_cmd,
1479 limit, s->io_buffer_offset) == -1) {
1480 trace_ahci_dma_prepare_buf_fail(ad->hba, ad->port_no);
1481 return -1;
1482 }
1483 s->io_buffer_size = s->sg.size;
1484
1485 trace_ahci_dma_prepare_buf(ad->hba, ad->port_no, limit, s->io_buffer_size);
1486 return s->io_buffer_size;
1487 }
1488
1489 /**
1490 * Updates the command header with a bytes-read value.
1491 * Called via dma_buf_commit, for both DMA and PIO paths.
1492 * sglist destruction is handled within dma_buf_commit.
1493 */
1494 static void ahci_commit_buf(const IDEDMA *dma, uint32_t tx_bytes)
1495 {
1496 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1497
1498 tx_bytes += le32_to_cpu(ad->cur_cmd->status);
1499 ad->cur_cmd->status = cpu_to_le32(tx_bytes);
1500 }
1501
1502 static int ahci_dma_rw_buf(const IDEDMA *dma, bool is_write)
1503 {
1504 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1505 IDEState *s = &ad->port.ifs[0];
1506 uint8_t *p = s->io_buffer + s->io_buffer_index;
1507 int l = s->io_buffer_size - s->io_buffer_index;
1508
1509 if (ahci_populate_sglist(ad, &s->sg, ad->cur_cmd, l, s->io_buffer_offset)) {
1510 return 0;
1511 }
1512
1513 if (is_write) {
1514 dma_buf_read(p, l, NULL, &s->sg, MEMTXATTRS_UNSPECIFIED);
1515 } else {
1516 dma_buf_write(p, l, NULL, &s->sg, MEMTXATTRS_UNSPECIFIED);
1517 }
1518
1519 /* free sglist, update byte count */
1520 dma_buf_commit(s, l);
1521 s->io_buffer_index += l;
1522
1523 trace_ahci_dma_rw_buf(ad->hba, ad->port_no, l);
1524 return 1;
1525 }
1526
1527 static void ahci_clear_cmd_issue(AHCIDevice *ad, uint8_t slot)
1528 {
1529 IDEState *ide_state = &ad->port.ifs[0];
1530
1531 if (!(ide_state->status & ERR_STAT) &&
1532 !(ide_state->status & (BUSY_STAT | DRQ_STAT))) {
1533 ad->port_regs.cmd_issue &= ~(1 << slot);
1534 }
1535 }
1536
1537 /* Non-NCQ command is done - This function is never called for NCQ commands. */
1538 static void ahci_cmd_done(const IDEDMA *dma)
1539 {
1540 AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);
1541 IDEState *ide_state = &ad->port.ifs[0];
1542
1543 trace_ahci_cmd_done(ad->hba, ad->port_no);
1544
1545 /* no longer busy */
1546 if (ad->busy_slot != -1) {
1547 ahci_clear_cmd_issue(ad, ad->busy_slot);
1548 ad->busy_slot = -1;
1549 }
1550
1551 /*
1552 * In reality, for non-NCQ commands, PxCI is cleared after receiving a D2H
1553 * FIS with the interrupt bit set, but since ahci_write_fis_d2h() will raise
1554 * an IRQ, we need to call them in reverse order.
1555 */
1556 ahci_write_fis_d2h(ad, true);
1557
1558 if (!(ide_state->status & ERR_STAT) &&
1559 ad->port_regs.cmd_issue && !ad->check_bh) {
1560 ad->check_bh = qemu_bh_new_guarded(ahci_check_cmd_bh, ad,
1561 &ad->mem_reentrancy_guard);
1562 qemu_bh_schedule(ad->check_bh);
1563 }
1564 }
1565
1566 static void ahci_irq_set(void *opaque, int n, int level)
1567 {
1568 qemu_log_mask(LOG_UNIMP, "ahci: IRQ#%d level:%d\n", n, level);
1569 }
1570
1571 static const IDEDMAOps ahci_dma_ops = {
1572 .start_dma = ahci_start_dma,
1573 .restart = ahci_restart,
1574 .restart_dma = ahci_restart_dma,
1575 .pio_transfer = ahci_pio_transfer,
1576 .prepare_buf = ahci_dma_prepare_buf,
1577 .commit_buf = ahci_commit_buf,
1578 .rw_buf = ahci_dma_rw_buf,
1579 .cmd_done = ahci_cmd_done,
1580 };
1581
1582 void ahci_init(AHCIState *s, DeviceState *qdev)
1583 {
1584 s->container = qdev;
1585 /* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */
1586 memory_region_init_io(&s->mem, OBJECT(qdev), &ahci_mem_ops, s,
1587 "ahci", AHCI_MEM_BAR_SIZE);
1588 memory_region_init_io(&s->idp, OBJECT(qdev), &ahci_idp_ops, s,
1589 "ahci-idp", 32);
1590 }
1591
1592 void ahci_realize(AHCIState *s, DeviceState *qdev, AddressSpace *as, int ports)
1593 {
1594 qemu_irq *irqs;
1595 int i;
1596
1597 s->as = as;
1598 s->ports = ports;
1599 s->dev = g_new0(AHCIDevice, ports);
1600 ahci_reg_init(s);
1601 irqs = qemu_allocate_irqs(ahci_irq_set, s, s->ports);
1602 for (i = 0; i < s->ports; i++) {
1603 AHCIDevice *ad = &s->dev[i];
1604
1605 ide_bus_init(&ad->port, sizeof(ad->port), qdev, i, 1);
1606 ide_bus_init_output_irq(&ad->port, irqs[i]);
1607
1608 ad->hba = s;
1609 ad->port_no = i;
1610 ad->port.dma = &ad->dma;
1611 ad->port.dma->ops = &ahci_dma_ops;
1612 ide_bus_register_restart_cb(&ad->port);
1613 }
1614 g_free(irqs);
1615 }
1616
1617 void ahci_uninit(AHCIState *s)
1618 {
1619 int i, j;
1620
1621 for (i = 0; i < s->ports; i++) {
1622 AHCIDevice *ad = &s->dev[i];
1623
1624 for (j = 0; j < 2; j++) {
1625 ide_exit(&ad->port.ifs[j]);
1626 }
1627 object_unparent(OBJECT(&ad->port));
1628 }
1629
1630 g_free(s->dev);
1631 }
1632
1633 void ahci_reset(AHCIState *s)
1634 {
1635 AHCIPortRegs *pr;
1636 int i;
1637
1638 trace_ahci_reset(s);
1639
1640 s->control_regs.irqstatus = 0;
1641 /* AHCI Enable (AE)
1642 * The implementation of this bit is dependent upon the value of the
1643 * CAP.SAM bit. If CAP.SAM is '0', then GHC.AE shall be read-write and
1644 * shall have a reset value of '0'. If CAP.SAM is '1', then AE shall be
1645 * read-only and shall have a reset value of '1'.
1646 *
1647 * We set HOST_CAP_AHCI so we must enable AHCI at reset.
1648 */
1649 s->control_regs.ghc = HOST_CTL_AHCI_EN;
1650
1651 for (i = 0; i < s->ports; i++) {
1652 pr = &s->dev[i].port_regs;
1653 pr->irq_stat = 0;
1654 pr->irq_mask = 0;
1655 pr->scr_ctl = 0;
1656 pr->cmd = PORT_CMD_SPIN_UP | PORT_CMD_POWER_ON;
1657 ahci_reset_port(s, i);
1658 }
1659 }
1660
1661 static const VMStateDescription vmstate_ncq_tfs = {
1662 .name = "ncq state",
1663 .version_id = 1,
1664 .fields = (VMStateField[]) {
1665 VMSTATE_UINT32(sector_count, NCQTransferState),
1666 VMSTATE_UINT64(lba, NCQTransferState),
1667 VMSTATE_UINT8(tag, NCQTransferState),
1668 VMSTATE_UINT8(cmd, NCQTransferState),
1669 VMSTATE_UINT8(slot, NCQTransferState),
1670 VMSTATE_BOOL(used, NCQTransferState),
1671 VMSTATE_BOOL(halt, NCQTransferState),
1672 VMSTATE_END_OF_LIST()
1673 },
1674 };
1675
1676 static const VMStateDescription vmstate_ahci_device = {
1677 .name = "ahci port",
1678 .version_id = 1,
1679 .fields = (VMStateField[]) {
1680 VMSTATE_IDE_BUS(port, AHCIDevice),
1681 VMSTATE_IDE_DRIVE(port.ifs[0], AHCIDevice),
1682 VMSTATE_UINT32(port_state, AHCIDevice),
1683 VMSTATE_UINT32(finished, AHCIDevice),
1684 VMSTATE_UINT32(port_regs.lst_addr, AHCIDevice),
1685 VMSTATE_UINT32(port_regs.lst_addr_hi, AHCIDevice),
1686 VMSTATE_UINT32(port_regs.fis_addr, AHCIDevice),
1687 VMSTATE_UINT32(port_regs.fis_addr_hi, AHCIDevice),
1688 VMSTATE_UINT32(port_regs.irq_stat, AHCIDevice),
1689 VMSTATE_UINT32(port_regs.irq_mask, AHCIDevice),
1690 VMSTATE_UINT32(port_regs.cmd, AHCIDevice),
1691 VMSTATE_UINT32(port_regs.tfdata, AHCIDevice),
1692 VMSTATE_UINT32(port_regs.sig, AHCIDevice),
1693 VMSTATE_UINT32(port_regs.scr_stat, AHCIDevice),
1694 VMSTATE_UINT32(port_regs.scr_ctl, AHCIDevice),
1695 VMSTATE_UINT32(port_regs.scr_err, AHCIDevice),
1696 VMSTATE_UINT32(port_regs.scr_act, AHCIDevice),
1697 VMSTATE_UINT32(port_regs.cmd_issue, AHCIDevice),
1698 VMSTATE_BOOL(done_first_drq, AHCIDevice),
1699 VMSTATE_INT32(busy_slot, AHCIDevice),
1700 VMSTATE_BOOL(init_d2h_sent, AHCIDevice),
1701 VMSTATE_STRUCT_ARRAY(ncq_tfs, AHCIDevice, AHCI_MAX_CMDS,
1702 1, vmstate_ncq_tfs, NCQTransferState),
1703 VMSTATE_END_OF_LIST()
1704 },
1705 };
1706
1707 static int ahci_state_post_load(void *opaque, int version_id)
1708 {
1709 int i, j;
1710 struct AHCIDevice *ad;
1711 NCQTransferState *ncq_tfs;
1712 AHCIPortRegs *pr;
1713 AHCIState *s = opaque;
1714
1715 for (i = 0; i < s->ports; i++) {
1716 ad = &s->dev[i];
1717 pr = &ad->port_regs;
1718
1719 if (!(pr->cmd & PORT_CMD_START) && (pr->cmd & PORT_CMD_LIST_ON)) {
1720 error_report("AHCI: DMA engine should be off, but status bit "
1721 "indicates it is still running.");
1722 return -1;
1723 }
1724 if (!(pr->cmd & PORT_CMD_FIS_RX) && (pr->cmd & PORT_CMD_FIS_ON)) {
1725 error_report("AHCI: FIS RX engine should be off, but status bit "
1726 "indicates it is still running.");
1727 return -1;
1728 }
1729
1730 /* After a migrate, the DMA/FIS engines are "off" and
1731 * need to be conditionally restarted */
1732 pr->cmd &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON);
1733 if (ahci_cond_start_engines(ad) != 0) {
1734 return -1;
1735 }
1736
1737 for (j = 0; j < AHCI_MAX_CMDS; j++) {
1738 ncq_tfs = &ad->ncq_tfs[j];
1739 ncq_tfs->drive = ad;
1740
1741 if (ncq_tfs->used != ncq_tfs->halt) {
1742 return -1;
1743 }
1744 if (!ncq_tfs->halt) {
1745 continue;
1746 }
1747 if (!is_ncq(ncq_tfs->cmd)) {
1748 return -1;
1749 }
1750 if (ncq_tfs->slot != ncq_tfs->tag) {
1751 return -1;
1752 }
1753 /* If ncq_tfs->halt is justly set, the engine should be engaged,
1754 * and the command list buffer should be mapped. */
1755 ncq_tfs->cmdh = get_cmd_header(s, i, ncq_tfs->slot);
1756 if (!ncq_tfs->cmdh) {
1757 return -1;
1758 }
1759 ahci_populate_sglist(ncq_tfs->drive, &ncq_tfs->sglist,
1760 ncq_tfs->cmdh,
1761 ncq_tfs->sector_count * BDRV_SECTOR_SIZE,
1762 0);
1763 if (ncq_tfs->sector_count != ncq_tfs->sglist.size >> 9) {
1764 return -1;
1765 }
1766 }
1767
1768
1769 /*
1770 * If an error is present, ad->busy_slot will be valid and not -1.
1771 * In this case, an operation is waiting to resume and will re-check
1772 * for additional AHCI commands to execute upon completion.
1773 *
1774 * In the case where no error was present, busy_slot will be -1,
1775 * and we should check to see if there are additional commands waiting.
1776 */
1777 if (ad->busy_slot == -1) {
1778 check_cmd(s, i);
1779 } else {
1780 /* We are in the middle of a command, and may need to access
1781 * the command header in guest memory again. */
1782 if (ad->busy_slot < 0 || ad->busy_slot >= AHCI_MAX_CMDS) {
1783 return -1;
1784 }
1785 ad->cur_cmd = get_cmd_header(s, i, ad->busy_slot);
1786 }
1787 }
1788
1789 return 0;
1790 }
1791
1792 const VMStateDescription vmstate_ahci = {
1793 .name = "ahci",
1794 .version_id = 1,
1795 .post_load = ahci_state_post_load,
1796 .fields = (VMStateField[]) {
1797 VMSTATE_STRUCT_VARRAY_POINTER_INT32(dev, AHCIState, ports,
1798 vmstate_ahci_device, AHCIDevice),
1799 VMSTATE_UINT32(control_regs.cap, AHCIState),
1800 VMSTATE_UINT32(control_regs.ghc, AHCIState),
1801 VMSTATE_UINT32(control_regs.irqstatus, AHCIState),
1802 VMSTATE_UINT32(control_regs.impl, AHCIState),
1803 VMSTATE_UINT32(control_regs.version, AHCIState),
1804 VMSTATE_UINT32(idp_index, AHCIState),
1805 VMSTATE_INT32_EQUAL(ports, AHCIState, NULL),
1806 VMSTATE_END_OF_LIST()
1807 },
1808 };
1809
1810 static const VMStateDescription vmstate_sysbus_ahci = {
1811 .name = "sysbus-ahci",
1812 .fields = (VMStateField[]) {
1813 VMSTATE_AHCI(ahci, SysbusAHCIState),
1814 VMSTATE_END_OF_LIST()
1815 },
1816 };
1817
1818 static void sysbus_ahci_reset(DeviceState *dev)
1819 {
1820 SysbusAHCIState *s = SYSBUS_AHCI(dev);
1821
1822 ahci_reset(&s->ahci);
1823 }
1824
1825 static void sysbus_ahci_init(Object *obj)
1826 {
1827 SysbusAHCIState *s = SYSBUS_AHCI(obj);
1828 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1829
1830 ahci_init(&s->ahci, DEVICE(obj));
1831
1832 sysbus_init_mmio(sbd, &s->ahci.mem);
1833 sysbus_init_irq(sbd, &s->ahci.irq);
1834 }
1835
1836 static void sysbus_ahci_realize(DeviceState *dev, Error **errp)
1837 {
1838 SysbusAHCIState *s = SYSBUS_AHCI(dev);
1839
1840 ahci_realize(&s->ahci, dev, &address_space_memory, s->num_ports);
1841 }
1842
1843 static Property sysbus_ahci_properties[] = {
1844 DEFINE_PROP_UINT32("num-ports", SysbusAHCIState, num_ports, 1),
1845 DEFINE_PROP_END_OF_LIST(),
1846 };
1847
1848 static void sysbus_ahci_class_init(ObjectClass *klass, void *data)
1849 {
1850 DeviceClass *dc = DEVICE_CLASS(klass);
1851
1852 dc->realize = sysbus_ahci_realize;
1853 dc->vmsd = &vmstate_sysbus_ahci;
1854 device_class_set_props(dc, sysbus_ahci_properties);
1855 dc->reset = sysbus_ahci_reset;
1856 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
1857 }
1858
1859 static const TypeInfo sysbus_ahci_info = {
1860 .name = TYPE_SYSBUS_AHCI,
1861 .parent = TYPE_SYS_BUS_DEVICE,
1862 .instance_size = sizeof(SysbusAHCIState),
1863 .instance_init = sysbus_ahci_init,
1864 .class_init = sysbus_ahci_class_init,
1865 };
1866
1867 static void sysbus_ahci_register_types(void)
1868 {
1869 type_register_static(&sysbus_ahci_info);
1870 }
1871
1872 type_init(sysbus_ahci_register_types)
1873
1874 int32_t ahci_get_num_ports(PCIDevice *dev)
1875 {
1876 AHCIPCIState *d = ICH9_AHCI(dev);
1877 AHCIState *ahci = &d->ahci;
1878
1879 return ahci->ports;
1880 }
1881
1882 void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd)
1883 {
1884 AHCIPCIState *d = ICH9_AHCI(dev);
1885 AHCIState *ahci = &d->ahci;
1886 int i;
1887
1888 for (i = 0; i < ahci->ports; i++) {
1889 if (hd[i] == NULL) {
1890 continue;
1891 }
1892 ide_bus_create_drive(&ahci->dev[i].port, 0, hd[i]);
1893 }
1894
1895 }
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