2 * ARM SBSA Reference Platform emulation
4 * Copyright (c) 2018 Linaro Limited
5 * Written by Hongbo Zhang <hongbo.zhang@linaro.org>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu/datadir.h"
22 #include "qapi/error.h"
23 #include "qemu/error-report.h"
24 #include "qemu/units.h"
25 #include "sysemu/device_tree.h"
26 #include "sysemu/kvm.h"
27 #include "sysemu/numa.h"
28 #include "sysemu/runstate.h"
29 #include "sysemu/sysemu.h"
30 #include "exec/hwaddr.h"
32 #include "hw/arm/boot.h"
33 #include "hw/arm/fdt.h"
34 #include "hw/arm/smmuv3.h"
35 #include "hw/block/flash.h"
36 #include "hw/boards.h"
37 #include "hw/ide/internal.h"
38 #include "hw/ide/ahci_internal.h"
39 #include "hw/intc/arm_gicv3_common.h"
40 #include "hw/intc/arm_gicv3_its_common.h"
41 #include "hw/loader.h"
42 #include "hw/pci-host/gpex.h"
43 #include "hw/qdev-properties.h"
45 #include "hw/usb/xhci.h"
46 #include "hw/char/pl011.h"
47 #include "hw/watchdog/sbsa_gwdt.h"
49 #include "qom/object.h"
51 #define RAMLIMIT_GB 8192
52 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB)
55 #define NUM_SMMU_IRQS 4
56 #define NUM_SATA_PORTS 6
58 #define VIRTUAL_PMU_IRQ 7
59 #define ARCH_GIC_MAINT_IRQ 9
60 #define ARCH_TIMER_VIRT_IRQ 11
61 #define ARCH_TIMER_S_EL1_IRQ 13
62 #define ARCH_TIMER_NS_EL1_IRQ 14
63 #define ARCH_TIMER_NS_EL2_IRQ 10
92 struct SBSAMachineState
{
94 struct arm_boot_info bootinfo
;
100 PFlashCFI01
*flash
[2];
103 #define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref")
104 OBJECT_DECLARE_SIMPLE_TYPE(SBSAMachineState
, SBSA_MACHINE
)
106 static const MemMapEntry sbsa_ref_memmap
[] = {
108 [SBSA_FLASH
] = { 0, 0x20000000 },
109 /* 512M secure memory */
110 [SBSA_SECURE_MEM
] = { 0x20000000, 0x20000000 },
111 /* Space reserved for CPU peripheral devices */
112 [SBSA_CPUPERIPHS
] = { 0x40000000, 0x00040000 },
113 [SBSA_GIC_DIST
] = { 0x40060000, 0x00010000 },
114 [SBSA_GIC_REDIST
] = { 0x40080000, 0x04000000 },
115 [SBSA_GIC_ITS
] = { 0x44081000, 0x00020000 },
116 [SBSA_SECURE_EC
] = { 0x50000000, 0x00001000 },
117 [SBSA_GWDT_REFRESH
] = { 0x50010000, 0x00001000 },
118 [SBSA_GWDT_CONTROL
] = { 0x50011000, 0x00001000 },
119 [SBSA_UART
] = { 0x60000000, 0x00001000 },
120 [SBSA_RTC
] = { 0x60010000, 0x00001000 },
121 [SBSA_GPIO
] = { 0x60020000, 0x00001000 },
122 [SBSA_SECURE_UART
] = { 0x60030000, 0x00001000 },
123 [SBSA_SECURE_UART_MM
] = { 0x60040000, 0x00001000 },
124 [SBSA_SMMU
] = { 0x60050000, 0x00020000 },
125 /* Space here reserved for more SMMUs */
126 [SBSA_AHCI
] = { 0x60100000, 0x00010000 },
127 [SBSA_XHCI
] = { 0x60110000, 0x00010000 },
128 /* Space here reserved for other devices */
129 [SBSA_PCIE_PIO
] = { 0x7fff0000, 0x00010000 },
130 /* 32-bit address PCIE MMIO space */
131 [SBSA_PCIE_MMIO
] = { 0x80000000, 0x70000000 },
132 /* 256M PCIE ECAM space */
133 [SBSA_PCIE_ECAM
] = { 0xf0000000, 0x10000000 },
134 /* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */
135 [SBSA_PCIE_MMIO_HIGH
] = { 0x100000000ULL
, 0xFF00000000ULL
},
136 [SBSA_MEM
] = { 0x10000000000ULL
, RAMLIMIT_BYTES
},
139 static const int sbsa_ref_irqmap
[] = {
142 [SBSA_PCIE
] = 3, /* ... to 6 */
144 [SBSA_SECURE_UART
] = 8,
145 [SBSA_SECURE_UART_MM
] = 9,
148 [SBSA_SMMU
] = 12, /* ... to 15 */
149 [SBSA_GWDT_WS0
] = 16,
152 static const char * const valid_cpus
[] = {
153 ARM_CPU_TYPE_NAME("cortex-a57"),
154 ARM_CPU_TYPE_NAME("cortex-a72"),
155 ARM_CPU_TYPE_NAME("neoverse-n1"),
156 ARM_CPU_TYPE_NAME("neoverse-v1"),
157 ARM_CPU_TYPE_NAME("max"),
160 static bool cpu_type_valid(const char *cpu
)
164 for (i
= 0; i
< ARRAY_SIZE(valid_cpus
); i
++) {
165 if (strcmp(cpu
, valid_cpus
[i
]) == 0) {
172 static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState
*sms
, int idx
)
174 uint8_t clustersz
= ARM_DEFAULT_CPUS_PER_CLUSTER
;
175 return arm_cpu_mp_affinity(idx
, clustersz
);
178 static void sbsa_fdt_add_gic_node(SBSAMachineState
*sms
)
182 nodename
= g_strdup_printf("/intc");
183 qemu_fdt_add_subnode(sms
->fdt
, nodename
);
184 qemu_fdt_setprop_sized_cells(sms
->fdt
, nodename
, "reg",
185 2, sbsa_ref_memmap
[SBSA_GIC_DIST
].base
,
186 2, sbsa_ref_memmap
[SBSA_GIC_DIST
].size
,
187 2, sbsa_ref_memmap
[SBSA_GIC_REDIST
].base
,
188 2, sbsa_ref_memmap
[SBSA_GIC_REDIST
].size
);
190 nodename
= g_strdup_printf("/intc/its");
191 qemu_fdt_add_subnode(sms
->fdt
, nodename
);
192 qemu_fdt_setprop_sized_cells(sms
->fdt
, nodename
, "reg",
193 2, sbsa_ref_memmap
[SBSA_GIC_ITS
].base
,
194 2, sbsa_ref_memmap
[SBSA_GIC_ITS
].size
);
200 * Firmware on this machine only uses ACPI table to load OS, these limited
201 * device tree nodes are just to let firmware know the info which varies from
202 * command line parameters, so it is not necessary to be fully compatible
203 * with the kernel CPU and NUMA binding rules.
205 static void create_fdt(SBSAMachineState
*sms
)
207 void *fdt
= create_device_tree(&sms
->fdt_size
);
208 const MachineState
*ms
= MACHINE(sms
);
209 int nb_numa_nodes
= ms
->numa_state
->num_nodes
;
213 error_report("create_device_tree() failed");
219 qemu_fdt_setprop_string(fdt
, "/", "compatible", "linux,sbsa-ref");
220 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 0x2);
221 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 0x2);
224 * This versioning scheme is for informing platform fw only. It is neither:
225 * - A QEMU versioned machine type; a given version of QEMU will emulate
226 * a given version of the platform.
227 * - A reflection of level of SBSA (now SystemReady SR) support provided.
229 * machine-version-major: updated when changes breaking fw compatibility
231 * machine-version-minor: updated when features are added that don't break
234 qemu_fdt_setprop_cell(fdt
, "/", "machine-version-major", 0);
235 qemu_fdt_setprop_cell(fdt
, "/", "machine-version-minor", 3);
237 if (ms
->numa_state
->have_numa_distance
) {
238 int size
= nb_numa_nodes
* nb_numa_nodes
* 3 * sizeof(uint32_t);
239 uint32_t *matrix
= g_malloc0(size
);
242 for (i
= 0; i
< nb_numa_nodes
; i
++) {
243 for (j
= 0; j
< nb_numa_nodes
; j
++) {
244 idx
= (i
* nb_numa_nodes
+ j
) * 3;
245 matrix
[idx
+ 0] = cpu_to_be32(i
);
246 matrix
[idx
+ 1] = cpu_to_be32(j
);
248 cpu_to_be32(ms
->numa_state
->nodes
[i
].distance
[j
]);
252 qemu_fdt_add_subnode(fdt
, "/distance-map");
253 qemu_fdt_setprop(fdt
, "/distance-map", "distance-matrix",
259 * From Documentation/devicetree/bindings/arm/cpus.yaml
260 * On ARM v8 64-bit systems this property is required
261 * and matches the MPIDR_EL1 register affinity bits.
263 * * If cpus node's #address-cells property is set to 2
265 * The first reg cell bits [7:0] must be set to
266 * bits [39:32] of MPIDR_EL1.
268 * The second reg cell bits [23:0] must be set to
269 * bits [23:0] of MPIDR_EL1.
271 qemu_fdt_add_subnode(sms
->fdt
, "/cpus");
272 qemu_fdt_setprop_cell(sms
->fdt
, "/cpus", "#address-cells", 2);
273 qemu_fdt_setprop_cell(sms
->fdt
, "/cpus", "#size-cells", 0x0);
275 for (cpu
= sms
->smp_cpus
- 1; cpu
>= 0; cpu
--) {
276 char *nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
277 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
278 CPUState
*cs
= CPU(armcpu
);
279 uint64_t mpidr
= sbsa_ref_cpu_mp_affinity(sms
, cpu
);
281 qemu_fdt_add_subnode(sms
->fdt
, nodename
);
282 qemu_fdt_setprop_u64(sms
->fdt
, nodename
, "reg", mpidr
);
284 if (ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.has_node_id
) {
285 qemu_fdt_setprop_cell(sms
->fdt
, nodename
, "numa-node-id",
286 ms
->possible_cpus
->cpus
[cs
->cpu_index
].props
.node_id
);
292 sbsa_fdt_add_gic_node(sms
);
295 #define SBSA_FLASH_SECTOR_SIZE (256 * KiB)
297 static PFlashCFI01
*sbsa_flash_create1(SBSAMachineState
*sms
,
299 const char *alias_prop_name
)
302 * Create a single flash device. We use the same parameters as
303 * the flash devices on the Versatile Express board.
305 DeviceState
*dev
= qdev_new(TYPE_PFLASH_CFI01
);
307 qdev_prop_set_uint64(dev
, "sector-length", SBSA_FLASH_SECTOR_SIZE
);
308 qdev_prop_set_uint8(dev
, "width", 4);
309 qdev_prop_set_uint8(dev
, "device-width", 2);
310 qdev_prop_set_bit(dev
, "big-endian", false);
311 qdev_prop_set_uint16(dev
, "id0", 0x89);
312 qdev_prop_set_uint16(dev
, "id1", 0x18);
313 qdev_prop_set_uint16(dev
, "id2", 0x00);
314 qdev_prop_set_uint16(dev
, "id3", 0x00);
315 qdev_prop_set_string(dev
, "name", name
);
316 object_property_add_child(OBJECT(sms
), name
, OBJECT(dev
));
317 object_property_add_alias(OBJECT(sms
), alias_prop_name
,
318 OBJECT(dev
), "drive");
319 return PFLASH_CFI01(dev
);
322 static void sbsa_flash_create(SBSAMachineState
*sms
)
324 sms
->flash
[0] = sbsa_flash_create1(sms
, "sbsa.flash0", "pflash0");
325 sms
->flash
[1] = sbsa_flash_create1(sms
, "sbsa.flash1", "pflash1");
328 static void sbsa_flash_map1(PFlashCFI01
*flash
,
329 hwaddr base
, hwaddr size
,
330 MemoryRegion
*sysmem
)
332 DeviceState
*dev
= DEVICE(flash
);
334 assert(QEMU_IS_ALIGNED(size
, SBSA_FLASH_SECTOR_SIZE
));
335 assert(size
/ SBSA_FLASH_SECTOR_SIZE
<= UINT32_MAX
);
336 qdev_prop_set_uint32(dev
, "num-blocks", size
/ SBSA_FLASH_SECTOR_SIZE
);
337 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
339 memory_region_add_subregion(sysmem
, base
,
340 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
),
344 static void sbsa_flash_map(SBSAMachineState
*sms
,
345 MemoryRegion
*sysmem
,
346 MemoryRegion
*secure_sysmem
)
349 * Map two flash devices to fill the SBSA_FLASH space in the memmap.
350 * sysmem is the system memory space. secure_sysmem is the secure view
351 * of the system, and the first flash device should be made visible only
352 * there. The second flash device is visible to both secure and nonsecure.
354 hwaddr flashsize
= sbsa_ref_memmap
[SBSA_FLASH
].size
/ 2;
355 hwaddr flashbase
= sbsa_ref_memmap
[SBSA_FLASH
].base
;
357 sbsa_flash_map1(sms
->flash
[0], flashbase
, flashsize
,
359 sbsa_flash_map1(sms
->flash
[1], flashbase
+ flashsize
, flashsize
,
363 static bool sbsa_firmware_init(SBSAMachineState
*sms
,
364 MemoryRegion
*sysmem
,
365 MemoryRegion
*secure_sysmem
)
367 const char *bios_name
;
369 BlockBackend
*pflash_blk0
;
371 /* Map legacy -drive if=pflash to machine properties */
372 for (i
= 0; i
< ARRAY_SIZE(sms
->flash
); i
++) {
373 pflash_cfi01_legacy_drive(sms
->flash
[i
],
374 drive_get(IF_PFLASH
, 0, i
));
377 sbsa_flash_map(sms
, sysmem
, secure_sysmem
);
379 pflash_blk0
= pflash_cfi01_get_blk(sms
->flash
[0]);
381 bios_name
= MACHINE(sms
)->firmware
;
388 error_report("The contents of the first flash device may be "
389 "specified with -bios or with -drive if=pflash... "
390 "but you cannot use both options at once");
394 /* Fall back to -bios */
396 fname
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
398 error_report("Could not find ROM image '%s'", bios_name
);
401 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(sms
->flash
[0]), 0);
402 image_size
= load_image_mr(fname
, mr
);
404 if (image_size
< 0) {
405 error_report("Could not load ROM image '%s'", bios_name
);
410 return pflash_blk0
|| bios_name
;
413 static void create_secure_ram(SBSAMachineState
*sms
,
414 MemoryRegion
*secure_sysmem
)
416 MemoryRegion
*secram
= g_new(MemoryRegion
, 1);
417 hwaddr base
= sbsa_ref_memmap
[SBSA_SECURE_MEM
].base
;
418 hwaddr size
= sbsa_ref_memmap
[SBSA_SECURE_MEM
].size
;
420 memory_region_init_ram(secram
, NULL
, "sbsa-ref.secure-ram", size
,
422 memory_region_add_subregion(secure_sysmem
, base
, secram
);
425 static void create_its(SBSAMachineState
*sms
)
427 const char *itsclass
= its_class_name();
430 dev
= qdev_new(itsclass
);
432 object_property_set_link(OBJECT(dev
), "parent-gicv3", OBJECT(sms
->gic
),
434 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
435 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, sbsa_ref_memmap
[SBSA_GIC_ITS
].base
);
438 static void create_gic(SBSAMachineState
*sms
, MemoryRegion
*mem
)
440 unsigned int smp_cpus
= MACHINE(sms
)->smp
.cpus
;
441 SysBusDevice
*gicbusdev
;
443 uint32_t redist0_capacity
, redist0_count
;
446 gictype
= gicv3_class_name();
448 sms
->gic
= qdev_new(gictype
);
449 qdev_prop_set_uint32(sms
->gic
, "revision", 3);
450 qdev_prop_set_uint32(sms
->gic
, "num-cpu", smp_cpus
);
452 * Note that the num-irq property counts both internal and external
453 * interrupts; there are always 32 of the former (mandated by GIC spec).
455 qdev_prop_set_uint32(sms
->gic
, "num-irq", NUM_IRQS
+ 32);
456 qdev_prop_set_bit(sms
->gic
, "has-security-extensions", true);
459 sbsa_ref_memmap
[SBSA_GIC_REDIST
].size
/ GICV3_REDIST_SIZE
;
460 redist0_count
= MIN(smp_cpus
, redist0_capacity
);
462 qdev_prop_set_uint32(sms
->gic
, "len-redist-region-count", 1);
463 qdev_prop_set_uint32(sms
->gic
, "redist-region-count[0]", redist0_count
);
465 object_property_set_link(OBJECT(sms
->gic
), "sysmem",
466 OBJECT(mem
), &error_fatal
);
467 qdev_prop_set_bit(sms
->gic
, "has-lpi", true);
469 gicbusdev
= SYS_BUS_DEVICE(sms
->gic
);
470 sysbus_realize_and_unref(gicbusdev
, &error_fatal
);
471 sysbus_mmio_map(gicbusdev
, 0, sbsa_ref_memmap
[SBSA_GIC_DIST
].base
);
472 sysbus_mmio_map(gicbusdev
, 1, sbsa_ref_memmap
[SBSA_GIC_REDIST
].base
);
475 * Wire the outputs from each CPU's generic timer and the GICv3
476 * maintenance interrupt signal to the appropriate GIC PPI inputs,
477 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
479 for (i
= 0; i
< smp_cpus
; i
++) {
480 DeviceState
*cpudev
= DEVICE(qemu_get_cpu(i
));
481 int ppibase
= NUM_IRQS
+ i
* GIC_INTERNAL
+ GIC_NR_SGIS
;
484 * Mapping from the output timer irq lines from the CPU to the
485 * GIC PPI inputs used for this board.
487 const int timer_irq
[] = {
488 [GTIMER_PHYS
] = ARCH_TIMER_NS_EL1_IRQ
,
489 [GTIMER_VIRT
] = ARCH_TIMER_VIRT_IRQ
,
490 [GTIMER_HYP
] = ARCH_TIMER_NS_EL2_IRQ
,
491 [GTIMER_SEC
] = ARCH_TIMER_S_EL1_IRQ
,
494 for (irq
= 0; irq
< ARRAY_SIZE(timer_irq
); irq
++) {
495 qdev_connect_gpio_out(cpudev
, irq
,
496 qdev_get_gpio_in(sms
->gic
,
497 ppibase
+ timer_irq
[irq
]));
500 qdev_connect_gpio_out_named(cpudev
, "gicv3-maintenance-interrupt", 0,
501 qdev_get_gpio_in(sms
->gic
, ppibase
502 + ARCH_GIC_MAINT_IRQ
));
503 qdev_connect_gpio_out_named(cpudev
, "pmu-interrupt", 0,
504 qdev_get_gpio_in(sms
->gic
, ppibase
507 sysbus_connect_irq(gicbusdev
, i
, qdev_get_gpio_in(cpudev
, ARM_CPU_IRQ
));
508 sysbus_connect_irq(gicbusdev
, i
+ smp_cpus
,
509 qdev_get_gpio_in(cpudev
, ARM_CPU_FIQ
));
510 sysbus_connect_irq(gicbusdev
, i
+ 2 * smp_cpus
,
511 qdev_get_gpio_in(cpudev
, ARM_CPU_VIRQ
));
512 sysbus_connect_irq(gicbusdev
, i
+ 3 * smp_cpus
,
513 qdev_get_gpio_in(cpudev
, ARM_CPU_VFIQ
));
518 static void create_uart(const SBSAMachineState
*sms
, int uart
,
519 MemoryRegion
*mem
, Chardev
*chr
)
521 hwaddr base
= sbsa_ref_memmap
[uart
].base
;
522 int irq
= sbsa_ref_irqmap
[uart
];
523 DeviceState
*dev
= qdev_new(TYPE_PL011
);
524 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
526 qdev_prop_set_chr(dev
, "chardev", chr
);
527 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
528 memory_region_add_subregion(mem
, base
,
529 sysbus_mmio_get_region(s
, 0));
530 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(sms
->gic
, irq
));
533 static void create_rtc(const SBSAMachineState
*sms
)
535 hwaddr base
= sbsa_ref_memmap
[SBSA_RTC
].base
;
536 int irq
= sbsa_ref_irqmap
[SBSA_RTC
];
538 sysbus_create_simple("pl031", base
, qdev_get_gpio_in(sms
->gic
, irq
));
541 static void create_wdt(const SBSAMachineState
*sms
)
543 hwaddr rbase
= sbsa_ref_memmap
[SBSA_GWDT_REFRESH
].base
;
544 hwaddr cbase
= sbsa_ref_memmap
[SBSA_GWDT_CONTROL
].base
;
545 DeviceState
*dev
= qdev_new(TYPE_WDT_SBSA
);
546 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
547 int irq
= sbsa_ref_irqmap
[SBSA_GWDT_WS0
];
549 sysbus_realize_and_unref(s
, &error_fatal
);
550 sysbus_mmio_map(s
, 0, rbase
);
551 sysbus_mmio_map(s
, 1, cbase
);
552 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(sms
->gic
, irq
));
555 static DeviceState
*gpio_key_dev
;
556 static void sbsa_ref_powerdown_req(Notifier
*n
, void *opaque
)
558 /* use gpio Pin 3 for power button event */
559 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev
, 0), 1);
562 static Notifier sbsa_ref_powerdown_notifier
= {
563 .notify
= sbsa_ref_powerdown_req
566 static void create_gpio(const SBSAMachineState
*sms
)
568 DeviceState
*pl061_dev
;
569 hwaddr base
= sbsa_ref_memmap
[SBSA_GPIO
].base
;
570 int irq
= sbsa_ref_irqmap
[SBSA_GPIO
];
572 pl061_dev
= sysbus_create_simple("pl061", base
,
573 qdev_get_gpio_in(sms
->gic
, irq
));
575 gpio_key_dev
= sysbus_create_simple("gpio-key", -1,
576 qdev_get_gpio_in(pl061_dev
, 3));
578 /* connect powerdown request */
579 qemu_register_powerdown_notifier(&sbsa_ref_powerdown_notifier
);
582 static void create_ahci(const SBSAMachineState
*sms
)
584 hwaddr base
= sbsa_ref_memmap
[SBSA_AHCI
].base
;
585 int irq
= sbsa_ref_irqmap
[SBSA_AHCI
];
587 DriveInfo
*hd
[NUM_SATA_PORTS
];
588 SysbusAHCIState
*sysahci
;
592 dev
= qdev_new("sysbus-ahci");
593 qdev_prop_set_uint32(dev
, "num-ports", NUM_SATA_PORTS
);
594 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
595 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);
596 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, qdev_get_gpio_in(sms
->gic
, irq
));
598 sysahci
= SYSBUS_AHCI(dev
);
599 ahci
= &sysahci
->ahci
;
600 ide_drive_get(hd
, ARRAY_SIZE(hd
));
601 for (i
= 0; i
< ahci
->ports
; i
++) {
605 ide_bus_create_drive(&ahci
->dev
[i
].port
, 0, hd
[i
]);
609 static void create_xhci(const SBSAMachineState
*sms
)
611 hwaddr base
= sbsa_ref_memmap
[SBSA_XHCI
].base
;
612 int irq
= sbsa_ref_irqmap
[SBSA_XHCI
];
613 DeviceState
*dev
= qdev_new(TYPE_XHCI_SYSBUS
);
614 qdev_prop_set_uint32(dev
, "slots", XHCI_MAXSLOTS
);
616 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
617 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);
618 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, qdev_get_gpio_in(sms
->gic
, irq
));
621 static void create_smmu(const SBSAMachineState
*sms
, PCIBus
*bus
)
623 hwaddr base
= sbsa_ref_memmap
[SBSA_SMMU
].base
;
624 int irq
= sbsa_ref_irqmap
[SBSA_SMMU
];
628 dev
= qdev_new(TYPE_ARM_SMMUV3
);
630 object_property_set_link(OBJECT(dev
), "primary-bus", OBJECT(bus
),
632 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
633 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);
634 for (i
= 0; i
< NUM_SMMU_IRQS
; i
++) {
635 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
636 qdev_get_gpio_in(sms
->gic
, irq
+ i
));
640 static void create_pcie(SBSAMachineState
*sms
)
642 hwaddr base_ecam
= sbsa_ref_memmap
[SBSA_PCIE_ECAM
].base
;
643 hwaddr size_ecam
= sbsa_ref_memmap
[SBSA_PCIE_ECAM
].size
;
644 hwaddr base_mmio
= sbsa_ref_memmap
[SBSA_PCIE_MMIO
].base
;
645 hwaddr size_mmio
= sbsa_ref_memmap
[SBSA_PCIE_MMIO
].size
;
646 hwaddr base_mmio_high
= sbsa_ref_memmap
[SBSA_PCIE_MMIO_HIGH
].base
;
647 hwaddr size_mmio_high
= sbsa_ref_memmap
[SBSA_PCIE_MMIO_HIGH
].size
;
648 hwaddr base_pio
= sbsa_ref_memmap
[SBSA_PCIE_PIO
].base
;
649 int irq
= sbsa_ref_irqmap
[SBSA_PCIE
];
650 MachineClass
*mc
= MACHINE_GET_CLASS(sms
);
651 MemoryRegion
*mmio_alias
, *mmio_alias_high
, *mmio_reg
;
652 MemoryRegion
*ecam_alias
, *ecam_reg
;
657 dev
= qdev_new(TYPE_GPEX_HOST
);
658 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
661 ecam_alias
= g_new0(MemoryRegion
, 1);
662 ecam_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
663 memory_region_init_alias(ecam_alias
, OBJECT(dev
), "pcie-ecam",
664 ecam_reg
, 0, size_ecam
);
665 memory_region_add_subregion(get_system_memory(), base_ecam
, ecam_alias
);
667 /* Map the MMIO space */
668 mmio_alias
= g_new0(MemoryRegion
, 1);
669 mmio_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
670 memory_region_init_alias(mmio_alias
, OBJECT(dev
), "pcie-mmio",
671 mmio_reg
, base_mmio
, size_mmio
);
672 memory_region_add_subregion(get_system_memory(), base_mmio
, mmio_alias
);
674 /* Map the MMIO_HIGH space */
675 mmio_alias_high
= g_new0(MemoryRegion
, 1);
676 memory_region_init_alias(mmio_alias_high
, OBJECT(dev
), "pcie-mmio-high",
677 mmio_reg
, base_mmio_high
, size_mmio_high
);
678 memory_region_add_subregion(get_system_memory(), base_mmio_high
,
681 /* Map IO port space */
682 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 2, base_pio
);
684 for (i
= 0; i
< GPEX_NUM_IRQS
; i
++) {
685 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
686 qdev_get_gpio_in(sms
->gic
, irq
+ i
));
687 gpex_set_irq_num(GPEX_HOST(dev
), i
, irq
+ i
);
690 pci
= PCI_HOST_BRIDGE(dev
);
692 for (i
= 0; i
< nb_nics
; i
++) {
693 pci_nic_init_nofail(&nd_table
[i
], pci
->bus
, mc
->default_nic
, NULL
);
697 pci_create_simple(pci
->bus
, -1, "bochs-display");
699 create_smmu(sms
, pci
->bus
);
702 static void *sbsa_ref_dtb(const struct arm_boot_info
*binfo
, int *fdt_size
)
704 const SBSAMachineState
*board
= container_of(binfo
, SBSAMachineState
,
707 *fdt_size
= board
->fdt_size
;
711 static void create_secure_ec(MemoryRegion
*mem
)
713 hwaddr base
= sbsa_ref_memmap
[SBSA_SECURE_EC
].base
;
714 DeviceState
*dev
= qdev_new("sbsa-ec");
715 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
717 memory_region_add_subregion(mem
, base
,
718 sysbus_mmio_get_region(s
, 0));
721 static void sbsa_ref_init(MachineState
*machine
)
723 unsigned int smp_cpus
= machine
->smp
.cpus
;
724 unsigned int max_cpus
= machine
->smp
.max_cpus
;
725 SBSAMachineState
*sms
= SBSA_MACHINE(machine
);
726 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
727 MemoryRegion
*sysmem
= get_system_memory();
728 MemoryRegion
*secure_sysmem
= g_new(MemoryRegion
, 1);
729 bool firmware_loaded
;
730 const CPUArchIdList
*possible_cpus
;
731 int n
, sbsa_max_cpus
;
733 if (!cpu_type_valid(machine
->cpu_type
)) {
734 error_report("sbsa-ref: CPU type %s not supported", machine
->cpu_type
);
739 error_report("sbsa-ref: KVM is not supported for this machine");
744 * The Secure view of the world is the same as the NonSecure,
745 * but with a few extra devices. Create it as a container region
746 * containing the system memory at low priority; any secure-only
747 * devices go in at higher priority and take precedence.
749 memory_region_init(secure_sysmem
, OBJECT(machine
), "secure-memory",
751 memory_region_add_subregion_overlap(secure_sysmem
, 0, sysmem
, -1);
753 firmware_loaded
= sbsa_firmware_init(sms
, sysmem
, secure_sysmem
);
756 * This machine has EL3 enabled, external firmware should supply PSCI
757 * implementation, so the QEMU's internal PSCI is disabled.
759 sms
->psci_conduit
= QEMU_PSCI_CONDUIT_DISABLED
;
761 sbsa_max_cpus
= sbsa_ref_memmap
[SBSA_GIC_REDIST
].size
/ GICV3_REDIST_SIZE
;
763 if (max_cpus
> sbsa_max_cpus
) {
764 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
765 "supported by machine 'sbsa-ref' (%d)",
766 max_cpus
, sbsa_max_cpus
);
770 sms
->smp_cpus
= smp_cpus
;
772 if (machine
->ram_size
> sbsa_ref_memmap
[SBSA_MEM
].size
) {
773 error_report("sbsa-ref: cannot model more than %dGB RAM", RAMLIMIT_GB
);
777 possible_cpus
= mc
->possible_cpu_arch_ids(machine
);
778 for (n
= 0; n
< possible_cpus
->len
; n
++) {
786 cpuobj
= object_new(possible_cpus
->cpus
[n
].type
);
787 object_property_set_int(cpuobj
, "mp-affinity",
788 possible_cpus
->cpus
[n
].arch_id
, NULL
);
793 numa_cpu_pre_plug(&possible_cpus
->cpus
[cs
->cpu_index
], DEVICE(cpuobj
),
796 if (object_property_find(cpuobj
, "reset-cbar")) {
797 object_property_set_int(cpuobj
, "reset-cbar",
798 sbsa_ref_memmap
[SBSA_CPUPERIPHS
].base
,
802 object_property_set_link(cpuobj
, "memory", OBJECT(sysmem
),
805 object_property_set_link(cpuobj
, "secure-memory",
806 OBJECT(secure_sysmem
), &error_abort
);
808 qdev_realize(DEVICE(cpuobj
), NULL
, &error_fatal
);
809 object_unref(cpuobj
);
812 memory_region_add_subregion(sysmem
, sbsa_ref_memmap
[SBSA_MEM
].base
,
817 create_secure_ram(sms
, secure_sysmem
);
819 create_gic(sms
, sysmem
);
821 create_uart(sms
, SBSA_UART
, sysmem
, serial_hd(0));
822 create_uart(sms
, SBSA_SECURE_UART
, secure_sysmem
, serial_hd(1));
823 /* Second secure UART for RAS and MM from EL0 */
824 create_uart(sms
, SBSA_SECURE_UART_MM
, secure_sysmem
, serial_hd(2));
838 create_secure_ec(secure_sysmem
);
840 sms
->bootinfo
.ram_size
= machine
->ram_size
;
841 sms
->bootinfo
.board_id
= -1;
842 sms
->bootinfo
.loader_start
= sbsa_ref_memmap
[SBSA_MEM
].base
;
843 sms
->bootinfo
.get_dtb
= sbsa_ref_dtb
;
844 sms
->bootinfo
.firmware_loaded
= firmware_loaded
;
845 arm_load_kernel(ARM_CPU(first_cpu
), machine
, &sms
->bootinfo
);
848 static const CPUArchIdList
*sbsa_ref_possible_cpu_arch_ids(MachineState
*ms
)
850 unsigned int max_cpus
= ms
->smp
.max_cpus
;
851 SBSAMachineState
*sms
= SBSA_MACHINE(ms
);
854 if (ms
->possible_cpus
) {
855 assert(ms
->possible_cpus
->len
== max_cpus
);
856 return ms
->possible_cpus
;
859 ms
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
860 sizeof(CPUArchId
) * max_cpus
);
861 ms
->possible_cpus
->len
= max_cpus
;
862 for (n
= 0; n
< ms
->possible_cpus
->len
; n
++) {
863 ms
->possible_cpus
->cpus
[n
].type
= ms
->cpu_type
;
864 ms
->possible_cpus
->cpus
[n
].arch_id
=
865 sbsa_ref_cpu_mp_affinity(sms
, n
);
866 ms
->possible_cpus
->cpus
[n
].props
.has_thread_id
= true;
867 ms
->possible_cpus
->cpus
[n
].props
.thread_id
= n
;
869 return ms
->possible_cpus
;
872 static CpuInstanceProperties
873 sbsa_ref_cpu_index_to_props(MachineState
*ms
, unsigned cpu_index
)
875 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
876 const CPUArchIdList
*possible_cpus
= mc
->possible_cpu_arch_ids(ms
);
878 assert(cpu_index
< possible_cpus
->len
);
879 return possible_cpus
->cpus
[cpu_index
].props
;
883 sbsa_ref_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
885 return idx
% ms
->numa_state
->num_nodes
;
888 static void sbsa_ref_instance_init(Object
*obj
)
890 SBSAMachineState
*sms
= SBSA_MACHINE(obj
);
892 sbsa_flash_create(sms
);
895 static void sbsa_ref_class_init(ObjectClass
*oc
, void *data
)
897 MachineClass
*mc
= MACHINE_CLASS(oc
);
899 mc
->init
= sbsa_ref_init
;
900 mc
->desc
= "QEMU 'SBSA Reference' ARM Virtual Machine";
901 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("neoverse-n1");
903 mc
->pci_allow_0_address
= true;
904 mc
->minimum_page_bits
= 12;
905 mc
->block_default_type
= IF_IDE
;
907 mc
->default_nic
= "e1000e";
908 mc
->default_ram_size
= 1 * GiB
;
909 mc
->default_ram_id
= "sbsa-ref.ram";
910 mc
->default_cpus
= 4;
911 mc
->possible_cpu_arch_ids
= sbsa_ref_possible_cpu_arch_ids
;
912 mc
->cpu_index_to_instance_props
= sbsa_ref_cpu_index_to_props
;
913 mc
->get_default_cpu_node_id
= sbsa_ref_get_default_cpu_node_id
;
914 /* platform instead of architectural choice */
915 mc
->cpu_cluster_has_numa_boundary
= true;
918 static const TypeInfo sbsa_ref_info
= {
919 .name
= TYPE_SBSA_MACHINE
,
920 .parent
= TYPE_MACHINE
,
921 .instance_init
= sbsa_ref_instance_init
,
922 .class_init
= sbsa_ref_class_init
,
923 .instance_size
= sizeof(SBSAMachineState
),
926 static void sbsa_ref_machine_init(void)
928 type_register_static(&sbsa_ref_info
);
931 type_init(sbsa_ref_machine_init
);