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qapi: Use 'if': { 'any': ... } where appropriate
[qemu/kevin.git] / target / arm / mve_helper.c
blobc2826eb5f9fdb95519d613d34e361886e749f169
1 /*
2 * M-profile MVE Operations
3 *
4 * Copyright (c) 2021 Linaro, Ltd.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "internals.h"
23 #include "vec_internal.h"
24 #include "exec/helper-proto.h"
25 #include "exec/cpu_ldst.h"
26 #include "exec/exec-all.h"
27 #include "tcg/tcg.h"
28
29 static uint16_t mve_eci_mask(CPUARMState *env)
30 {
31 /*
32 * Return the mask of which elements in the MVE vector correspond
33 * to beats being executed. The mask has 1 bits for executed lanes
34 * and 0 bits where ECI says this beat was already executed.
35 */
36 int eci;
37
38 if ((env->condexec_bits & 0xf) != 0) {
39 return 0xffff;
40 }
41
42 eci = env->condexec_bits >> 4;
43 switch (eci) {
44 case ECI_NONE:
45 return 0xffff;
46 case ECI_A0:
47 return 0xfff0;
48 case ECI_A0A1:
49 return 0xff00;
50 case ECI_A0A1A2:
51 case ECI_A0A1A2B0:
52 return 0xf000;
53 default:
54 g_assert_not_reached();
55 }
56 }
57
58 static uint16_t mve_element_mask(CPUARMState *env)
59 {
60 /*
61 * Return the mask of which elements in the MVE vector should be
62 * updated. This is a combination of multiple things:
63 * (1) by default, we update every lane in the vector
64 * (2) VPT predication stores its state in the VPR register;
65 * (3) low-overhead-branch tail predication will mask out part
66 * the vector on the final iteration of the loop
67 * (4) if EPSR.ECI is set then we must execute only some beats
68 * of the insn
69 * We combine all these into a 16-bit result with the same semantics
70 * as VPR.P0: 0 to mask the lane, 1 if it is active.
71 * 8-bit vector ops will look at all bits of the result;
72 * 16-bit ops will look at bits 0, 2, 4, ...;
73 * 32-bit ops will look at bits 0, 4, 8 and 12.
74 * Compare pseudocode GetCurInstrBeat(), though that only returns
75 * the 4-bit slice of the mask corresponding to a single beat.
76 */
77 uint16_t mask = FIELD_EX32(env->v7m.vpr, V7M_VPR, P0);
78
79 if (!(env->v7m.vpr & R_V7M_VPR_MASK01_MASK)) {
80 mask |= 0xff;
81 }
82 if (!(env->v7m.vpr & R_V7M_VPR_MASK23_MASK)) {
83 mask |= 0xff00;
84 }
85
86 if (env->v7m.ltpsize < 4 &&
87 env->regs[14] <= (1 << (4 - env->v7m.ltpsize))) {
88 /*
89 * Tail predication active, and this is the last loop iteration.
90 * The element size is (1 << ltpsize), and we only want to process
91 * loopcount elements, so we want to retain the least significant
92 * (loopcount * esize) predicate bits and zero out bits above that.
93 */
94 int masklen = env->regs[14] << env->v7m.ltpsize;
95 assert(masklen <= 16);
96 uint16_t ltpmask = masklen ? MAKE_64BIT_MASK(0, masklen) : 0;
97 mask &= ltpmask;
98 }
99
100 /*
101 * ECI bits indicate which beats are already executed;
102 * we handle this by effectively predicating them out.
103 */
104 mask &= mve_eci_mask(env);
105 return mask;
106 }
107
108 static void mve_advance_vpt(CPUARMState *env)
109 {
110 /* Advance the VPT and ECI state if necessary */
111 uint32_t vpr = env->v7m.vpr;
112 unsigned mask01, mask23;
113 uint16_t inv_mask;
114 uint16_t eci_mask = mve_eci_mask(env);
115
116 if ((env->condexec_bits & 0xf) == 0) {
117 env->condexec_bits = (env->condexec_bits == (ECI_A0A1A2B0 << 4)) ?
118 (ECI_A0 << 4) : (ECI_NONE << 4);
119 }
120
121 if (!(vpr & (R_V7M_VPR_MASK01_MASK | R_V7M_VPR_MASK23_MASK))) {
122 /* VPT not enabled, nothing to do */
123 return;
124 }
125
126 /* Invert P0 bits if needed, but only for beats we actually executed */
127 mask01 = FIELD_EX32(vpr, V7M_VPR, MASK01);
128 mask23 = FIELD_EX32(vpr, V7M_VPR, MASK23);
129 /* Start by assuming we invert all bits corresponding to executed beats */
130 inv_mask = eci_mask;
131 if (mask01 <= 8) {
132 /* MASK01 says don't invert low half of P0 */
133 inv_mask &= ~0xff;
134 }
135 if (mask23 <= 8) {
136 /* MASK23 says don't invert high half of P0 */
137 inv_mask &= ~0xff00;
138 }
139 vpr ^= inv_mask;
140 /* Only update MASK01 if beat 1 executed */
141 if (eci_mask & 0xf0) {
142 vpr = FIELD_DP32(vpr, V7M_VPR, MASK01, mask01 << 1);
143 }
144 /* Beat 3 always executes, so update MASK23 */
145 vpr = FIELD_DP32(vpr, V7M_VPR, MASK23, mask23 << 1);
146 env->v7m.vpr = vpr;
147 }
148
149 /* For loads, predicated lanes are zeroed instead of keeping their old values */
150 #define DO_VLDR(OP, MSIZE, LDTYPE, ESIZE, TYPE) \
151 void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t addr) \
152 { \
153 TYPE *d = vd; \
154 uint16_t mask = mve_element_mask(env); \
155 uint16_t eci_mask = mve_eci_mask(env); \
156 unsigned b, e; \
157 /* \
158 * R_SXTM allows the dest reg to become UNKNOWN for abandoned \
159 * beats so we don't care if we update part of the dest and \
160 * then take an exception. \
161 */ \
162 for (b = 0, e = 0; b < 16; b += ESIZE, e++) { \
163 if (eci_mask & (1 << b)) { \
164 d[H##ESIZE(e)] = (mask & (1 << b)) ? \
165 cpu_##LDTYPE##_data_ra(env, addr, GETPC()) : 0; \
166 } \
167 addr += MSIZE; \
168 } \
169 mve_advance_vpt(env); \
170 }
171
172 #define DO_VSTR(OP, MSIZE, STTYPE, ESIZE, TYPE) \
173 void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t addr) \
174 { \
175 TYPE *d = vd; \
176 uint16_t mask = mve_element_mask(env); \
177 unsigned b, e; \
178 for (b = 0, e = 0; b < 16; b += ESIZE, e++) { \
179 if (mask & (1 << b)) { \
180 cpu_##STTYPE##_data_ra(env, addr, d[H##ESIZE(e)], GETPC()); \
181 } \
182 addr += MSIZE; \
183 } \
184 mve_advance_vpt(env); \
185 }
186
187 DO_VLDR(vldrb, 1, ldub, 1, uint8_t)
188 DO_VLDR(vldrh, 2, lduw, 2, uint16_t)
189 DO_VLDR(vldrw, 4, ldl, 4, uint32_t)
190
191 DO_VSTR(vstrb, 1, stb, 1, uint8_t)
192 DO_VSTR(vstrh, 2, stw, 2, uint16_t)
193 DO_VSTR(vstrw, 4, stl, 4, uint32_t)
194
195 DO_VLDR(vldrb_sh, 1, ldsb, 2, int16_t)
196 DO_VLDR(vldrb_sw, 1, ldsb, 4, int32_t)
197 DO_VLDR(vldrb_uh, 1, ldub, 2, uint16_t)
198 DO_VLDR(vldrb_uw, 1, ldub, 4, uint32_t)
199 DO_VLDR(vldrh_sw, 2, ldsw, 4, int32_t)
200 DO_VLDR(vldrh_uw, 2, lduw, 4, uint32_t)
201
202 DO_VSTR(vstrb_h, 1, stb, 2, int16_t)
203 DO_VSTR(vstrb_w, 1, stb, 4, int32_t)
204 DO_VSTR(vstrh_w, 2, stw, 4, int32_t)
205
206 #undef DO_VLDR
207 #undef DO_VSTR
208
209 /*
210 * Gather loads/scatter stores. Here each element of Qm specifies
211 * an offset to use from the base register Rm. In the _os_ versions
212 * that offset is scaled by the element size.
213 * For loads, predicated lanes are zeroed instead of retaining
214 * their previous values.
215 */
216 #define DO_VLDR_SG(OP, LDTYPE, ESIZE, TYPE, OFFTYPE, ADDRFN, WB) \
217 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm, \
218 uint32_t base) \
219 { \
220 TYPE *d = vd; \
221 OFFTYPE *m = vm; \
222 uint16_t mask = mve_element_mask(env); \
223 uint16_t eci_mask = mve_eci_mask(env); \
224 unsigned e; \
225 uint32_t addr; \
226 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE, eci_mask >>= ESIZE) { \
227 if (!(eci_mask & 1)) { \
228 continue; \
229 } \
230 addr = ADDRFN(base, m[H##ESIZE(e)]); \
231 d[H##ESIZE(e)] = (mask & 1) ? \
232 cpu_##LDTYPE##_data_ra(env, addr, GETPC()) : 0; \
233 if (WB) { \
234 m[H##ESIZE(e)] = addr; \
235 } \
236 } \
237 mve_advance_vpt(env); \
238 }
239
240 /* We know here TYPE is unsigned so always the same as the offset type */
241 #define DO_VSTR_SG(OP, STTYPE, ESIZE, TYPE, ADDRFN, WB) \
242 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm, \
243 uint32_t base) \
244 { \
245 TYPE *d = vd; \
246 TYPE *m = vm; \
247 uint16_t mask = mve_element_mask(env); \
248 uint16_t eci_mask = mve_eci_mask(env); \
249 unsigned e; \
250 uint32_t addr; \
251 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE, eci_mask >>= ESIZE) { \
252 if (!(eci_mask & 1)) { \
253 continue; \
254 } \
255 addr = ADDRFN(base, m[H##ESIZE(e)]); \
256 if (mask & 1) { \
257 cpu_##STTYPE##_data_ra(env, addr, d[H##ESIZE(e)], GETPC()); \
258 } \
259 if (WB) { \
260 m[H##ESIZE(e)] = addr; \
261 } \
262 } \
263 mve_advance_vpt(env); \
264 }
265
266 /*
267 * 64-bit accesses are slightly different: they are done as two 32-bit
268 * accesses, controlled by the predicate mask for the relevant beat,
269 * and with a single 32-bit offset in the first of the two Qm elements.
270 * Note that for QEMU our IMPDEF AIRCR.ENDIANNESS is always 0 (little).
271 * Address writeback happens on the odd beats and updates the address
272 * stored in the even-beat element.
273 */
274 #define DO_VLDR64_SG(OP, ADDRFN, WB) \
275 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm, \
276 uint32_t base) \
277 { \
278 uint32_t *d = vd; \
279 uint32_t *m = vm; \
280 uint16_t mask = mve_element_mask(env); \
281 uint16_t eci_mask = mve_eci_mask(env); \
282 unsigned e; \
283 uint32_t addr; \
284 for (e = 0; e < 16 / 4; e++, mask >>= 4, eci_mask >>= 4) { \
285 if (!(eci_mask & 1)) { \
286 continue; \
287 } \
288 addr = ADDRFN(base, m[H4(e & ~1)]); \
289 addr += 4 * (e & 1); \
290 d[H4(e)] = (mask & 1) ? cpu_ldl_data_ra(env, addr, GETPC()) : 0; \
291 if (WB && (e & 1)) { \
292 m[H4(e & ~1)] = addr - 4; \
293 } \
294 } \
295 mve_advance_vpt(env); \
296 }
297
298 #define DO_VSTR64_SG(OP, ADDRFN, WB) \
299 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm, \
300 uint32_t base) \
301 { \
302 uint32_t *d = vd; \
303 uint32_t *m = vm; \
304 uint16_t mask = mve_element_mask(env); \
305 uint16_t eci_mask = mve_eci_mask(env); \
306 unsigned e; \
307 uint32_t addr; \
308 for (e = 0; e < 16 / 4; e++, mask >>= 4, eci_mask >>= 4) { \
309 if (!(eci_mask & 1)) { \
310 continue; \
311 } \
312 addr = ADDRFN(base, m[H4(e & ~1)]); \
313 addr += 4 * (e & 1); \
314 if (mask & 1) { \
315 cpu_stl_data_ra(env, addr, d[H4(e)], GETPC()); \
316 } \
317 if (WB && (e & 1)) { \
318 m[H4(e & ~1)] = addr - 4; \
319 } \
320 } \
321 mve_advance_vpt(env); \
322 }
323
324 #define ADDR_ADD(BASE, OFFSET) ((BASE) + (OFFSET))
325 #define ADDR_ADD_OSH(BASE, OFFSET) ((BASE) + ((OFFSET) << 1))
326 #define ADDR_ADD_OSW(BASE, OFFSET) ((BASE) + ((OFFSET) << 2))
327 #define ADDR_ADD_OSD(BASE, OFFSET) ((BASE) + ((OFFSET) << 3))
328
329 DO_VLDR_SG(vldrb_sg_sh, ldsb, 2, int16_t, uint16_t, ADDR_ADD, false)
330 DO_VLDR_SG(vldrb_sg_sw, ldsb, 4, int32_t, uint32_t, ADDR_ADD, false)
331 DO_VLDR_SG(vldrh_sg_sw, ldsw, 4, int32_t, uint32_t, ADDR_ADD, false)
332
333 DO_VLDR_SG(vldrb_sg_ub, ldub, 1, uint8_t, uint8_t, ADDR_ADD, false)
334 DO_VLDR_SG(vldrb_sg_uh, ldub, 2, uint16_t, uint16_t, ADDR_ADD, false)
335 DO_VLDR_SG(vldrb_sg_uw, ldub, 4, uint32_t, uint32_t, ADDR_ADD, false)
336 DO_VLDR_SG(vldrh_sg_uh, lduw, 2, uint16_t, uint16_t, ADDR_ADD, false)
337 DO_VLDR_SG(vldrh_sg_uw, lduw, 4, uint32_t, uint32_t, ADDR_ADD, false)
338 DO_VLDR_SG(vldrw_sg_uw, ldl, 4, uint32_t, uint32_t, ADDR_ADD, false)
339 DO_VLDR64_SG(vldrd_sg_ud, ADDR_ADD, false)
340
341 DO_VLDR_SG(vldrh_sg_os_sw, ldsw, 4, int32_t, uint32_t, ADDR_ADD_OSH, false)
342 DO_VLDR_SG(vldrh_sg_os_uh, lduw, 2, uint16_t, uint16_t, ADDR_ADD_OSH, false)
343 DO_VLDR_SG(vldrh_sg_os_uw, lduw, 4, uint32_t, uint32_t, ADDR_ADD_OSH, false)
344 DO_VLDR_SG(vldrw_sg_os_uw, ldl, 4, uint32_t, uint32_t, ADDR_ADD_OSW, false)
345 DO_VLDR64_SG(vldrd_sg_os_ud, ADDR_ADD_OSD, false)
346
347 DO_VSTR_SG(vstrb_sg_ub, stb, 1, uint8_t, ADDR_ADD, false)
348 DO_VSTR_SG(vstrb_sg_uh, stb, 2, uint16_t, ADDR_ADD, false)
349 DO_VSTR_SG(vstrb_sg_uw, stb, 4, uint32_t, ADDR_ADD, false)
350 DO_VSTR_SG(vstrh_sg_uh, stw, 2, uint16_t, ADDR_ADD, false)
351 DO_VSTR_SG(vstrh_sg_uw, stw, 4, uint32_t, ADDR_ADD, false)
352 DO_VSTR_SG(vstrw_sg_uw, stl, 4, uint32_t, ADDR_ADD, false)
353 DO_VSTR64_SG(vstrd_sg_ud, ADDR_ADD, false)
354
355 DO_VSTR_SG(vstrh_sg_os_uh, stw, 2, uint16_t, ADDR_ADD_OSH, false)
356 DO_VSTR_SG(vstrh_sg_os_uw, stw, 4, uint32_t, ADDR_ADD_OSH, false)
357 DO_VSTR_SG(vstrw_sg_os_uw, stl, 4, uint32_t, ADDR_ADD_OSW, false)
358 DO_VSTR64_SG(vstrd_sg_os_ud, ADDR_ADD_OSD, false)
359
360 DO_VLDR_SG(vldrw_sg_wb_uw, ldl, 4, uint32_t, uint32_t, ADDR_ADD, true)
361 DO_VLDR64_SG(vldrd_sg_wb_ud, ADDR_ADD, true)
362 DO_VSTR_SG(vstrw_sg_wb_uw, stl, 4, uint32_t, ADDR_ADD, true)
363 DO_VSTR64_SG(vstrd_sg_wb_ud, ADDR_ADD, true)
364
365 /*
366 * Deinterleaving loads/interleaving stores.
367 *
368 * For these helpers we are passed the index of the first Qreg
369 * (VLD2/VST2 will also access Qn+1, VLD4/VST4 access Qn .. Qn+3)
370 * and the value of the base address register Rn.
371 * The helpers are specialized for pattern and element size, so
372 * for instance vld42h is VLD4 with pattern 2, element size MO_16.
373 *
374 * These insns are beatwise but not predicated, so we must honour ECI,
375 * but need not look at mve_element_mask().
376 *
377 * The pseudocode implements these insns with multiple memory accesses
378 * of the element size, but rules R_VVVG and R_FXDM permit us to make
379 * one 32-bit memory access per beat.
380 */
381 #define DO_VLD4B(OP, O1, O2, O3, O4) \
382 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \
383 uint32_t base) \
384 { \
385 int beat, e; \
386 uint16_t mask = mve_eci_mask(env); \
387 static const uint8_t off[4] = { O1, O2, O3, O4 }; \
388 uint32_t addr, data; \
389 for (beat = 0; beat < 4; beat++, mask >>= 4) { \
390 if ((mask & 1) == 0) { \
391 /* ECI says skip this beat */ \
392 continue; \
393 } \
394 addr = base + off[beat] * 4; \
395 data = cpu_ldl_le_data_ra(env, addr, GETPC()); \
396 for (e = 0; e < 4; e++, data >>= 8) { \
397 uint8_t *qd = (uint8_t *)aa32_vfp_qreg(env, qnidx + e); \
398 qd[H1(off[beat])] = data; \
399 } \
400 } \
401 }
402
403 #define DO_VLD4H(OP, O1, O2) \
404 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \
405 uint32_t base) \
406 { \
407 int beat; \
408 uint16_t mask = mve_eci_mask(env); \
409 static const uint8_t off[4] = { O1, O1, O2, O2 }; \
410 uint32_t addr, data; \
411 int y; /* y counts 0 2 0 2 */ \
412 uint16_t *qd; \
413 for (beat = 0, y = 0; beat < 4; beat++, mask >>= 4, y ^= 2) { \
414 if ((mask & 1) == 0) { \
415 /* ECI says skip this beat */ \
416 continue; \
417 } \
418 addr = base + off[beat] * 8 + (beat & 1) * 4; \
419 data = cpu_ldl_le_data_ra(env, addr, GETPC()); \
420 qd = (uint16_t *)aa32_vfp_qreg(env, qnidx + y); \
421 qd[H2(off[beat])] = data; \
422 data >>= 16; \
423 qd = (uint16_t *)aa32_vfp_qreg(env, qnidx + y + 1); \
424 qd[H2(off[beat])] = data; \
425 } \
426 }
427
428 #define DO_VLD4W(OP, O1, O2, O3, O4) \
429 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \
430 uint32_t base) \
431 { \
432 int beat; \
433 uint16_t mask = mve_eci_mask(env); \
434 static const uint8_t off[4] = { O1, O2, O3, O4 }; \
435 uint32_t addr, data; \
436 uint32_t *qd; \
437 int y; \
438 for (beat = 0; beat < 4; beat++, mask >>= 4) { \
439 if ((mask & 1) == 0) { \
440 /* ECI says skip this beat */ \
441 continue; \
442 } \
443 addr = base + off[beat] * 4; \
444 data = cpu_ldl_le_data_ra(env, addr, GETPC()); \
445 y = (beat + (O1 & 2)) & 3; \
446 qd = (uint32_t *)aa32_vfp_qreg(env, qnidx + y); \
447 qd[H4(off[beat] >> 2)] = data; \
448 } \
449 }
450
451 DO_VLD4B(vld40b, 0, 1, 10, 11)
452 DO_VLD4B(vld41b, 2, 3, 12, 13)
453 DO_VLD4B(vld42b, 4, 5, 14, 15)
454 DO_VLD4B(vld43b, 6, 7, 8, 9)
455
456 DO_VLD4H(vld40h, 0, 5)
457 DO_VLD4H(vld41h, 1, 6)
458 DO_VLD4H(vld42h, 2, 7)
459 DO_VLD4H(vld43h, 3, 4)
460
461 DO_VLD4W(vld40w, 0, 1, 10, 11)
462 DO_VLD4W(vld41w, 2, 3, 12, 13)
463 DO_VLD4W(vld42w, 4, 5, 14, 15)
464 DO_VLD4W(vld43w, 6, 7, 8, 9)
465
466 #define DO_VLD2B(OP, O1, O2, O3, O4) \
467 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \
468 uint32_t base) \
469 { \
470 int beat, e; \
471 uint16_t mask = mve_eci_mask(env); \
472 static const uint8_t off[4] = { O1, O2, O3, O4 }; \
473 uint32_t addr, data; \
474 uint8_t *qd; \
475 for (beat = 0; beat < 4; beat++, mask >>= 4) { \
476 if ((mask & 1) == 0) { \
477 /* ECI says skip this beat */ \
478 continue; \
479 } \
480 addr = base + off[beat] * 2; \
481 data = cpu_ldl_le_data_ra(env, addr, GETPC()); \
482 for (e = 0; e < 4; e++, data >>= 8) { \
483 qd = (uint8_t *)aa32_vfp_qreg(env, qnidx + (e & 1)); \
484 qd[H1(off[beat] + (e >> 1))] = data; \
485 } \
486 } \
487 }
488
489 #define DO_VLD2H(OP, O1, O2, O3, O4) \
490 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \
491 uint32_t base) \
492 { \
493 int beat; \
494 uint16_t mask = mve_eci_mask(env); \
495 static const uint8_t off[4] = { O1, O2, O3, O4 }; \
496 uint32_t addr, data; \
497 int e; \
498 uint16_t *qd; \
499 for (beat = 0; beat < 4; beat++, mask >>= 4) { \
500 if ((mask & 1) == 0) { \
501 /* ECI says skip this beat */ \
502 continue; \
503 } \
504 addr = base + off[beat] * 4; \
505 data = cpu_ldl_le_data_ra(env, addr, GETPC()); \
506 for (e = 0; e < 2; e++, data >>= 16) { \
507 qd = (uint16_t *)aa32_vfp_qreg(env, qnidx + e); \
508 qd[H2(off[beat])] = data; \
509 } \
510 } \
511 }
512
513 #define DO_VLD2W(OP, O1, O2, O3, O4) \
514 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \
515 uint32_t base) \
516 { \
517 int beat; \
518 uint16_t mask = mve_eci_mask(env); \
519 static const uint8_t off[4] = { O1, O2, O3, O4 }; \
520 uint32_t addr, data; \
521 uint32_t *qd; \
522 for (beat = 0; beat < 4; beat++, mask >>= 4) { \
523 if ((mask & 1) == 0) { \
524 /* ECI says skip this beat */ \
525 continue; \
526 } \
527 addr = base + off[beat]; \
528 data = cpu_ldl_le_data_ra(env, addr, GETPC()); \
529 qd = (uint32_t *)aa32_vfp_qreg(env, qnidx + (beat & 1)); \
530 qd[H4(off[beat] >> 3)] = data; \
531 } \
532 }
533
534 DO_VLD2B(vld20b, 0, 2, 12, 14)
535 DO_VLD2B(vld21b, 4, 6, 8, 10)
536
537 DO_VLD2H(vld20h, 0, 1, 6, 7)
538 DO_VLD2H(vld21h, 2, 3, 4, 5)
539
540 DO_VLD2W(vld20w, 0, 4, 24, 28)
541 DO_VLD2W(vld21w, 8, 12, 16, 20)
542
543 #define DO_VST4B(OP, O1, O2, O3, O4) \
544 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \
545 uint32_t base) \
546 { \
547 int beat, e; \
548 uint16_t mask = mve_eci_mask(env); \
549 static const uint8_t off[4] = { O1, O2, O3, O4 }; \
550 uint32_t addr, data; \
551 for (beat = 0; beat < 4; beat++, mask >>= 4) { \
552 if ((mask & 1) == 0) { \
553 /* ECI says skip this beat */ \
554 continue; \
555 } \
556 addr = base + off[beat] * 4; \
557 data = 0; \
558 for (e = 3; e >= 0; e--) { \
559 uint8_t *qd = (uint8_t *)aa32_vfp_qreg(env, qnidx + e); \
560 data = (data << 8) | qd[H1(off[beat])]; \
561 } \
562 cpu_stl_le_data_ra(env, addr, data, GETPC()); \
563 } \
564 }
565
566 #define DO_VST4H(OP, O1, O2) \
567 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \
568 uint32_t base) \
569 { \
570 int beat; \
571 uint16_t mask = mve_eci_mask(env); \
572 static const uint8_t off[4] = { O1, O1, O2, O2 }; \
573 uint32_t addr, data; \
574 int y; /* y counts 0 2 0 2 */ \
575 uint16_t *qd; \
576 for (beat = 0, y = 0; beat < 4; beat++, mask >>= 4, y ^= 2) { \
577 if ((mask & 1) == 0) { \
578 /* ECI says skip this beat */ \
579 continue; \
580 } \
581 addr = base + off[beat] * 8 + (beat & 1) * 4; \
582 qd = (uint16_t *)aa32_vfp_qreg(env, qnidx + y); \
583 data = qd[H2(off[beat])]; \
584 qd = (uint16_t *)aa32_vfp_qreg(env, qnidx + y + 1); \
585 data |= qd[H2(off[beat])] << 16; \
586 cpu_stl_le_data_ra(env, addr, data, GETPC()); \
587 } \
588 }
589
590 #define DO_VST4W(OP, O1, O2, O3, O4) \
591 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \
592 uint32_t base) \
593 { \
594 int beat; \
595 uint16_t mask = mve_eci_mask(env); \
596 static const uint8_t off[4] = { O1, O2, O3, O4 }; \
597 uint32_t addr, data; \
598 uint32_t *qd; \
599 int y; \
600 for (beat = 0; beat < 4; beat++, mask >>= 4) { \
601 if ((mask & 1) == 0) { \
602 /* ECI says skip this beat */ \
603 continue; \
604 } \
605 addr = base + off[beat] * 4; \
606 y = (beat + (O1 & 2)) & 3; \
607 qd = (uint32_t *)aa32_vfp_qreg(env, qnidx + y); \
608 data = qd[H4(off[beat] >> 2)]; \
609 cpu_stl_le_data_ra(env, addr, data, GETPC()); \
610 } \
611 }
612
613 DO_VST4B(vst40b, 0, 1, 10, 11)
614 DO_VST4B(vst41b, 2, 3, 12, 13)
615 DO_VST4B(vst42b, 4, 5, 14, 15)
616 DO_VST4B(vst43b, 6, 7, 8, 9)
617
618 DO_VST4H(vst40h, 0, 5)
619 DO_VST4H(vst41h, 1, 6)
620 DO_VST4H(vst42h, 2, 7)
621 DO_VST4H(vst43h, 3, 4)
622
623 DO_VST4W(vst40w, 0, 1, 10, 11)
624 DO_VST4W(vst41w, 2, 3, 12, 13)
625 DO_VST4W(vst42w, 4, 5, 14, 15)
626 DO_VST4W(vst43w, 6, 7, 8, 9)
627
628 #define DO_VST2B(OP, O1, O2, O3, O4) \
629 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \
630 uint32_t base) \
631 { \
632 int beat, e; \
633 uint16_t mask = mve_eci_mask(env); \
634 static const uint8_t off[4] = { O1, O2, O3, O4 }; \
635 uint32_t addr, data; \
636 uint8_t *qd; \
637 for (beat = 0; beat < 4; beat++, mask >>= 4) { \
638 if ((mask & 1) == 0) { \
639 /* ECI says skip this beat */ \
640 continue; \
641 } \
642 addr = base + off[beat] * 2; \
643 data = 0; \
644 for (e = 3; e >= 0; e--) { \
645 qd = (uint8_t *)aa32_vfp_qreg(env, qnidx + (e & 1)); \
646 data = (data << 8) | qd[H1(off[beat] + (e >> 1))]; \
647 } \
648 cpu_stl_le_data_ra(env, addr, data, GETPC()); \
649 } \
650 }
651
652 #define DO_VST2H(OP, O1, O2, O3, O4) \
653 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \
654 uint32_t base) \
655 { \
656 int beat; \
657 uint16_t mask = mve_eci_mask(env); \
658 static const uint8_t off[4] = { O1, O2, O3, O4 }; \
659 uint32_t addr, data; \
660 int e; \
661 uint16_t *qd; \
662 for (beat = 0; beat < 4; beat++, mask >>= 4) { \
663 if ((mask & 1) == 0) { \
664 /* ECI says skip this beat */ \
665 continue; \
666 } \
667 addr = base + off[beat] * 4; \
668 data = 0; \
669 for (e = 1; e >= 0; e--) { \
670 qd = (uint16_t *)aa32_vfp_qreg(env, qnidx + e); \
671 data = (data << 16) | qd[H2(off[beat])]; \
672 } \
673 cpu_stl_le_data_ra(env, addr, data, GETPC()); \
674 } \
675 }
676
677 #define DO_VST2W(OP, O1, O2, O3, O4) \
678 void HELPER(mve_##OP)(CPUARMState *env, uint32_t qnidx, \
679 uint32_t base) \
680 { \
681 int beat; \
682 uint16_t mask = mve_eci_mask(env); \
683 static const uint8_t off[4] = { O1, O2, O3, O4 }; \
684 uint32_t addr, data; \
685 uint32_t *qd; \
686 for (beat = 0; beat < 4; beat++, mask >>= 4) { \
687 if ((mask & 1) == 0) { \
688 /* ECI says skip this beat */ \
689 continue; \
690 } \
691 addr = base + off[beat]; \
692 qd = (uint32_t *)aa32_vfp_qreg(env, qnidx + (beat & 1)); \
693 data = qd[H4(off[beat] >> 3)]; \
694 cpu_stl_le_data_ra(env, addr, data, GETPC()); \
695 } \
696 }
697
698 DO_VST2B(vst20b, 0, 2, 12, 14)
699 DO_VST2B(vst21b, 4, 6, 8, 10)
700
701 DO_VST2H(vst20h, 0, 1, 6, 7)
702 DO_VST2H(vst21h, 2, 3, 4, 5)
703
704 DO_VST2W(vst20w, 0, 4, 24, 28)
705 DO_VST2W(vst21w, 8, 12, 16, 20)
706
707 /*
708 * The mergemask(D, R, M) macro performs the operation "*D = R" but
709 * storing only the bytes which correspond to 1 bits in M,
710 * leaving other bytes in *D unchanged. We use _Generic
711 * to select the correct implementation based on the type of D.
712 */
713
714 static void mergemask_ub(uint8_t *d, uint8_t r, uint16_t mask)
715 {
716 if (mask & 1) {
717 *d = r;
718 }
719 }
720
721 static void mergemask_sb(int8_t *d, int8_t r, uint16_t mask)
722 {
723 mergemask_ub((uint8_t *)d, r, mask);
724 }
725
726 static void mergemask_uh(uint16_t *d, uint16_t r, uint16_t mask)
727 {
728 uint16_t bmask = expand_pred_b_data[mask & 3];
729 *d = (*d & ~bmask) | (r & bmask);
730 }
731
732 static void mergemask_sh(int16_t *d, int16_t r, uint16_t mask)
733 {
734 mergemask_uh((uint16_t *)d, r, mask);
735 }
736
737 static void mergemask_uw(uint32_t *d, uint32_t r, uint16_t mask)
738 {
739 uint32_t bmask = expand_pred_b_data[mask & 0xf];
740 *d = (*d & ~bmask) | (r & bmask);
741 }
742
743 static void mergemask_sw(int32_t *d, int32_t r, uint16_t mask)
744 {
745 mergemask_uw((uint32_t *)d, r, mask);
746 }
747
748 static void mergemask_uq(uint64_t *d, uint64_t r, uint16_t mask)
749 {
750 uint64_t bmask = expand_pred_b_data[mask & 0xff];
751 *d = (*d & ~bmask) | (r & bmask);
752 }
753
754 static void mergemask_sq(int64_t *d, int64_t r, uint16_t mask)
755 {
756 mergemask_uq((uint64_t *)d, r, mask);
757 }
758
759 #define mergemask(D, R, M) \
760 _Generic(D, \
761 uint8_t *: mergemask_ub, \
762 int8_t *: mergemask_sb, \
763 uint16_t *: mergemask_uh, \
764 int16_t *: mergemask_sh, \
765 uint32_t *: mergemask_uw, \
766 int32_t *: mergemask_sw, \
767 uint64_t *: mergemask_uq, \
768 int64_t *: mergemask_sq)(D, R, M)
769
770 void HELPER(mve_vdup)(CPUARMState *env, void *vd, uint32_t val)
771 {
772 /*
773 * The generated code already replicated an 8 or 16 bit constant
774 * into the 32-bit value, so we only need to write the 32-bit
775 * value to all elements of the Qreg, allowing for predication.
776 */
777 uint32_t *d = vd;
778 uint16_t mask = mve_element_mask(env);
779 unsigned e;
780 for (e = 0; e < 16 / 4; e++, mask >>= 4) {
781 mergemask(&d[H4(e)], val, mask);
782 }
783 mve_advance_vpt(env);
784 }
785
786 #define DO_1OP(OP, ESIZE, TYPE, FN) \
787 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \
788 { \
789 TYPE *d = vd, *m = vm; \
790 uint16_t mask = mve_element_mask(env); \
791 unsigned e; \
792 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
793 mergemask(&d[H##ESIZE(e)], FN(m[H##ESIZE(e)]), mask); \
794 } \
795 mve_advance_vpt(env); \
796 }
797
798 #define DO_CLS_B(N) (clrsb32(N) - 24)
799 #define DO_CLS_H(N) (clrsb32(N) - 16)
800
801 DO_1OP(vclsb, 1, int8_t, DO_CLS_B)
802 DO_1OP(vclsh, 2, int16_t, DO_CLS_H)
803 DO_1OP(vclsw, 4, int32_t, clrsb32)
804
805 #define DO_CLZ_B(N) (clz32(N) - 24)
806 #define DO_CLZ_H(N) (clz32(N) - 16)
807
808 DO_1OP(vclzb, 1, uint8_t, DO_CLZ_B)
809 DO_1OP(vclzh, 2, uint16_t, DO_CLZ_H)
810 DO_1OP(vclzw, 4, uint32_t, clz32)
811
812 DO_1OP(vrev16b, 2, uint16_t, bswap16)
813 DO_1OP(vrev32b, 4, uint32_t, bswap32)
814 DO_1OP(vrev32h, 4, uint32_t, hswap32)
815 DO_1OP(vrev64b, 8, uint64_t, bswap64)
816 DO_1OP(vrev64h, 8, uint64_t, hswap64)
817 DO_1OP(vrev64w, 8, uint64_t, wswap64)
818
819 #define DO_NOT(N) (~(N))
820
821 DO_1OP(vmvn, 8, uint64_t, DO_NOT)
822
823 #define DO_ABS(N) ((N) < 0 ? -(N) : (N))
824 #define DO_FABSH(N) ((N) & dup_const(MO_16, 0x7fff))
825 #define DO_FABSS(N) ((N) & dup_const(MO_32, 0x7fffffff))
826
827 DO_1OP(vabsb, 1, int8_t, DO_ABS)
828 DO_1OP(vabsh, 2, int16_t, DO_ABS)
829 DO_1OP(vabsw, 4, int32_t, DO_ABS)
830
831 /* We can do these 64 bits at a time */
832 DO_1OP(vfabsh, 8, uint64_t, DO_FABSH)
833 DO_1OP(vfabss, 8, uint64_t, DO_FABSS)
834
835 #define DO_NEG(N) (-(N))
836 #define DO_FNEGH(N) ((N) ^ dup_const(MO_16, 0x8000))
837 #define DO_FNEGS(N) ((N) ^ dup_const(MO_32, 0x80000000))
838
839 DO_1OP(vnegb, 1, int8_t, DO_NEG)
840 DO_1OP(vnegh, 2, int16_t, DO_NEG)
841 DO_1OP(vnegw, 4, int32_t, DO_NEG)
842
843 /* We can do these 64 bits at a time */
844 DO_1OP(vfnegh, 8, uint64_t, DO_FNEGH)
845 DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS)
846
847 /*
848 * 1 operand immediates: Vda is destination and possibly also one source.
849 * All these insns work at 64-bit widths.
850 */
851 #define DO_1OP_IMM(OP, FN) \
852 void HELPER(mve_##OP)(CPUARMState *env, void *vda, uint64_t imm) \
853 { \
854 uint64_t *da = vda; \
855 uint16_t mask = mve_element_mask(env); \
856 unsigned e; \
857 for (e = 0; e < 16 / 8; e++, mask >>= 8) { \
858 mergemask(&da[H8(e)], FN(da[H8(e)], imm), mask); \
859 } \
860 mve_advance_vpt(env); \
861 }
862
863 #define DO_MOVI(N, I) (I)
864 #define DO_ANDI(N, I) ((N) & (I))
865 #define DO_ORRI(N, I) ((N) | (I))
866
867 DO_1OP_IMM(vmovi, DO_MOVI)
868 DO_1OP_IMM(vandi, DO_ANDI)
869 DO_1OP_IMM(vorri, DO_ORRI)
870
871 #define DO_2OP(OP, ESIZE, TYPE, FN) \
872 void HELPER(glue(mve_, OP))(CPUARMState *env, \
873 void *vd, void *vn, void *vm) \
874 { \
875 TYPE *d = vd, *n = vn, *m = vm; \
876 uint16_t mask = mve_element_mask(env); \
877 unsigned e; \
878 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
879 mergemask(&d[H##ESIZE(e)], \
880 FN(n[H##ESIZE(e)], m[H##ESIZE(e)]), mask); \
881 } \
882 mve_advance_vpt(env); \
883 }
884
885 /* provide unsigned 2-op helpers for all sizes */
886 #define DO_2OP_U(OP, FN) \
887 DO_2OP(OP##b, 1, uint8_t, FN) \
888 DO_2OP(OP##h, 2, uint16_t, FN) \
889 DO_2OP(OP##w, 4, uint32_t, FN)
890
891 /* provide signed 2-op helpers for all sizes */
892 #define DO_2OP_S(OP, FN) \
893 DO_2OP(OP##b, 1, int8_t, FN) \
894 DO_2OP(OP##h, 2, int16_t, FN) \
895 DO_2OP(OP##w, 4, int32_t, FN)
896
897 /*
898 * "Long" operations where two half-sized inputs (taken from either the
899 * top or the bottom of the input vector) produce a double-width result.
900 * Here ESIZE, TYPE are for the input, and LESIZE, LTYPE for the output.
901 */
902 #define DO_2OP_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \
903 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \
904 { \
905 LTYPE *d = vd; \
906 TYPE *n = vn, *m = vm; \
907 uint16_t mask = mve_element_mask(env); \
908 unsigned le; \
909 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
910 LTYPE r = FN((LTYPE)n[H##ESIZE(le * 2 + TOP)], \
911 m[H##ESIZE(le * 2 + TOP)]); \
912 mergemask(&d[H##LESIZE(le)], r, mask); \
913 } \
914 mve_advance_vpt(env); \
915 }
916
917 #define DO_2OP_SAT(OP, ESIZE, TYPE, FN) \
918 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \
919 { \
920 TYPE *d = vd, *n = vn, *m = vm; \
921 uint16_t mask = mve_element_mask(env); \
922 unsigned e; \
923 bool qc = false; \
924 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
925 bool sat = false; \
926 TYPE r = FN(n[H##ESIZE(e)], m[H##ESIZE(e)], &sat); \
927 mergemask(&d[H##ESIZE(e)], r, mask); \
928 qc |= sat & mask & 1; \
929 } \
930 if (qc) { \
931 env->vfp.qc[0] = qc; \
932 } \
933 mve_advance_vpt(env); \
934 }
935
936 /* provide unsigned 2-op helpers for all sizes */
937 #define DO_2OP_SAT_U(OP, FN) \
938 DO_2OP_SAT(OP##b, 1, uint8_t, FN) \
939 DO_2OP_SAT(OP##h, 2, uint16_t, FN) \
940 DO_2OP_SAT(OP##w, 4, uint32_t, FN)
941
942 /* provide signed 2-op helpers for all sizes */
943 #define DO_2OP_SAT_S(OP, FN) \
944 DO_2OP_SAT(OP##b, 1, int8_t, FN) \
945 DO_2OP_SAT(OP##h, 2, int16_t, FN) \
946 DO_2OP_SAT(OP##w, 4, int32_t, FN)
947
948 #define DO_AND(N, M) ((N) & (M))
949 #define DO_BIC(N, M) ((N) & ~(M))
950 #define DO_ORR(N, M) ((N) | (M))
951 #define DO_ORN(N, M) ((N) | ~(M))
952 #define DO_EOR(N, M) ((N) ^ (M))
953
954 DO_2OP(vand, 8, uint64_t, DO_AND)
955 DO_2OP(vbic, 8, uint64_t, DO_BIC)
956 DO_2OP(vorr, 8, uint64_t, DO_ORR)
957 DO_2OP(vorn, 8, uint64_t, DO_ORN)
958 DO_2OP(veor, 8, uint64_t, DO_EOR)
959
960 #define DO_ADD(N, M) ((N) + (M))
961 #define DO_SUB(N, M) ((N) - (M))
962 #define DO_MUL(N, M) ((N) * (M))
963
964 DO_2OP_U(vadd, DO_ADD)
965 DO_2OP_U(vsub, DO_SUB)
966 DO_2OP_U(vmul, DO_MUL)
967
968 DO_2OP_L(vmullbsb, 0, 1, int8_t, 2, int16_t, DO_MUL)
969 DO_2OP_L(vmullbsh, 0, 2, int16_t, 4, int32_t, DO_MUL)
970 DO_2OP_L(vmullbsw, 0, 4, int32_t, 8, int64_t, DO_MUL)
971 DO_2OP_L(vmullbub, 0, 1, uint8_t, 2, uint16_t, DO_MUL)
972 DO_2OP_L(vmullbuh, 0, 2, uint16_t, 4, uint32_t, DO_MUL)
973 DO_2OP_L(vmullbuw, 0, 4, uint32_t, 8, uint64_t, DO_MUL)
974
975 DO_2OP_L(vmulltsb, 1, 1, int8_t, 2, int16_t, DO_MUL)
976 DO_2OP_L(vmulltsh, 1, 2, int16_t, 4, int32_t, DO_MUL)
977 DO_2OP_L(vmulltsw, 1, 4, int32_t, 8, int64_t, DO_MUL)
978 DO_2OP_L(vmulltub, 1, 1, uint8_t, 2, uint16_t, DO_MUL)
979 DO_2OP_L(vmulltuh, 1, 2, uint16_t, 4, uint32_t, DO_MUL)
980 DO_2OP_L(vmulltuw, 1, 4, uint32_t, 8, uint64_t, DO_MUL)
981
982 /*
983 * Polynomial multiply. We can always do this generating 64 bits
984 * of the result at a time, so we don't need to use DO_2OP_L.
985 */
986 #define VMULLPH_MASK 0x00ff00ff00ff00ffULL
987 #define VMULLPW_MASK 0x0000ffff0000ffffULL
988 #define DO_VMULLPBH(N, M) pmull_h((N) & VMULLPH_MASK, (M) & VMULLPH_MASK)
989 #define DO_VMULLPTH(N, M) DO_VMULLPBH((N) >> 8, (M) >> 8)
990 #define DO_VMULLPBW(N, M) pmull_w((N) & VMULLPW_MASK, (M) & VMULLPW_MASK)
991 #define DO_VMULLPTW(N, M) DO_VMULLPBW((N) >> 16, (M) >> 16)
992
993 DO_2OP(vmullpbh, 8, uint64_t, DO_VMULLPBH)
994 DO_2OP(vmullpth, 8, uint64_t, DO_VMULLPTH)
995 DO_2OP(vmullpbw, 8, uint64_t, DO_VMULLPBW)
996 DO_2OP(vmullptw, 8, uint64_t, DO_VMULLPTW)
997
998 /*
999 * Because the computation type is at least twice as large as required,
1000 * these work for both signed and unsigned source types.
1001 */
1002 static inline uint8_t do_mulh_b(int32_t n, int32_t m)
1003 {
1004 return (n * m) >> 8;
1005 }
1006
1007 static inline uint16_t do_mulh_h(int32_t n, int32_t m)
1008 {
1009 return (n * m) >> 16;
1010 }
1011
1012 static inline uint32_t do_mulh_w(int64_t n, int64_t m)
1013 {
1014 return (n * m) >> 32;
1015 }
1016
1017 static inline uint8_t do_rmulh_b(int32_t n, int32_t m)
1018 {
1019 return (n * m + (1U << 7)) >> 8;
1020 }
1021
1022 static inline uint16_t do_rmulh_h(int32_t n, int32_t m)
1023 {
1024 return (n * m + (1U << 15)) >> 16;
1025 }
1026
1027 static inline uint32_t do_rmulh_w(int64_t n, int64_t m)
1028 {
1029 return (n * m + (1U << 31)) >> 32;
1030 }
1031
1032 DO_2OP(vmulhsb, 1, int8_t, do_mulh_b)
1033 DO_2OP(vmulhsh, 2, int16_t, do_mulh_h)
1034 DO_2OP(vmulhsw, 4, int32_t, do_mulh_w)
1035 DO_2OP(vmulhub, 1, uint8_t, do_mulh_b)
1036 DO_2OP(vmulhuh, 2, uint16_t, do_mulh_h)
1037 DO_2OP(vmulhuw, 4, uint32_t, do_mulh_w)
1038
1039 DO_2OP(vrmulhsb, 1, int8_t, do_rmulh_b)
1040 DO_2OP(vrmulhsh, 2, int16_t, do_rmulh_h)
1041 DO_2OP(vrmulhsw, 4, int32_t, do_rmulh_w)
1042 DO_2OP(vrmulhub, 1, uint8_t, do_rmulh_b)
1043 DO_2OP(vrmulhuh, 2, uint16_t, do_rmulh_h)
1044 DO_2OP(vrmulhuw, 4, uint32_t, do_rmulh_w)
1045
1046 #define DO_MAX(N, M) ((N) >= (M) ? (N) : (M))
1047 #define DO_MIN(N, M) ((N) >= (M) ? (M) : (N))
1048
1049 DO_2OP_S(vmaxs, DO_MAX)
1050 DO_2OP_U(vmaxu, DO_MAX)
1051 DO_2OP_S(vmins, DO_MIN)
1052 DO_2OP_U(vminu, DO_MIN)
1053
1054 #define DO_ABD(N, M) ((N) >= (M) ? (N) - (M) : (M) - (N))
1055
1056 DO_2OP_S(vabds, DO_ABD)
1057 DO_2OP_U(vabdu, DO_ABD)
1058
1059 static inline uint32_t do_vhadd_u(uint32_t n, uint32_t m)
1060 {
1061 return ((uint64_t)n + m) >> 1;
1062 }
1063
1064 static inline int32_t do_vhadd_s(int32_t n, int32_t m)
1065 {
1066 return ((int64_t)n + m) >> 1;
1067 }
1068
1069 static inline uint32_t do_vhsub_u(uint32_t n, uint32_t m)
1070 {
1071 return ((uint64_t)n - m) >> 1;
1072 }
1073
1074 static inline int32_t do_vhsub_s(int32_t n, int32_t m)
1075 {
1076 return ((int64_t)n - m) >> 1;
1077 }
1078
1079 DO_2OP_S(vhadds, do_vhadd_s)
1080 DO_2OP_U(vhaddu, do_vhadd_u)
1081 DO_2OP_S(vhsubs, do_vhsub_s)
1082 DO_2OP_U(vhsubu, do_vhsub_u)
1083
1084 #define DO_VSHLS(N, M) do_sqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, false, NULL)
1085 #define DO_VSHLU(N, M) do_uqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, false, NULL)
1086 #define DO_VRSHLS(N, M) do_sqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, true, NULL)
1087 #define DO_VRSHLU(N, M) do_uqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, true, NULL)
1088
1089 DO_2OP_S(vshls, DO_VSHLS)
1090 DO_2OP_U(vshlu, DO_VSHLU)
1091 DO_2OP_S(vrshls, DO_VRSHLS)
1092 DO_2OP_U(vrshlu, DO_VRSHLU)
1093
1094 #define DO_RHADD_S(N, M) (((int64_t)(N) + (M) + 1) >> 1)
1095 #define DO_RHADD_U(N, M) (((uint64_t)(N) + (M) + 1) >> 1)
1096
1097 DO_2OP_S(vrhadds, DO_RHADD_S)
1098 DO_2OP_U(vrhaddu, DO_RHADD_U)
1099
1100 static void do_vadc(CPUARMState *env, uint32_t *d, uint32_t *n, uint32_t *m,
1101 uint32_t inv, uint32_t carry_in, bool update_flags)
1102 {
1103 uint16_t mask = mve_element_mask(env);
1104 unsigned e;
1105
1106 /* If any additions trigger, we will update flags. */
1107 if (mask & 0x1111) {
1108 update_flags = true;
1109 }
1110
1111 for (e = 0; e < 16 / 4; e++, mask >>= 4) {
1112 uint64_t r = carry_in;
1113 r += n[H4(e)];
1114 r += m[H4(e)] ^ inv;
1115 if (mask & 1) {
1116 carry_in = r >> 32;
1117 }
1118 mergemask(&d[H4(e)], r, mask);
1119 }
1120
1121 if (update_flags) {
1122 /* Store C, clear NZV. */
1123 env->vfp.xregs[ARM_VFP_FPSCR] &= ~FPCR_NZCV_MASK;
1124 env->vfp.xregs[ARM_VFP_FPSCR] |= carry_in * FPCR_C;
1125 }
1126 mve_advance_vpt(env);
1127 }
1128
1129 void HELPER(mve_vadc)(CPUARMState *env, void *vd, void *vn, void *vm)
1130 {
1131 bool carry_in = env->vfp.xregs[ARM_VFP_FPSCR] & FPCR_C;
1132 do_vadc(env, vd, vn, vm, 0, carry_in, false);
1133 }
1134
1135 void HELPER(mve_vsbc)(CPUARMState *env, void *vd, void *vn, void *vm)
1136 {
1137 bool carry_in = env->vfp.xregs[ARM_VFP_FPSCR] & FPCR_C;
1138 do_vadc(env, vd, vn, vm, -1, carry_in, false);
1139 }
1140
1141
1142 void HELPER(mve_vadci)(CPUARMState *env, void *vd, void *vn, void *vm)
1143 {
1144 do_vadc(env, vd, vn, vm, 0, 0, true);
1145 }
1146
1147 void HELPER(mve_vsbci)(CPUARMState *env, void *vd, void *vn, void *vm)
1148 {
1149 do_vadc(env, vd, vn, vm, -1, 1, true);
1150 }
1151
1152 #define DO_VCADD(OP, ESIZE, TYPE, FN0, FN1) \
1153 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \
1154 { \
1155 TYPE *d = vd, *n = vn, *m = vm; \
1156 uint16_t mask = mve_element_mask(env); \
1157 unsigned e; \
1158 TYPE r[16 / ESIZE]; \
1159 /* Calculate all results first to avoid overwriting inputs */ \
1160 for (e = 0; e < 16 / ESIZE; e++) { \
1161 if (!(e & 1)) { \
1162 r[e] = FN0(n[H##ESIZE(e)], m[H##ESIZE(e + 1)]); \
1163 } else { \
1164 r[e] = FN1(n[H##ESIZE(e)], m[H##ESIZE(e - 1)]); \
1165 } \
1166 } \
1167 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
1168 mergemask(&d[H##ESIZE(e)], r[e], mask); \
1169 } \
1170 mve_advance_vpt(env); \
1171 }
1172
1173 #define DO_VCADD_ALL(OP, FN0, FN1) \
1174 DO_VCADD(OP##b, 1, int8_t, FN0, FN1) \
1175 DO_VCADD(OP##h, 2, int16_t, FN0, FN1) \
1176 DO_VCADD(OP##w, 4, int32_t, FN0, FN1)
1177
1178 DO_VCADD_ALL(vcadd90, DO_SUB, DO_ADD)
1179 DO_VCADD_ALL(vcadd270, DO_ADD, DO_SUB)
1180 DO_VCADD_ALL(vhcadd90, do_vhsub_s, do_vhadd_s)
1181 DO_VCADD_ALL(vhcadd270, do_vhadd_s, do_vhsub_s)
1182
1183 static inline int32_t do_sat_bhw(int64_t val, int64_t min, int64_t max, bool *s)
1184 {
1185 if (val > max) {
1186 *s = true;
1187 return max;
1188 } else if (val < min) {
1189 *s = true;
1190 return min;
1191 }
1192 return val;
1193 }
1194
1195 #define DO_SQADD_B(n, m, s) do_sat_bhw((int64_t)n + m, INT8_MIN, INT8_MAX, s)
1196 #define DO_SQADD_H(n, m, s) do_sat_bhw((int64_t)n + m, INT16_MIN, INT16_MAX, s)
1197 #define DO_SQADD_W(n, m, s) do_sat_bhw((int64_t)n + m, INT32_MIN, INT32_MAX, s)
1198
1199 #define DO_UQADD_B(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT8_MAX, s)
1200 #define DO_UQADD_H(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT16_MAX, s)
1201 #define DO_UQADD_W(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT32_MAX, s)
1202
1203 #define DO_SQSUB_B(n, m, s) do_sat_bhw((int64_t)n - m, INT8_MIN, INT8_MAX, s)
1204 #define DO_SQSUB_H(n, m, s) do_sat_bhw((int64_t)n - m, INT16_MIN, INT16_MAX, s)
1205 #define DO_SQSUB_W(n, m, s) do_sat_bhw((int64_t)n - m, INT32_MIN, INT32_MAX, s)
1206
1207 #define DO_UQSUB_B(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT8_MAX, s)
1208 #define DO_UQSUB_H(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT16_MAX, s)
1209 #define DO_UQSUB_W(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT32_MAX, s)
1210
1211 /*
1212 * For QDMULH and QRDMULH we simplify "double and shift by esize" into
1213 * "shift by esize-1", adjusting the QRDMULH rounding constant to match.
1214 */
1215 #define DO_QDMULH_B(n, m, s) do_sat_bhw(((int64_t)n * m) >> 7, \
1216 INT8_MIN, INT8_MAX, s)
1217 #define DO_QDMULH_H(n, m, s) do_sat_bhw(((int64_t)n * m) >> 15, \
1218 INT16_MIN, INT16_MAX, s)
1219 #define DO_QDMULH_W(n, m, s) do_sat_bhw(((int64_t)n * m) >> 31, \
1220 INT32_MIN, INT32_MAX, s)
1221
1222 #define DO_QRDMULH_B(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 6)) >> 7, \
1223 INT8_MIN, INT8_MAX, s)
1224 #define DO_QRDMULH_H(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 14)) >> 15, \
1225 INT16_MIN, INT16_MAX, s)
1226 #define DO_QRDMULH_W(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 30)) >> 31, \
1227 INT32_MIN, INT32_MAX, s)
1228
1229 DO_2OP_SAT(vqdmulhb, 1, int8_t, DO_QDMULH_B)
1230 DO_2OP_SAT(vqdmulhh, 2, int16_t, DO_QDMULH_H)
1231 DO_2OP_SAT(vqdmulhw, 4, int32_t, DO_QDMULH_W)
1232
1233 DO_2OP_SAT(vqrdmulhb, 1, int8_t, DO_QRDMULH_B)
1234 DO_2OP_SAT(vqrdmulhh, 2, int16_t, DO_QRDMULH_H)
1235 DO_2OP_SAT(vqrdmulhw, 4, int32_t, DO_QRDMULH_W)
1236
1237 DO_2OP_SAT(vqaddub, 1, uint8_t, DO_UQADD_B)
1238 DO_2OP_SAT(vqadduh, 2, uint16_t, DO_UQADD_H)
1239 DO_2OP_SAT(vqadduw, 4, uint32_t, DO_UQADD_W)
1240 DO_2OP_SAT(vqaddsb, 1, int8_t, DO_SQADD_B)
1241 DO_2OP_SAT(vqaddsh, 2, int16_t, DO_SQADD_H)
1242 DO_2OP_SAT(vqaddsw, 4, int32_t, DO_SQADD_W)
1243
1244 DO_2OP_SAT(vqsubub, 1, uint8_t, DO_UQSUB_B)
1245 DO_2OP_SAT(vqsubuh, 2, uint16_t, DO_UQSUB_H)
1246 DO_2OP_SAT(vqsubuw, 4, uint32_t, DO_UQSUB_W)
1247 DO_2OP_SAT(vqsubsb, 1, int8_t, DO_SQSUB_B)
1248 DO_2OP_SAT(vqsubsh, 2, int16_t, DO_SQSUB_H)
1249 DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W)
1250
1251 /*
1252 * This wrapper fixes up the impedance mismatch between do_sqrshl_bhs()
1253 * and friends wanting a uint32_t* sat and our needing a bool*.
1254 */
1255 #define WRAP_QRSHL_HELPER(FN, N, M, ROUND, satp) \
1256 ({ \
1257 uint32_t su32 = 0; \
1258 typeof(N) r = FN(N, (int8_t)(M), sizeof(N) * 8, ROUND, &su32); \
1259 if (su32) { \
1260 *satp = true; \
1261 } \
1262 r; \
1263 })
1264
1265 #define DO_SQSHL_OP(N, M, satp) \
1266 WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, false, satp)
1267 #define DO_UQSHL_OP(N, M, satp) \
1268 WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, false, satp)
1269 #define DO_SQRSHL_OP(N, M, satp) \
1270 WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp)
1271 #define DO_UQRSHL_OP(N, M, satp) \
1272 WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp)
1273 #define DO_SUQSHL_OP(N, M, satp) \
1274 WRAP_QRSHL_HELPER(do_suqrshl_bhs, N, M, false, satp)
1275
1276 DO_2OP_SAT_S(vqshls, DO_SQSHL_OP)
1277 DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP)
1278 DO_2OP_SAT_S(vqrshls, DO_SQRSHL_OP)
1279 DO_2OP_SAT_U(vqrshlu, DO_UQRSHL_OP)
1280
1281 /*
1282 * Multiply add dual returning high half
1283 * The 'FN' here takes four inputs A, B, C, D, a 0/1 indicator of
1284 * whether to add the rounding constant, and the pointer to the
1285 * saturation flag, and should do "(A * B + C * D) * 2 + rounding constant",
1286 * saturate to twice the input size and return the high half; or
1287 * (A * B - C * D) etc for VQDMLSDH.
1288 */
1289 #define DO_VQDMLADH_OP(OP, ESIZE, TYPE, XCHG, ROUND, FN) \
1290 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \
1291 void *vm) \
1292 { \
1293 TYPE *d = vd, *n = vn, *m = vm; \
1294 uint16_t mask = mve_element_mask(env); \
1295 unsigned e; \
1296 bool qc = false; \
1297 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
1298 bool sat = false; \
1299 if ((e & 1) == XCHG) { \
1300 TYPE r = FN(n[H##ESIZE(e)], \
1301 m[H##ESIZE(e - XCHG)], \
1302 n[H##ESIZE(e + (1 - 2 * XCHG))], \
1303 m[H##ESIZE(e + (1 - XCHG))], \
1304 ROUND, &sat); \
1305 mergemask(&d[H##ESIZE(e)], r, mask); \
1306 qc |= sat & mask & 1; \
1307 } \
1308 } \
1309 if (qc) { \
1310 env->vfp.qc[0] = qc; \
1311 } \
1312 mve_advance_vpt(env); \
1313 }
1314
1315 static int8_t do_vqdmladh_b(int8_t a, int8_t b, int8_t c, int8_t d,
1316 int round, bool *sat)
1317 {
1318 int64_t r = ((int64_t)a * b + (int64_t)c * d) * 2 + (round << 7);
1319 return do_sat_bhw(r, INT16_MIN, INT16_MAX, sat) >> 8;
1320 }
1321
1322 static int16_t do_vqdmladh_h(int16_t a, int16_t b, int16_t c, int16_t d,
1323 int round, bool *sat)
1324 {
1325 int64_t r = ((int64_t)a * b + (int64_t)c * d) * 2 + (round << 15);
1326 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat) >> 16;
1327 }
1328
1329 static int32_t do_vqdmladh_w(int32_t a, int32_t b, int32_t c, int32_t d,
1330 int round, bool *sat)
1331 {
1332 int64_t m1 = (int64_t)a * b;
1333 int64_t m2 = (int64_t)c * d;
1334 int64_t r;
1335 /*
1336 * Architecturally we should do the entire add, double, round
1337 * and then check for saturation. We do three saturating adds,
1338 * but we need to be careful about the order. If the first
1339 * m1 + m2 saturates then it's impossible for the *2+rc to
1340 * bring it back into the non-saturated range. However, if
1341 * m1 + m2 is negative then it's possible that doing the doubling
1342 * would take the intermediate result below INT64_MAX and the
1343 * addition of the rounding constant then brings it back in range.
1344 * So we add half the rounding constant before doubling rather
1345 * than adding the rounding constant after the doubling.
1346 */
1347 if (sadd64_overflow(m1, m2, &r) ||
1348 sadd64_overflow(r, (round << 30), &r) ||
1349 sadd64_overflow(r, r, &r)) {
1350 *sat = true;
1351 return r < 0 ? INT32_MAX : INT32_MIN;
1352 }
1353 return r >> 32;
1354 }
1355
1356 static int8_t do_vqdmlsdh_b(int8_t a, int8_t b, int8_t c, int8_t d,
1357 int round, bool *sat)
1358 {
1359 int64_t r = ((int64_t)a * b - (int64_t)c * d) * 2 + (round << 7);
1360 return do_sat_bhw(r, INT16_MIN, INT16_MAX, sat) >> 8;
1361 }
1362
1363 static int16_t do_vqdmlsdh_h(int16_t a, int16_t b, int16_t c, int16_t d,
1364 int round, bool *sat)
1365 {
1366 int64_t r = ((int64_t)a * b - (int64_t)c * d) * 2 + (round << 15);
1367 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat) >> 16;
1368 }
1369
1370 static int32_t do_vqdmlsdh_w(int32_t a, int32_t b, int32_t c, int32_t d,
1371 int round, bool *sat)
1372 {
1373 int64_t m1 = (int64_t)a * b;
1374 int64_t m2 = (int64_t)c * d;
1375 int64_t r;
1376 /* The same ordering issue as in do_vqdmladh_w applies here too */
1377 if (ssub64_overflow(m1, m2, &r) ||
1378 sadd64_overflow(r, (round << 30), &r) ||
1379 sadd64_overflow(r, r, &r)) {
1380 *sat = true;
1381 return r < 0 ? INT32_MAX : INT32_MIN;
1382 }
1383 return r >> 32;
1384 }
1385
1386 DO_VQDMLADH_OP(vqdmladhb, 1, int8_t, 0, 0, do_vqdmladh_b)
1387 DO_VQDMLADH_OP(vqdmladhh, 2, int16_t, 0, 0, do_vqdmladh_h)
1388 DO_VQDMLADH_OP(vqdmladhw, 4, int32_t, 0, 0, do_vqdmladh_w)
1389 DO_VQDMLADH_OP(vqdmladhxb, 1, int8_t, 1, 0, do_vqdmladh_b)
1390 DO_VQDMLADH_OP(vqdmladhxh, 2, int16_t, 1, 0, do_vqdmladh_h)
1391 DO_VQDMLADH_OP(vqdmladhxw, 4, int32_t, 1, 0, do_vqdmladh_w)
1392
1393 DO_VQDMLADH_OP(vqrdmladhb, 1, int8_t, 0, 1, do_vqdmladh_b)
1394 DO_VQDMLADH_OP(vqrdmladhh, 2, int16_t, 0, 1, do_vqdmladh_h)
1395 DO_VQDMLADH_OP(vqrdmladhw, 4, int32_t, 0, 1, do_vqdmladh_w)
1396 DO_VQDMLADH_OP(vqrdmladhxb, 1, int8_t, 1, 1, do_vqdmladh_b)
1397 DO_VQDMLADH_OP(vqrdmladhxh, 2, int16_t, 1, 1, do_vqdmladh_h)
1398 DO_VQDMLADH_OP(vqrdmladhxw, 4, int32_t, 1, 1, do_vqdmladh_w)
1399
1400 DO_VQDMLADH_OP(vqdmlsdhb, 1, int8_t, 0, 0, do_vqdmlsdh_b)
1401 DO_VQDMLADH_OP(vqdmlsdhh, 2, int16_t, 0, 0, do_vqdmlsdh_h)
1402 DO_VQDMLADH_OP(vqdmlsdhw, 4, int32_t, 0, 0, do_vqdmlsdh_w)
1403 DO_VQDMLADH_OP(vqdmlsdhxb, 1, int8_t, 1, 0, do_vqdmlsdh_b)
1404 DO_VQDMLADH_OP(vqdmlsdhxh, 2, int16_t, 1, 0, do_vqdmlsdh_h)
1405 DO_VQDMLADH_OP(vqdmlsdhxw, 4, int32_t, 1, 0, do_vqdmlsdh_w)
1406
1407 DO_VQDMLADH_OP(vqrdmlsdhb, 1, int8_t, 0, 1, do_vqdmlsdh_b)
1408 DO_VQDMLADH_OP(vqrdmlsdhh, 2, int16_t, 0, 1, do_vqdmlsdh_h)
1409 DO_VQDMLADH_OP(vqrdmlsdhw, 4, int32_t, 0, 1, do_vqdmlsdh_w)
1410 DO_VQDMLADH_OP(vqrdmlsdhxb, 1, int8_t, 1, 1, do_vqdmlsdh_b)
1411 DO_VQDMLADH_OP(vqrdmlsdhxh, 2, int16_t, 1, 1, do_vqdmlsdh_h)
1412 DO_VQDMLADH_OP(vqrdmlsdhxw, 4, int32_t, 1, 1, do_vqdmlsdh_w)
1413
1414 #define DO_2OP_SCALAR(OP, ESIZE, TYPE, FN) \
1415 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \
1416 uint32_t rm) \
1417 { \
1418 TYPE *d = vd, *n = vn; \
1419 TYPE m = rm; \
1420 uint16_t mask = mve_element_mask(env); \
1421 unsigned e; \
1422 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
1423 mergemask(&d[H##ESIZE(e)], FN(n[H##ESIZE(e)], m), mask); \
1424 } \
1425 mve_advance_vpt(env); \
1426 }
1427
1428 #define DO_2OP_SAT_SCALAR(OP, ESIZE, TYPE, FN) \
1429 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \
1430 uint32_t rm) \
1431 { \
1432 TYPE *d = vd, *n = vn; \
1433 TYPE m = rm; \
1434 uint16_t mask = mve_element_mask(env); \
1435 unsigned e; \
1436 bool qc = false; \
1437 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
1438 bool sat = false; \
1439 mergemask(&d[H##ESIZE(e)], FN(n[H##ESIZE(e)], m, &sat), \
1440 mask); \
1441 qc |= sat & mask & 1; \
1442 } \
1443 if (qc) { \
1444 env->vfp.qc[0] = qc; \
1445 } \
1446 mve_advance_vpt(env); \
1447 }
1448
1449 /* "accumulating" version where FN takes d as well as n and m */
1450 #define DO_2OP_ACC_SCALAR(OP, ESIZE, TYPE, FN) \
1451 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \
1452 uint32_t rm) \
1453 { \
1454 TYPE *d = vd, *n = vn; \
1455 TYPE m = rm; \
1456 uint16_t mask = mve_element_mask(env); \
1457 unsigned e; \
1458 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
1459 mergemask(&d[H##ESIZE(e)], \
1460 FN(d[H##ESIZE(e)], n[H##ESIZE(e)], m), mask); \
1461 } \
1462 mve_advance_vpt(env); \
1463 }
1464
1465 #define DO_2OP_SAT_ACC_SCALAR(OP, ESIZE, TYPE, FN) \
1466 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \
1467 uint32_t rm) \
1468 { \
1469 TYPE *d = vd, *n = vn; \
1470 TYPE m = rm; \
1471 uint16_t mask = mve_element_mask(env); \
1472 unsigned e; \
1473 bool qc = false; \
1474 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
1475 bool sat = false; \
1476 mergemask(&d[H##ESIZE(e)], \
1477 FN(d[H##ESIZE(e)], n[H##ESIZE(e)], m, &sat), \
1478 mask); \
1479 qc |= sat & mask & 1; \
1480 } \
1481 if (qc) { \
1482 env->vfp.qc[0] = qc; \
1483 } \
1484 mve_advance_vpt(env); \
1485 }
1486
1487 /* provide unsigned 2-op scalar helpers for all sizes */
1488 #define DO_2OP_SCALAR_U(OP, FN) \
1489 DO_2OP_SCALAR(OP##b, 1, uint8_t, FN) \
1490 DO_2OP_SCALAR(OP##h, 2, uint16_t, FN) \
1491 DO_2OP_SCALAR(OP##w, 4, uint32_t, FN)
1492 #define DO_2OP_SCALAR_S(OP, FN) \
1493 DO_2OP_SCALAR(OP##b, 1, int8_t, FN) \
1494 DO_2OP_SCALAR(OP##h, 2, int16_t, FN) \
1495 DO_2OP_SCALAR(OP##w, 4, int32_t, FN)
1496
1497 #define DO_2OP_ACC_SCALAR_U(OP, FN) \
1498 DO_2OP_ACC_SCALAR(OP##b, 1, uint8_t, FN) \
1499 DO_2OP_ACC_SCALAR(OP##h, 2, uint16_t, FN) \
1500 DO_2OP_ACC_SCALAR(OP##w, 4, uint32_t, FN)
1501
1502 DO_2OP_SCALAR_U(vadd_scalar, DO_ADD)
1503 DO_2OP_SCALAR_U(vsub_scalar, DO_SUB)
1504 DO_2OP_SCALAR_U(vmul_scalar, DO_MUL)
1505 DO_2OP_SCALAR_S(vhadds_scalar, do_vhadd_s)
1506 DO_2OP_SCALAR_U(vhaddu_scalar, do_vhadd_u)
1507 DO_2OP_SCALAR_S(vhsubs_scalar, do_vhsub_s)
1508 DO_2OP_SCALAR_U(vhsubu_scalar, do_vhsub_u)
1509
1510 DO_2OP_SAT_SCALAR(vqaddu_scalarb, 1, uint8_t, DO_UQADD_B)
1511 DO_2OP_SAT_SCALAR(vqaddu_scalarh, 2, uint16_t, DO_UQADD_H)
1512 DO_2OP_SAT_SCALAR(vqaddu_scalarw, 4, uint32_t, DO_UQADD_W)
1513 DO_2OP_SAT_SCALAR(vqadds_scalarb, 1, int8_t, DO_SQADD_B)
1514 DO_2OP_SAT_SCALAR(vqadds_scalarh, 2, int16_t, DO_SQADD_H)
1515 DO_2OP_SAT_SCALAR(vqadds_scalarw, 4, int32_t, DO_SQADD_W)
1516
1517 DO_2OP_SAT_SCALAR(vqsubu_scalarb, 1, uint8_t, DO_UQSUB_B)
1518 DO_2OP_SAT_SCALAR(vqsubu_scalarh, 2, uint16_t, DO_UQSUB_H)
1519 DO_2OP_SAT_SCALAR(vqsubu_scalarw, 4, uint32_t, DO_UQSUB_W)
1520 DO_2OP_SAT_SCALAR(vqsubs_scalarb, 1, int8_t, DO_SQSUB_B)
1521 DO_2OP_SAT_SCALAR(vqsubs_scalarh, 2, int16_t, DO_SQSUB_H)
1522 DO_2OP_SAT_SCALAR(vqsubs_scalarw, 4, int32_t, DO_SQSUB_W)
1523
1524 DO_2OP_SAT_SCALAR(vqdmulh_scalarb, 1, int8_t, DO_QDMULH_B)
1525 DO_2OP_SAT_SCALAR(vqdmulh_scalarh, 2, int16_t, DO_QDMULH_H)
1526 DO_2OP_SAT_SCALAR(vqdmulh_scalarw, 4, int32_t, DO_QDMULH_W)
1527 DO_2OP_SAT_SCALAR(vqrdmulh_scalarb, 1, int8_t, DO_QRDMULH_B)
1528 DO_2OP_SAT_SCALAR(vqrdmulh_scalarh, 2, int16_t, DO_QRDMULH_H)
1529 DO_2OP_SAT_SCALAR(vqrdmulh_scalarw, 4, int32_t, DO_QRDMULH_W)
1530
1531 static int8_t do_vqdmlah_b(int8_t a, int8_t b, int8_t c, int round, bool *sat)
1532 {
1533 int64_t r = (int64_t)a * b * 2 + ((int64_t)c << 8) + (round << 7);
1534 return do_sat_bhw(r, INT16_MIN, INT16_MAX, sat) >> 8;
1535 }
1536
1537 static int16_t do_vqdmlah_h(int16_t a, int16_t b, int16_t c,
1538 int round, bool *sat)
1539 {
1540 int64_t r = (int64_t)a * b * 2 + ((int64_t)c << 16) + (round << 15);
1541 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat) >> 16;
1542 }
1543
1544 static int32_t do_vqdmlah_w(int32_t a, int32_t b, int32_t c,
1545 int round, bool *sat)
1546 {
1547 /*
1548 * Architecturally we should do the entire add, double, round
1549 * and then check for saturation. We do three saturating adds,
1550 * but we need to be careful about the order. If the first
1551 * m1 + m2 saturates then it's impossible for the *2+rc to
1552 * bring it back into the non-saturated range. However, if
1553 * m1 + m2 is negative then it's possible that doing the doubling
1554 * would take the intermediate result below INT64_MAX and the
1555 * addition of the rounding constant then brings it back in range.
1556 * So we add half the rounding constant and half the "c << esize"
1557 * before doubling rather than adding the rounding constant after
1558 * the doubling.
1559 */
1560 int64_t m1 = (int64_t)a * b;
1561 int64_t m2 = (int64_t)c << 31;
1562 int64_t r;
1563 if (sadd64_overflow(m1, m2, &r) ||
1564 sadd64_overflow(r, (round << 30), &r) ||
1565 sadd64_overflow(r, r, &r)) {
1566 *sat = true;
1567 return r < 0 ? INT32_MAX : INT32_MIN;
1568 }
1569 return r >> 32;
1570 }
1571
1572 /*
1573 * The *MLAH insns are vector * scalar + vector;
1574 * the *MLASH insns are vector * vector + scalar
1575 */
1576 #define DO_VQDMLAH_B(D, N, M, S) do_vqdmlah_b(N, M, D, 0, S)
1577 #define DO_VQDMLAH_H(D, N, M, S) do_vqdmlah_h(N, M, D, 0, S)
1578 #define DO_VQDMLAH_W(D, N, M, S) do_vqdmlah_w(N, M, D, 0, S)
1579 #define DO_VQRDMLAH_B(D, N, M, S) do_vqdmlah_b(N, M, D, 1, S)
1580 #define DO_VQRDMLAH_H(D, N, M, S) do_vqdmlah_h(N, M, D, 1, S)
1581 #define DO_VQRDMLAH_W(D, N, M, S) do_vqdmlah_w(N, M, D, 1, S)
1582
1583 #define DO_VQDMLASH_B(D, N, M, S) do_vqdmlah_b(N, D, M, 0, S)
1584 #define DO_VQDMLASH_H(D, N, M, S) do_vqdmlah_h(N, D, M, 0, S)
1585 #define DO_VQDMLASH_W(D, N, M, S) do_vqdmlah_w(N, D, M, 0, S)
1586 #define DO_VQRDMLASH_B(D, N, M, S) do_vqdmlah_b(N, D, M, 1, S)
1587 #define DO_VQRDMLASH_H(D, N, M, S) do_vqdmlah_h(N, D, M, 1, S)
1588 #define DO_VQRDMLASH_W(D, N, M, S) do_vqdmlah_w(N, D, M, 1, S)
1589
1590 DO_2OP_SAT_ACC_SCALAR(vqdmlahb, 1, int8_t, DO_VQDMLAH_B)
1591 DO_2OP_SAT_ACC_SCALAR(vqdmlahh, 2, int16_t, DO_VQDMLAH_H)
1592 DO_2OP_SAT_ACC_SCALAR(vqdmlahw, 4, int32_t, DO_VQDMLAH_W)
1593 DO_2OP_SAT_ACC_SCALAR(vqrdmlahb, 1, int8_t, DO_VQRDMLAH_B)
1594 DO_2OP_SAT_ACC_SCALAR(vqrdmlahh, 2, int16_t, DO_VQRDMLAH_H)
1595 DO_2OP_SAT_ACC_SCALAR(vqrdmlahw, 4, int32_t, DO_VQRDMLAH_W)
1596
1597 DO_2OP_SAT_ACC_SCALAR(vqdmlashb, 1, int8_t, DO_VQDMLASH_B)
1598 DO_2OP_SAT_ACC_SCALAR(vqdmlashh, 2, int16_t, DO_VQDMLASH_H)
1599 DO_2OP_SAT_ACC_SCALAR(vqdmlashw, 4, int32_t, DO_VQDMLASH_W)
1600 DO_2OP_SAT_ACC_SCALAR(vqrdmlashb, 1, int8_t, DO_VQRDMLASH_B)
1601 DO_2OP_SAT_ACC_SCALAR(vqrdmlashh, 2, int16_t, DO_VQRDMLASH_H)
1602 DO_2OP_SAT_ACC_SCALAR(vqrdmlashw, 4, int32_t, DO_VQRDMLASH_W)
1603
1604 /* Vector by scalar plus vector */
1605 #define DO_VMLA(D, N, M) ((N) * (M) + (D))
1606
1607 DO_2OP_ACC_SCALAR_U(vmla, DO_VMLA)
1608
1609 /* Vector by vector plus scalar */
1610 #define DO_VMLAS(D, N, M) ((N) * (D) + (M))
1611
1612 DO_2OP_ACC_SCALAR_U(vmlas, DO_VMLAS)
1613
1614 /*
1615 * Long saturating scalar ops. As with DO_2OP_L, TYPE and H are for the
1616 * input (smaller) type and LESIZE, LTYPE, LH for the output (long) type.
1617 * SATMASK specifies which bits of the predicate mask matter for determining
1618 * whether to propagate a saturation indication into FPSCR.QC -- for
1619 * the 16x16->32 case we must check only the bit corresponding to the T or B
1620 * half that we used, but for the 32x32->64 case we propagate if the mask
1621 * bit is set for either half.
1622 */
1623 #define DO_2OP_SAT_SCALAR_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN, SATMASK) \
1624 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \
1625 uint32_t rm) \
1626 { \
1627 LTYPE *d = vd; \
1628 TYPE *n = vn; \
1629 TYPE m = rm; \
1630 uint16_t mask = mve_element_mask(env); \
1631 unsigned le; \
1632 bool qc = false; \
1633 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
1634 bool sat = false; \
1635 LTYPE r = FN((LTYPE)n[H##ESIZE(le * 2 + TOP)], m, &sat); \
1636 mergemask(&d[H##LESIZE(le)], r, mask); \
1637 qc |= sat && (mask & SATMASK); \
1638 } \
1639 if (qc) { \
1640 env->vfp.qc[0] = qc; \
1641 } \
1642 mve_advance_vpt(env); \
1643 }
1644
1645 static inline int32_t do_qdmullh(int16_t n, int16_t m, bool *sat)
1646 {
1647 int64_t r = ((int64_t)n * m) * 2;
1648 return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat);
1649 }
1650
1651 static inline int64_t do_qdmullw(int32_t n, int32_t m, bool *sat)
1652 {
1653 /* The multiply can't overflow, but the doubling might */
1654 int64_t r = (int64_t)n * m;
1655 if (r > INT64_MAX / 2) {
1656 *sat = true;
1657 return INT64_MAX;
1658 } else if (r < INT64_MIN / 2) {
1659 *sat = true;
1660 return INT64_MIN;
1661 } else {
1662 return r * 2;
1663 }
1664 }
1665
1666 #define SATMASK16B 1
1667 #define SATMASK16T (1 << 2)
1668 #define SATMASK32 ((1 << 4) | 1)
1669
1670 DO_2OP_SAT_SCALAR_L(vqdmullb_scalarh, 0, 2, int16_t, 4, int32_t, \
1671 do_qdmullh, SATMASK16B)
1672 DO_2OP_SAT_SCALAR_L(vqdmullb_scalarw, 0, 4, int32_t, 8, int64_t, \
1673 do_qdmullw, SATMASK32)
1674 DO_2OP_SAT_SCALAR_L(vqdmullt_scalarh, 1, 2, int16_t, 4, int32_t, \
1675 do_qdmullh, SATMASK16T)
1676 DO_2OP_SAT_SCALAR_L(vqdmullt_scalarw, 1, 4, int32_t, 8, int64_t, \
1677 do_qdmullw, SATMASK32)
1678
1679 /*
1680 * Long saturating ops
1681 */
1682 #define DO_2OP_SAT_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN, SATMASK) \
1683 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \
1684 void *vm) \
1685 { \
1686 LTYPE *d = vd; \
1687 TYPE *n = vn, *m = vm; \
1688 uint16_t mask = mve_element_mask(env); \
1689 unsigned le; \
1690 bool qc = false; \
1691 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
1692 bool sat = false; \
1693 LTYPE op1 = n[H##ESIZE(le * 2 + TOP)]; \
1694 LTYPE op2 = m[H##ESIZE(le * 2 + TOP)]; \
1695 mergemask(&d[H##LESIZE(le)], FN(op1, op2, &sat), mask); \
1696 qc |= sat && (mask & SATMASK); \
1697 } \
1698 if (qc) { \
1699 env->vfp.qc[0] = qc; \
1700 } \
1701 mve_advance_vpt(env); \
1702 }
1703
1704 DO_2OP_SAT_L(vqdmullbh, 0, 2, int16_t, 4, int32_t, do_qdmullh, SATMASK16B)
1705 DO_2OP_SAT_L(vqdmullbw, 0, 4, int32_t, 8, int64_t, do_qdmullw, SATMASK32)
1706 DO_2OP_SAT_L(vqdmullth, 1, 2, int16_t, 4, int32_t, do_qdmullh, SATMASK16T)
1707 DO_2OP_SAT_L(vqdmulltw, 1, 4, int32_t, 8, int64_t, do_qdmullw, SATMASK32)
1708
1709 static inline uint32_t do_vbrsrb(uint32_t n, uint32_t m)
1710 {
1711 m &= 0xff;
1712 if (m == 0) {
1713 return 0;
1714 }
1715 n = revbit8(n);
1716 if (m < 8) {
1717 n >>= 8 - m;
1718 }
1719 return n;
1720 }
1721
1722 static inline uint32_t do_vbrsrh(uint32_t n, uint32_t m)
1723 {
1724 m &= 0xff;
1725 if (m == 0) {
1726 return 0;
1727 }
1728 n = revbit16(n);
1729 if (m < 16) {
1730 n >>= 16 - m;
1731 }
1732 return n;
1733 }
1734
1735 static inline uint32_t do_vbrsrw(uint32_t n, uint32_t m)
1736 {
1737 m &= 0xff;
1738 if (m == 0) {
1739 return 0;
1740 }
1741 n = revbit32(n);
1742 if (m < 32) {
1743 n >>= 32 - m;
1744 }
1745 return n;
1746 }
1747
1748 DO_2OP_SCALAR(vbrsrb, 1, uint8_t, do_vbrsrb)
1749 DO_2OP_SCALAR(vbrsrh, 2, uint16_t, do_vbrsrh)
1750 DO_2OP_SCALAR(vbrsrw, 4, uint32_t, do_vbrsrw)
1751
1752 /*
1753 * Multiply add long dual accumulate ops.
1754 */
1755 #define DO_LDAV(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC) \
1756 uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \
1757 void *vm, uint64_t a) \
1758 { \
1759 uint16_t mask = mve_element_mask(env); \
1760 unsigned e; \
1761 TYPE *n = vn, *m = vm; \
1762 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
1763 if (mask & 1) { \
1764 if (e & 1) { \
1765 a ODDACC \
1766 (int64_t)n[H##ESIZE(e - 1 * XCHG)] * m[H##ESIZE(e)]; \
1767 } else { \
1768 a EVENACC \
1769 (int64_t)n[H##ESIZE(e + 1 * XCHG)] * m[H##ESIZE(e)]; \
1770 } \
1771 } \
1772 } \
1773 mve_advance_vpt(env); \
1774 return a; \
1775 }
1776
1777 DO_LDAV(vmlaldavsh, 2, int16_t, false, +=, +=)
1778 DO_LDAV(vmlaldavxsh, 2, int16_t, true, +=, +=)
1779 DO_LDAV(vmlaldavsw, 4, int32_t, false, +=, +=)
1780 DO_LDAV(vmlaldavxsw, 4, int32_t, true, +=, +=)
1781
1782 DO_LDAV(vmlaldavuh, 2, uint16_t, false, +=, +=)
1783 DO_LDAV(vmlaldavuw, 4, uint32_t, false, +=, +=)
1784
1785 DO_LDAV(vmlsldavsh, 2, int16_t, false, +=, -=)
1786 DO_LDAV(vmlsldavxsh, 2, int16_t, true, +=, -=)
1787 DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=)
1788 DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
1789
1790 /*
1791 * Multiply add dual accumulate ops
1792 */
1793 #define DO_DAV(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC) \
1794 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \
1795 void *vm, uint32_t a) \
1796 { \
1797 uint16_t mask = mve_element_mask(env); \
1798 unsigned e; \
1799 TYPE *n = vn, *m = vm; \
1800 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
1801 if (mask & 1) { \
1802 if (e & 1) { \
1803 a ODDACC \
1804 n[H##ESIZE(e - 1 * XCHG)] * m[H##ESIZE(e)]; \
1805 } else { \
1806 a EVENACC \
1807 n[H##ESIZE(e + 1 * XCHG)] * m[H##ESIZE(e)]; \
1808 } \
1809 } \
1810 } \
1811 mve_advance_vpt(env); \
1812 return a; \
1813 }
1814
1815 #define DO_DAV_S(INSN, XCHG, EVENACC, ODDACC) \
1816 DO_DAV(INSN##b, 1, int8_t, XCHG, EVENACC, ODDACC) \
1817 DO_DAV(INSN##h, 2, int16_t, XCHG, EVENACC, ODDACC) \
1818 DO_DAV(INSN##w, 4, int32_t, XCHG, EVENACC, ODDACC)
1819
1820 #define DO_DAV_U(INSN, XCHG, EVENACC, ODDACC) \
1821 DO_DAV(INSN##b, 1, uint8_t, XCHG, EVENACC, ODDACC) \
1822 DO_DAV(INSN##h, 2, uint16_t, XCHG, EVENACC, ODDACC) \
1823 DO_DAV(INSN##w, 4, uint32_t, XCHG, EVENACC, ODDACC)
1824
1825 DO_DAV_S(vmladavs, false, +=, +=)
1826 DO_DAV_U(vmladavu, false, +=, +=)
1827 DO_DAV_S(vmlsdav, false, +=, -=)
1828 DO_DAV_S(vmladavsx, true, +=, +=)
1829 DO_DAV_S(vmlsdavx, true, +=, -=)
1830
1831 /*
1832 * Rounding multiply add long dual accumulate high. In the pseudocode
1833 * this is implemented with a 72-bit internal accumulator value of which
1834 * the top 64 bits are returned. We optimize this to avoid having to
1835 * use 128-bit arithmetic -- we can do this because the 74-bit accumulator
1836 * is squashed back into 64-bits after each beat.
1837 */
1838 #define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB) \
1839 uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \
1840 void *vm, uint64_t a) \
1841 { \
1842 uint16_t mask = mve_element_mask(env); \
1843 unsigned e; \
1844 TYPE *n = vn, *m = vm; \
1845 for (e = 0; e < 16 / 4; e++, mask >>= 4) { \
1846 if (mask & 1) { \
1847 LTYPE mul; \
1848 if (e & 1) { \
1849 mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)]; \
1850 if (SUB) { \
1851 mul = -mul; \
1852 } \
1853 } else { \
1854 mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)]; \
1855 } \
1856 mul = (mul >> 8) + ((mul >> 7) & 1); \
1857 a += mul; \
1858 } \
1859 } \
1860 mve_advance_vpt(env); \
1861 return a; \
1862 }
1863
1864 DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false)
1865 DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false)
1866
1867 DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false)
1868
1869 DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true)
1870 DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true)
1871
1872 /* Vector add across vector */
1873 #define DO_VADDV(OP, ESIZE, TYPE) \
1874 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \
1875 uint32_t ra) \
1876 { \
1877 uint16_t mask = mve_element_mask(env); \
1878 unsigned e; \
1879 TYPE *m = vm; \
1880 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
1881 if (mask & 1) { \
1882 ra += m[H##ESIZE(e)]; \
1883 } \
1884 } \
1885 mve_advance_vpt(env); \
1886 return ra; \
1887 } \
1888
1889 DO_VADDV(vaddvsb, 1, int8_t)
1890 DO_VADDV(vaddvsh, 2, int16_t)
1891 DO_VADDV(vaddvsw, 4, int32_t)
1892 DO_VADDV(vaddvub, 1, uint8_t)
1893 DO_VADDV(vaddvuh, 2, uint16_t)
1894 DO_VADDV(vaddvuw, 4, uint32_t)
1895
1896 /*
1897 * Vector max/min across vector. Unlike VADDV, we must
1898 * read ra as the element size, not its full width.
1899 * We work with int64_t internally for simplicity.
1900 */
1901 #define DO_VMAXMINV(OP, ESIZE, TYPE, RATYPE, FN) \
1902 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \
1903 uint32_t ra_in) \
1904 { \
1905 uint16_t mask = mve_element_mask(env); \
1906 unsigned e; \
1907 TYPE *m = vm; \
1908 int64_t ra = (RATYPE)ra_in; \
1909 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
1910 if (mask & 1) { \
1911 ra = FN(ra, m[H##ESIZE(e)]); \
1912 } \
1913 } \
1914 mve_advance_vpt(env); \
1915 return ra; \
1916 } \
1917
1918 #define DO_VMAXMINV_U(INSN, FN) \
1919 DO_VMAXMINV(INSN##b, 1, uint8_t, uint8_t, FN) \
1920 DO_VMAXMINV(INSN##h, 2, uint16_t, uint16_t, FN) \
1921 DO_VMAXMINV(INSN##w, 4, uint32_t, uint32_t, FN)
1922 #define DO_VMAXMINV_S(INSN, FN) \
1923 DO_VMAXMINV(INSN##b, 1, int8_t, int8_t, FN) \
1924 DO_VMAXMINV(INSN##h, 2, int16_t, int16_t, FN) \
1925 DO_VMAXMINV(INSN##w, 4, int32_t, int32_t, FN)
1926
1927 /*
1928 * Helpers for max and min of absolute values across vector:
1929 * note that we only take the absolute value of 'm', not 'n'
1930 */
1931 static int64_t do_maxa(int64_t n, int64_t m)
1932 {
1933 if (m < 0) {
1934 m = -m;
1935 }
1936 return MAX(n, m);
1937 }
1938
1939 static int64_t do_mina(int64_t n, int64_t m)
1940 {
1941 if (m < 0) {
1942 m = -m;
1943 }
1944 return MIN(n, m);
1945 }
1946
1947 DO_VMAXMINV_S(vmaxvs, DO_MAX)
1948 DO_VMAXMINV_U(vmaxvu, DO_MAX)
1949 DO_VMAXMINV_S(vminvs, DO_MIN)
1950 DO_VMAXMINV_U(vminvu, DO_MIN)
1951 /*
1952 * VMAXAV, VMINAV treat the general purpose input as unsigned
1953 * and the vector elements as signed.
1954 */
1955 DO_VMAXMINV(vmaxavb, 1, int8_t, uint8_t, do_maxa)
1956 DO_VMAXMINV(vmaxavh, 2, int16_t, uint16_t, do_maxa)
1957 DO_VMAXMINV(vmaxavw, 4, int32_t, uint32_t, do_maxa)
1958 DO_VMAXMINV(vminavb, 1, int8_t, uint8_t, do_mina)
1959 DO_VMAXMINV(vminavh, 2, int16_t, uint16_t, do_mina)
1960 DO_VMAXMINV(vminavw, 4, int32_t, uint32_t, do_mina)
1961
1962 #define DO_VABAV(OP, ESIZE, TYPE) \
1963 uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \
1964 void *vm, uint32_t ra) \
1965 { \
1966 uint16_t mask = mve_element_mask(env); \
1967 unsigned e; \
1968 TYPE *m = vm, *n = vn; \
1969 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
1970 if (mask & 1) { \
1971 int64_t n0 = n[H##ESIZE(e)]; \
1972 int64_t m0 = m[H##ESIZE(e)]; \
1973 uint32_t r = n0 >= m0 ? (n0 - m0) : (m0 - n0); \
1974 ra += r; \
1975 } \
1976 } \
1977 mve_advance_vpt(env); \
1978 return ra; \
1979 }
1980
1981 DO_VABAV(vabavsb, 1, int8_t)
1982 DO_VABAV(vabavsh, 2, int16_t)
1983 DO_VABAV(vabavsw, 4, int32_t)
1984 DO_VABAV(vabavub, 1, uint8_t)
1985 DO_VABAV(vabavuh, 2, uint16_t)
1986 DO_VABAV(vabavuw, 4, uint32_t)
1987
1988 #define DO_VADDLV(OP, TYPE, LTYPE) \
1989 uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \
1990 uint64_t ra) \
1991 { \
1992 uint16_t mask = mve_element_mask(env); \
1993 unsigned e; \
1994 TYPE *m = vm; \
1995 for (e = 0; e < 16 / 4; e++, mask >>= 4) { \
1996 if (mask & 1) { \
1997 ra += (LTYPE)m[H4(e)]; \
1998 } \
1999 } \
2000 mve_advance_vpt(env); \
2001 return ra; \
2002 } \
2003
2004 DO_VADDLV(vaddlv_s, int32_t, int64_t)
2005 DO_VADDLV(vaddlv_u, uint32_t, uint64_t)
2006
2007 /* Shifts by immediate */
2008 #define DO_2SHIFT(OP, ESIZE, TYPE, FN) \
2009 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
2010 void *vm, uint32_t shift) \
2011 { \
2012 TYPE *d = vd, *m = vm; \
2013 uint16_t mask = mve_element_mask(env); \
2014 unsigned e; \
2015 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
2016 mergemask(&d[H##ESIZE(e)], \
2017 FN(m[H##ESIZE(e)], shift), mask); \
2018 } \
2019 mve_advance_vpt(env); \
2020 }
2021
2022 #define DO_2SHIFT_SAT(OP, ESIZE, TYPE, FN) \
2023 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
2024 void *vm, uint32_t shift) \
2025 { \
2026 TYPE *d = vd, *m = vm; \
2027 uint16_t mask = mve_element_mask(env); \
2028 unsigned e; \
2029 bool qc = false; \
2030 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
2031 bool sat = false; \
2032 mergemask(&d[H##ESIZE(e)], \
2033 FN(m[H##ESIZE(e)], shift, &sat), mask); \
2034 qc |= sat & mask & 1; \
2035 } \
2036 if (qc) { \
2037 env->vfp.qc[0] = qc; \
2038 } \
2039 mve_advance_vpt(env); \
2040 }
2041
2042 /* provide unsigned 2-op shift helpers for all sizes */
2043 #define DO_2SHIFT_U(OP, FN) \
2044 DO_2SHIFT(OP##b, 1, uint8_t, FN) \
2045 DO_2SHIFT(OP##h, 2, uint16_t, FN) \
2046 DO_2SHIFT(OP##w, 4, uint32_t, FN)
2047 #define DO_2SHIFT_S(OP, FN) \
2048 DO_2SHIFT(OP##b, 1, int8_t, FN) \
2049 DO_2SHIFT(OP##h, 2, int16_t, FN) \
2050 DO_2SHIFT(OP##w, 4, int32_t, FN)
2051
2052 #define DO_2SHIFT_SAT_U(OP, FN) \
2053 DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \
2054 DO_2SHIFT_SAT(OP##h, 2, uint16_t, FN) \
2055 DO_2SHIFT_SAT(OP##w, 4, uint32_t, FN)
2056 #define DO_2SHIFT_SAT_S(OP, FN) \
2057 DO_2SHIFT_SAT(OP##b, 1, int8_t, FN) \
2058 DO_2SHIFT_SAT(OP##h, 2, int16_t, FN) \
2059 DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
2060
2061 DO_2SHIFT_U(vshli_u, DO_VSHLU)
2062 DO_2SHIFT_S(vshli_s, DO_VSHLS)
2063 DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
2064 DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
2065 DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
2066 DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
2067 DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
2068 DO_2SHIFT_SAT_U(vqrshli_u, DO_UQRSHL_OP)
2069 DO_2SHIFT_SAT_S(vqrshli_s, DO_SQRSHL_OP)
2070
2071 /* Shift-and-insert; we always work with 64 bits at a time */
2072 #define DO_2SHIFT_INSERT(OP, ESIZE, SHIFTFN, MASKFN) \
2073 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
2074 void *vm, uint32_t shift) \
2075 { \
2076 uint64_t *d = vd, *m = vm; \
2077 uint16_t mask; \
2078 uint64_t shiftmask; \
2079 unsigned e; \
2080 if (shift == ESIZE * 8) { \
2081 /* \
2082 * Only VSRI can shift by <dt>; it should mean "don't \
2083 * update the destination". The generic logic can't handle \
2084 * this because it would try to shift by an out-of-range \
2085 * amount, so special case it here. \
2086 */ \
2087 goto done; \
2088 } \
2089 assert(shift < ESIZE * 8); \
2090 mask = mve_element_mask(env); \
2091 /* ESIZE / 2 gives the MO_* value if ESIZE is in [1,2,4] */ \
2092 shiftmask = dup_const(ESIZE / 2, MASKFN(ESIZE * 8, shift)); \
2093 for (e = 0; e < 16 / 8; e++, mask >>= 8) { \
2094 uint64_t r = (SHIFTFN(m[H8(e)], shift) & shiftmask) | \
2095 (d[H8(e)] & ~shiftmask); \
2096 mergemask(&d[H8(e)], r, mask); \
2097 } \
2098 done: \
2099 mve_advance_vpt(env); \
2100 }
2101
2102 #define DO_SHL(N, SHIFT) ((N) << (SHIFT))
2103 #define DO_SHR(N, SHIFT) ((N) >> (SHIFT))
2104 #define SHL_MASK(EBITS, SHIFT) MAKE_64BIT_MASK((SHIFT), (EBITS) - (SHIFT))
2105 #define SHR_MASK(EBITS, SHIFT) MAKE_64BIT_MASK(0, (EBITS) - (SHIFT))
2106
2107 DO_2SHIFT_INSERT(vsrib, 1, DO_SHR, SHR_MASK)
2108 DO_2SHIFT_INSERT(vsrih, 2, DO_SHR, SHR_MASK)
2109 DO_2SHIFT_INSERT(vsriw, 4, DO_SHR, SHR_MASK)
2110 DO_2SHIFT_INSERT(vslib, 1, DO_SHL, SHL_MASK)
2111 DO_2SHIFT_INSERT(vslih, 2, DO_SHL, SHL_MASK)
2112 DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK)
2113
2114 /*
2115 * Long shifts taking half-sized inputs from top or bottom of the input
2116 * vector and producing a double-width result. ESIZE, TYPE are for
2117 * the input, and LESIZE, LTYPE for the output.
2118 * Unlike the normal shift helpers, we do not handle negative shift counts,
2119 * because the long shift is strictly left-only.
2120 */
2121 #define DO_VSHLL(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE) \
2122 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
2123 void *vm, uint32_t shift) \
2124 { \
2125 LTYPE *d = vd; \
2126 TYPE *m = vm; \
2127 uint16_t mask = mve_element_mask(env); \
2128 unsigned le; \
2129 assert(shift <= 16); \
2130 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
2131 LTYPE r = (LTYPE)m[H##ESIZE(le * 2 + TOP)] << shift; \
2132 mergemask(&d[H##LESIZE(le)], r, mask); \
2133 } \
2134 mve_advance_vpt(env); \
2135 }
2136
2137 #define DO_VSHLL_ALL(OP, TOP) \
2138 DO_VSHLL(OP##sb, TOP, 1, int8_t, 2, int16_t) \
2139 DO_VSHLL(OP##ub, TOP, 1, uint8_t, 2, uint16_t) \
2140 DO_VSHLL(OP##sh, TOP, 2, int16_t, 4, int32_t) \
2141 DO_VSHLL(OP##uh, TOP, 2, uint16_t, 4, uint32_t) \
2142
2143 DO_VSHLL_ALL(vshllb, false)
2144 DO_VSHLL_ALL(vshllt, true)
2145
2146 /*
2147 * Narrowing right shifts, taking a double sized input, shifting it
2148 * and putting the result in either the top or bottom half of the output.
2149 * ESIZE, TYPE are the output, and LESIZE, LTYPE the input.
2150 */
2151 #define DO_VSHRN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \
2152 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
2153 void *vm, uint32_t shift) \
2154 { \
2155 LTYPE *m = vm; \
2156 TYPE *d = vd; \
2157 uint16_t mask = mve_element_mask(env); \
2158 unsigned le; \
2159 mask >>= ESIZE * TOP; \
2160 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
2161 TYPE r = FN(m[H##LESIZE(le)], shift); \
2162 mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \
2163 } \
2164 mve_advance_vpt(env); \
2165 }
2166
2167 #define DO_VSHRN_ALL(OP, FN) \
2168 DO_VSHRN(OP##bb, false, 1, uint8_t, 2, uint16_t, FN) \
2169 DO_VSHRN(OP##bh, false, 2, uint16_t, 4, uint32_t, FN) \
2170 DO_VSHRN(OP##tb, true, 1, uint8_t, 2, uint16_t, FN) \
2171 DO_VSHRN(OP##th, true, 2, uint16_t, 4, uint32_t, FN)
2172
2173 static inline uint64_t do_urshr(uint64_t x, unsigned sh)
2174 {
2175 if (likely(sh < 64)) {
2176 return (x >> sh) + ((x >> (sh - 1)) & 1);
2177 } else if (sh == 64) {
2178 return x >> 63;
2179 } else {
2180 return 0;
2181 }
2182 }
2183
2184 static inline int64_t do_srshr(int64_t x, unsigned sh)
2185 {
2186 if (likely(sh < 64)) {
2187 return (x >> sh) + ((x >> (sh - 1)) & 1);
2188 } else {
2189 /* Rounding the sign bit always produces 0. */
2190 return 0;
2191 }
2192 }
2193
2194 DO_VSHRN_ALL(vshrn, DO_SHR)
2195 DO_VSHRN_ALL(vrshrn, do_urshr)
2196
2197 static inline int32_t do_sat_bhs(int64_t val, int64_t min, int64_t max,
2198 bool *satp)
2199 {
2200 if (val > max) {
2201 *satp = true;
2202 return max;
2203 } else if (val < min) {
2204 *satp = true;
2205 return min;
2206 } else {
2207 return val;
2208 }
2209 }
2210
2211 /* Saturating narrowing right shifts */
2212 #define DO_VSHRN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \
2213 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
2214 void *vm, uint32_t shift) \
2215 { \
2216 LTYPE *m = vm; \
2217 TYPE *d = vd; \
2218 uint16_t mask = mve_element_mask(env); \
2219 bool qc = false; \
2220 unsigned le; \
2221 mask >>= ESIZE * TOP; \
2222 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
2223 bool sat = false; \
2224 TYPE r = FN(m[H##LESIZE(le)], shift, &sat); \
2225 mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \
2226 qc |= sat & mask & 1; \
2227 } \
2228 if (qc) { \
2229 env->vfp.qc[0] = qc; \
2230 } \
2231 mve_advance_vpt(env); \
2232 }
2233
2234 #define DO_VSHRN_SAT_UB(BOP, TOP, FN) \
2235 DO_VSHRN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN) \
2236 DO_VSHRN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN)
2237
2238 #define DO_VSHRN_SAT_UH(BOP, TOP, FN) \
2239 DO_VSHRN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN) \
2240 DO_VSHRN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN)
2241
2242 #define DO_VSHRN_SAT_SB(BOP, TOP, FN) \
2243 DO_VSHRN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN) \
2244 DO_VSHRN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN)
2245
2246 #define DO_VSHRN_SAT_SH(BOP, TOP, FN) \
2247 DO_VSHRN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN) \
2248 DO_VSHRN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN)
2249
2250 #define DO_SHRN_SB(N, M, SATP) \
2251 do_sat_bhs((int64_t)(N) >> (M), INT8_MIN, INT8_MAX, SATP)
2252 #define DO_SHRN_UB(N, M, SATP) \
2253 do_sat_bhs((uint64_t)(N) >> (M), 0, UINT8_MAX, SATP)
2254 #define DO_SHRUN_B(N, M, SATP) \
2255 do_sat_bhs((int64_t)(N) >> (M), 0, UINT8_MAX, SATP)
2256
2257 #define DO_SHRN_SH(N, M, SATP) \
2258 do_sat_bhs((int64_t)(N) >> (M), INT16_MIN, INT16_MAX, SATP)
2259 #define DO_SHRN_UH(N, M, SATP) \
2260 do_sat_bhs((uint64_t)(N) >> (M), 0, UINT16_MAX, SATP)
2261 #define DO_SHRUN_H(N, M, SATP) \
2262 do_sat_bhs((int64_t)(N) >> (M), 0, UINT16_MAX, SATP)
2263
2264 #define DO_RSHRN_SB(N, M, SATP) \
2265 do_sat_bhs(do_srshr(N, M), INT8_MIN, INT8_MAX, SATP)
2266 #define DO_RSHRN_UB(N, M, SATP) \
2267 do_sat_bhs(do_urshr(N, M), 0, UINT8_MAX, SATP)
2268 #define DO_RSHRUN_B(N, M, SATP) \
2269 do_sat_bhs(do_srshr(N, M), 0, UINT8_MAX, SATP)
2270
2271 #define DO_RSHRN_SH(N, M, SATP) \
2272 do_sat_bhs(do_srshr(N, M), INT16_MIN, INT16_MAX, SATP)
2273 #define DO_RSHRN_UH(N, M, SATP) \
2274 do_sat_bhs(do_urshr(N, M), 0, UINT16_MAX, SATP)
2275 #define DO_RSHRUN_H(N, M, SATP) \
2276 do_sat_bhs(do_srshr(N, M), 0, UINT16_MAX, SATP)
2277
2278 DO_VSHRN_SAT_SB(vqshrnb_sb, vqshrnt_sb, DO_SHRN_SB)
2279 DO_VSHRN_SAT_SH(vqshrnb_sh, vqshrnt_sh, DO_SHRN_SH)
2280 DO_VSHRN_SAT_UB(vqshrnb_ub, vqshrnt_ub, DO_SHRN_UB)
2281 DO_VSHRN_SAT_UH(vqshrnb_uh, vqshrnt_uh, DO_SHRN_UH)
2282 DO_VSHRN_SAT_SB(vqshrunbb, vqshruntb, DO_SHRUN_B)
2283 DO_VSHRN_SAT_SH(vqshrunbh, vqshrunth, DO_SHRUN_H)
2284
2285 DO_VSHRN_SAT_SB(vqrshrnb_sb, vqrshrnt_sb, DO_RSHRN_SB)
2286 DO_VSHRN_SAT_SH(vqrshrnb_sh, vqrshrnt_sh, DO_RSHRN_SH)
2287 DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
2288 DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
2289 DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
2290 DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
2291
2292 #define DO_VMOVN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE) \
2293 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \
2294 { \
2295 LTYPE *m = vm; \
2296 TYPE *d = vd; \
2297 uint16_t mask = mve_element_mask(env); \
2298 unsigned le; \
2299 mask >>= ESIZE * TOP; \
2300 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
2301 mergemask(&d[H##ESIZE(le * 2 + TOP)], \
2302 m[H##LESIZE(le)], mask); \
2303 } \
2304 mve_advance_vpt(env); \
2305 }
2306
2307 DO_VMOVN(vmovnbb, false, 1, uint8_t, 2, uint16_t)
2308 DO_VMOVN(vmovnbh, false, 2, uint16_t, 4, uint32_t)
2309 DO_VMOVN(vmovntb, true, 1, uint8_t, 2, uint16_t)
2310 DO_VMOVN(vmovnth, true, 2, uint16_t, 4, uint32_t)
2311
2312 #define DO_VMOVN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \
2313 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \
2314 { \
2315 LTYPE *m = vm; \
2316 TYPE *d = vd; \
2317 uint16_t mask = mve_element_mask(env); \
2318 bool qc = false; \
2319 unsigned le; \
2320 mask >>= ESIZE * TOP; \
2321 for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
2322 bool sat = false; \
2323 TYPE r = FN(m[H##LESIZE(le)], &sat); \
2324 mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \
2325 qc |= sat & mask & 1; \
2326 } \
2327 if (qc) { \
2328 env->vfp.qc[0] = qc; \
2329 } \
2330 mve_advance_vpt(env); \
2331 }
2332
2333 #define DO_VMOVN_SAT_UB(BOP, TOP, FN) \
2334 DO_VMOVN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN) \
2335 DO_VMOVN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN)
2336
2337 #define DO_VMOVN_SAT_UH(BOP, TOP, FN) \
2338 DO_VMOVN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN) \
2339 DO_VMOVN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN)
2340
2341 #define DO_VMOVN_SAT_SB(BOP, TOP, FN) \
2342 DO_VMOVN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN) \
2343 DO_VMOVN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN)
2344
2345 #define DO_VMOVN_SAT_SH(BOP, TOP, FN) \
2346 DO_VMOVN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN) \
2347 DO_VMOVN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN)
2348
2349 #define DO_VQMOVN_SB(N, SATP) \
2350 do_sat_bhs((int64_t)(N), INT8_MIN, INT8_MAX, SATP)
2351 #define DO_VQMOVN_UB(N, SATP) \
2352 do_sat_bhs((uint64_t)(N), 0, UINT8_MAX, SATP)
2353 #define DO_VQMOVUN_B(N, SATP) \
2354 do_sat_bhs((int64_t)(N), 0, UINT8_MAX, SATP)
2355
2356 #define DO_VQMOVN_SH(N, SATP) \
2357 do_sat_bhs((int64_t)(N), INT16_MIN, INT16_MAX, SATP)
2358 #define DO_VQMOVN_UH(N, SATP) \
2359 do_sat_bhs((uint64_t)(N), 0, UINT16_MAX, SATP)
2360 #define DO_VQMOVUN_H(N, SATP) \
2361 do_sat_bhs((int64_t)(N), 0, UINT16_MAX, SATP)
2362
2363 DO_VMOVN_SAT_SB(vqmovnbsb, vqmovntsb, DO_VQMOVN_SB)
2364 DO_VMOVN_SAT_SH(vqmovnbsh, vqmovntsh, DO_VQMOVN_SH)
2365 DO_VMOVN_SAT_UB(vqmovnbub, vqmovntub, DO_VQMOVN_UB)
2366 DO_VMOVN_SAT_UH(vqmovnbuh, vqmovntuh, DO_VQMOVN_UH)
2367 DO_VMOVN_SAT_SB(vqmovunbb, vqmovuntb, DO_VQMOVUN_B)
2368 DO_VMOVN_SAT_SH(vqmovunbh, vqmovunth, DO_VQMOVUN_H)
2369
2370 uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
2371 uint32_t shift)
2372 {
2373 uint32_t *d = vd;
2374 uint16_t mask = mve_element_mask(env);
2375 unsigned e;
2376 uint32_t r;
2377
2378 /*
2379 * For each 32-bit element, we shift it left, bringing in the
2380 * low 'shift' bits of rdm at the bottom. Bits shifted out at
2381 * the top become the new rdm, if the predicate mask permits.
2382 * The final rdm value is returned to update the register.
2383 * shift == 0 here means "shift by 32 bits".
2384 */
2385 if (shift == 0) {
2386 for (e = 0; e < 16 / 4; e++, mask >>= 4) {
2387 r = rdm;
2388 if (mask & 1) {
2389 rdm = d[H4(e)];
2390 }
2391 mergemask(&d[H4(e)], r, mask);
2392 }
2393 } else {
2394 uint32_t shiftmask = MAKE_64BIT_MASK(0, shift);
2395
2396 for (e = 0; e < 16 / 4; e++, mask >>= 4) {
2397 r = (d[H4(e)] << shift) | (rdm & shiftmask);
2398 if (mask & 1) {
2399 rdm = d[H4(e)] >> (32 - shift);
2400 }
2401 mergemask(&d[H4(e)], r, mask);
2402 }
2403 }
2404 mve_advance_vpt(env);
2405 return rdm;
2406 }
2407
2408 uint64_t HELPER(mve_sshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
2409 {
2410 return do_sqrshl_d(n, -(int8_t)shift, false, NULL);
2411 }
2412
2413 uint64_t HELPER(mve_ushll)(CPUARMState *env, uint64_t n, uint32_t shift)
2414 {
2415 return do_uqrshl_d(n, (int8_t)shift, false, NULL);
2416 }
2417
2418 uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
2419 {
2420 return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
2421 }
2422
2423 uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
2424 {
2425 return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
2426 }
2427
2428 uint64_t HELPER(mve_sqrshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
2429 {
2430 return do_sqrshl_d(n, -(int8_t)shift, true, &env->QF);
2431 }
2432
2433 uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift)
2434 {
2435 return do_uqrshl_d(n, (int8_t)shift, true, &env->QF);
2436 }
2437
2438 /* Operate on 64-bit values, but saturate at 48 bits */
2439 static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift,
2440 bool round, uint32_t *sat)
2441 {
2442 int64_t val, extval;
2443
2444 if (shift <= -48) {
2445 /* Rounding the sign bit always produces 0. */
2446 if (round) {
2447 return 0;
2448 }
2449 return src >> 63;
2450 } else if (shift < 0) {
2451 if (round) {
2452 src >>= -shift - 1;
2453 val = (src >> 1) + (src & 1);
2454 } else {
2455 val = src >> -shift;
2456 }
2457 extval = sextract64(val, 0, 48);
2458 if (!sat || val == extval) {
2459 return extval;
2460 }
2461 } else if (shift < 48) {
2462 int64_t extval = sextract64(src << shift, 0, 48);
2463 if (!sat || src == (extval >> shift)) {
2464 return extval;
2465 }
2466 } else if (!sat || src == 0) {
2467 return 0;
2468 }
2469
2470 *sat = 1;
2471 return src >= 0 ? MAKE_64BIT_MASK(0, 47) : MAKE_64BIT_MASK(47, 17);
2472 }
2473
2474 /* Operate on 64-bit values, but saturate at 48 bits */
2475 static inline uint64_t do_uqrshl48_d(uint64_t src, int64_t shift,
2476 bool round, uint32_t *sat)
2477 {
2478 uint64_t val, extval;
2479
2480 if (shift <= -(48 + round)) {
2481 return 0;
2482 } else if (shift < 0) {
2483 if (round) {
2484 val = src >> (-shift - 1);
2485 val = (val >> 1) + (val & 1);
2486 } else {
2487 val = src >> -shift;
2488 }
2489 extval = extract64(val, 0, 48);
2490 if (!sat || val == extval) {
2491 return extval;
2492 }
2493 } else if (shift < 48) {
2494 uint64_t extval = extract64(src << shift, 0, 48);
2495 if (!sat || src == (extval >> shift)) {
2496 return extval;
2497 }
2498 } else if (!sat || src == 0) {
2499 return 0;
2500 }
2501
2502 *sat = 1;
2503 return MAKE_64BIT_MASK(0, 48);
2504 }
2505
2506 uint64_t HELPER(mve_sqrshrl48)(CPUARMState *env, uint64_t n, uint32_t shift)
2507 {
2508 return do_sqrshl48_d(n, -(int8_t)shift, true, &env->QF);
2509 }
2510
2511 uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
2512 {
2513 return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
2514 }
2515
2516 uint32_t HELPER(mve_uqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
2517 {
2518 return do_uqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
2519 }
2520
2521 uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
2522 {
2523 return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
2524 }
2525
2526 uint32_t HELPER(mve_uqrshl)(CPUARMState *env, uint32_t n, uint32_t shift)
2527 {
2528 return do_uqrshl_bhs(n, (int8_t)shift, 32, true, &env->QF);
2529 }
2530
2531 uint32_t HELPER(mve_sqrshr)(CPUARMState *env, uint32_t n, uint32_t shift)
2532 {
2533 return do_sqrshl_bhs(n, -(int8_t)shift, 32, true, &env->QF);
2534 }
2535
2536 #define DO_VIDUP(OP, ESIZE, TYPE, FN) \
2537 uint32_t HELPER(mve_##OP)(CPUARMState *env, void *vd, \
2538 uint32_t offset, uint32_t imm) \
2539 { \
2540 TYPE *d = vd; \
2541 uint16_t mask = mve_element_mask(env); \
2542 unsigned e; \
2543 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
2544 mergemask(&d[H##ESIZE(e)], offset, mask); \
2545 offset = FN(offset, imm); \
2546 } \
2547 mve_advance_vpt(env); \
2548 return offset; \
2549 }
2550
2551 #define DO_VIWDUP(OP, ESIZE, TYPE, FN) \
2552 uint32_t HELPER(mve_##OP)(CPUARMState *env, void *vd, \
2553 uint32_t offset, uint32_t wrap, \
2554 uint32_t imm) \
2555 { \
2556 TYPE *d = vd; \
2557 uint16_t mask = mve_element_mask(env); \
2558 unsigned e; \
2559 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
2560 mergemask(&d[H##ESIZE(e)], offset, mask); \
2561 offset = FN(offset, wrap, imm); \
2562 } \
2563 mve_advance_vpt(env); \
2564 return offset; \
2565 }
2566
2567 #define DO_VIDUP_ALL(OP, FN) \
2568 DO_VIDUP(OP##b, 1, int8_t, FN) \
2569 DO_VIDUP(OP##h, 2, int16_t, FN) \
2570 DO_VIDUP(OP##w, 4, int32_t, FN)
2571
2572 #define DO_VIWDUP_ALL(OP, FN) \
2573 DO_VIWDUP(OP##b, 1, int8_t, FN) \
2574 DO_VIWDUP(OP##h, 2, int16_t, FN) \
2575 DO_VIWDUP(OP##w, 4, int32_t, FN)
2576
2577 static uint32_t do_add_wrap(uint32_t offset, uint32_t wrap, uint32_t imm)
2578 {
2579 offset += imm;
2580 if (offset == wrap) {
2581 offset = 0;
2582 }
2583 return offset;
2584 }
2585
2586 static uint32_t do_sub_wrap(uint32_t offset, uint32_t wrap, uint32_t imm)
2587 {
2588 if (offset == 0) {
2589 offset = wrap;
2590 }
2591 offset -= imm;
2592 return offset;
2593 }
2594
2595 DO_VIDUP_ALL(vidup, DO_ADD)
2596 DO_VIWDUP_ALL(viwdup, do_add_wrap)
2597 DO_VIWDUP_ALL(vdwdup, do_sub_wrap)
2598
2599 /*
2600 * Vector comparison.
2601 * P0 bits for non-executed beats (where eci_mask is 0) are unchanged.
2602 * P0 bits for predicated lanes in executed beats (where mask is 0) are 0.
2603 * P0 bits otherwise are updated with the results of the comparisons.
2604 * We must also keep unchanged the MASK fields at the top of v7m.vpr.
2605 */
2606 #define DO_VCMP(OP, ESIZE, TYPE, FN) \
2607 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, void *vm) \
2608 { \
2609 TYPE *n = vn, *m = vm; \
2610 uint16_t mask = mve_element_mask(env); \
2611 uint16_t eci_mask = mve_eci_mask(env); \
2612 uint16_t beatpred = 0; \
2613 uint16_t emask = MAKE_64BIT_MASK(0, ESIZE); \
2614 unsigned e; \
2615 for (e = 0; e < 16 / ESIZE; e++) { \
2616 bool r = FN(n[H##ESIZE(e)], m[H##ESIZE(e)]); \
2617 /* Comparison sets 0/1 bits for each byte in the element */ \
2618 beatpred |= r * emask; \
2619 emask <<= ESIZE; \
2620 } \
2621 beatpred &= mask; \
2622 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | \
2623 (beatpred & eci_mask); \
2624 mve_advance_vpt(env); \
2625 }
2626
2627 #define DO_VCMP_SCALAR(OP, ESIZE, TYPE, FN) \
2628 void HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \
2629 uint32_t rm) \
2630 { \
2631 TYPE *n = vn; \
2632 uint16_t mask = mve_element_mask(env); \
2633 uint16_t eci_mask = mve_eci_mask(env); \
2634 uint16_t beatpred = 0; \
2635 uint16_t emask = MAKE_64BIT_MASK(0, ESIZE); \
2636 unsigned e; \
2637 for (e = 0; e < 16 / ESIZE; e++) { \
2638 bool r = FN(n[H##ESIZE(e)], (TYPE)rm); \
2639 /* Comparison sets 0/1 bits for each byte in the element */ \
2640 beatpred |= r * emask; \
2641 emask <<= ESIZE; \
2642 } \
2643 beatpred &= mask; \
2644 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | \
2645 (beatpred & eci_mask); \
2646 mve_advance_vpt(env); \
2647 }
2648
2649 #define DO_VCMP_S(OP, FN) \
2650 DO_VCMP(OP##b, 1, int8_t, FN) \
2651 DO_VCMP(OP##h, 2, int16_t, FN) \
2652 DO_VCMP(OP##w, 4, int32_t, FN) \
2653 DO_VCMP_SCALAR(OP##_scalarb, 1, int8_t, FN) \
2654 DO_VCMP_SCALAR(OP##_scalarh, 2, int16_t, FN) \
2655 DO_VCMP_SCALAR(OP##_scalarw, 4, int32_t, FN)
2656
2657 #define DO_VCMP_U(OP, FN) \
2658 DO_VCMP(OP##b, 1, uint8_t, FN) \
2659 DO_VCMP(OP##h, 2, uint16_t, FN) \
2660 DO_VCMP(OP##w, 4, uint32_t, FN) \
2661 DO_VCMP_SCALAR(OP##_scalarb, 1, uint8_t, FN) \
2662 DO_VCMP_SCALAR(OP##_scalarh, 2, uint16_t, FN) \
2663 DO_VCMP_SCALAR(OP##_scalarw, 4, uint32_t, FN)
2664
2665 #define DO_EQ(N, M) ((N) == (M))
2666 #define DO_NE(N, M) ((N) != (M))
2667 #define DO_EQ(N, M) ((N) == (M))
2668 #define DO_EQ(N, M) ((N) == (M))
2669 #define DO_GE(N, M) ((N) >= (M))
2670 #define DO_LT(N, M) ((N) < (M))
2671 #define DO_GT(N, M) ((N) > (M))
2672 #define DO_LE(N, M) ((N) <= (M))
2673
2674 DO_VCMP_U(vcmpeq, DO_EQ)
2675 DO_VCMP_U(vcmpne, DO_NE)
2676 DO_VCMP_U(vcmpcs, DO_GE)
2677 DO_VCMP_U(vcmphi, DO_GT)
2678 DO_VCMP_S(vcmpge, DO_GE)
2679 DO_VCMP_S(vcmplt, DO_LT)
2680 DO_VCMP_S(vcmpgt, DO_GT)
2681 DO_VCMP_S(vcmple, DO_LE)
2682
2683 void HELPER(mve_vpsel)(CPUARMState *env, void *vd, void *vn, void *vm)
2684 {
2685 /*
2686 * Qd[n] = VPR.P0[n] ? Qn[n] : Qm[n]
2687 * but note that whether bytes are written to Qd is still subject
2688 * to (all forms of) predication in the usual way.
2689 */
2690 uint64_t *d = vd, *n = vn, *m = vm;
2691 uint16_t mask = mve_element_mask(env);
2692 uint16_t p0 = FIELD_EX32(env->v7m.vpr, V7M_VPR, P0);
2693 unsigned e;
2694 for (e = 0; e < 16 / 8; e++, mask >>= 8, p0 >>= 8) {
2695 uint64_t r = m[H8(e)];
2696 mergemask(&r, n[H8(e)], p0);
2697 mergemask(&d[H8(e)], r, mask);
2698 }
2699 mve_advance_vpt(env);
2700 }
2701
2702 void HELPER(mve_vpnot)(CPUARMState *env)
2703 {
2704 /*
2705 * P0 bits for unexecuted beats (where eci_mask is 0) are unchanged.
2706 * P0 bits for predicated lanes in executed bits (where mask is 0) are 0.
2707 * P0 bits otherwise are inverted.
2708 * (This is the same logic as VCMP.)
2709 * This insn is itself subject to predication and to beat-wise execution,
2710 * and after it executes VPT state advances in the usual way.
2711 */
2712 uint16_t mask = mve_element_mask(env);
2713 uint16_t eci_mask = mve_eci_mask(env);
2714 uint16_t beatpred = ~env->v7m.vpr & mask;
2715 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | (beatpred & eci_mask);
2716 mve_advance_vpt(env);
2717 }
2718
2719 /*
2720 * VCTP: P0 unexecuted bits unchanged, predicated bits zeroed,
2721 * otherwise set according to value of Rn. The calculation of
2722 * newmask here works in the same way as the calculation of the
2723 * ltpmask in mve_element_mask(), but we have pre-calculated
2724 * the masklen in the generated code.
2725 */
2726 void HELPER(mve_vctp)(CPUARMState *env, uint32_t masklen)
2727 {
2728 uint16_t mask = mve_element_mask(env);
2729 uint16_t eci_mask = mve_eci_mask(env);
2730 uint16_t newmask;
2731
2732 assert(masklen <= 16);
2733 newmask = masklen ? MAKE_64BIT_MASK(0, masklen) : 0;
2734 newmask &= mask;
2735 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | (newmask & eci_mask);
2736 mve_advance_vpt(env);
2737 }
2738
2739 #define DO_1OP_SAT(OP, ESIZE, TYPE, FN) \
2740 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \
2741 { \
2742 TYPE *d = vd, *m = vm; \
2743 uint16_t mask = mve_element_mask(env); \
2744 unsigned e; \
2745 bool qc = false; \
2746 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
2747 bool sat = false; \
2748 mergemask(&d[H##ESIZE(e)], FN(m[H##ESIZE(e)], &sat), mask); \
2749 qc |= sat & mask & 1; \
2750 } \
2751 if (qc) { \
2752 env->vfp.qc[0] = qc; \
2753 } \
2754 mve_advance_vpt(env); \
2755 }
2756
2757 #define DO_VQABS_B(N, SATP) \
2758 do_sat_bhs(DO_ABS((int64_t)N), INT8_MIN, INT8_MAX, SATP)
2759 #define DO_VQABS_H(N, SATP) \
2760 do_sat_bhs(DO_ABS((int64_t)N), INT16_MIN, INT16_MAX, SATP)
2761 #define DO_VQABS_W(N, SATP) \
2762 do_sat_bhs(DO_ABS((int64_t)N), INT32_MIN, INT32_MAX, SATP)
2763
2764 #define DO_VQNEG_B(N, SATP) do_sat_bhs(-(int64_t)N, INT8_MIN, INT8_MAX, SATP)
2765 #define DO_VQNEG_H(N, SATP) do_sat_bhs(-(int64_t)N, INT16_MIN, INT16_MAX, SATP)
2766 #define DO_VQNEG_W(N, SATP) do_sat_bhs(-(int64_t)N, INT32_MIN, INT32_MAX, SATP)
2767
2768 DO_1OP_SAT(vqabsb, 1, int8_t, DO_VQABS_B)
2769 DO_1OP_SAT(vqabsh, 2, int16_t, DO_VQABS_H)
2770 DO_1OP_SAT(vqabsw, 4, int32_t, DO_VQABS_W)
2771
2772 DO_1OP_SAT(vqnegb, 1, int8_t, DO_VQNEG_B)
2773 DO_1OP_SAT(vqnegh, 2, int16_t, DO_VQNEG_H)
2774 DO_1OP_SAT(vqnegw, 4, int32_t, DO_VQNEG_W)
2775
2776 /*
2777 * VMAXA, VMINA: vd is unsigned; vm is signed, and we take its
2778 * absolute value; we then do an unsigned comparison.
2779 */
2780 #define DO_VMAXMINA(OP, ESIZE, STYPE, UTYPE, FN) \
2781 void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \
2782 { \
2783 UTYPE *d = vd; \
2784 STYPE *m = vm; \
2785 uint16_t mask = mve_element_mask(env); \
2786 unsigned e; \
2787 for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
2788 UTYPE r = DO_ABS(m[H##ESIZE(e)]); \
2789 r = FN(d[H##ESIZE(e)], r); \
2790 mergemask(&d[H##ESIZE(e)], r, mask); \
2791 } \
2792 mve_advance_vpt(env); \
2793 }
2794
2795 DO_VMAXMINA(vmaxab, 1, int8_t, uint8_t, DO_MAX)
2796 DO_VMAXMINA(vmaxah, 2, int16_t, uint16_t, DO_MAX)
2797 DO_VMAXMINA(vmaxaw, 4, int32_t, uint32_t, DO_MAX)
2798 DO_VMAXMINA(vminab, 1, int8_t, uint8_t, DO_MIN)
2799 DO_VMAXMINA(vminah, 2, int16_t, uint16_t, DO_MIN)
2800 DO_VMAXMINA(vminaw, 4, int32_t, uint32_t, DO_MIN)
Random patches