target/avr/helper.c

   1 /*
   2  * QEMU AVR CPU helpers
   3  *
   4  * Copyright (c) 2016-2020 Michael Rolnik
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "cpu.h"
  23 #include "hw/core/tcg-cpu-ops.h"
  24 #include "exec/exec-all.h"
  25 #include "exec/address-spaces.h"
  26 #include "exec/helper-proto.h"
  27
  28 bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
  29 {
  30     bool ret = false;
  31     CPUClass *cc = CPU_GET_CLASS(cs);
  32     AVRCPU *cpu = AVR_CPU(cs);
  33     CPUAVRState *env = &cpu->env;
  34
  35     if (interrupt_request & CPU_INTERRUPT_RESET) {
  36         if (cpu_interrupts_enabled(env)) {
  37             cs->exception_index = EXCP_RESET;
  38             cc->tcg_ops->do_interrupt(cs);
  39
  40             cs->interrupt_request &= ~CPU_INTERRUPT_RESET;
  41
  42             ret = true;
  43         }
  44     }
  45     if (interrupt_request & CPU_INTERRUPT_HARD) {
  46         if (cpu_interrupts_enabled(env) && env->intsrc != 0) {
  47             int index = ctz32(env->intsrc);
  48             cs->exception_index = EXCP_INT(index);
  49             cc->tcg_ops->do_interrupt(cs);
  50
  51             env->intsrc &= env->intsrc - 1; /* clear the interrupt */
  52             if (!env->intsrc) {
  53                 cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
  54             }
  55
  56             ret = true;
  57         }
  58     }
  59     return ret;
  60 }
  61
  62 void avr_cpu_do_interrupt(CPUState *cs)
  63 {
  64     AVRCPU *cpu = AVR_CPU(cs);
  65     CPUAVRState *env = &cpu->env;
  66
  67     uint32_t ret = env->pc_w;
  68     int vector = 0;
  69     int size = avr_feature(env, AVR_FEATURE_JMP_CALL) ? 2 : 1;
  70     int base = 0;
  71
  72     if (cs->exception_index == EXCP_RESET) {
  73         vector = 0;
  74     } else if (env->intsrc != 0) {
  75         vector = ctz32(env->intsrc) + 1;
  76     }
  77
  78     if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) {
  79         cpu_stb_data(env, env->sp--, (ret & 0x0000ff));
  80         cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8);
  81         cpu_stb_data(env, env->sp--, (ret & 0xff0000) >> 16);
  82     } else if (avr_feature(env, AVR_FEATURE_2_BYTE_PC)) {
  83         cpu_stb_data(env, env->sp--, (ret & 0x0000ff));
  84         cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8);
  85     } else {
  86         cpu_stb_data(env, env->sp--, (ret & 0x0000ff));
  87     }
  88
  89     env->pc_w = base + vector * size;
  90     env->sregI = 0; /* clear Global Interrupt Flag */
  91
  92     cs->exception_index = -1;
  93 }
  94
  95 int avr_cpu_memory_rw_debug(CPUState *cs, vaddr addr, uint8_t *buf,
  96                             int len, bool is_write)
  97 {
  98     return cpu_memory_rw_debug(cs, addr, buf, len, is_write);
  99 }
 100
 101 hwaddr avr_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 102 {
 103     return addr; /* I assume 1:1 address correspondence */
 104 }
 105
 106 bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 107                       MMUAccessType access_type, int mmu_idx,
 108                       bool probe, uintptr_t retaddr)
 109 {
 110     int prot = 0;
 111     MemTxAttrs attrs = {};
 112     uint32_t paddr;
 113
 114     address &= TARGET_PAGE_MASK;
 115
 116     if (mmu_idx == MMU_CODE_IDX) {
 117         /* access to code in flash */
 118         paddr = OFFSET_CODE + address;
 119         prot = PAGE_READ | PAGE_EXEC;
 120         if (paddr + TARGET_PAGE_SIZE > OFFSET_DATA) {
 121             error_report("execution left flash memory");
 122             abort();
 123         }
 124     } else if (address < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) {
 125         /*
 126          * access to CPU registers, exit and rebuilt this TB to use full access
 127          * incase it touches specially handled registers like SREG or SP
 128          */
 129         AVRCPU *cpu = AVR_CPU(cs);
 130         CPUAVRState *env = &cpu->env;
 131         env->fullacc = 1;
 132         cpu_loop_exit_restore(cs, retaddr);
 133     } else {
 134         /* access to memory. nothing special */
 135         paddr = OFFSET_DATA + address;
 136         prot = PAGE_READ | PAGE_WRITE;
 137     }
 138
 139     tlb_set_page_with_attrs(cs, address, paddr, attrs, prot,
 140                             mmu_idx, TARGET_PAGE_SIZE);
 141
 142     return true;
 143 }
 144
 145 /*
 146  *  helpers
 147  */
 148
 149 void helper_sleep(CPUAVRState *env)
 150 {
 151     CPUState *cs = env_cpu(env);
 152
 153     cs->exception_index = EXCP_HLT;
 154     cpu_loop_exit(cs);
 155 }
 156
 157 void helper_unsupported(CPUAVRState *env)
 158 {
 159     CPUState *cs = env_cpu(env);
 160
 161     /*
 162      *  I count not find what happens on the real platform, so
 163      *  it's EXCP_DEBUG for meanwhile
 164      */
 165     cs->exception_index = EXCP_DEBUG;
 166     if (qemu_loglevel_mask(LOG_UNIMP)) {
 167         qemu_log("UNSUPPORTED\n");
 168         cpu_dump_state(cs, stderr, 0);
 169     }
 170     cpu_loop_exit(cs);
 171 }
 172
 173 void helper_debug(CPUAVRState *env)
 174 {
 175     CPUState *cs = env_cpu(env);
 176
 177     cs->exception_index = EXCP_DEBUG;
 178     cpu_loop_exit(cs);
 179 }
 180
 181 void helper_break(CPUAVRState *env)
 182 {
 183     CPUState *cs = env_cpu(env);
 184
 185     cs->exception_index = EXCP_DEBUG;
 186     cpu_loop_exit(cs);
 187 }
 188
 189 void helper_wdr(CPUAVRState *env)
 190 {
 191     qemu_log_mask(LOG_UNIMP, "WDG reset (not implemented)\n");
 192 }
 193
 194 /*
 195  * This function implements IN instruction
 196  *
 197  * It does the following
 198  * a.  if an IO register belongs to CPU, its value is read and returned
 199  * b.  otherwise io address is translated to mem address and physical memory
 200  *     is read.
 201  * c.  it caches the value for sake of SBI, SBIC, SBIS & CBI implementation
 202  *
 203  */
 204 target_ulong helper_inb(CPUAVRState *env, uint32_t port)
 205 {
 206     target_ulong data = 0;
 207
 208     switch (port) {
 209     case 0x38: /* RAMPD */
 210         data = 0xff & (env->rampD >> 16);
 211         break;
 212     case 0x39: /* RAMPX */
 213         data = 0xff & (env->rampX >> 16);
 214         break;
 215     case 0x3a: /* RAMPY */
 216         data = 0xff & (env->rampY >> 16);
 217         break;
 218     case 0x3b: /* RAMPZ */
 219         data = 0xff & (env->rampZ >> 16);
 220         break;
 221     case 0x3c: /* EIND */
 222         data = 0xff & (env->eind >> 16);
 223         break;
 224     case 0x3d: /* SPL */
 225         data = env->sp & 0x00ff;
 226         break;
 227     case 0x3e: /* SPH */
 228         data = env->sp >> 8;
 229         break;
 230     case 0x3f: /* SREG */
 231         data = cpu_get_sreg(env);
 232         break;
 233     default:
 234         /* not a special register, pass to normal memory access */
 235         data = address_space_ldub(&address_space_memory,
 236                                   OFFSET_IO_REGISTERS + port,
 237                                   MEMTXATTRS_UNSPECIFIED, NULL);
 238     }
 239
 240     return data;
 241 }
 242
 243 /*
 244  *  This function implements OUT instruction
 245  *
 246  *  It does the following
 247  *  a.  if an IO register belongs to CPU, its value is written into the register
 248  *  b.  otherwise io address is translated to mem address and physical memory
 249  *      is written.
 250  *  c.  it caches the value for sake of SBI, SBIC, SBIS & CBI implementation
 251  *
 252  */
 253 void helper_outb(CPUAVRState *env, uint32_t port, uint32_t data)
 254 {
 255     data &= 0x000000ff;
 256
 257     switch (port) {
 258     case 0x38: /* RAMPD */
 259         if (avr_feature(env, AVR_FEATURE_RAMPD)) {
 260             env->rampD = (data & 0xff) << 16;
 261         }
 262         break;
 263     case 0x39: /* RAMPX */
 264         if (avr_feature(env, AVR_FEATURE_RAMPX)) {
 265             env->rampX = (data & 0xff) << 16;
 266         }
 267         break;
 268     case 0x3a: /* RAMPY */
 269         if (avr_feature(env, AVR_FEATURE_RAMPY)) {
 270             env->rampY = (data & 0xff) << 16;
 271         }
 272         break;
 273     case 0x3b: /* RAMPZ */
 274         if (avr_feature(env, AVR_FEATURE_RAMPZ)) {
 275             env->rampZ = (data & 0xff) << 16;
 276         }
 277         break;
 278     case 0x3c: /* EIDN */
 279         env->eind = (data & 0xff) << 16;
 280         break;
 281     case 0x3d: /* SPL */
 282         env->sp = (env->sp & 0xff00) | (data);
 283         break;
 284     case 0x3e: /* SPH */
 285         if (avr_feature(env, AVR_FEATURE_2_BYTE_SP)) {
 286             env->sp = (env->sp & 0x00ff) | (data << 8);
 287         }
 288         break;
 289     case 0x3f: /* SREG */
 290         cpu_set_sreg(env, data);
 291         break;
 292     default:
 293         /* not a special register, pass to normal memory access */
 294         address_space_stb(&address_space_memory, OFFSET_IO_REGISTERS + port,
 295                           data, MEMTXATTRS_UNSPECIFIED, NULL);
 296     }
 297 }
 298
 299 /*
 300  *  this function implements LD instruction when there is a possibility to read
 301  *  from a CPU register
 302  */
 303 target_ulong helper_fullrd(CPUAVRState *env, uint32_t addr)
 304 {
 305     uint8_t data;
 306
 307     env->fullacc = false;
 308
 309     if (addr < NUMBER_OF_CPU_REGISTERS) {
 310         /* CPU registers */
 311         data = env->r[addr];
 312     } else if (addr < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) {
 313         /* IO registers */
 314         data = helper_inb(env, addr - NUMBER_OF_CPU_REGISTERS);
 315     } else {
 316         /* memory */
 317         data = address_space_ldub(&address_space_memory, OFFSET_DATA + addr,
 318                                   MEMTXATTRS_UNSPECIFIED, NULL);
 319     }
 320     return data;
 321 }
 322
 323 /*
 324  *  this function implements ST instruction when there is a possibility to write
 325  *  into a CPU register
 326  */
 327 void helper_fullwr(CPUAVRState *env, uint32_t data, uint32_t addr)
 328 {
 329     env->fullacc = false;
 330
 331     /* Following logic assumes this: */
 332     assert(OFFSET_CPU_REGISTERS == OFFSET_DATA);
 333     assert(OFFSET_IO_REGISTERS == OFFSET_CPU_REGISTERS +
 334                                   NUMBER_OF_CPU_REGISTERS);
 335
 336     if (addr < NUMBER_OF_CPU_REGISTERS) {
 337         /* CPU registers */
 338         env->r[addr] = data;
 339     } else if (addr < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) {
 340         /* IO registers */
 341         helper_outb(env, addr - NUMBER_OF_CPU_REGISTERS, data);
 342     } else {
 343         /* memory */
 344         address_space_stb(&address_space_memory, OFFSET_DATA + addr, data,
 345                           MEMTXATTRS_UNSPECIFIED, NULL);
 346     }
 347 }