4 * Altivec/VMX translation
7 /*** Altivec vector extension ***/
8 /* Altivec registers moves */
10 static inline TCGv_ptr
gen_avr_ptr(int reg
)
12 TCGv_ptr r
= tcg_temp_new_ptr();
13 tcg_gen_addi_ptr(r
, cpu_env
, avr_full_offset(reg
));
17 #define GEN_VR_LDX(name, opc2, opc3) \
18 static void glue(gen_, name)(DisasContext *ctx) \
22 if (unlikely(!ctx->altivec_enabled)) { \
23 gen_exception(ctx, POWERPC_EXCP_VPU); \
26 gen_set_access_type(ctx, ACCESS_INT); \
27 avr = tcg_temp_new_i64(); \
28 EA = tcg_temp_new(); \
29 gen_addr_reg_index(ctx, EA); \
30 tcg_gen_andi_tl(EA, EA, ~0xf); \
32 * We only need to swap high and low halves. gen_qemu_ld64_i64 \
33 * does necessary 64-bit byteswap already. \
36 gen_qemu_ld64_i64(ctx, avr, EA); \
37 set_avr64(rD(ctx->opcode), avr, false); \
38 tcg_gen_addi_tl(EA, EA, 8); \
39 gen_qemu_ld64_i64(ctx, avr, EA); \
40 set_avr64(rD(ctx->opcode), avr, true); \
42 gen_qemu_ld64_i64(ctx, avr, EA); \
43 set_avr64(rD(ctx->opcode), avr, true); \
44 tcg_gen_addi_tl(EA, EA, 8); \
45 gen_qemu_ld64_i64(ctx, avr, EA); \
46 set_avr64(rD(ctx->opcode), avr, false); \
49 tcg_temp_free_i64(avr); \
52 #define GEN_VR_STX(name, opc2, opc3) \
53 static void gen_st##name(DisasContext *ctx) \
57 if (unlikely(!ctx->altivec_enabled)) { \
58 gen_exception(ctx, POWERPC_EXCP_VPU); \
61 gen_set_access_type(ctx, ACCESS_INT); \
62 avr = tcg_temp_new_i64(); \
63 EA = tcg_temp_new(); \
64 gen_addr_reg_index(ctx, EA); \
65 tcg_gen_andi_tl(EA, EA, ~0xf); \
67 * We only need to swap high and low halves. gen_qemu_st64_i64 \
68 * does necessary 64-bit byteswap already. \
71 get_avr64(avr, rD(ctx->opcode), false); \
72 gen_qemu_st64_i64(ctx, avr, EA); \
73 tcg_gen_addi_tl(EA, EA, 8); \
74 get_avr64(avr, rD(ctx->opcode), true); \
75 gen_qemu_st64_i64(ctx, avr, EA); \
77 get_avr64(avr, rD(ctx->opcode), true); \
78 gen_qemu_st64_i64(ctx, avr, EA); \
79 tcg_gen_addi_tl(EA, EA, 8); \
80 get_avr64(avr, rD(ctx->opcode), false); \
81 gen_qemu_st64_i64(ctx, avr, EA); \
84 tcg_temp_free_i64(avr); \
87 #define GEN_VR_LVE(name, opc2, opc3, size) \
88 static void gen_lve##name(DisasContext *ctx) \
92 if (unlikely(!ctx->altivec_enabled)) { \
93 gen_exception(ctx, POWERPC_EXCP_VPU); \
96 gen_set_access_type(ctx, ACCESS_INT); \
97 EA = tcg_temp_new(); \
98 gen_addr_reg_index(ctx, EA); \
100 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
102 rs = gen_avr_ptr(rS(ctx->opcode)); \
103 gen_helper_lve##name(cpu_env, rs, EA); \
105 tcg_temp_free_ptr(rs); \
108 #define GEN_VR_STVE(name, opc2, opc3, size) \
109 static void gen_stve##name(DisasContext *ctx) \
113 if (unlikely(!ctx->altivec_enabled)) { \
114 gen_exception(ctx, POWERPC_EXCP_VPU); \
117 gen_set_access_type(ctx, ACCESS_INT); \
118 EA = tcg_temp_new(); \
119 gen_addr_reg_index(ctx, EA); \
121 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
123 rs = gen_avr_ptr(rS(ctx->opcode)); \
124 gen_helper_stve##name(cpu_env, rs, EA); \
126 tcg_temp_free_ptr(rs); \
129 GEN_VR_LDX(lvx
, 0x07, 0x03);
130 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
131 GEN_VR_LDX(lvxl
, 0x07, 0x0B);
133 GEN_VR_LVE(bx
, 0x07, 0x00, 1);
134 GEN_VR_LVE(hx
, 0x07, 0x01, 2);
135 GEN_VR_LVE(wx
, 0x07, 0x02, 4);
137 GEN_VR_STX(svx
, 0x07, 0x07);
138 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
139 GEN_VR_STX(svxl
, 0x07, 0x0F);
141 GEN_VR_STVE(bx
, 0x07, 0x04, 1);
142 GEN_VR_STVE(hx
, 0x07, 0x05, 2);
143 GEN_VR_STVE(wx
, 0x07, 0x06, 4);
145 static void gen_mfvscr(DisasContext
*ctx
)
149 if (unlikely(!ctx
->altivec_enabled
)) {
150 gen_exception(ctx
, POWERPC_EXCP_VPU
);
153 avr
= tcg_temp_new_i64();
154 tcg_gen_movi_i64(avr
, 0);
155 set_avr64(rD(ctx
->opcode
), avr
, true);
156 t
= tcg_temp_new_i32();
157 gen_helper_mfvscr(t
, cpu_env
);
158 tcg_gen_extu_i32_i64(avr
, t
);
159 set_avr64(rD(ctx
->opcode
), avr
, false);
160 tcg_temp_free_i32(t
);
161 tcg_temp_free_i64(avr
);
164 static void gen_mtvscr(DisasContext
*ctx
)
169 if (unlikely(!ctx
->altivec_enabled
)) {
170 gen_exception(ctx
, POWERPC_EXCP_VPU
);
174 val
= tcg_temp_new_i32();
175 bofs
= avr_full_offset(rB(ctx
->opcode
));
176 #ifdef HOST_WORDS_BIGENDIAN
180 tcg_gen_ld_i32(val
, cpu_env
, bofs
);
181 gen_helper_mtvscr(cpu_env
, val
);
182 tcg_temp_free_i32(val
);
185 #define GEN_VX_VMUL10(name, add_cin, ret_carry) \
186 static void glue(gen_, name)(DisasContext *ctx) \
194 if (unlikely(!ctx->altivec_enabled)) { \
195 gen_exception(ctx, POWERPC_EXCP_VPU); \
199 t0 = tcg_temp_new_i64(); \
200 t1 = tcg_temp_new_i64(); \
201 t2 = tcg_temp_new_i64(); \
202 avr = tcg_temp_new_i64(); \
203 ten = tcg_const_i64(10); \
204 z = tcg_const_i64(0); \
207 get_avr64(avr, rA(ctx->opcode), false); \
208 tcg_gen_mulu2_i64(t0, t1, avr, ten); \
209 get_avr64(avr, rB(ctx->opcode), false); \
210 tcg_gen_andi_i64(t2, avr, 0xF); \
211 tcg_gen_add2_i64(avr, t2, t0, t1, t2, z); \
212 set_avr64(rD(ctx->opcode), avr, false); \
214 get_avr64(avr, rA(ctx->opcode), false); \
215 tcg_gen_mulu2_i64(avr, t2, avr, ten); \
216 set_avr64(rD(ctx->opcode), avr, false); \
220 get_avr64(avr, rA(ctx->opcode), true); \
221 tcg_gen_mulu2_i64(t0, t1, avr, ten); \
222 tcg_gen_add2_i64(t0, avr, t0, t1, t2, z); \
223 set_avr64(rD(ctx->opcode), avr, false); \
224 set_avr64(rD(ctx->opcode), z, true); \
226 get_avr64(avr, rA(ctx->opcode), true); \
227 tcg_gen_mul_i64(t0, avr, ten); \
228 tcg_gen_add_i64(avr, t0, t2); \
229 set_avr64(rD(ctx->opcode), avr, true); \
232 tcg_temp_free_i64(t0); \
233 tcg_temp_free_i64(t1); \
234 tcg_temp_free_i64(t2); \
235 tcg_temp_free_i64(avr); \
236 tcg_temp_free_i64(ten); \
237 tcg_temp_free_i64(z); \
240 GEN_VX_VMUL10(vmul10uq, 0, 0);
241 GEN_VX_VMUL10(vmul10euq
, 1, 0);
242 GEN_VX_VMUL10(vmul10cuq
, 0, 1);
243 GEN_VX_VMUL10(vmul10ecuq
, 1, 1);
245 #define GEN_VXFORM_V(name, vece, tcg_op, opc2, opc3) \
246 static void glue(gen_, name)(DisasContext *ctx) \
248 if (unlikely(!ctx->altivec_enabled)) { \
249 gen_exception(ctx, POWERPC_EXCP_VPU); \
254 avr_full_offset(rD(ctx->opcode)), \
255 avr_full_offset(rA(ctx->opcode)), \
256 avr_full_offset(rB(ctx->opcode)), \
260 /* Logical operations */
261 GEN_VXFORM_V(vand
, MO_64
, tcg_gen_gvec_and
, 2, 16);
262 GEN_VXFORM_V(vandc
, MO_64
, tcg_gen_gvec_andc
, 2, 17);
263 GEN_VXFORM_V(vor
, MO_64
, tcg_gen_gvec_or
, 2, 18);
264 GEN_VXFORM_V(vxor
, MO_64
, tcg_gen_gvec_xor
, 2, 19);
265 GEN_VXFORM_V(vnor
, MO_64
, tcg_gen_gvec_nor
, 2, 20);
266 GEN_VXFORM_V(veqv
, MO_64
, tcg_gen_gvec_eqv
, 2, 26);
267 GEN_VXFORM_V(vnand
, MO_64
, tcg_gen_gvec_nand
, 2, 22);
268 GEN_VXFORM_V(vorc
, MO_64
, tcg_gen_gvec_orc
, 2, 21);
270 #define GEN_VXFORM(name, opc2, opc3) \
271 static void glue(gen_, name)(DisasContext *ctx) \
273 TCGv_ptr ra, rb, rd; \
274 if (unlikely(!ctx->altivec_enabled)) { \
275 gen_exception(ctx, POWERPC_EXCP_VPU); \
278 ra = gen_avr_ptr(rA(ctx->opcode)); \
279 rb = gen_avr_ptr(rB(ctx->opcode)); \
280 rd = gen_avr_ptr(rD(ctx->opcode)); \
281 gen_helper_##name(rd, ra, rb); \
282 tcg_temp_free_ptr(ra); \
283 tcg_temp_free_ptr(rb); \
284 tcg_temp_free_ptr(rd); \
287 #define GEN_VXFORM_TRANS(name, opc2, opc3) \
288 static void glue(gen_, name)(DisasContext *ctx) \
290 if (unlikely(!ctx->altivec_enabled)) { \
291 gen_exception(ctx, POWERPC_EXCP_VPU); \
297 #define GEN_VXFORM_ENV(name, opc2, opc3) \
298 static void glue(gen_, name)(DisasContext *ctx) \
300 TCGv_ptr ra, rb, rd; \
301 if (unlikely(!ctx->altivec_enabled)) { \
302 gen_exception(ctx, POWERPC_EXCP_VPU); \
305 ra = gen_avr_ptr(rA(ctx->opcode)); \
306 rb = gen_avr_ptr(rB(ctx->opcode)); \
307 rd = gen_avr_ptr(rD(ctx->opcode)); \
308 gen_helper_##name(cpu_env, rd, ra, rb); \
309 tcg_temp_free_ptr(ra); \
310 tcg_temp_free_ptr(rb); \
311 tcg_temp_free_ptr(rd); \
314 #define GEN_VXFORM3(name, opc2, opc3) \
315 static void glue(gen_, name)(DisasContext *ctx) \
317 TCGv_ptr ra, rb, rc, rd; \
318 if (unlikely(!ctx->altivec_enabled)) { \
319 gen_exception(ctx, POWERPC_EXCP_VPU); \
322 ra = gen_avr_ptr(rA(ctx->opcode)); \
323 rb = gen_avr_ptr(rB(ctx->opcode)); \
324 rc = gen_avr_ptr(rC(ctx->opcode)); \
325 rd = gen_avr_ptr(rD(ctx->opcode)); \
326 gen_helper_##name(rd, ra, rb, rc); \
327 tcg_temp_free_ptr(ra); \
328 tcg_temp_free_ptr(rb); \
329 tcg_temp_free_ptr(rc); \
330 tcg_temp_free_ptr(rd); \
334 * Support for Altivec instruction pairs that use bit 31 (Rc) as
335 * an opcode bit. In general, these pairs come from different
336 * versions of the ISA, so we must also support a pair of flags for
339 #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
340 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
342 if ((Rc(ctx->opcode) == 0) && \
343 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
345 } else if ((Rc(ctx->opcode) == 1) && \
346 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
349 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
354 * We use this macro if one instruction is realized with direct
355 * translation, and second one with helper.
357 #define GEN_VXFORM_TRANS_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1)\
358 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
360 if ((Rc(ctx->opcode) == 0) && \
361 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
362 if (unlikely(!ctx->altivec_enabled)) { \
363 gen_exception(ctx, POWERPC_EXCP_VPU); \
366 trans_##name0(ctx); \
367 } else if ((Rc(ctx->opcode) == 1) && \
368 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
371 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
375 /* Adds support to provide invalid mask */
376 #define GEN_VXFORM_DUAL_EXT(name0, flg0, flg2_0, inval0, \
377 name1, flg1, flg2_1, inval1) \
378 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
380 if ((Rc(ctx->opcode) == 0) && \
381 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0)) && \
382 !(ctx->opcode & inval0)) { \
384 } else if ((Rc(ctx->opcode) == 1) && \
385 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1)) && \
386 !(ctx->opcode & inval1)) { \
389 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
393 #define GEN_VXFORM_HETRO(name, opc2, opc3) \
394 static void glue(gen_, name)(DisasContext *ctx) \
397 if (unlikely(!ctx->altivec_enabled)) { \
398 gen_exception(ctx, POWERPC_EXCP_VPU); \
401 rb = gen_avr_ptr(rB(ctx->opcode)); \
402 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], rb); \
403 tcg_temp_free_ptr(rb); \
406 GEN_VXFORM_V(vaddubm
, MO_8
, tcg_gen_gvec_add
, 0, 0);
407 GEN_VXFORM_DUAL_EXT(vaddubm
, PPC_ALTIVEC
, PPC_NONE
, 0, \
408 vmul10cuq
, PPC_NONE
, PPC2_ISA300
, 0x0000F800)
409 GEN_VXFORM_V(vadduhm
, MO_16
, tcg_gen_gvec_add
, 0, 1);
410 GEN_VXFORM_DUAL(vadduhm
, PPC_ALTIVEC
, PPC_NONE
, \
411 vmul10ecuq
, PPC_NONE
, PPC2_ISA300
)
412 GEN_VXFORM_V(vadduwm
, MO_32
, tcg_gen_gvec_add
, 0, 2);
413 GEN_VXFORM_V(vaddudm
, MO_64
, tcg_gen_gvec_add
, 0, 3);
414 GEN_VXFORM_V(vsububm
, MO_8
, tcg_gen_gvec_sub
, 0, 16);
415 GEN_VXFORM_V(vsubuhm
, MO_16
, tcg_gen_gvec_sub
, 0, 17);
416 GEN_VXFORM_V(vsubuwm
, MO_32
, tcg_gen_gvec_sub
, 0, 18);
417 GEN_VXFORM_V(vsubudm
, MO_64
, tcg_gen_gvec_sub
, 0, 19);
418 GEN_VXFORM_V(vmaxub
, MO_8
, tcg_gen_gvec_umax
, 1, 0);
419 GEN_VXFORM_V(vmaxuh
, MO_16
, tcg_gen_gvec_umax
, 1, 1);
420 GEN_VXFORM_V(vmaxuw
, MO_32
, tcg_gen_gvec_umax
, 1, 2);
421 GEN_VXFORM_V(vmaxud
, MO_64
, tcg_gen_gvec_umax
, 1, 3);
422 GEN_VXFORM_V(vmaxsb
, MO_8
, tcg_gen_gvec_smax
, 1, 4);
423 GEN_VXFORM_V(vmaxsh
, MO_16
, tcg_gen_gvec_smax
, 1, 5);
424 GEN_VXFORM_V(vmaxsw
, MO_32
, tcg_gen_gvec_smax
, 1, 6);
425 GEN_VXFORM_V(vmaxsd
, MO_64
, tcg_gen_gvec_smax
, 1, 7);
426 GEN_VXFORM_V(vminub
, MO_8
, tcg_gen_gvec_umin
, 1, 8);
427 GEN_VXFORM_V(vminuh
, MO_16
, tcg_gen_gvec_umin
, 1, 9);
428 GEN_VXFORM_V(vminuw
, MO_32
, tcg_gen_gvec_umin
, 1, 10);
429 GEN_VXFORM_V(vminud
, MO_64
, tcg_gen_gvec_umin
, 1, 11);
430 GEN_VXFORM_V(vminsb
, MO_8
, tcg_gen_gvec_smin
, 1, 12);
431 GEN_VXFORM_V(vminsh
, MO_16
, tcg_gen_gvec_smin
, 1, 13);
432 GEN_VXFORM_V(vminsw
, MO_32
, tcg_gen_gvec_smin
, 1, 14);
433 GEN_VXFORM_V(vminsd
, MO_64
, tcg_gen_gvec_smin
, 1, 15);
434 GEN_VXFORM(vavgub
, 1, 16);
435 GEN_VXFORM(vabsdub
, 1, 16);
436 GEN_VXFORM_DUAL(vavgub
, PPC_ALTIVEC
, PPC_NONE
, \
437 vabsdub
, PPC_NONE
, PPC2_ISA300
)
438 GEN_VXFORM(vavguh
, 1, 17);
439 GEN_VXFORM(vabsduh
, 1, 17);
440 GEN_VXFORM_DUAL(vavguh
, PPC_ALTIVEC
, PPC_NONE
, \
441 vabsduh
, PPC_NONE
, PPC2_ISA300
)
442 GEN_VXFORM(vavguw
, 1, 18);
443 GEN_VXFORM(vabsduw
, 1, 18);
444 GEN_VXFORM_DUAL(vavguw
, PPC_ALTIVEC
, PPC_NONE
, \
445 vabsduw
, PPC_NONE
, PPC2_ISA300
)
446 GEN_VXFORM(vavgsb
, 1, 20);
447 GEN_VXFORM(vavgsh
, 1, 21);
448 GEN_VXFORM(vavgsw
, 1, 22);
449 GEN_VXFORM(vmrghb
, 6, 0);
450 GEN_VXFORM(vmrghh
, 6, 1);
451 GEN_VXFORM(vmrghw
, 6, 2);
452 GEN_VXFORM(vmrglb
, 6, 4);
453 GEN_VXFORM(vmrglh
, 6, 5);
454 GEN_VXFORM(vmrglw
, 6, 6);
456 static void trans_vmrgew(DisasContext
*ctx
)
458 int VT
= rD(ctx
->opcode
);
459 int VA
= rA(ctx
->opcode
);
460 int VB
= rB(ctx
->opcode
);
461 TCGv_i64 tmp
= tcg_temp_new_i64();
462 TCGv_i64 avr
= tcg_temp_new_i64();
464 get_avr64(avr
, VB
, true);
465 tcg_gen_shri_i64(tmp
, avr
, 32);
466 get_avr64(avr
, VA
, true);
467 tcg_gen_deposit_i64(avr
, avr
, tmp
, 0, 32);
468 set_avr64(VT
, avr
, true);
470 get_avr64(avr
, VB
, false);
471 tcg_gen_shri_i64(tmp
, avr
, 32);
472 get_avr64(avr
, VA
, false);
473 tcg_gen_deposit_i64(avr
, avr
, tmp
, 0, 32);
474 set_avr64(VT
, avr
, false);
476 tcg_temp_free_i64(tmp
);
477 tcg_temp_free_i64(avr
);
480 static void trans_vmrgow(DisasContext
*ctx
)
482 int VT
= rD(ctx
->opcode
);
483 int VA
= rA(ctx
->opcode
);
484 int VB
= rB(ctx
->opcode
);
485 TCGv_i64 t0
= tcg_temp_new_i64();
486 TCGv_i64 t1
= tcg_temp_new_i64();
487 TCGv_i64 avr
= tcg_temp_new_i64();
489 get_avr64(t0
, VB
, true);
490 get_avr64(t1
, VA
, true);
491 tcg_gen_deposit_i64(avr
, t0
, t1
, 32, 32);
492 set_avr64(VT
, avr
, true);
494 get_avr64(t0
, VB
, false);
495 get_avr64(t1
, VA
, false);
496 tcg_gen_deposit_i64(avr
, t0
, t1
, 32, 32);
497 set_avr64(VT
, avr
, false);
499 tcg_temp_free_i64(t0
);
500 tcg_temp_free_i64(t1
);
501 tcg_temp_free_i64(avr
);
505 * lvsl VRT,RA,RB - Load Vector for Shift Left
507 * Let the EA be the sum (rA|0)+(rB). Let sh=EA[28–31].
508 * Let X be the 32-byte value 0x00 || 0x01 || 0x02 || ... || 0x1E || 0x1F.
509 * Bytes sh:sh+15 of X are placed into vD.
511 static void trans_lvsl(DisasContext
*ctx
)
513 int VT
= rD(ctx
->opcode
);
514 TCGv_i64 result
= tcg_temp_new_i64();
515 TCGv_i64 sh
= tcg_temp_new_i64();
516 TCGv EA
= tcg_temp_new();
518 /* Get sh(from description) by anding EA with 0xf. */
519 gen_addr_reg_index(ctx
, EA
);
520 tcg_gen_extu_tl_i64(sh
, EA
);
521 tcg_gen_andi_i64(sh
, sh
, 0xfULL
);
524 * Create bytes sh:sh+7 of X(from description) and place them in
525 * higher doubleword of vD.
527 tcg_gen_muli_i64(sh
, sh
, 0x0101010101010101ULL
);
528 tcg_gen_addi_i64(result
, sh
, 0x0001020304050607ull
);
529 set_avr64(VT
, result
, true);
531 * Create bytes sh+8:sh+15 of X(from description) and place them in
532 * lower doubleword of vD.
534 tcg_gen_addi_i64(result
, sh
, 0x08090a0b0c0d0e0fULL
);
535 set_avr64(VT
, result
, false);
537 tcg_temp_free_i64(result
);
538 tcg_temp_free_i64(sh
);
543 * lvsr VRT,RA,RB - Load Vector for Shift Right
545 * Let the EA be the sum (rA|0)+(rB). Let sh=EA[28–31].
546 * Let X be the 32-byte value 0x00 || 0x01 || 0x02 || ... || 0x1E || 0x1F.
547 * Bytes (16-sh):(31-sh) of X are placed into vD.
549 static void trans_lvsr(DisasContext
*ctx
)
551 int VT
= rD(ctx
->opcode
);
552 TCGv_i64 result
= tcg_temp_new_i64();
553 TCGv_i64 sh
= tcg_temp_new_i64();
554 TCGv EA
= tcg_temp_new();
557 /* Get sh(from description) by anding EA with 0xf. */
558 gen_addr_reg_index(ctx
, EA
);
559 tcg_gen_extu_tl_i64(sh
, EA
);
560 tcg_gen_andi_i64(sh
, sh
, 0xfULL
);
563 * Create bytes (16-sh):(23-sh) of X(from description) and place them in
564 * higher doubleword of vD.
566 tcg_gen_muli_i64(sh
, sh
, 0x0101010101010101ULL
);
567 tcg_gen_subfi_i64(result
, 0x1011121314151617ULL
, sh
);
568 set_avr64(VT
, result
, true);
570 * Create bytes (24-sh):(32-sh) of X(from description) and place them in
571 * lower doubleword of vD.
573 tcg_gen_subfi_i64(result
, 0x18191a1b1c1d1e1fULL
, sh
);
574 set_avr64(VT
, result
, false);
576 tcg_temp_free_i64(result
);
577 tcg_temp_free_i64(sh
);
582 * vsl VRT,VRA,VRB - Vector Shift Left
584 * Shifting left 128 bit value of vA by value specified in bits 125-127 of vB.
585 * Lowest 3 bits in each byte element of register vB must be identical or
586 * result is undefined.
588 static void trans_vsl(DisasContext
*ctx
)
590 int VT
= rD(ctx
->opcode
);
591 int VA
= rA(ctx
->opcode
);
592 int VB
= rB(ctx
->opcode
);
593 TCGv_i64 avrA
= tcg_temp_new_i64();
594 TCGv_i64 avrB
= tcg_temp_new_i64();
595 TCGv_i64 sh
= tcg_temp_new_i64();
596 TCGv_i64 shifted
= tcg_temp_new_i64();
597 TCGv_i64 tmp
= tcg_temp_new_i64();
599 /* Place bits 125-127 of vB in sh. */
600 get_avr64(avrB
, VB
, false);
601 tcg_gen_andi_i64(sh
, avrB
, 0x07ULL
);
604 * Save highest sh bits of lower doubleword element of vA in variable
605 * shifted and perform shift on lower doubleword.
607 get_avr64(avrA
, VA
, false);
608 tcg_gen_subfi_i64(tmp
, 64, sh
);
609 tcg_gen_shr_i64(shifted
, avrA
, tmp
);
610 tcg_gen_andi_i64(shifted
, shifted
, 0x7fULL
);
611 tcg_gen_shl_i64(avrA
, avrA
, sh
);
612 set_avr64(VT
, avrA
, false);
615 * Perform shift on higher doubleword element of vA and replace lowest
616 * sh bits with shifted.
618 get_avr64(avrA
, VA
, true);
619 tcg_gen_shl_i64(avrA
, avrA
, sh
);
620 tcg_gen_or_i64(avrA
, avrA
, shifted
);
621 set_avr64(VT
, avrA
, true);
623 tcg_temp_free_i64(avrA
);
624 tcg_temp_free_i64(avrB
);
625 tcg_temp_free_i64(sh
);
626 tcg_temp_free_i64(shifted
);
627 tcg_temp_free_i64(tmp
);
631 * vsr VRT,VRA,VRB - Vector Shift Right
633 * Shifting right 128 bit value of vA by value specified in bits 125-127 of vB.
634 * Lowest 3 bits in each byte element of register vB must be identical or
635 * result is undefined.
637 static void trans_vsr(DisasContext
*ctx
)
639 int VT
= rD(ctx
->opcode
);
640 int VA
= rA(ctx
->opcode
);
641 int VB
= rB(ctx
->opcode
);
642 TCGv_i64 avrA
= tcg_temp_new_i64();
643 TCGv_i64 avrB
= tcg_temp_new_i64();
644 TCGv_i64 sh
= tcg_temp_new_i64();
645 TCGv_i64 shifted
= tcg_temp_new_i64();
646 TCGv_i64 tmp
= tcg_temp_new_i64();
648 /* Place bits 125-127 of vB in sh. */
649 get_avr64(avrB
, VB
, false);
650 tcg_gen_andi_i64(sh
, avrB
, 0x07ULL
);
653 * Save lowest sh bits of higher doubleword element of vA in variable
654 * shifted and perform shift on higher doubleword.
656 get_avr64(avrA
, VA
, true);
657 tcg_gen_subfi_i64(tmp
, 64, sh
);
658 tcg_gen_shl_i64(shifted
, avrA
, tmp
);
659 tcg_gen_andi_i64(shifted
, shifted
, 0xfe00000000000000ULL
);
660 tcg_gen_shr_i64(avrA
, avrA
, sh
);
661 set_avr64(VT
, avrA
, true);
663 * Perform shift on lower doubleword element of vA and replace highest
664 * sh bits with shifted.
666 get_avr64(avrA
, VA
, false);
667 tcg_gen_shr_i64(avrA
, avrA
, sh
);
668 tcg_gen_or_i64(avrA
, avrA
, shifted
);
669 set_avr64(VT
, avrA
, false);
671 tcg_temp_free_i64(avrA
);
672 tcg_temp_free_i64(avrB
);
673 tcg_temp_free_i64(sh
);
674 tcg_temp_free_i64(shifted
);
675 tcg_temp_free_i64(tmp
);
679 * vgbbd VRT,VRB - Vector Gather Bits by Bytes by Doubleword
681 * All ith bits (i in range 1 to 8) of each byte of doubleword element in source
682 * register are concatenated and placed into ith byte of appropriate doubleword
683 * element in destination register.
685 * Following solution is done for both doubleword elements of source register
686 * in parallel, in order to reduce the number of instructions needed(that's why
688 * First, both doubleword elements of source register vB are placed in
689 * appropriate element of array avr. Bits are gathered in 2x8 iterations(2 for
690 * loops). In first iteration bit 1 of byte 1, bit 2 of byte 2,... bit 8 of
691 * byte 8 are in their final spots so avr[i], i={0,1} can be and-ed with
692 * tcg_mask. For every following iteration, both avr[i] and tcg_mask variables
693 * have to be shifted right for 7 and 8 places, respectively, in order to get
694 * bit 1 of byte 2, bit 2 of byte 3.. bit 7 of byte 8 in their final spots so
695 * shifted avr values(saved in tmp) can be and-ed with new value of tcg_mask...
696 * After first 8 iteration(first loop), all the first bits are in their final
697 * places, all second bits but second bit from eight byte are in their places...
698 * only 1 eight bit from eight byte is in it's place). In second loop we do all
699 * operations symmetrically, in order to get other half of bits in their final
700 * spots. Results for first and second doubleword elements are saved in
701 * result[0] and result[1] respectively. In the end those results are saved in
702 * appropriate doubleword element of destination register vD.
704 static void trans_vgbbd(DisasContext
*ctx
)
706 int VT
= rD(ctx
->opcode
);
707 int VB
= rB(ctx
->opcode
);
708 TCGv_i64 tmp
= tcg_temp_new_i64();
709 uint64_t mask
= 0x8040201008040201ULL
;
713 result
[0] = tcg_temp_new_i64();
714 result
[1] = tcg_temp_new_i64();
716 avr
[0] = tcg_temp_new_i64();
717 avr
[1] = tcg_temp_new_i64();
718 TCGv_i64 tcg_mask
= tcg_temp_new_i64();
720 tcg_gen_movi_i64(tcg_mask
, mask
);
721 for (j
= 0; j
< 2; j
++) {
722 get_avr64(avr
[j
], VB
, j
);
723 tcg_gen_and_i64(result
[j
], avr
[j
], tcg_mask
);
725 for (i
= 1; i
< 8; i
++) {
726 tcg_gen_movi_i64(tcg_mask
, mask
>> (i
* 8));
727 for (j
= 0; j
< 2; j
++) {
728 tcg_gen_shri_i64(tmp
, avr
[j
], i
* 7);
729 tcg_gen_and_i64(tmp
, tmp
, tcg_mask
);
730 tcg_gen_or_i64(result
[j
], result
[j
], tmp
);
733 for (i
= 1; i
< 8; i
++) {
734 tcg_gen_movi_i64(tcg_mask
, mask
<< (i
* 8));
735 for (j
= 0; j
< 2; j
++) {
736 tcg_gen_shli_i64(tmp
, avr
[j
], i
* 7);
737 tcg_gen_and_i64(tmp
, tmp
, tcg_mask
);
738 tcg_gen_or_i64(result
[j
], result
[j
], tmp
);
741 for (j
= 0; j
< 2; j
++) {
742 set_avr64(VT
, result
[j
], j
);
745 tcg_temp_free_i64(tmp
);
746 tcg_temp_free_i64(tcg_mask
);
747 tcg_temp_free_i64(result
[0]);
748 tcg_temp_free_i64(result
[1]);
749 tcg_temp_free_i64(avr
[0]);
750 tcg_temp_free_i64(avr
[1]);
754 * vclzw VRT,VRB - Vector Count Leading Zeros Word
756 * Counting the number of leading zero bits of each word element in source
757 * register and placing result in appropriate word element of destination
760 static void trans_vclzw(DisasContext
*ctx
)
762 int VT
= rD(ctx
->opcode
);
763 int VB
= rB(ctx
->opcode
);
764 TCGv_i32 tmp
= tcg_temp_new_i32();
767 /* Perform count for every word element using tcg_gen_clzi_i32. */
768 for (i
= 0; i
< 4; i
++) {
769 tcg_gen_ld_i32(tmp
, cpu_env
,
770 offsetof(CPUPPCState
, vsr
[32 + VB
].u64
[0]) + i
* 4);
771 tcg_gen_clzi_i32(tmp
, tmp
, 32);
772 tcg_gen_st_i32(tmp
, cpu_env
,
773 offsetof(CPUPPCState
, vsr
[32 + VT
].u64
[0]) + i
* 4);
776 tcg_temp_free_i32(tmp
);
780 * vclzd VRT,VRB - Vector Count Leading Zeros Doubleword
782 * Counting the number of leading zero bits of each doubleword element in source
783 * register and placing result in appropriate doubleword element of destination
786 static void trans_vclzd(DisasContext
*ctx
)
788 int VT
= rD(ctx
->opcode
);
789 int VB
= rB(ctx
->opcode
);
790 TCGv_i64 avr
= tcg_temp_new_i64();
792 /* high doubleword */
793 get_avr64(avr
, VB
, true);
794 tcg_gen_clzi_i64(avr
, avr
, 64);
795 set_avr64(VT
, avr
, true);
798 get_avr64(avr
, VB
, false);
799 tcg_gen_clzi_i64(avr
, avr
, 64);
800 set_avr64(VT
, avr
, false);
802 tcg_temp_free_i64(avr
);
805 GEN_VXFORM(vmuloub
, 4, 0);
806 GEN_VXFORM(vmulouh
, 4, 1);
807 GEN_VXFORM(vmulouw
, 4, 2);
808 GEN_VXFORM(vmuluwm
, 4, 2);
809 GEN_VXFORM_DUAL(vmulouw
, PPC_ALTIVEC
, PPC_NONE
,
810 vmuluwm
, PPC_NONE
, PPC2_ALTIVEC_207
)
811 GEN_VXFORM(vmulosb
, 4, 4);
812 GEN_VXFORM(vmulosh
, 4, 5);
813 GEN_VXFORM(vmulosw
, 4, 6);
814 GEN_VXFORM(vmuleub
, 4, 8);
815 GEN_VXFORM(vmuleuh
, 4, 9);
816 GEN_VXFORM(vmuleuw
, 4, 10);
817 GEN_VXFORM(vmulesb
, 4, 12);
818 GEN_VXFORM(vmulesh
, 4, 13);
819 GEN_VXFORM(vmulesw
, 4, 14);
820 GEN_VXFORM_V(vslb
, MO_8
, tcg_gen_gvec_shlv
, 2, 4);
821 GEN_VXFORM_V(vslh
, MO_16
, tcg_gen_gvec_shlv
, 2, 5);
822 GEN_VXFORM_V(vslw
, MO_32
, tcg_gen_gvec_shlv
, 2, 6);
823 GEN_VXFORM(vrlwnm
, 2, 6);
824 GEN_VXFORM_DUAL(vslw
, PPC_ALTIVEC
, PPC_NONE
, \
825 vrlwnm
, PPC_NONE
, PPC2_ISA300
)
826 GEN_VXFORM_V(vsld
, MO_64
, tcg_gen_gvec_shlv
, 2, 23);
827 GEN_VXFORM_V(vsrb
, MO_8
, tcg_gen_gvec_shrv
, 2, 8);
828 GEN_VXFORM_V(vsrh
, MO_16
, tcg_gen_gvec_shrv
, 2, 9);
829 GEN_VXFORM_V(vsrw
, MO_32
, tcg_gen_gvec_shrv
, 2, 10);
830 GEN_VXFORM_V(vsrd
, MO_64
, tcg_gen_gvec_shrv
, 2, 27);
831 GEN_VXFORM_V(vsrab
, MO_8
, tcg_gen_gvec_sarv
, 2, 12);
832 GEN_VXFORM_V(vsrah
, MO_16
, tcg_gen_gvec_sarv
, 2, 13);
833 GEN_VXFORM_V(vsraw
, MO_32
, tcg_gen_gvec_sarv
, 2, 14);
834 GEN_VXFORM_V(vsrad
, MO_64
, tcg_gen_gvec_sarv
, 2, 15);
835 GEN_VXFORM(vsrv
, 2, 28);
836 GEN_VXFORM(vslv
, 2, 29);
837 GEN_VXFORM(vslo
, 6, 16);
838 GEN_VXFORM(vsro
, 6, 17);
839 GEN_VXFORM(vaddcuw
, 0, 6);
840 GEN_VXFORM(vsubcuw
, 0, 22);
842 #define GEN_VXFORM_SAT(NAME, VECE, NORM, SAT, OPC2, OPC3) \
843 static void glue(glue(gen_, NAME), _vec)(unsigned vece, TCGv_vec t, \
844 TCGv_vec sat, TCGv_vec a, \
847 TCGv_vec x = tcg_temp_new_vec_matching(t); \
848 glue(glue(tcg_gen_, NORM), _vec)(VECE, x, a, b); \
849 glue(glue(tcg_gen_, SAT), _vec)(VECE, t, a, b); \
850 tcg_gen_cmp_vec(TCG_COND_NE, VECE, x, x, t); \
851 tcg_gen_or_vec(VECE, sat, sat, x); \
852 tcg_temp_free_vec(x); \
854 static void glue(gen_, NAME)(DisasContext *ctx) \
856 static const TCGOpcode vecop_list[] = { \
857 glue(glue(INDEX_op_, NORM), _vec), \
858 glue(glue(INDEX_op_, SAT), _vec), \
859 INDEX_op_cmp_vec, 0 \
861 static const GVecGen4 g = { \
862 .fniv = glue(glue(gen_, NAME), _vec), \
863 .fno = glue(gen_helper_, NAME), \
864 .opt_opc = vecop_list, \
865 .write_aofs = true, \
868 if (unlikely(!ctx->altivec_enabled)) { \
869 gen_exception(ctx, POWERPC_EXCP_VPU); \
872 tcg_gen_gvec_4(avr_full_offset(rD(ctx->opcode)), \
873 offsetof(CPUPPCState, vscr_sat), \
874 avr_full_offset(rA(ctx->opcode)), \
875 avr_full_offset(rB(ctx->opcode)), \
879 GEN_VXFORM_SAT(vaddubs
, MO_8
, add
, usadd
, 0, 8);
880 GEN_VXFORM_DUAL_EXT(vaddubs
, PPC_ALTIVEC
, PPC_NONE
, 0, \
881 vmul10uq
, PPC_NONE
, PPC2_ISA300
, 0x0000F800)
882 GEN_VXFORM_SAT(vadduhs
, MO_16
, add
, usadd
, 0, 9);
883 GEN_VXFORM_DUAL(vadduhs
, PPC_ALTIVEC
, PPC_NONE
, \
884 vmul10euq
, PPC_NONE
, PPC2_ISA300
)
885 GEN_VXFORM_SAT(vadduws
, MO_32
, add
, usadd
, 0, 10);
886 GEN_VXFORM_SAT(vaddsbs
, MO_8
, add
, ssadd
, 0, 12);
887 GEN_VXFORM_SAT(vaddshs
, MO_16
, add
, ssadd
, 0, 13);
888 GEN_VXFORM_SAT(vaddsws
, MO_32
, add
, ssadd
, 0, 14);
889 GEN_VXFORM_SAT(vsububs
, MO_8
, sub
, ussub
, 0, 24);
890 GEN_VXFORM_SAT(vsubuhs
, MO_16
, sub
, ussub
, 0, 25);
891 GEN_VXFORM_SAT(vsubuws
, MO_32
, sub
, ussub
, 0, 26);
892 GEN_VXFORM_SAT(vsubsbs
, MO_8
, sub
, sssub
, 0, 28);
893 GEN_VXFORM_SAT(vsubshs
, MO_16
, sub
, sssub
, 0, 29);
894 GEN_VXFORM_SAT(vsubsws
, MO_32
, sub
, sssub
, 0, 30);
895 GEN_VXFORM(vadduqm
, 0, 4);
896 GEN_VXFORM(vaddcuq
, 0, 5);
897 GEN_VXFORM3(vaddeuqm
, 30, 0);
898 GEN_VXFORM3(vaddecuq
, 30, 0);
899 GEN_VXFORM_DUAL(vaddeuqm
, PPC_NONE
, PPC2_ALTIVEC_207
, \
900 vaddecuq
, PPC_NONE
, PPC2_ALTIVEC_207
)
901 GEN_VXFORM(vsubuqm
, 0, 20);
902 GEN_VXFORM(vsubcuq
, 0, 21);
903 GEN_VXFORM3(vsubeuqm
, 31, 0);
904 GEN_VXFORM3(vsubecuq
, 31, 0);
905 GEN_VXFORM_DUAL(vsubeuqm
, PPC_NONE
, PPC2_ALTIVEC_207
, \
906 vsubecuq
, PPC_NONE
, PPC2_ALTIVEC_207
)
907 GEN_VXFORM(vrlb
, 2, 0);
908 GEN_VXFORM(vrlh
, 2, 1);
909 GEN_VXFORM(vrlw
, 2, 2);
910 GEN_VXFORM(vrlwmi
, 2, 2);
911 GEN_VXFORM_DUAL(vrlw
, PPC_ALTIVEC
, PPC_NONE
, \
912 vrlwmi
, PPC_NONE
, PPC2_ISA300
)
913 GEN_VXFORM(vrld
, 2, 3);
914 GEN_VXFORM(vrldmi
, 2, 3);
915 GEN_VXFORM_DUAL(vrld
, PPC_NONE
, PPC2_ALTIVEC_207
, \
916 vrldmi
, PPC_NONE
, PPC2_ISA300
)
917 GEN_VXFORM_TRANS(vsl
, 2, 7);
918 GEN_VXFORM(vrldnm
, 2, 7);
919 GEN_VXFORM_DUAL(vsl
, PPC_ALTIVEC
, PPC_NONE
, \
920 vrldnm
, PPC_NONE
, PPC2_ISA300
)
921 GEN_VXFORM_TRANS(vsr
, 2, 11);
922 GEN_VXFORM_ENV(vpkuhum
, 7, 0);
923 GEN_VXFORM_ENV(vpkuwum
, 7, 1);
924 GEN_VXFORM_ENV(vpkudum
, 7, 17);
925 GEN_VXFORM_ENV(vpkuhus
, 7, 2);
926 GEN_VXFORM_ENV(vpkuwus
, 7, 3);
927 GEN_VXFORM_ENV(vpkudus
, 7, 19);
928 GEN_VXFORM_ENV(vpkshus
, 7, 4);
929 GEN_VXFORM_ENV(vpkswus
, 7, 5);
930 GEN_VXFORM_ENV(vpksdus
, 7, 21);
931 GEN_VXFORM_ENV(vpkshss
, 7, 6);
932 GEN_VXFORM_ENV(vpkswss
, 7, 7);
933 GEN_VXFORM_ENV(vpksdss
, 7, 23);
934 GEN_VXFORM(vpkpx
, 7, 12);
935 GEN_VXFORM_ENV(vsum4ubs
, 4, 24);
936 GEN_VXFORM_ENV(vsum4sbs
, 4, 28);
937 GEN_VXFORM_ENV(vsum4shs
, 4, 25);
938 GEN_VXFORM_ENV(vsum2sws
, 4, 26);
939 GEN_VXFORM_ENV(vsumsws
, 4, 30);
940 GEN_VXFORM_ENV(vaddfp
, 5, 0);
941 GEN_VXFORM_ENV(vsubfp
, 5, 1);
942 GEN_VXFORM_ENV(vmaxfp
, 5, 16);
943 GEN_VXFORM_ENV(vminfp
, 5, 17);
944 GEN_VXFORM_HETRO(vextublx
, 6, 24)
945 GEN_VXFORM_HETRO(vextuhlx
, 6, 25)
946 GEN_VXFORM_HETRO(vextuwlx
, 6, 26)
947 GEN_VXFORM_TRANS_DUAL(vmrgow
, PPC_NONE
, PPC2_ALTIVEC_207
,
948 vextuwlx
, PPC_NONE
, PPC2_ISA300
)
949 GEN_VXFORM_HETRO(vextubrx
, 6, 28)
950 GEN_VXFORM_HETRO(vextuhrx
, 6, 29)
951 GEN_VXFORM_HETRO(vextuwrx
, 6, 30)
952 GEN_VXFORM_TRANS(lvsl
, 6, 31)
953 GEN_VXFORM_TRANS(lvsr
, 6, 32)
954 GEN_VXFORM_TRANS_DUAL(vmrgew
, PPC_NONE
, PPC2_ALTIVEC_207
,
955 vextuwrx
, PPC_NONE
, PPC2_ISA300
)
957 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
958 static void glue(gen_, name)(DisasContext *ctx) \
960 TCGv_ptr ra, rb, rd; \
961 if (unlikely(!ctx->altivec_enabled)) { \
962 gen_exception(ctx, POWERPC_EXCP_VPU); \
965 ra = gen_avr_ptr(rA(ctx->opcode)); \
966 rb = gen_avr_ptr(rB(ctx->opcode)); \
967 rd = gen_avr_ptr(rD(ctx->opcode)); \
968 gen_helper_##opname(cpu_env, rd, ra, rb); \
969 tcg_temp_free_ptr(ra); \
970 tcg_temp_free_ptr(rb); \
971 tcg_temp_free_ptr(rd); \
974 #define GEN_VXRFORM(name, opc2, opc3) \
975 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
976 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
979 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
980 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
981 * come from different versions of the ISA, so we must also support a
982 * pair of flags for each instruction.
984 #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
985 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
987 if ((Rc(ctx->opcode) == 0) && \
988 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
989 if (Rc21(ctx->opcode) == 0) { \
992 gen_##name0##_(ctx); \
994 } else if ((Rc(ctx->opcode) == 1) && \
995 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
996 if (Rc21(ctx->opcode) == 0) { \
999 gen_##name1##_(ctx); \
1002 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
1006 GEN_VXRFORM(vcmpequb
, 3, 0)
1007 GEN_VXRFORM(vcmpequh
, 3, 1)
1008 GEN_VXRFORM(vcmpequw
, 3, 2)
1009 GEN_VXRFORM(vcmpequd
, 3, 3)
1010 GEN_VXRFORM(vcmpnezb
, 3, 4)
1011 GEN_VXRFORM(vcmpnezh
, 3, 5)
1012 GEN_VXRFORM(vcmpnezw
, 3, 6)
1013 GEN_VXRFORM(vcmpgtsb
, 3, 12)
1014 GEN_VXRFORM(vcmpgtsh
, 3, 13)
1015 GEN_VXRFORM(vcmpgtsw
, 3, 14)
1016 GEN_VXRFORM(vcmpgtsd
, 3, 15)
1017 GEN_VXRFORM(vcmpgtub
, 3, 8)
1018 GEN_VXRFORM(vcmpgtuh
, 3, 9)
1019 GEN_VXRFORM(vcmpgtuw
, 3, 10)
1020 GEN_VXRFORM(vcmpgtud
, 3, 11)
1021 GEN_VXRFORM(vcmpeqfp
, 3, 3)
1022 GEN_VXRFORM(vcmpgefp
, 3, 7)
1023 GEN_VXRFORM(vcmpgtfp
, 3, 11)
1024 GEN_VXRFORM(vcmpbfp
, 3, 15)
1025 GEN_VXRFORM(vcmpneb
, 3, 0)
1026 GEN_VXRFORM(vcmpneh
, 3, 1)
1027 GEN_VXRFORM(vcmpnew
, 3, 2)
1029 GEN_VXRFORM_DUAL(vcmpequb
, PPC_ALTIVEC
, PPC_NONE
, \
1030 vcmpneb
, PPC_NONE
, PPC2_ISA300
)
1031 GEN_VXRFORM_DUAL(vcmpequh
, PPC_ALTIVEC
, PPC_NONE
, \
1032 vcmpneh
, PPC_NONE
, PPC2_ISA300
)
1033 GEN_VXRFORM_DUAL(vcmpequw
, PPC_ALTIVEC
, PPC_NONE
, \
1034 vcmpnew
, PPC_NONE
, PPC2_ISA300
)
1035 GEN_VXRFORM_DUAL(vcmpeqfp
, PPC_ALTIVEC
, PPC_NONE
, \
1036 vcmpequd
, PPC_NONE
, PPC2_ALTIVEC_207
)
1037 GEN_VXRFORM_DUAL(vcmpbfp
, PPC_ALTIVEC
, PPC_NONE
, \
1038 vcmpgtsd
, PPC_NONE
, PPC2_ALTIVEC_207
)
1039 GEN_VXRFORM_DUAL(vcmpgtfp
, PPC_ALTIVEC
, PPC_NONE
, \
1040 vcmpgtud
, PPC_NONE
, PPC2_ALTIVEC_207
)
1042 #define GEN_VXFORM_DUPI(name, tcg_op, opc2, opc3) \
1043 static void glue(gen_, name)(DisasContext *ctx) \
1046 if (unlikely(!ctx->altivec_enabled)) { \
1047 gen_exception(ctx, POWERPC_EXCP_VPU); \
1050 simm = SIMM5(ctx->opcode); \
1051 tcg_op(avr_full_offset(rD(ctx->opcode)), 16, 16, simm); \
1054 GEN_VXFORM_DUPI(vspltisb
, tcg_gen_gvec_dup8i
, 6, 12);
1055 GEN_VXFORM_DUPI(vspltish
, tcg_gen_gvec_dup16i
, 6, 13);
1056 GEN_VXFORM_DUPI(vspltisw
, tcg_gen_gvec_dup32i
, 6, 14);
1058 #define GEN_VXFORM_NOA(name, opc2, opc3) \
1059 static void glue(gen_, name)(DisasContext *ctx) \
1062 if (unlikely(!ctx->altivec_enabled)) { \
1063 gen_exception(ctx, POWERPC_EXCP_VPU); \
1066 rb = gen_avr_ptr(rB(ctx->opcode)); \
1067 rd = gen_avr_ptr(rD(ctx->opcode)); \
1068 gen_helper_##name(rd, rb); \
1069 tcg_temp_free_ptr(rb); \
1070 tcg_temp_free_ptr(rd); \
1073 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
1074 static void glue(gen_, name)(DisasContext *ctx) \
1078 if (unlikely(!ctx->altivec_enabled)) { \
1079 gen_exception(ctx, POWERPC_EXCP_VPU); \
1082 rb = gen_avr_ptr(rB(ctx->opcode)); \
1083 rd = gen_avr_ptr(rD(ctx->opcode)); \
1084 gen_helper_##name(cpu_env, rd, rb); \
1085 tcg_temp_free_ptr(rb); \
1086 tcg_temp_free_ptr(rd); \
1089 #define GEN_VXFORM_NOA_2(name, opc2, opc3, opc4) \
1090 static void glue(gen_, name)(DisasContext *ctx) \
1093 if (unlikely(!ctx->altivec_enabled)) { \
1094 gen_exception(ctx, POWERPC_EXCP_VPU); \
1097 rb = gen_avr_ptr(rB(ctx->opcode)); \
1098 rd = gen_avr_ptr(rD(ctx->opcode)); \
1099 gen_helper_##name(rd, rb); \
1100 tcg_temp_free_ptr(rb); \
1101 tcg_temp_free_ptr(rd); \
1104 #define GEN_VXFORM_NOA_3(name, opc2, opc3, opc4) \
1105 static void glue(gen_, name)(DisasContext *ctx) \
1108 if (unlikely(!ctx->altivec_enabled)) { \
1109 gen_exception(ctx, POWERPC_EXCP_VPU); \
1112 rb = gen_avr_ptr(rB(ctx->opcode)); \
1113 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], rb); \
1114 tcg_temp_free_ptr(rb); \
1116 GEN_VXFORM_NOA(vupkhsb
, 7, 8);
1117 GEN_VXFORM_NOA(vupkhsh
, 7, 9);
1118 GEN_VXFORM_NOA(vupkhsw
, 7, 25);
1119 GEN_VXFORM_NOA(vupklsb
, 7, 10);
1120 GEN_VXFORM_NOA(vupklsh
, 7, 11);
1121 GEN_VXFORM_NOA(vupklsw
, 7, 27);
1122 GEN_VXFORM_NOA(vupkhpx
, 7, 13);
1123 GEN_VXFORM_NOA(vupklpx
, 7, 15);
1124 GEN_VXFORM_NOA_ENV(vrefp
, 5, 4);
1125 GEN_VXFORM_NOA_ENV(vrsqrtefp
, 5, 5);
1126 GEN_VXFORM_NOA_ENV(vexptefp
, 5, 6);
1127 GEN_VXFORM_NOA_ENV(vlogefp
, 5, 7);
1128 GEN_VXFORM_NOA_ENV(vrfim
, 5, 11);
1129 GEN_VXFORM_NOA_ENV(vrfin
, 5, 8);
1130 GEN_VXFORM_NOA_ENV(vrfip
, 5, 10);
1131 GEN_VXFORM_NOA_ENV(vrfiz
, 5, 9);
1132 GEN_VXFORM_NOA(vprtybw
, 1, 24);
1133 GEN_VXFORM_NOA(vprtybd
, 1, 24);
1134 GEN_VXFORM_NOA(vprtybq
, 1, 24);
1136 static void gen_vsplt(DisasContext
*ctx
, int vece
)
1138 int uimm
, dofs
, bofs
;
1140 if (unlikely(!ctx
->altivec_enabled
)) {
1141 gen_exception(ctx
, POWERPC_EXCP_VPU
);
1145 uimm
= UIMM5(ctx
->opcode
);
1146 bofs
= avr_full_offset(rB(ctx
->opcode
));
1147 dofs
= avr_full_offset(rD(ctx
->opcode
));
1149 /* Experimental testing shows that hardware masks the immediate. */
1150 bofs
+= (uimm
<< vece
) & 15;
1151 #ifndef HOST_WORDS_BIGENDIAN
1153 bofs
&= ~((1 << vece
) - 1);
1156 tcg_gen_gvec_dup_mem(vece
, dofs
, bofs
, 16, 16);
1159 #define GEN_VXFORM_VSPLT(name, vece, opc2, opc3) \
1160 static void glue(gen_, name)(DisasContext *ctx) { gen_vsplt(ctx, vece); }
1162 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
1163 static void glue(gen_, name)(DisasContext *ctx) \
1168 if (unlikely(!ctx->altivec_enabled)) { \
1169 gen_exception(ctx, POWERPC_EXCP_VPU); \
1172 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
1173 rb = gen_avr_ptr(rB(ctx->opcode)); \
1174 rd = gen_avr_ptr(rD(ctx->opcode)); \
1175 gen_helper_##name(cpu_env, rd, rb, uimm); \
1176 tcg_temp_free_i32(uimm); \
1177 tcg_temp_free_ptr(rb); \
1178 tcg_temp_free_ptr(rd); \
1181 #define GEN_VXFORM_UIMM_SPLAT(name, opc2, opc3, splat_max) \
1182 static void glue(gen_, name)(DisasContext *ctx) \
1185 uint8_t uimm = UIMM4(ctx->opcode); \
1187 if (unlikely(!ctx->altivec_enabled)) { \
1188 gen_exception(ctx, POWERPC_EXCP_VPU); \
1191 if (uimm > splat_max) { \
1194 t0 = tcg_temp_new_i32(); \
1195 tcg_gen_movi_i32(t0, uimm); \
1196 rb = gen_avr_ptr(rB(ctx->opcode)); \
1197 rd = gen_avr_ptr(rD(ctx->opcode)); \
1198 gen_helper_##name(rd, rb, t0); \
1199 tcg_temp_free_i32(t0); \
1200 tcg_temp_free_ptr(rb); \
1201 tcg_temp_free_ptr(rd); \
1204 GEN_VXFORM_VSPLT(vspltb
, MO_8
, 6, 8);
1205 GEN_VXFORM_VSPLT(vsplth
, MO_16
, 6, 9);
1206 GEN_VXFORM_VSPLT(vspltw
, MO_32
, 6, 10);
1207 GEN_VXFORM_UIMM_SPLAT(vextractub
, 6, 8, 15);
1208 GEN_VXFORM_UIMM_SPLAT(vextractuh
, 6, 9, 14);
1209 GEN_VXFORM_UIMM_SPLAT(vextractuw
, 6, 10, 12);
1210 GEN_VXFORM_UIMM_SPLAT(vextractd
, 6, 11, 8);
1211 GEN_VXFORM_UIMM_SPLAT(vinsertb
, 6, 12, 15);
1212 GEN_VXFORM_UIMM_SPLAT(vinserth
, 6, 13, 14);
1213 GEN_VXFORM_UIMM_SPLAT(vinsertw
, 6, 14, 12);
1214 GEN_VXFORM_UIMM_SPLAT(vinsertd
, 6, 15, 8);
1215 GEN_VXFORM_UIMM_ENV(vcfux
, 5, 12);
1216 GEN_VXFORM_UIMM_ENV(vcfsx
, 5, 13);
1217 GEN_VXFORM_UIMM_ENV(vctuxs
, 5, 14);
1218 GEN_VXFORM_UIMM_ENV(vctsxs
, 5, 15);
1219 GEN_VXFORM_DUAL(vspltb
, PPC_ALTIVEC
, PPC_NONE
,
1220 vextractub
, PPC_NONE
, PPC2_ISA300
);
1221 GEN_VXFORM_DUAL(vsplth
, PPC_ALTIVEC
, PPC_NONE
,
1222 vextractuh
, PPC_NONE
, PPC2_ISA300
);
1223 GEN_VXFORM_DUAL(vspltw
, PPC_ALTIVEC
, PPC_NONE
,
1224 vextractuw
, PPC_NONE
, PPC2_ISA300
);
1225 GEN_VXFORM_DUAL(vspltisb
, PPC_ALTIVEC
, PPC_NONE
,
1226 vinsertb
, PPC_NONE
, PPC2_ISA300
);
1227 GEN_VXFORM_DUAL(vspltish
, PPC_ALTIVEC
, PPC_NONE
,
1228 vinserth
, PPC_NONE
, PPC2_ISA300
);
1229 GEN_VXFORM_DUAL(vspltisw
, PPC_ALTIVEC
, PPC_NONE
,
1230 vinsertw
, PPC_NONE
, PPC2_ISA300
);
1232 static void gen_vsldoi(DisasContext
*ctx
)
1234 TCGv_ptr ra
, rb
, rd
;
1236 if (unlikely(!ctx
->altivec_enabled
)) {
1237 gen_exception(ctx
, POWERPC_EXCP_VPU
);
1240 ra
= gen_avr_ptr(rA(ctx
->opcode
));
1241 rb
= gen_avr_ptr(rB(ctx
->opcode
));
1242 rd
= gen_avr_ptr(rD(ctx
->opcode
));
1243 sh
= tcg_const_i32(VSH(ctx
->opcode
));
1244 gen_helper_vsldoi(rd
, ra
, rb
, sh
);
1245 tcg_temp_free_ptr(ra
);
1246 tcg_temp_free_ptr(rb
);
1247 tcg_temp_free_ptr(rd
);
1248 tcg_temp_free_i32(sh
);
1251 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
1252 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
1254 TCGv_ptr ra, rb, rc, rd; \
1255 if (unlikely(!ctx->altivec_enabled)) { \
1256 gen_exception(ctx, POWERPC_EXCP_VPU); \
1259 ra = gen_avr_ptr(rA(ctx->opcode)); \
1260 rb = gen_avr_ptr(rB(ctx->opcode)); \
1261 rc = gen_avr_ptr(rC(ctx->opcode)); \
1262 rd = gen_avr_ptr(rD(ctx->opcode)); \
1263 if (Rc(ctx->opcode)) { \
1264 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
1266 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
1268 tcg_temp_free_ptr(ra); \
1269 tcg_temp_free_ptr(rb); \
1270 tcg_temp_free_ptr(rc); \
1271 tcg_temp_free_ptr(rd); \
1274 GEN_VAFORM_PAIRED(vmhaddshs
, vmhraddshs
, 16)
1276 static void gen_vmladduhm(DisasContext
*ctx
)
1278 TCGv_ptr ra
, rb
, rc
, rd
;
1279 if (unlikely(!ctx
->altivec_enabled
)) {
1280 gen_exception(ctx
, POWERPC_EXCP_VPU
);
1283 ra
= gen_avr_ptr(rA(ctx
->opcode
));
1284 rb
= gen_avr_ptr(rB(ctx
->opcode
));
1285 rc
= gen_avr_ptr(rC(ctx
->opcode
));
1286 rd
= gen_avr_ptr(rD(ctx
->opcode
));
1287 gen_helper_vmladduhm(rd
, ra
, rb
, rc
);
1288 tcg_temp_free_ptr(ra
);
1289 tcg_temp_free_ptr(rb
);
1290 tcg_temp_free_ptr(rc
);
1291 tcg_temp_free_ptr(rd
);
1294 static void gen_vpermr(DisasContext
*ctx
)
1296 TCGv_ptr ra
, rb
, rc
, rd
;
1297 if (unlikely(!ctx
->altivec_enabled
)) {
1298 gen_exception(ctx
, POWERPC_EXCP_VPU
);
1301 ra
= gen_avr_ptr(rA(ctx
->opcode
));
1302 rb
= gen_avr_ptr(rB(ctx
->opcode
));
1303 rc
= gen_avr_ptr(rC(ctx
->opcode
));
1304 rd
= gen_avr_ptr(rD(ctx
->opcode
));
1305 gen_helper_vpermr(cpu_env
, rd
, ra
, rb
, rc
);
1306 tcg_temp_free_ptr(ra
);
1307 tcg_temp_free_ptr(rb
);
1308 tcg_temp_free_ptr(rc
);
1309 tcg_temp_free_ptr(rd
);
1312 GEN_VAFORM_PAIRED(vmsumubm
, vmsummbm
, 18)
1313 GEN_VAFORM_PAIRED(vmsumuhm
, vmsumuhs
, 19)
1314 GEN_VAFORM_PAIRED(vmsumshm
, vmsumshs
, 20)
1315 GEN_VAFORM_PAIRED(vsel
, vperm
, 21)
1316 GEN_VAFORM_PAIRED(vmaddfp
, vnmsubfp
, 23)
1318 GEN_VXFORM_NOA(vclzb
, 1, 28)
1319 GEN_VXFORM_NOA(vclzh
, 1, 29)
1320 GEN_VXFORM_TRANS(vclzw
, 1, 30)
1321 GEN_VXFORM_TRANS(vclzd
, 1, 31)
1322 GEN_VXFORM_NOA_2(vnegw
, 1, 24, 6)
1323 GEN_VXFORM_NOA_2(vnegd
, 1, 24, 7)
1324 GEN_VXFORM_NOA_2(vextsb2w
, 1, 24, 16)
1325 GEN_VXFORM_NOA_2(vextsh2w
, 1, 24, 17)
1326 GEN_VXFORM_NOA_2(vextsb2d
, 1, 24, 24)
1327 GEN_VXFORM_NOA_2(vextsh2d
, 1, 24, 25)
1328 GEN_VXFORM_NOA_2(vextsw2d
, 1, 24, 26)
1329 GEN_VXFORM_NOA_2(vctzb
, 1, 24, 28)
1330 GEN_VXFORM_NOA_2(vctzh
, 1, 24, 29)
1331 GEN_VXFORM_NOA_2(vctzw
, 1, 24, 30)
1332 GEN_VXFORM_NOA_2(vctzd
, 1, 24, 31)
1333 GEN_VXFORM_NOA_3(vclzlsbb
, 1, 24, 0)
1334 GEN_VXFORM_NOA_3(vctzlsbb
, 1, 24, 1)
1335 GEN_VXFORM_NOA(vpopcntb
, 1, 28)
1336 GEN_VXFORM_NOA(vpopcnth
, 1, 29)
1337 GEN_VXFORM_NOA(vpopcntw
, 1, 30)
1338 GEN_VXFORM_NOA(vpopcntd
, 1, 31)
1339 GEN_VXFORM_DUAL(vclzb
, PPC_NONE
, PPC2_ALTIVEC_207
, \
1340 vpopcntb
, PPC_NONE
, PPC2_ALTIVEC_207
)
1341 GEN_VXFORM_DUAL(vclzh
, PPC_NONE
, PPC2_ALTIVEC_207
, \
1342 vpopcnth
, PPC_NONE
, PPC2_ALTIVEC_207
)
1343 GEN_VXFORM_DUAL(vclzw
, PPC_NONE
, PPC2_ALTIVEC_207
, \
1344 vpopcntw
, PPC_NONE
, PPC2_ALTIVEC_207
)
1345 GEN_VXFORM_DUAL(vclzd
, PPC_NONE
, PPC2_ALTIVEC_207
, \
1346 vpopcntd
, PPC_NONE
, PPC2_ALTIVEC_207
)
1347 GEN_VXFORM(vbpermd
, 6, 23);
1348 GEN_VXFORM(vbpermq
, 6, 21);
1349 GEN_VXFORM_TRANS(vgbbd
, 6, 20);
1350 GEN_VXFORM(vpmsumb
, 4, 16)
1351 GEN_VXFORM(vpmsumh
, 4, 17)
1352 GEN_VXFORM(vpmsumw
, 4, 18)
1353 GEN_VXFORM(vpmsumd
, 4, 19)
1355 #define GEN_BCD(op) \
1356 static void gen_##op(DisasContext *ctx) \
1358 TCGv_ptr ra, rb, rd; \
1361 if (unlikely(!ctx->altivec_enabled)) { \
1362 gen_exception(ctx, POWERPC_EXCP_VPU); \
1366 ra = gen_avr_ptr(rA(ctx->opcode)); \
1367 rb = gen_avr_ptr(rB(ctx->opcode)); \
1368 rd = gen_avr_ptr(rD(ctx->opcode)); \
1370 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
1372 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
1374 tcg_temp_free_ptr(ra); \
1375 tcg_temp_free_ptr(rb); \
1376 tcg_temp_free_ptr(rd); \
1377 tcg_temp_free_i32(ps); \
1380 #define GEN_BCD2(op) \
1381 static void gen_##op(DisasContext *ctx) \
1386 if (unlikely(!ctx->altivec_enabled)) { \
1387 gen_exception(ctx, POWERPC_EXCP_VPU); \
1391 rb = gen_avr_ptr(rB(ctx->opcode)); \
1392 rd = gen_avr_ptr(rD(ctx->opcode)); \
1394 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
1396 gen_helper_##op(cpu_crf[6], rd, rb, ps); \
1398 tcg_temp_free_ptr(rb); \
1399 tcg_temp_free_ptr(rd); \
1400 tcg_temp_free_i32(ps); \
1419 static void gen_xpnd04_1(DisasContext
*ctx
)
1421 switch (opc4(ctx
->opcode
)) {
1449 static void gen_xpnd04_2(DisasContext
*ctx
)
1451 switch (opc4(ctx
->opcode
)) {
1477 GEN_VXFORM_DUAL(vsubcuw
, PPC_ALTIVEC
, PPC_NONE
, \
1478 xpnd04_1
, PPC_NONE
, PPC2_ISA300
)
1479 GEN_VXFORM_DUAL(vsubsws
, PPC_ALTIVEC
, PPC_NONE
, \
1480 xpnd04_2
, PPC_NONE
, PPC2_ISA300
)
1482 GEN_VXFORM_DUAL(vsububm
, PPC_ALTIVEC
, PPC_NONE
, \
1483 bcdadd
, PPC_NONE
, PPC2_ALTIVEC_207
)
1484 GEN_VXFORM_DUAL(vsububs
, PPC_ALTIVEC
, PPC_NONE
, \
1485 bcdadd
, PPC_NONE
, PPC2_ALTIVEC_207
)
1486 GEN_VXFORM_DUAL(vsubuhm
, PPC_ALTIVEC
, PPC_NONE
, \
1487 bcdsub
, PPC_NONE
, PPC2_ALTIVEC_207
)
1488 GEN_VXFORM_DUAL(vsubuhs
, PPC_ALTIVEC
, PPC_NONE
, \
1489 bcdsub
, PPC_NONE
, PPC2_ALTIVEC_207
)
1490 GEN_VXFORM_DUAL(vaddshs
, PPC_ALTIVEC
, PPC_NONE
, \
1491 bcdcpsgn
, PPC_NONE
, PPC2_ISA300
)
1492 GEN_VXFORM_DUAL(vsubudm
, PPC2_ALTIVEC_207
, PPC_NONE
, \
1493 bcds
, PPC_NONE
, PPC2_ISA300
)
1494 GEN_VXFORM_DUAL(vsubuwm
, PPC_ALTIVEC
, PPC_NONE
, \
1495 bcdus
, PPC_NONE
, PPC2_ISA300
)
1496 GEN_VXFORM_DUAL(vsubsbs
, PPC_ALTIVEC
, PPC_NONE
, \
1497 bcdtrunc
, PPC_NONE
, PPC2_ISA300
)
1498 GEN_VXFORM_DUAL(vsubuqm
, PPC2_ALTIVEC_207
, PPC_NONE
, \
1499 bcdtrunc
, PPC_NONE
, PPC2_ISA300
)
1500 GEN_VXFORM_DUAL(vsubcuq
, PPC2_ALTIVEC_207
, PPC_NONE
, \
1501 bcdutrunc
, PPC_NONE
, PPC2_ISA300
)
1504 static void gen_vsbox(DisasContext
*ctx
)
1507 if (unlikely(!ctx
->altivec_enabled
)) {
1508 gen_exception(ctx
, POWERPC_EXCP_VPU
);
1511 ra
= gen_avr_ptr(rA(ctx
->opcode
));
1512 rd
= gen_avr_ptr(rD(ctx
->opcode
));
1513 gen_helper_vsbox(rd
, ra
);
1514 tcg_temp_free_ptr(ra
);
1515 tcg_temp_free_ptr(rd
);
1518 GEN_VXFORM(vcipher
, 4, 20)
1519 GEN_VXFORM(vcipherlast
, 4, 20)
1520 GEN_VXFORM(vncipher
, 4, 21)
1521 GEN_VXFORM(vncipherlast
, 4, 21)
1523 GEN_VXFORM_DUAL(vcipher
, PPC_NONE
, PPC2_ALTIVEC_207
,
1524 vcipherlast
, PPC_NONE
, PPC2_ALTIVEC_207
)
1525 GEN_VXFORM_DUAL(vncipher
, PPC_NONE
, PPC2_ALTIVEC_207
,
1526 vncipherlast
, PPC_NONE
, PPC2_ALTIVEC_207
)
1528 #define VSHASIGMA(op) \
1529 static void gen_##op(DisasContext *ctx) \
1533 if (unlikely(!ctx->altivec_enabled)) { \
1534 gen_exception(ctx, POWERPC_EXCP_VPU); \
1537 ra = gen_avr_ptr(rA(ctx->opcode)); \
1538 rd = gen_avr_ptr(rD(ctx->opcode)); \
1539 st_six = tcg_const_i32(rB(ctx->opcode)); \
1540 gen_helper_##op(rd, ra, st_six); \
1541 tcg_temp_free_ptr(ra); \
1542 tcg_temp_free_ptr(rd); \
1543 tcg_temp_free_i32(st_six); \
1546 VSHASIGMA(vshasigmaw
)
1547 VSHASIGMA(vshasigmad
)
1549 GEN_VXFORM3(vpermxor
, 22, 0xFF)
1550 GEN_VXFORM_DUAL(vsldoi
, PPC_ALTIVEC
, PPC_NONE
,
1551 vpermxor
, PPC_NONE
, PPC2_ALTIVEC_207
)
1558 #undef GEN_VX_LOGICAL
1559 #undef GEN_VX_LOGICAL_207
1561 #undef GEN_VXFORM_207
1562 #undef GEN_VXFORM_DUAL
1563 #undef GEN_VXRFORM_DUAL
1566 #undef GEN_VXFORM_DUPI
1567 #undef GEN_VXFORM_NOA
1568 #undef GEN_VXFORM_UIMM
1569 #undef GEN_VAFORM_PAIRED